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-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/ssi.c134
-rw-r--r--arch/arm/mach-ux500/include/mach/hsi.h124
-rw-r--r--arch/arm/plat-omap/include/plat/ssi.h204
4 files changed, 465 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 49f92bc1c31..95578bb571d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -187,6 +187,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),)
obj-y += dsp.o
endif
+omap-ssi-$(CONFIG_OMAP_SSI) := ssi.o
+obj-y += $(omap-ssi-m) $(omap-ssi-y)
+
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
diff --git a/arch/arm/mach-omap2/ssi.c b/arch/arm/mach-omap2/ssi.c
new file mode 100644
index 00000000000..e822a77f5ca
--- /dev/null
+++ b/arch/arm/mach-omap2/ssi.c
@@ -0,0 +1,134 @@
+/*
+ * linux/arch/arm/mach-omap2/ssi.c
+ *
+ * Copyright (C) 2010 Nokia Corporation. All rights reserved.
+ *
+ * Contact: Carlos Chinea <carlos.chinea@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <plat/omap-pm.h>
+#include <plat/ssi.h>
+
+static struct omap_ssi_platform_data ssi_pdata = {
+ .num_ports = SSI_NUM_PORTS,
+ .get_dev_context_loss_count = omap_pm_get_dev_context_loss_count,
+};
+
+static struct resource ssi_resources[] = {
+ /* SSI controller */
+ [0] = {
+ .start = 0x48058000,
+ .end = 0x48058fff,
+ .name = "omap_ssi_sys",
+ .flags = IORESOURCE_MEM,
+ },
+ /* GDD */
+ [1] = {
+ .start = 0x48059000,
+ .end = 0x48059fff,
+ .name = "omap_ssi_gdd",
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = 71,
+ .end = 71,
+ .name = "ssi_gdd",
+ .flags = IORESOURCE_IRQ,
+ },
+ /* SSI port 1 */
+ [3] = {
+ .start = 0x4805a000,
+ .end = 0x4805a7ff,
+ .name = "omap_ssi_sst1",
+ .flags = IORESOURCE_MEM,
+ },
+ [4] = {
+ .start = 0x4805a800,
+ .end = 0x4805afff,
+ .name = "omap_ssi_ssr1",
+ .flags = IORESOURCE_MEM,
+ },
+ [5] = {
+ .start = 67,
+ .end = 67,
+ .name = "ssi_p1_mpu_irq0",
+ .flags = IORESOURCE_IRQ,
+ },
+ [6] = {
+ .start = 68,
+ .end = 68,
+ .name = "ssi_p1_mpu_irq1",
+ .flags = IORESOURCE_IRQ,
+ },
+ [7] = {
+ .start = 0,
+ .end = 0,
+ .name = "ssi_p1_cawake",
+ .flags = IORESOURCE_IRQ | IORESOURCE_UNSET,
+ },
+};
+
+static struct platform_device ssi_pdev = {
+ .name = "omap_ssi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(ssi_resources),
+ .resource = ssi_resources,
+ .dev = {
+ .platform_data = &ssi_pdata,
+ },
+};
+
+int __init omap_ssi_config(struct omap_ssi_board_config *ssi_config)
+{
+ unsigned int port, offset, cawake_gpio;
+ int err;
+
+ ssi_pdata.num_ports = ssi_config->num_ports;
+ for (port = 0, offset = 7; port < ssi_config->num_ports;
+ port++, offset += 5) {
+ cawake_gpio = ssi_config->cawake_gpio[port];
+ if (!cawake_gpio)
+ continue; /* Nothing to do */
+ err = gpio_request(cawake_gpio, "cawake");
+ if (err < 0)
+ goto rback;
+ gpio_direction_input(cawake_gpio);
+ ssi_resources[offset].start = gpio_to_irq(cawake_gpio);
+ ssi_resources[offset].flags &= ~IORESOURCE_UNSET;
+ ssi_resources[offset].flags |= IORESOURCE_IRQ_HIGHEDGE |
+ IORESOURCE_IRQ_LOWEDGE;
+ }
+
+ return 0;
+rback:
+ dev_err(&ssi_pdev.dev, "Request cawake (gpio%d) failed\n", cawake_gpio);
+ while (port > 0)
+ gpio_free(ssi_config->cawake_gpio[--port]);
+
+ return err;
+}
+
+static int __init ssi_init(void)
+{
+ return platform_device_register(&ssi_pdev);
+}
+subsys_initcall(ssi_init);
diff --git a/arch/arm/mach-ux500/include/mach/hsi.h b/arch/arm/mach-ux500/include/mach/hsi.h
new file mode 100644
index 00000000000..58d33249cae
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/hsi.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ */
+
+#ifndef __MACH_HSI_H
+#define __MACH_HSI_H
+
+#include <plat/ste_dma40.h>
+
+/* HSIT register offsets */
+#define STE_HSI_TX_ID 0x000
+#define STE_HSI_TX_MODE 0x004
+#define STE_HSI_TX_STATE 0x008
+#define STE_HSI_TX_IOSTATE 0x00C
+#define STE_HSI_TX_BUFSTATE 0x010
+#define STE_HSI_TX_DIVISOR 0x014
+#define STE_HSI_TX_BREAK 0x01C
+#define STE_HSI_TX_CHANNELS 0x020
+#define STE_HSI_TX_FLUSHBITS 0x024
+#define STE_HSI_TX_PRIORITY 0x028
+#define STE_HSI_TX_STATICCONFID 0x02C
+#define STE_HSI_TX_DATASWAP 0x034
+#define STE_HSI_TX_FRAMELENX 0x080
+#define STE_HSI_TX_BUFFERX 0x0C0
+#define STE_HSI_TX_BASEX 0x100
+#define STE_HSI_TX_SPANX 0x140
+#define STE_HSI_TX_GAUGEX 0x180
+#define STE_HSI_TX_WATERMARKX 0x1C0
+#define STE_HSI_TX_DMAEN 0x200
+#define STE_HSI_TX_WATERMARKMIS 0x204
+#define STE_HSI_TX_WATERMARKIM 0x208
+#define STE_HSI_TX_WATERMARKIC 0x20C
+#define STE_HSI_TX_WATERMARKID 0x210
+#define STE_HSI_TX_WATERMARKIS 0x214
+#define STE_HSI_TX_PERIPHID0 0xFE0
+#define STE_HSI_TX_PERIPHID1 0xFE4
+#define STE_HSI_TX_PERIPHID2 0xFE8
+#define STE_HSI_TX_PERIPHID3 0xFEC
+
+/* HSIR register offsets */
+#define STE_HSI_RX_ID 0x000
+#define STE_HSI_RX_MODE 0x004
+#define STE_HSI_RX_STATE 0x008
+#define STE_HSI_RX_BUFSTATE 0x00C
+#define STE_HSI_RX_THRESHOLD 0x010
+#define STE_HSI_RX_DETECTOR 0x018
+#define STE_HSI_RX_EXCEP 0x01C
+#define STE_HSI_RX_ACK 0x020
+#define STE_HSI_RX_CHANNELS 0x024
+#define STE_HSI_RX_REALTIME 0x028
+#define STE_HSI_RX_OVERRUN 0x02C
+#define STE_HSI_RX_OVERRUNACK 0x030
+#define STE_HSI_RX_PREAMBLE 0x034
+#define STE_HSI_RX_PIPEGAUGE 0x038
+#define STE_HSI_RX_STATICCONFID 0x03C
+#define STE_HSI_RX_BUFFERX 0x080
+#define STE_HSI_RX_FRAMELENX 0x0C0
+#define STE_HSI_RX_BASEX 0x100
+#define STE_HSI_RX_SPANX 0x140
+#define STE_HSI_RX_GAUGEX 0x180
+#define STE_HSI_RX_WATERMARKX 0x1C0
+#define STE_HSI_RX_FRAMEBURSTCNT 0x1E0
+#define STE_HSI_RX_DMAEN 0x200
+#define STE_HSI_RX_WATERMARKMIS 0x204
+#define STE_HSI_RX_WATERMARKIM 0x208
+#define STE_HSI_RX_WATERMARKIC 0x20C
+#define STE_HSI_RX_WATERMARKID 0x210
+#define STE_HSI_RX_OVERRUNMIS 0x214
+#define STE_HSI_RX_OVERRUNIM 0x218
+#define STE_HSI_RX_EXCEPMIS 0x21C
+#define STE_HSI_RX_EXCEPIM 0x220
+#define STE_HSI_RX_WATERMARKIS 0x224
+#define STE_HSI_RX_PERIPHID0 0xFE0
+#define STE_HSI_RX_PERIPHID1 0xFE4
+#define STE_HSI_RX_PERIPHID2 0xFE8
+#define STE_HSI_RX_PERIPHID3 0xFEC
+
+/* HSI states */
+#define STE_HSI_STATE_IDLE 0x00
+#define STE_HSI_STATE_START 0x01
+#define STE_HSI_STATE_TRANSMIT 0x02
+#define STE_HSI_STATE_BREAK 0x03
+#define STE_HSI_STATE_FLUSH 0x04
+#define STE_HSI_STATE_HALT 0x05
+
+/* HSI exceptions */
+#define STE_HSI_EXCEP_TIMEOUT 0x01
+#define STE_HSI_EXCEP_OVERRUN 0x02
+#define STE_HSI_EXCEP_BREAK 0x04
+#define STE_HSI_EXCEP_PARITY 0x08
+
+/* HSI modes */
+#define STE_HSI_MODE_SLEEP 0x00
+#define STE_HSI_MODE_STREAM 0x01
+#define STE_HSI_MODE_FRAME 0x02
+#define STE_HSI_MODE_PIPELINED 0x03
+#define STE_HSI_MODE_FAILSAFE 0x04
+
+#define STE_HSI_MAX_BUFFERS 32
+
+/* Max channels of STE HSI controller */
+#define STE_HSI_MAX_CHANNELS 2
+
+#define STE_HSI_DMA_MAX_BURST 1
+
+struct stedma40_chan_cfg;
+
+struct ste_hsi_port_cfg {
+#ifdef CONFIG_STE_DMA40
+ bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+ struct stedma40_chan_cfg *dma_tx_cfg;
+ struct stedma40_chan_cfg *dma_rx_cfg;
+#endif
+};
+
+struct ste_hsi_platform_data {
+ int num_ports;
+ int use_dma;
+ struct ste_hsi_port_cfg *port_cfg;
+};
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/ssi.h b/arch/arm/plat-omap/include/plat/ssi.h
new file mode 100644
index 00000000000..eb84c3a69f7
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/ssi.h
@@ -0,0 +1,204 @@
+/*
+ * plat/ssi.h
+ *
+ * Hardware definitions for SSI.
+ *
+ * Copyright (C) 2010 Nokia Corporation. All rights reserved.
+ *
+ * Contact: Carlos Chinea <carlos.chinea@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef __OMAP_SSI_REGS_H__
+#define __OMAP_SSI_REGS_H__
+
+#define SSI_NUM_PORTS 1
+/*
+ * SSI SYS registers
+ */
+#define SSI_REVISION_REG 0
+# define SSI_REV_MAJOR 0xf0
+# define SSI_REV_MINOR 0xf
+#define SSI_SYSCONFIG_REG 0x10
+# define SSI_AUTOIDLE (1 << 0)
+# define SSI_SOFTRESET (1 << 1)
+# define SSI_SIDLEMODE_FORCE 0
+# define SSI_SIDLEMODE_NO (1 << 3)
+# define SSI_SIDLEMODE_SMART (1 << 4)
+# define SSI_SIDLEMODE_MASK 0x18
+# define SSI_MIDLEMODE_FORCE 0
+# define SSI_MIDLEMODE_NO (1 << 12)
+# define SSI_MIDLEMODE_SMART (1 << 13)
+# define SSI_MIDLEMODE_MASK 0x3000
+#define SSI_SYSSTATUS_REG 0x14
+# define SSI_RESETDONE 1
+#define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2))
+#define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8))
+# define SSI_DATAACCEPT(channel) (1 << (channel))
+# define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8))
+# define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16))
+# define SSI_ERROROCCURED (1 << 24)
+# define SSI_BREAKDETECTED (1 << 25)
+#define SSI_GDD_MPU_IRQ_STATUS_REG 0x0800
+#define SSI_GDD_MPU_IRQ_ENABLE_REG 0x0804
+# define SSI_GDD_LCH(channel) (1 << (channel))
+#define SSI_WAKE_REG(port) (0xc00 + ((port) * 0x10))
+#define SSI_CLEAR_WAKE_REG(port) (0xc04 + ((port) * 0x10))
+#define SSI_SET_WAKE_REG(port) (0xc08 + ((port) * 0x10))
+# define SSI_WAKE(channel) (1 << (channel))
+# define SSI_WAKE_MASK 0xff
+
+/*
+ * SSI SST registers
+ */
+#define SSI_SST_ID_REG 0
+#define SSI_SST_MODE_REG 4
+# define SSI_MODE_VAL_MASK 3
+# define SSI_MODE_SLEEP 0
+# define SSI_MODE_STREAM 1
+# define SSI_MODE_FRAME 2
+# define SSI_MODE_MULTIPOINTS 3
+#define SSI_SST_FRAMESIZE_REG 8
+# define SSI_FRAMESIZE_DEFAULT 31
+#define SSI_SST_TXSTATE_REG 0xc
+# define SSI_TXSTATE_IDLE 0
+#define SSI_SST_BUFSTATE_REG 0x10
+# define SSI_FULL(channel) (1 << (channel))
+#define SSI_SST_DIVISOR_REG 0x18
+# define SSI_MAX_DIVISOR 127
+#define SSI_SST_BREAK_REG 0x20
+#define SSI_SST_CHANNELS_REG 0x24
+# define SSI_CHANNELS_DEFAULT 4
+#define SSI_SST_ARBMODE_REG 0x28
+# define SSI_ARBMODE_ROUNDROBIN 0
+# define SSI_ARBMODE_PRIORITY 1
+#define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
+#define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
+
+/*
+ * SSI SSR registers
+ */
+#define SSI_SSR_ID_REG 0
+#define SSI_SSR_MODE_REG 4
+#define SSI_SSR_FRAMESIZE_REG 8
+#define SSI_SSR_RXSTATE_REG 0xc
+#define SSI_SSR_BUFSTATE_REG 0x10
+# define SSI_NOTEMPTY(channel) (1 << (channel))
+#define SSI_SSR_BREAK_REG 0x1c
+#define SSI_SSR_ERROR_REG 0x20
+#define SSI_SSR_ERRORACK_REG 0x24
+#define SSI_SSR_OVERRUN_REG 0x2c
+#define SSI_SSR_OVERRUNACK_REG 0x30
+#define SSI_SSR_TIMEOUT_REG 0x34
+# define SSI_TIMEOUT_DEFAULT 0
+#define SSI_SSR_CHANNELS_REG 0x28
+#define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4))
+#define SSI_SSR_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4))
+
+/*
+ * SSI GDD registers
+ */
+#define SSI_GDD_HW_ID_REG 0
+#define SSI_GDD_PPORT_ID_REG 0x10
+#define SSI_GDD_MPORT_ID_REG 0x14
+#define SSI_GDD_PPORT_SR_REG 0x20
+#define SSI_GDD_MPORT_SR_REG 0x24
+# define SSI_ACTIVE_LCH_NUM_MASK 0xff
+#define SSI_GDD_TEST_REG 0x40
+# define SSI_TEST 1
+#define SSI_GDD_GCR_REG 0x100
+# define SSI_CLK_AUTOGATING_ON (1 << 3)
+# define SSI_FREE (1 << 2)
+# define SSI_SWITCH_OFF (1 << 0)
+#define SSI_GDD_GRST_REG 0x200
+# define SSI_SWRESET 1
+#define SSI_GDD_CSDP_REG(channel) (0x800 + ((channel) * 0x40))
+# define SSI_DST_BURST_EN_MASK 0xc000
+# define SSI_DST_SINGLE_ACCESS0 0
+# define SSI_DST_SINGLE_ACCESS (1 << 14)
+# define SSI_DST_BURST_4x32_BIT (2 << 14)
+# define SSI_DST_BURST_8x32_BIT (3 << 14)
+# define SSI_DST_MASK 0x1e00
+# define SSI_DST_MEMORY_PORT (8 << 9)
+# define SSI_DST_PERIPHERAL_PORT (9 << 9)
+# define SSI_SRC_BURST_EN_MASK 0x180
+# define SSI_SRC_SINGLE_ACCESS0 0
+# define SSI_SRC_SINGLE_ACCESS (1 << 7)
+# define SSI_SRC_BURST_4x32_BIT (2 << 7)
+# define SSI_SRC_BURST_8x32_BIT (3 << 7)
+# define SSI_SRC_MASK 0x3c
+# define SSI_SRC_MEMORY_PORT (8 << 2)
+# define SSI_SRC_PERIPHERAL_PORT (9 << 2)
+# define SSI_DATA_TYPE_MASK 3
+# define SSI_DATA_TYPE_S32 2
+#define SSI_GDD_CCR_REG(channel) (0x802 + ((channel) * 0x40))
+# define SSI_DST_AMODE_MASK (3 << 14)
+# define SSI_DST_AMODE_CONST 0
+# define SSI_DST_AMODE_POSTINC (1 << 12)
+# define SSI_SRC_AMODE_MASK (3 << 12)
+# define SSI_SRC_AMODE_CONST 0
+# define SSI_SRC_AMODE_POSTINC (1 << 12)
+# define SSI_CCR_ENABLE (1 << 7)
+# define SSI_CCR_SYNC_MASK 0x1f
+#define SSI_GDD_CICR_REG(channel) (0x804 + ((channel) * 0x40))
+# define SSI_BLOCK_IE (1 << 5)
+# define SSI_HALF_IE (1 << 2)
+# define SSI_TOUT_IE (1 << 0)
+#define SSI_GDD_CSR_REG(channel) (0x806 + ((channel) * 0x40))
+# define SSI_CSR_SYNC (1 << 6)
+# define SSI_CSR_BLOCK (1 << 5)
+# define SSI_CSR_HALF (1 << 2)
+# define SSI_CSR_TOUR (1 << 0)
+#define SSI_GDD_CSSA_REG(channel) (0x808 + ((channel) * 0x40))
+#define SSI_GDD_CDSA_REG(channel) (0x80c + ((channel) * 0x40))
+#define SSI_GDD_CEN_REG(channel) (0x810 + ((channel) * 0x40))
+#define SSI_GDD_CSAC_REG(channel) (0x818 + ((channel) * 0x40))
+#define SSI_GDD_CDAC_REG(channel) (0x81a + ((channel) * 0x40))
+#define SSI_GDD_CLNK_CTRL_REG(channel) (0x828 + ((channel) * 0x40))
+# define SSI_ENABLE_LNK (1 << 15)
+# define SSI_STOP_LNK (1 << 14)
+# define SSI_NEXT_CH_ID_MASK 0xf
+
+/**
+ * struct omap_ssi_platform_data - OMAP SSI platform data
+ * @num_ports: Number of ports on the controller
+ * @ctxt_loss_count: Pointer to omap_pm_get_dev_context_loss_count
+ */
+struct omap_ssi_platform_data {
+ unsigned int num_ports;
+ int (*get_dev_context_loss_count)(struct device *dev);
+};
+
+/**
+ * struct omap_ssi_config - SSI board configuration
+ * @num_ports: Number of ports in use
+ * @cawake_line: Array of cawake gpio lines
+ */
+struct omap_ssi_board_config {
+ unsigned int num_ports;
+ int cawake_gpio[SSI_NUM_PORTS];
+};
+
+#ifdef CONFIG_OMAP_SSI_CONFIG
+extern int omap_ssi_config(struct omap_ssi_board_config *ssi_config);
+#else
+static inline int omap_ssi_config(struct omap_ssi_board_config *ssi_config)
+{
+ return 0;
+}
+#endif /* CONFIG_OMAP_SSI_CONFIG */
+
+#endif /* __OMAP_SSI_REGS_H__ */
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