diff options
Diffstat (limited to 'drivers/net/wireless/bcmdhd/include/bcmdevs.h')
| -rw-r--r-- | drivers/net/wireless/bcmdhd/include/bcmdevs.h | 386 |
1 files changed, 61 insertions, 325 deletions
diff --git a/drivers/net/wireless/bcmdhd/include/bcmdevs.h b/drivers/net/wireless/bcmdhd/include/bcmdevs.h index ee01d8b4567..c49d68eecd6 100644 --- a/drivers/net/wireless/bcmdhd/include/bcmdevs.h +++ b/drivers/net/wireless/bcmdhd/include/bcmdevs.h @@ -1,9 +1,9 @@ /* * Broadcom device-specific manifest constants. * - * Copyright (C) 1999-2011, Broadcom Corporation + * Copyright (C) 1999-2012, Broadcom Corporation * - * Unless you and Broadcom execute a separate written software license + * Unless you and Broadcom execute a separate written software license * agreement governing use of this software, this software is licensed to you * under the terms of the GNU General Public License version 2 (the "GPL"), * available at http://www.broadcom.com/licenses/GPLv2.php, with the @@ -21,10 +21,9 @@ * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * - * $Id: bcmdevs.h 295140 2011-11-09 17:22:01Z $ + * $Id: bcmdevs.h 309997 2012-01-21 06:26:00Z $ */ - #ifndef _BCMDEVS_H #define _BCMDEVS_H @@ -60,7 +59,11 @@ #define BCM_DNGL_BL_PID_43236 0xbd17 #define BCM_DNGL_BL_PID_4332 0xbd18 #define BCM_DNGL_BL_PID_4330 0xbd19 +#define BCM_DNGL_BL_PID_4334 0xbd1a #define BCM_DNGL_BL_PID_43239 0xbd1b +#define BCM_DNGL_BL_PID_4324 0xbd1c +#define BCM_DNGL_BL_PID_4360 0xbd1d + #define BCM_DNGL_BDC_PID 0x0bdc #define BCM_DNGL_JTAG_PID 0x4a44 @@ -134,16 +137,31 @@ #define BCM43237_D11N_ID 0x4355 #define BCM43237_D11N5G_ID 0x4356 #define BCM43227_D11N2G_ID 0x4358 -#define BCM43228_D11N_ID 0x4359 +#define BCM43228_D11N_ID 0x4359 #define BCM43228_D11N5G_ID 0x435a #define BCM43362_D11N_ID 0x4363 #define BCM43239_D11N_ID 0x4370 #define BCM4324_D11N_ID 0x4374 #define BCM43217_D11N2G_ID 0x43a9 #define BCM43131_D11N2G_ID 0x43aa - #define BCM4314_D11N2G_ID 0x4364 #define BCM43142_D11N2G_ID 0x4365 +#define BCM4334_D11N_ID 0x4380 +#define BCM4334_D11N2G_ID 0x4381 +#define BCM4334_D11N5G_ID 0x4382 +#define BCM4360_D11AC_ID 0x43a0 +#define BCM4360_D11AC2G_ID 0x43a1 +#define BCM4360_D11AC5G_ID 0x43a2 + + +#define BCM943228HMB_SSID_VEN1 0x0607 +#define BCM94313HMGBL_SSID_VEN1 0x0608 +#define BCM94313HMG_SSID_VEN1 0x0609 + + +#define BCM4335_D11AC_ID 0x43a9 +#define BCM4335_D11AC2G_ID 0x43aa +#define BCM4335_D11AC5G_ID 0x43ab #define BCMGPRS_UART_ID 0x4333 #define BCMGPRS2_UART_ID 0x4344 @@ -225,6 +243,7 @@ #define BCM43421_CHIP_ID 43421 #define BCM43428_CHIP_ID 43428 #define BCM43431_CHIP_ID 43431 +#define BCM43460_CHIP_ID 43460 #define BCM4325_CHIP_ID 0x4325 #define BCM4328_CHIP_ID 0x4328 #define BCM4329_CHIP_ID 0x4329 @@ -235,11 +254,17 @@ #define BCM6362_CHIP_ID 0x6362 #define BCM4314_CHIP_ID 0x4314 #define BCM43142_CHIP_ID 43142 -#define BCM4324_CHIP_ID 0x4324 +#define BCM4324_CHIP_ID 0x4324 +#define BCM43242_CHIP_ID 43242 +#define BCM4334_CHIP_ID 0x4334 +#define BCM4360_CHIP_ID 0x4360 + +#define BCM4335_CHIP_ID 0x4335 #define BCM4342_CHIP_ID 4342 #define BCM4402_CHIP_ID 0x4402 #define BCM4704_CHIP_ID 0x4704 +#define BCM4706_CHIP_ID 0x5300 #define BCM4710_CHIP_ID 0x4710 #define BCM4712_CHIP_ID 0x4712 #define BCM4716_CHIP_ID 0x4716 @@ -278,11 +303,14 @@ #define BCM5357_PKG_ID 11 #define BCM5356U_PKG_ID 12 #define BCM53572_PKG_ID 8 +#define BCM5357C0_PKG_ID 8 #define BCM47188_PKG_ID 9 +#define BCM5358C0_PKG_ID 0xa +#define BCM5356C0_PKG_ID 0xb #define BCM4331TT_PKG_ID 8 #define BCM4331TN_PKG_ID 9 #define BCM4331TNA0_PKG_ID 0xb - +#define BCM4706L_PKG_ID 1 #define HDLSIM5350_PKG_ID 1 #define HDLSIM_PKG_ID 14 @@ -312,9 +340,7 @@ #define BFL_CCKHIPWR 0x00000040 #define BFL_ENETADM 0x00000080 #define BFL_ENETVLAN 0x00000100 -#ifdef WLAFTERBURNER -#define BFL_AFTERBURNER 0x00000200 -#endif +#define BFL_UNUSED 0x00000200 #define BFL_NOPCI 0x00000400 #define BFL_FEM 0x00000800 #define BFL_EXTLNA 0x00001000 @@ -362,6 +388,9 @@ #define BFL2_IPALVLSHIFT_3P3 0x00020000 #define BFL2_INTERNDET_TXIQCAL 0x00040000 #define BFL2_XTALBUFOUTEN 0x00080000 + + + #define BFL2_ANAPACTRL_2G 0x00100000 #define BFL2_ANAPACTRL_5G 0x00200000 #define BFL2_ELNACTRL_TRSW_2G 0x00400000 @@ -369,10 +398,11 @@ #define BFL2_TEMPSENSE_HIGHER 0x01000000 #define BFL2_BTC3WIREONLY 0x02000000 #define BFL2_PWR_NOMINAL 0x04000000 -#define BFL2_EXTLNA_TX 0x08000000 +#define BFL2_EXTLNA_PWRSAVE 0x08000000 #define BFL2_4313_RADIOREG 0x10000000 +#define BFL2_SDR_EN 0x20000000 #define BOARD_GPIO_BTC3W_IN 0x850 @@ -388,7 +418,8 @@ #define BOARD_GPIO_BTC4_BT 0x2000 #define BOARD_GPIO_BTC4_STAT 0x4000 #define BOARD_GPIO_BTC4_WLAN 0x8000 -#define BOARD_GPIO_1_WLAN_PWR 0x2 +#define BOARD_GPIO_1_WLAN_PWR 0x02 +#define BOARD_GPIO_3_WLAN_PWR 0x08 #define BOARD_GPIO_4_WLAN_PWR 0x10 #define GPIO_BTC4W_OUT_4312 0x010 @@ -397,6 +428,7 @@ #define GPIO_BTC4W_OUT_43225 0x0e0 #define GPIO_BTC4W_OUT_43421 0x020 #define GPIO_BTC4W_OUT_4313 0x060 +#define GPIO_BTC4W_OUT_4331_SHARED 0x010 #define PCI_CFG_GPIO_SCS 0x10 #define PCI_CFG_GPIO_HWRAD 0x20 @@ -410,316 +442,6 @@ #define XTAL_ON_DELAY 1000 -#define BU4710_BOARD 0x0400 -#define VSIM4710_BOARD 0x0401 -#define QT4710_BOARD 0x0402 - -#define BU4309_BOARD 0x040a -#define BCM94309CB_BOARD 0x040b -#define BCM94309MP_BOARD 0x040c -#define BCM4309AP_BOARD 0x040d - -#define BCM94302MP_BOARD 0x040e - -#define BU4306_BOARD 0x0416 -#define BCM94306CB_BOARD 0x0417 -#define BCM94306MP_BOARD 0x0418 - -#define BCM94710D_BOARD 0x041a -#define BCM94710R1_BOARD 0x041b -#define BCM94710R4_BOARD 0x041c -#define BCM94710AP_BOARD 0x041d - -#define BU2050_BOARD 0x041f - -#define BCM94306P50_BOARD 0x0420 - -#define BCM94309G_BOARD 0x0421 - -#define BU4704_BOARD 0x0423 -#define BU4702_BOARD 0x0424 - -#define BCM94306PC_BOARD 0x0425 - -#define MPSG4306_BOARD 0x0427 - -#define BCM94702MN_BOARD 0x0428 - - -#define BCM94702CPCI_BOARD 0x0429 - - -#define BCM95380RR_BOARD 0x042a - - -#define BCM94306CBSG_BOARD 0x042b - - -#define PCSG94306_BOARD 0x042d - - -#define BU4704SD_BOARD 0x042e - - -#define BCM94704AGR_BOARD 0x042f - - -#define BCM94308MP_BOARD 0x0430 - - -#define BCM94306GPRS_BOARD 0x0432 - - -#define BU5365_FPGA_BOARD 0x0433 - -#define BU4712_BOARD 0x0444 -#define BU4712SD_BOARD 0x045d -#define BU4712L_BOARD 0x045f - - -#define BCM94712AP_BOARD 0x0445 -#define BCM94712P_BOARD 0x0446 - - -#define BU4318_BOARD 0x0447 -#define CB4318_BOARD 0x0448 -#define MPG4318_BOARD 0x0449 -#define MP4318_BOARD 0x044a -#define SD4318_BOARD 0x044b - - -#define BCM94313BU_BOARD 0x050f -#define BCM94313HM_BOARD 0x0510 -#define BCM94313EPA_BOARD 0x0511 -#define BCM94313HMG_BOARD 0x051C - - -#define BCM96338_BOARD 0x6338 -#define BCM96348_BOARD 0x6348 -#define BCM96358_BOARD 0x6358 -#define BCM96368_BOARD 0x6368 - - -#define BCM94306P_BOARD 0x044c - - -#define BCM94303MP_BOARD 0x044e - - -#define BCM94306MPSGH_BOARD 0x044f - - -#define BCM94306MPM 0x0450 -#define BCM94306MPL 0x0453 - - -#define BCM94712AGR_BOARD 0x0451 - - -#define PC4303_BOARD 0x0454 - - -#define BCM95350K_BOARD 0x0455 - - -#define BCM95350R_BOARD 0x0456 - - -#define BCM94306MPLNA_BOARD 0x0457 - - -#define BU4320_BOARD 0x0458 -#define BU4320S_BOARD 0x0459 -#define BCM94320PH_BOARD 0x045a - - -#define BCM94306MPH_BOARD 0x045b - - -#define BCM94306PCIV_BOARD 0x045c - -#define BU4712SD_BOARD 0x045d - -#define BCM94320PFLSH_BOARD 0x045e - -#define BU4712L_BOARD 0x045f -#define BCM94712LGR_BOARD 0x0460 -#define BCM94320R_BOARD 0x0461 - -#define BU5352_BOARD 0x0462 - -#define BCM94318MPGH_BOARD 0x0463 - -#define BU4311_BOARD 0x0464 -#define BCM94311MC_BOARD 0x0465 -#define BCM94311MCAG_BOARD 0x0466 - -#define BCM95352GR_BOARD 0x0467 - - -#define BCM95351AGR_BOARD 0x0470 - - -#define BCM94704MPCB_BOARD 0x0472 - - -#define BU4785_BOARD 0x0478 - - -#define BU4321_BOARD 0x046b -#define BU4321E_BOARD 0x047c -#define MP4321_BOARD 0x046c -#define CB2_4321_BOARD 0x046d -#define CB2_4321_AG_BOARD 0x0066 -#define MC4321_BOARD 0x046e - - -#define BU4328_BOARD 0x0481 -#define BCM4328SDG_BOARD 0x0482 -#define BCM4328SDAG_BOARD 0x0483 -#define BCM4328UG_BOARD 0x0484 -#define BCM4328UAG_BOARD 0x0485 -#define BCM4328PC_BOARD 0x0486 -#define BCM4328CF_BOARD 0x0487 - - -#define BCM94325DEVBU_BOARD 0x0490 -#define BCM94325BGABU_BOARD 0x0491 - -#define BCM94325SDGWB_BOARD 0x0492 - -#define BCM94325SDGMDL_BOARD 0x04aa -#define BCM94325SDGMDL2_BOARD 0x04c6 -#define BCM94325SDGMDL3_BOARD 0x04c9 - -#define BCM94325SDABGWBA_BOARD 0x04e1 - - -#define BCM94322MC_SSID 0x04a4 -#define BCM94322USB_SSID 0x04a8 -#define BCM94322HM_SSID 0x04b0 -#define BCM94322USB2D_SSID 0x04bf - - -#define BCM4312MCGSG_BOARD 0x04b5 - - -#define BCM94315DEVBU_SSID 0x04c2 -#define BCM94315USBGP_SSID 0x04c7 -#define BCM94315BGABU_SSID 0x04ca -#define BCM94315USBGP41_SSID 0x04cb - - -#define BCM94319DEVBU_SSID 0X04e5 -#define BCM94319USB_SSID 0X04e6 -#define BCM94319SD_SSID 0X04e7 - - -#define BCM94716NR2_SSID 0x04cd - - -#define BCM94319DEVBU_SSID 0X04e5 -#define BCM94319USBNP4L_SSID 0X04e6 -#define BCM94319WLUSBN4L_SSID 0X04e7 -#define BCM94319SDG_SSID 0X04ea -#define BCM94319LCUSBSDN4L_SSID 0X04eb -#define BCM94319USBB_SSID 0x04ee -#define BCM94319LCSDN4L_SSID 0X0507 -#define BCM94319LSUSBN4L_SSID 0X0508 -#define BCM94319SDNA4L_SSID 0X0517 -#define BCM94319SDELNA4L_SSID 0X0518 -#define BCM94319SDELNA6L_SSID 0X0539 -#define BCM94319ARCADYAN_SSID 0X0546 -#define BCM94319WINDSOR_SSID 0x0561 -#define BCM94319MLAP_SSID 0x0562 -#define BCM94319SDNA_SSID 0x058b -#define BCM94319BHEMU3_SSID 0x0563 -#define BCM94319SDHMB_SSID 0x058c -#define BCM94319SDBREF_SSID 0x05a1 -#define BCM94319USBSDB_SSID 0x05a2 - - - -#define BCM94329AGB_SSID 0X04b9 -#define BCM94329TDKMDL1_SSID 0X04ba -#define BCM94329TDKMDL11_SSID 0X04fc -#define BCM94329OLYMPICN18_SSID 0X04fd -#define BCM94329OLYMPICN90_SSID 0X04fe -#define BCM94329OLYMPICN90U_SSID 0X050c -#define BCM94329OLYMPICN90M_SSID 0X050b -#define BCM94329AGBF_SSID 0X04ff -#define BCM94329OLYMPICX17_SSID 0X0504 -#define BCM94329OLYMPICX17M_SSID 0X050a -#define BCM94329OLYMPICX17U_SSID 0X0509 -#define BCM94329OLYMPICUNO_SSID 0X0564 -#define BCM94329MOTOROLA_SSID 0X0565 -#define BCM94329OLYMPICLOCO_SSID 0X0568 - -#define BCM94336SD_WLBGABU_SSID 0x0511 -#define BCM94336SD_WLBGAREF_SSID 0x0519 -#define BCM94336SDGP_SSID 0x0538 -#define BCM94336SDG_SSID 0x0519 -#define BCM94336SDGN_SSID 0x0538 -#define BCM94336SDGFC_SSID 0x056B - - -#define BCM94330SDG_SSID 0x0528 -#define BCM94330SD_FCBGABU_SSID 0x052e -#define BCM94330SD_WLBGABU_SSID 0x052f -#define BCM94330SD_FCBGA_SSID 0x0530 -#define BCM94330FCSDAGB_SSID 0x0532 -#define BCM94330OLYMPICAMG_SSID 0x0549 -#define BCM94330OLYMPICAMGEPA_SSID 0x054F -#define BCM94330OLYMPICUNO3_SSID 0x0551 -#define BCM94330WLSDAGB_SSID 0x0547 -#define BCM94330CSPSDAGBB_SSID 0x054A - - -#define BCM943224X21 0x056e -#define BCM943224X21_FCC 0x00d1 - - -#define BCM943228BU8_SSID 0x0540 -#define BCM943228BU9_SSID 0x0541 -#define BCM943228BU_SSID 0x0542 -#define BCM943227HM4L_SSID 0x0543 -#define BCM943227HMB_SSID 0x0544 -#define BCM943228HM4L_SSID 0x0545 -#define BCM943228SD_SSID 0x0573 - - -#define BCM943239MOD_SSID 0x05ac -#define BCM943239REF_SSID 0x05aa - - -#define BCM94331X19 0x00D6 -#define BCM94331PCIEBT3Ax_SSID 0x00E4 -#define BCM94331X12_2G_SSID 0x00EC -#define BCM94331X12_5G_SSID 0x00ED -#define BCM94331X29B 0x00EF -#define BCM94331BU_SSID 0x0523 -#define BCM94331S9BU_SSID 0x0524 -#define BCM94331MC_SSID 0x0525 -#define BCM94331MCI_SSID 0x0526 -#define BCM94331PCIEBT4_SSID 0x0527 -#define BCM94331HM_SSID 0x0574 -#define BCM94331PCIEDUAL_SSID 0x059B -#define BCM94331MCH5_SSID 0x05A9 -#define BCM94331PCIEDUALV2_SSID 0x05B7 -#define BCM94331CS_SSID 0x05C6 -#define BCM94331CSAX_SSID 0x00EF - - -#define BCM953572BU_SSID 0x058D -#define BCM953572NR2_SSID 0x058E -#define BCM947188NR2_SSID 0x058F -#define BCM953572SDRNR2_SSID 0x0590 - - -#define BCM943236OLYMPICSULLEY_SSID 0x594 -#define BCM943236PREPROTOBLU2O3_SSID 0x5b9 -#define BCM943236USBELNA_SSID 0x5f8 - #define GPIO_NUMPINS 32 @@ -738,8 +460,22 @@ #define MUXENAB_UART 0x00000001 #define MUXENAB_GPIO 0x00000002 -#define MUXENAB_ERCX 0x00000004 +#define MUXENAB_ERCX 0x00000004 #define MUXENAB_JTAG 0x00000008 -#define MUXENAB_HOST_WAKE 0x00000010 +#define MUXENAB_HOST_WAKE 0x00000010 +#define MUXENAB_I2S_EN 0x00000020 +#define MUXENAB_I2S_MASTER 0x00000040 +#define MUXENAB_I2S_FULL 0x00000080 +#define MUXENAB_SFLASH 0x00000100 +#define MUXENAB_RFSWCTRL0 0x00000200 +#define MUXENAB_RFSWCTRL1 0x00000400 +#define MUXENAB_RFSWCTRL2 0x00000800 +#define MUXENAB_SECI 0x00001000 +#define MUXENAB_BT_LEGACY 0x00002000 +#define MUXENAB_HOST_WAKE1 0x00004000 + + +#define FLASH_KERNEL_NFLASH 0x00000001 +#define FLASH_BOOT_NFLASH 0x00000002 #endif |