diff options
Diffstat (limited to 'sound/soc/omap/abe/abe_cm_addr.h')
| -rw-r--r-- | sound/soc/omap/abe/abe_cm_addr.h | 284 |
1 files changed, 284 insertions, 0 deletions
diff --git a/sound/soc/omap/abe/abe_cm_addr.h b/sound/soc/omap/abe/abe_cm_addr.h new file mode 100644 index 00000000000..070c961c6ed --- /dev/null +++ b/sound/soc/omap/abe/abe_cm_addr.h @@ -0,0 +1,284 @@ +/* + * ALSA SoC OMAP ABE driver +* + * Author: Laurent Le Faucheur <l-le-faucheur@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ +#ifndef _ABE_CM_ADDR_H_ +#define _ABE_CM_ADDR_H_ +#define init_CM_ADDR 0 +#define init_CM_ADDR_END 309 +#define init_CM_sizeof 310 +#define C_Data_LSB_2_ADDR 310 +#define C_Data_LSB_2_ADDR_END 310 +#define C_Data_LSB_2_sizeof 1 +#define C_1_Alpha_ADDR 311 +#define C_1_Alpha_ADDR_END 328 +#define C_1_Alpha_sizeof 18 +#define C_Alpha_ADDR 329 +#define C_Alpha_ADDR_END 346 +#define C_Alpha_sizeof 18 +#define C_GainsWRamp_ADDR 347 +#define C_GainsWRamp_ADDR_END 360 +#define C_GainsWRamp_sizeof 14 +#define C_Gains_DL1M_ADDR 361 +#define C_Gains_DL1M_ADDR_END 364 +#define C_Gains_DL1M_sizeof 4 +#define C_Gains_DL2M_ADDR 365 +#define C_Gains_DL2M_ADDR_END 368 +#define C_Gains_DL2M_sizeof 4 +#define C_Gains_EchoM_ADDR 369 +#define C_Gains_EchoM_ADDR_END 370 +#define C_Gains_EchoM_sizeof 2 +#define C_Gains_SDTM_ADDR 371 +#define C_Gains_SDTM_ADDR_END 372 +#define C_Gains_SDTM_sizeof 2 +#define C_Gains_VxRecM_ADDR 373 +#define C_Gains_VxRecM_ADDR_END 376 +#define C_Gains_VxRecM_sizeof 4 +#define C_Gains_ULM_ADDR 377 +#define C_Gains_ULM_ADDR_END 380 +#define C_Gains_ULM_sizeof 4 +#define C_Gains_unused_ADDR 381 +#define C_Gains_unused_ADDR_END 382 +#define C_Gains_unused_sizeof 2 +#define C_SDT_Coefs_ADDR 383 +#define C_SDT_Coefs_ADDR_END 391 +#define C_SDT_Coefs_sizeof 9 +#define C_CoefASRC1_VX_ADDR 392 +#define C_CoefASRC1_VX_ADDR_END 410 +#define C_CoefASRC1_VX_sizeof 19 +#define C_CoefASRC2_VX_ADDR 411 +#define C_CoefASRC2_VX_ADDR_END 429 +#define C_CoefASRC2_VX_sizeof 19 +#define C_CoefASRC3_VX_ADDR 430 +#define C_CoefASRC3_VX_ADDR_END 448 +#define C_CoefASRC3_VX_sizeof 19 +#define C_CoefASRC4_VX_ADDR 449 +#define C_CoefASRC4_VX_ADDR_END 467 +#define C_CoefASRC4_VX_sizeof 19 +#define C_CoefASRC5_VX_ADDR 468 +#define C_CoefASRC5_VX_ADDR_END 486 +#define C_CoefASRC5_VX_sizeof 19 +#define C_CoefASRC6_VX_ADDR 487 +#define C_CoefASRC6_VX_ADDR_END 505 +#define C_CoefASRC6_VX_sizeof 19 +#define C_CoefASRC7_VX_ADDR 506 +#define C_CoefASRC7_VX_ADDR_END 524 +#define C_CoefASRC7_VX_sizeof 19 +#define C_CoefASRC8_VX_ADDR 525 +#define C_CoefASRC8_VX_ADDR_END 543 +#define C_CoefASRC8_VX_sizeof 19 +#define C_CoefASRC9_VX_ADDR 544 +#define C_CoefASRC9_VX_ADDR_END 562 +#define C_CoefASRC9_VX_sizeof 19 +#define C_CoefASRC10_VX_ADDR 563 +#define C_CoefASRC10_VX_ADDR_END 581 +#define C_CoefASRC10_VX_sizeof 19 +#define C_CoefASRC11_VX_ADDR 582 +#define C_CoefASRC11_VX_ADDR_END 600 +#define C_CoefASRC11_VX_sizeof 19 +#define C_CoefASRC12_VX_ADDR 601 +#define C_CoefASRC12_VX_ADDR_END 619 +#define C_CoefASRC12_VX_sizeof 19 +#define C_CoefASRC13_VX_ADDR 620 +#define C_CoefASRC13_VX_ADDR_END 638 +#define C_CoefASRC13_VX_sizeof 19 +#define C_CoefASRC14_VX_ADDR 639 +#define C_CoefASRC14_VX_ADDR_END 657 +#define C_CoefASRC14_VX_sizeof 19 +#define C_CoefASRC15_VX_ADDR 658 +#define C_CoefASRC15_VX_ADDR_END 676 +#define C_CoefASRC15_VX_sizeof 19 +#define C_CoefASRC16_VX_ADDR 677 +#define C_CoefASRC16_VX_ADDR_END 695 +#define C_CoefASRC16_VX_sizeof 19 +#define C_AlphaCurrent_UL_VX_ADDR 696 +#define C_AlphaCurrent_UL_VX_ADDR_END 696 +#define C_AlphaCurrent_UL_VX_sizeof 1 +#define C_BetaCurrent_UL_VX_ADDR 697 +#define C_BetaCurrent_UL_VX_ADDR_END 697 +#define C_BetaCurrent_UL_VX_sizeof 1 +#define C_AlphaCurrent_DL_VX_ADDR 698 +#define C_AlphaCurrent_DL_VX_ADDR_END 698 +#define C_AlphaCurrent_DL_VX_sizeof 1 +#define C_BetaCurrent_DL_VX_ADDR 699 +#define C_BetaCurrent_DL_VX_ADDR_END 699 +#define C_BetaCurrent_DL_VX_sizeof 1 +#define C_CoefASRC1_MM_ADDR 700 +#define C_CoefASRC1_MM_ADDR_END 717 +#define C_CoefASRC1_MM_sizeof 18 +#define C_CoefASRC2_MM_ADDR 718 +#define C_CoefASRC2_MM_ADDR_END 735 +#define C_CoefASRC2_MM_sizeof 18 +#define C_CoefASRC3_MM_ADDR 736 +#define C_CoefASRC3_MM_ADDR_END 753 +#define C_CoefASRC3_MM_sizeof 18 +#define C_CoefASRC4_MM_ADDR 754 +#define C_CoefASRC4_MM_ADDR_END 771 +#define C_CoefASRC4_MM_sizeof 18 +#define C_CoefASRC5_MM_ADDR 772 +#define C_CoefASRC5_MM_ADDR_END 789 +#define C_CoefASRC5_MM_sizeof 18 +#define C_CoefASRC6_MM_ADDR 790 +#define C_CoefASRC6_MM_ADDR_END 807 +#define C_CoefASRC6_MM_sizeof 18 +#define C_CoefASRC7_MM_ADDR 808 +#define C_CoefASRC7_MM_ADDR_END 825 +#define C_CoefASRC7_MM_sizeof 18 +#define C_CoefASRC8_MM_ADDR 826 +#define C_CoefASRC8_MM_ADDR_END 843 +#define C_CoefASRC8_MM_sizeof 18 +#define C_CoefASRC9_MM_ADDR 844 +#define C_CoefASRC9_MM_ADDR_END 861 +#define C_CoefASRC9_MM_sizeof 18 +#define C_CoefASRC10_MM_ADDR 862 +#define C_CoefASRC10_MM_ADDR_END 879 +#define C_CoefASRC10_MM_sizeof 18 +#define C_CoefASRC11_MM_ADDR 880 +#define C_CoefASRC11_MM_ADDR_END 897 +#define C_CoefASRC11_MM_sizeof 18 +#define C_CoefASRC12_MM_ADDR 898 +#define C_CoefASRC12_MM_ADDR_END 915 +#define C_CoefASRC12_MM_sizeof 18 +#define C_CoefASRC13_MM_ADDR 916 +#define C_CoefASRC13_MM_ADDR_END 933 +#define C_CoefASRC13_MM_sizeof 18 +#define C_CoefASRC14_MM_ADDR 934 +#define C_CoefASRC14_MM_ADDR_END 951 +#define C_CoefASRC14_MM_sizeof 18 +#define C_CoefASRC15_MM_ADDR 952 +#define C_CoefASRC15_MM_ADDR_END 969 +#define C_CoefASRC15_MM_sizeof 18 +#define C_CoefASRC16_MM_ADDR 970 +#define C_CoefASRC16_MM_ADDR_END 987 +#define C_CoefASRC16_MM_sizeof 18 +#define C_AlphaCurrent_MM_EXT_IN_ADDR 988 +#define C_AlphaCurrent_MM_EXT_IN_ADDR_END 988 +#define C_AlphaCurrent_MM_EXT_IN_sizeof 1 +#define C_BetaCurrent_MM_EXT_IN_ADDR 989 +#define C_BetaCurrent_MM_EXT_IN_ADDR_END 989 +#define C_BetaCurrent_MM_EXT_IN_sizeof 1 +#define C_DL2_L_Coefs_ADDR 990 +#define C_DL2_L_Coefs_ADDR_END 1014 +#define C_DL2_L_Coefs_sizeof 25 +#define C_DL2_R_Coefs_ADDR 1015 +#define C_DL2_R_Coefs_ADDR_END 1039 +#define C_DL2_R_Coefs_sizeof 25 +#define C_DL1_Coefs_ADDR 1040 +#define C_DL1_Coefs_ADDR_END 1064 +#define C_DL1_Coefs_sizeof 25 +#define C_SRC_3_LP_Coefs_ADDR 1065 +#define C_SRC_3_LP_Coefs_ADDR_END 1075 +#define C_SRC_3_LP_Coefs_sizeof 11 +#define C_SRC_3_LP_GAIN_Coefs_ADDR 1076 +#define C_SRC_3_LP_GAIN_Coefs_ADDR_END 1086 +#define C_SRC_3_LP_GAIN_Coefs_sizeof 11 +#define C_SRC_3_HP_Coefs_ADDR 1087 +#define C_SRC_3_HP_Coefs_ADDR_END 1091 +#define C_SRC_3_HP_Coefs_sizeof 5 +#define C_SRC_6_LP_Coefs_ADDR 1092 +#define C_SRC_6_LP_Coefs_ADDR_END 1102 +#define C_SRC_6_LP_Coefs_sizeof 11 +#define C_SRC_6_LP_GAIN_Coefs_ADDR 1103 +#define C_SRC_6_LP_GAIN_Coefs_ADDR_END 1113 +#define C_SRC_6_LP_GAIN_Coefs_sizeof 11 +#define C_SRC_6_HP_Coefs_ADDR 1114 +#define C_SRC_6_HP_Coefs_ADDR_END 1120 +#define C_SRC_6_HP_Coefs_sizeof 7 +#define C_APS_DL1_coeffs1_ADDR 1121 +#define C_APS_DL1_coeffs1_ADDR_END 1129 +#define C_APS_DL1_coeffs1_sizeof 9 +#define C_APS_DL1_M_coeffs2_ADDR 1130 +#define C_APS_DL1_M_coeffs2_ADDR_END 1132 +#define C_APS_DL1_M_coeffs2_sizeof 3 +#define C_APS_DL1_C_coeffs2_ADDR 1133 +#define C_APS_DL1_C_coeffs2_ADDR_END 1135 +#define C_APS_DL1_C_coeffs2_sizeof 3 +#define C_APS_DL2_L_coeffs1_ADDR 1136 +#define C_APS_DL2_L_coeffs1_ADDR_END 1144 +#define C_APS_DL2_L_coeffs1_sizeof 9 +#define C_APS_DL2_R_coeffs1_ADDR 1145 +#define C_APS_DL2_R_coeffs1_ADDR_END 1153 +#define C_APS_DL2_R_coeffs1_sizeof 9 +#define C_APS_DL2_L_M_coeffs2_ADDR 1154 +#define C_APS_DL2_L_M_coeffs2_ADDR_END 1156 +#define C_APS_DL2_L_M_coeffs2_sizeof 3 +#define C_APS_DL2_R_M_coeffs2_ADDR 1157 +#define C_APS_DL2_R_M_coeffs2_ADDR_END 1159 +#define C_APS_DL2_R_M_coeffs2_sizeof 3 +#define C_APS_DL2_L_C_coeffs2_ADDR 1160 +#define C_APS_DL2_L_C_coeffs2_ADDR_END 1162 +#define C_APS_DL2_L_C_coeffs2_sizeof 3 +#define C_APS_DL2_R_C_coeffs2_ADDR 1163 +#define C_APS_DL2_R_C_coeffs2_ADDR_END 1165 +#define C_APS_DL2_R_C_coeffs2_sizeof 3 +#define C_AlphaCurrent_ECHO_REF_ADDR 1166 +#define C_AlphaCurrent_ECHO_REF_ADDR_END 1166 +#define C_AlphaCurrent_ECHO_REF_sizeof 1 +#define C_BetaCurrent_ECHO_REF_ADDR 1167 +#define C_BetaCurrent_ECHO_REF_ADDR_END 1167 +#define C_BetaCurrent_ECHO_REF_sizeof 1 +#define C_APS_DL1_EQ_ADDR 1168 +#define C_APS_DL1_EQ_ADDR_END 1176 +#define C_APS_DL1_EQ_sizeof 9 +#define C_APS_DL2_L_EQ_ADDR 1177 +#define C_APS_DL2_L_EQ_ADDR_END 1185 +#define C_APS_DL2_L_EQ_sizeof 9 +#define C_APS_DL2_R_EQ_ADDR 1186 +#define C_APS_DL2_R_EQ_ADDR_END 1194 +#define C_APS_DL2_R_EQ_sizeof 9 +#define C_Vibra2_consts_ADDR 1195 +#define C_Vibra2_consts_ADDR_END 1198 +#define C_Vibra2_consts_sizeof 4 +#define C_Vibra1_coeffs_ADDR 1199 +#define C_Vibra1_coeffs_ADDR_END 1209 +#define C_Vibra1_coeffs_sizeof 11 +#define C_48_96_LP_Coefs_ADDR 1210 +#define C_48_96_LP_Coefs_ADDR_END 1224 +#define C_48_96_LP_Coefs_sizeof 15 +#define C_96_48_AMIC_Coefs_ADDR 1225 +#define C_96_48_AMIC_Coefs_ADDR_END 1243 +#define C_96_48_AMIC_Coefs_sizeof 19 +#define C_96_48_DMIC_Coefs_ADDR 1244 +#define C_96_48_DMIC_Coefs_ADDR_END 1262 +#define C_96_48_DMIC_Coefs_sizeof 19 +#define C_INPUT_SCALE_ADDR 1263 +#define C_INPUT_SCALE_ADDR_END 1263 +#define C_INPUT_SCALE_sizeof 1 +#define C_OUTPUT_SCALE_ADDR 1264 +#define C_OUTPUT_SCALE_ADDR_END 1264 +#define C_OUTPUT_SCALE_sizeof 1 +#define C_MUTE_SCALING_ADDR 1265 +#define C_MUTE_SCALING_ADDR_END 1265 +#define C_MUTE_SCALING_sizeof 1 +#define C_GAINS_0DB_ADDR 1266 +#define C_GAINS_0DB_ADDR_END 1267 +#define C_GAINS_0DB_sizeof 2 +#define C_AlphaCurrent_BT_UL_ADDR 1268 +#define C_AlphaCurrent_BT_UL_ADDR_END 1268 +#define C_AlphaCurrent_BT_UL_sizeof 1 +#define C_BetaCurrent_BT_UL_ADDR 1269 +#define C_BetaCurrent_BT_UL_ADDR_END 1269 +#define C_BetaCurrent_BT_UL_sizeof 1 +#define C_AlphaCurrent_BT_DL_ADDR 1270 +#define C_AlphaCurrent_BT_DL_ADDR_END 1270 +#define C_AlphaCurrent_BT_DL_sizeof 1 +#define C_BetaCurrent_BT_DL_ADDR 1271 +#define C_BetaCurrent_BT_DL_ADDR_END 1271 +#define C_BetaCurrent_BT_DL_sizeof 1 +#endif/* _ABECM_ADDR_H_ */ |