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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into linaro-2.6.38
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Fix number of CPUs for OMAP4
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This patchset adds support for OMAP4 MPU DVFS with following changes
- add vdd information for omap4
- enable all relevant OPPs for MPU VDD
- define and register get_rate and set_rate with DVFS layer
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This patch adds support for DVFS in cpufreq driver by replacing clock api with
DVFS api.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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On OMAP SMP configuartion, both processors share the voltage
and clock. So both CPUs needs to be scaled together and hence
needs software co-ordination.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
cc: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This patch is an attempt to cleanup the #ifdeferry in the
omap cpufreq drivers.
The split betwenn omap1 and omap2plus is logical because
- omap1 doesn't support opp layer.
- omap1 build is seperate from omap2plus.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Add an alias clock node for cpu clock control on all OMAP2PLUS devices.
The intention is avoid cpu_is_xxxx() checks in the common cpufreq driver.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This reverts commit de1c81cf2d50cba25e3ed399d3fe6c412781827f since there is
another patch set for omap cpufreq changes at
https://patchwork.kernel.org/patch/589081/
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This patch has changes to update the C state latencies for OMAP3630 and
disables the useless C-States, keeping only the optimized ones with their
corresponding measured latencies. Only 4 C-states are kept instead of 7
C-States:
* C1 . MPU WFI clock gated + Core autogating
* C3 . MPU CSWR + Core inactive
* C5 . MPU CSWR + Core CSWR
* C7 . MPU OFF + Core OFF
Thanks to Nicole Chaloub<n-chalhoub@ti.com> and Vincent Bour <v-bour@ti.com>
for their investigation.
Tested on ZOOM3 board using latest pm branch.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Currently function omap3_cpuidle_update_states updates valid flag of all the C
states which includes the one which are disabled at init. So it's not really
possible to selectively disable some of the C states using valid flag.
This is fixed now by adding another flag called enabled which will be
initialized at omap_init_power_states. So update_states will operated only on
enabled C states.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Currently clock gating for MPU and core are denied whenever C1 state is
selected. It should be denied only when safe state is selected.
Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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Various binutils versions can resolve Thumb-2 branches to
locally-defined, preemptible global symbols as short-range "b.n"
branch instructions.
This is a problem, because there's no guarantee the final
destination of the symbol, or any candidate locations for a
trampoline, are within range of the branch. For this reason, the
kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
relocation in modules at all, and it makes little sense to add
support.
The symptom is that the kernel fails with an "unsupported
relocation" error when loading some modules.
Until fixed tools are available, passing
-fno-optimize-sibling-calls to gcc should prevent gcc generating
code which hits this problem, at the cost of a bit of extra runtime
stack usage in some cases.
The problem is described in more detail at:
https://bugs.launchpad.net/binutils-linaro/+bug/725126
Only Thumb-2 kernels are affected.
This patch adds a new CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 config
option which adds -fno-optimize-sibling-calls to CFLAGS_MODULE
when building a Thumb-2 kernel.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into fixes
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Since f0fba2ad1b it's required to register platform devices even for
AC'97 codecs. Register one on tosa (wm9712-codec).
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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pxa25x platforms were left out of major ASoC Update patch.
Since f0fba2ad1b a registration of pxa-pcm-audio device is required for
ASoC to function on pxa platforms. Register one also for pxa210/pxa25x.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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PXA supports multi-machine kernels since long ago. However a kernel
compiled with support for colibri and any other PXA machine and with
PCMCIA enabled will barf at runtime about duplicate registration of
pxa2xx-pcmcia device. Fix that.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Since 2e48928d8a0f38c1b5c81eb3f1294de8a6382c68 it's no longer possible to set
the name of the LED trigger for RFKILL events. Drop respective code from tosa-bt.c
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Stephen Hemminger <shemminger@vyatta.com>
Cc: John W. Linville <linville@tuxdriver.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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We currently presume a 4x expansion to guess the decompressed kernel size
in order to determine if the decompressed kernel is in conflict with
the location where zImage is loaded. This guess may cause many issues
by overestimating the final kernel image size:
- This may force a needless relocation if the location of zImage was
fine, wasting some precious microseconds of boot time.
- The relocation may be located way too far, possibly overwriting the
initrd image in RAM.
- If the kernel image includes a large already-compressed initramfs image
then the problem is even more exacerbated.
And if by some strange means the 4x guess is too low then we may overwrite
ourselves with the decompressed image.
So let's use the exact decompressed kernel image size instead. For that
we need to rely on the stat command, but this is hardly a new build
dependency as the kernel already depends on many external commands
to be built provided by the coreutils package where stat is found.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The S5P6442 and S5PC100 SoCs have 4 VICs. However, default VIC number
is defined 2 in arch/arm/common. So can be happened some problem on it.
Basically, it requires for suspend and resume.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The S5PV210 SoC have 4 VICs. It requires for suspend and resume.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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ARMv7 allows the debug core logic to be powered down and provides the
DBGPRSR register so that software can power-up and check the status of
the logic.
This patch ensures that the debug logic is powered up on ARMv7 cores
before we attempt to access the extended debug registers.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The GETHBPREGS ptrace request incorrectly maps its index argument onto
the thread's saved debug state when the index != 0. This has not yet
been seen from userspace because GDB (the only user of this request)
only reads from register 0.
This patch fixes the indexing.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Since commit 6fc31d54 this comment is no longer true.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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devel-fixes
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CPU0 and CPU1 clockdomain is at the offset of 0x18 from the LPRM base.
The header file has set it wrongly to 0x0. Offset 0x0 is for CPUx power
domain control register
Fix the same.
The autogen scripts is fixed thanks to Benoit Cousson
With the old value, the clockdomain code would access the
*_PWRSTCTRL.POWERSTATE field when it thought it was accessing the
*_CLKSTCTRL.CLKTRCTRL field. In the worst case, this could cause
system power management to behave incorrectly.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
[paul@pwsan.com: added second paragraph to commit message]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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OMAP2+ kernels built without CONFIG_OMAP_32K_TIMER crash on boot after the
2.6.38 sched_clock changes:
[ 0.000000] OMAP clockevent source: GPTIMER1 at 13000000 Hz
[ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[ 0.000000] pgd = c0004000
[ 0.000000] [00000000] *pgd=00000000
[ 0.000000] Internal error: Oops: 80000005 [#1] SMP
[ 0.000000] last sysfs file:
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (2.6.38-rc5-00057-g04aa67d #152)
[ 0.000000] PC is at 0x0
[ 0.000000] LR is at sched_clock_poll+0x2c/0x3c
Without CONFIG_OMAP_32K_TIMER, the kernel has an clockevent and
clocksource resolution about three orders of magnitude higher than
with CONFIG_OMAP_32K_TIMER set. The tradeoff is that the lowest
power consumption states are not available.
Fix by calling init_sched_clock() from the GPTIMER clocksource init code.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Most suspend/resume code depends on CONFIG_PM. This causes problems
if one wants to enable Runtime PM (to control power domains for example),
but doesn't need system suspend/resume feature. This also enables to use
Runtime PM feature on S5PV310 which doesn't implement system suspend/resume
callbacks yet.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Amit Daniel Kachhap <amit.kachhap@linaro.org>
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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git://git.secretlab.ca/git/linux-2.6 into linaro-2.6.38
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In the case of a conflict between the memory used by the compressed
kernel with its decompressor code and the memory used for the
decompressed kernel, we currently store the later after the former and
relocate it afterwards.
This would be more efficient to do this the other way around i.e.
relocate the compressed data up front instead, resulting in a smaller
copy. That also has the advantage of making the code smaller and more
straight forward.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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PTRACE_SINGLESTEP is a ptrace request designed to offer single-stepping
support to userspace when the underlying architecture has hardware
support for this operation.
On ARM, we set arch_has_single_step() to 1 and attempt to emulate hardware
single-stepping by disassembling the current instruction to determine the
next pc and placing a software breakpoint on that location.
Unfortunately this has the following problems:
1.) Only a subset of ARMv7 instructions are supported
2.) Thumb-2 is unsupported
3.) The code is not SMP safe
We could try to fix this code, but it turns out that because of the above
issues it is rarely used in practice. GDB, for example, uses PTRACE_POKETEXT
and PTRACE_PEEKTEXT to manage breakpoints itself and does not require any
kernel assistance.
This patch removes the single-step emulation code from ptrace meaning that
the PTRACE_SINGLESTEP request will return -EIO on ARM. Portable code must
check the return value from a ptrace call and handle the failure gracefully.
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Move L1_CACHE_SHIFT related options together, rather than spreading them
across two separate Kconfig files.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Some installers would binary patch the kernel zImage to replace the
first few nops with custom instructions. This breaks the Thumb2 kernel
as the mode switch is right at the beginning. Let's move it towards the
end of the nop sequence instead.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Improve the documentation for the VFP hotplug notifier handler, so
that people better understand what's going on there and what has
been done for them.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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In commit e616c591405c168f6dc3dfd1221e105adfe49b8d, highmem support was
deactivated for SMP platforms without hardware TLB ops broadcast because
usage of kmap_high_get() requires that IRQs be disabled when kmap_lock
is locked which is incompatible with the IPI mechanism used by the
software TLB ops broadcast invoked through flush_all_zero_pkmaps().
The reason for kmap_high_get() is to ensure that the currently kmap'd
page usage count does not decrease to zero while we're using its
existing virtual mapping in an atomic context. With a VIVT cache this
is essential to do due to cache coherency issues, but with a VIPT cache
this is only an optimization so not to pay the price of establishing a
second mapping if an existing one can be used. However, on VIPT
platforms without hardware TLB maintenance we can give up on that
optimization in order to be able to use highmem.
From ARMv7 onwards the TLB ops are broadcasted in hardware, so let's
disable ARCH_NEEDS_KMAP_HIGH_GET only when CONFIG_SMP and
CONFIG_CPU_TLB_V6 are defined.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Saeed Bishara <saeed.bishara@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This cleans up after the conversion to irq_data. Rename the function
to match the method, and remove the now useless lookup of the irq
descriptor which is never used. Move the bitmask calculation out of
the irq_controller_lock region.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Ensure appropriate locks are taken to ensure that IRQ migration off
the current CPU is race-free. We may have a concurrent set_affinity
via procfs running on another CPU in parallel with the IRQ migration,
resulting in unpredictable results.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The force argument to irq_set_affinity really should be 'true' as
moving IRQs off a CPU which is going down isn't optional.
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Add a missing call to pci_enable_bridges() so that devices behind
bridges get found by the pci bus scan.
Signed-off-by: Chris Partington <chris.partington@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Current diagnostics are rather poor when things go wrong:
ipv6: relocation out of range, section 2 reloc 0 sym 'snmp_mib_free'
Let's include a little more information about the problem:
ipv6: section 2 reloc 0 sym 'snmp_mib_free': relocation 28 out of range (0xbf0000a4 -> 0xc11b4858)
so that we show exactly what the problem is - not only what type of
relocation but also the offending address range too.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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We have 'install' and 'zinstall' for installing Image and zImage
kernels, so add 'uinstall' to complete the set.
This allows developers to have a ~/bin/installkernel script which (eg)
copies the kernel to the tftp server automatically once the kernel
has built, resulting in a better workflow.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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arch/arm/kernel/return_address.c:37:6: warning: symbol 'return_address' was not declared. Should it be static?
arch/arm/kernel/setup.c:76:14: warning: symbol 'processor_id' was not declared. Should it be static?
arch/arm/kernel/traps.c:259:1: warning: symbol 'die_lock' was not declared. Should it be static?
arch/arm/vfp/vfpmodule.c:156:6: warning: symbol 'vfp_raise_sigfpe' was not declared. Should it be static?
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Achieve better usage of the DMA coherent region by doing top-down
allocation rather than bottom up. If we ask for a 128kB allocation,
this will be aligned to 128kB and satisfied from the very bottom
address. If we then ask for a 600kB allocation, this will be aligned
to 1MB, and we will have a 896kB hole.
Performing top-down allocation resolves this by allocating the 128kB
at the very top, and then the 600kB can come in below it without any
unnecessary wastage.
This problem was reported by Janusz Krzysztofik, who had 2 x 128kB +
1 x 640kB allocations which wouldn't fit into 1MB.
Tested-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Commit
06824ba (ARM: tlb: delay page freeing for SMP and ARMv7 CPUs)
introduced a build failure for builds with CONFIG_SWAP=n:
In file included from arch/arm/mm/init.c:27:
arch/arm/include/asm/tlb.h: In function 'tlb_flush_mmu':
arch/arm/include/asm/tlb.h:101: error: implicit declaration of function 'release_pages'
arch/arm/include/asm/tlb.h: In function 'tlb_remove_page':
arch/arm/include/asm/tlb.h:165: error: implicit declaration of function 'page_cache_release'
as linux/swap.h doesn't include linux/pagemap.h but actually needs it
(see comments in linux/swap.h as to why this is.)
Fix that by #including <linux/pagemap.h> in <asm/pgalloc.h> as it's done
by x86.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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git://git.linaro.org/people/dmart/linux-2.6-arm into linaro-2.6.38
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Loading Thumb-2 modules into an ARM kernel or vice-versa isn't
guaranteed to work safely, since the kernel is not interworking-
aware everywhere.
This patch adds "thumb2" to the module vermagic when
CONFIG_THUMB2_KERNEL is enabled, to help avoid accidental loading
of modules into the wrong kernel.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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