From 2c82676cdc339dc5d70b94771c700db4fd3aad36 Mon Sep 17 00:00:00 2001 From: Michel JAOUEN Date: Thu, 26 Jan 2012 10:20:53 +0100 Subject: mach-ux500 : 9540 prcmu dump, context ST-Ericsson ID: 409625 Signed-off-by: Guillaume Kouadio Carry Signed-off-by: Alex MACRO Signed-off-by: David Paris Signed-off-by: Michel JAOUEN --- arch/arm/mach-ux500/include/mach/context.h | 3 + arch/arm/mach-ux500/include/mach/prcmu-debug.h | 4 +- arch/arm/mach-ux500/pm/Makefile | 2 +- arch/arm/mach-ux500/pm/context-db9540.c | 651 +++++++++++++++++++++++++ arch/arm/mach-ux500/pm/context.c | 27 +- 5 files changed, 678 insertions(+), 9 deletions(-) create mode 100644 arch/arm/mach-ux500/pm/context-db9540.c diff --git a/arch/arm/mach-ux500/include/mach/context.h b/arch/arm/mach-ux500/include/mach/context.h index 22b56351284..6975a69eddc 100644 --- a/arch/arm/mach-ux500/include/mach/context.h +++ b/arch/arm/mach-ux500/include/mach/context.h @@ -73,6 +73,9 @@ void u5500_context_save_icn(void); void u5500_context_restore_icn(void); void u5500_context_init(void); +void u9540_context_save_icn(void); +void u9540_context_restore_icn(void); +void u9540_context_init(void); #else static inline void context_varm_save_core(void) {} diff --git a/arch/arm/mach-ux500/include/mach/prcmu-debug.h b/arch/arm/mach-ux500/include/mach/prcmu-debug.h index 8a5be350147..df71df49f2d 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu-debug.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-debug.h @@ -14,13 +14,13 @@ #ifdef CONFIG_DBX500_PRCMU_DEBUG void prcmu_debug_ape_opp_log(u8 opp); void prcmu_debug_ddr_opp_log(u8 opp); -void prcmu_debug_arm_opp_log(u8 opp); +void prcmu_debug_arm_opp_log(u32 value); void prcmu_debug_dump_data_mem(void); void prcmu_debug_dump_regs(void); #else static inline void prcmu_debug_ape_opp_log(u8 opp) {} static inline void prcmu_debug_ddr_opp_log(u8 opp) {} -static inline void prcmu_debug_arm_opp_log(u8 opp) {} +static inline void prcmu_debug_arm_opp_log(u32 value) {} static inline void prcmu_debug_dump_data_mem(void) {} static inline void prcmu_debug_dump_regs(void) {} #endif diff --git a/arch/arm/mach-ux500/pm/Makefile b/arch/arm/mach-ux500/pm/Makefile index c0af28e5d3e..ef33bdf0d4e 100644 --- a/arch/arm/mach-ux500/pm/Makefile +++ b/arch/arm/mach-ux500/pm/Makefile @@ -4,7 +4,7 @@ obj-y := pm.o runtime.o obj-$(CONFIG_DBX500_PRCMU_QOS_POWER) += prcmu-qos-power.o -obj-$(CONFIG_UX500_CONTEXT) += context.o context_arm.o context-db8500.o context-db5500.o +obj-$(CONFIG_UX500_CONTEXT) += context.o context_arm.o context-db8500.o context-db5500.o context-db9540.o obj-$(CONFIG_UX500_CPUIDLE) += timer.o obj-$(CONFIG_UX500_SUSPEND) += suspend.o obj-$(CONFIG_UX500_SUSPEND_DBG) += suspend_dbg.o diff --git a/arch/arm/mach-ux500/pm/context-db9540.c b/arch/arm/mach-ux500/pm/context-db9540.c new file mode 100644 index 00000000000..8d8aaeb9d8f --- /dev/null +++ b/arch/arm/mach-ux500/pm/context-db9540.c @@ -0,0 +1,651 @@ +/* + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010-2011 + * + * License Terms: GNU General Public License v2 + * Author: Sundar Iyer for ST-Ericsson + * + */ + +#include + +#include +#include + +/* + * ST-Interconnect context + */ + +/* priority, bw limiter register offsets */ +#define NODE_HIBW1_ESRAM_IN_0_PRIORITY 0x00 +#define NODE_HIBW1_ESRAM_IN_1_PRIORITY 0x04 +#define NODE_HIBW1_ESRAM_IN_2_PRIORITY 0x08 +#define NODE_HIBW1_ESRAM_IN_3_PRIORITY 0x0C +#define NODE_HIBW1_ESRAM_IN_0_ARB_1_LIMIT 0x30 +#define NODE_HIBW1_ESRAM_IN_0_ARB_2_LIMIT 0x34 +#define NODE_HIBW1_ESRAM_IN_0_ARB_3_LIMIT 0x38 +#define NODE_HIBW1_ESRAM_IN_1_ARB_1_LIMIT 0x3C +#define NODE_HIBW1_ESRAM_IN_1_ARB_2_LIMIT 0x40 +#define NODE_HIBW1_ESRAM_IN_1_ARB_3_LIMIT 0x44 +#define NODE_HIBW1_ESRAM_IN_2_ARB_1_LIMIT 0x48 +#define NODE_HIBW1_ESRAM_IN_2_ARB_2_LIMIT 0x4C +#define NODE_HIBW1_ESRAM_IN_2_ARB_3_LIMIT 0x50 +#define NODE_HIBW1_ESRAM_IN_3_ARB_1_LIMIT 0x54 +#define NODE_HIBW1_ESRAM_IN_3_ARB_2_LIMIT 0x58 +#define NODE_HIBW1_ESRAM_IN_3_ARB_3_LIMIT 0x5C +#define NODE_HIBW1_DDR0_IN_0_PRIORITY 0x400 +#define NODE_HIBW1_DDR0_IN_1_PRIORITY 0x404 +#define NODE_HIBW1_DDR0_IN_2_PRIORITY 0x408 +#define NODE_HIBW1_DDR0_IN_3_PRIORITY 0x40C +#define NODE_HIBW1_DDR0_IN_0_LIMIT 0x430 +#define NODE_HIBW1_DDR0_IN_1_LIMIT 0x434 +#define NODE_HIBW1_DDR0_IN_2_LIMIT 0x438 +#define NODE_HIBW1_DDR0_IN_3_LIMIT 0x43C +#define NODE_HIBW1_DDR0_OUT_0_PRIORITY 0x440 +#define NODE_HIBW2_ESRAM_IN_0_PRIORITY 0x800 +#define NODE_HIBW2_ESRAM_IN_1_PRIORITY 0x804 +#define NODE_HIBW2_ESRAM_IN_0_ARB_1_LIMIT 0x818 +#define NODE_HIBW2_ESRAM_IN_0_ARB_2_LIMIT 0x81C +#define NODE_HIBW2_ESRAM_IN_0_ARB_3_LIMIT 0x820 +#define NODE_HIBW2_ESRAM_IN_1_ARB_1_LIMIT 0x824 +#define NODE_HIBW2_ESRAM_IN_1_ARB_2_LIMIT 0x828 +#define NODE_HIBW2_ESRAM_IN_1_ARB_3_LIMIT 0x82C + +#define NODE_HIBW2_DDR0_IN_0_PRIORITY 0xC00 +#define NODE_HIBW2_DDR0_IN_1_PRIORITY 0xC04 + +#define NODE_HIBW2_DDR0_IN_0_LIMIT 0xC18 +#define NODE_HIBW2_DDR0_IN_1_LIMIT 0xC1C + +#define NODE_HIBW2_DDR0_OUT_0_PRIORITY 0xC20 + +/* + * Note the following addresses are presented in + * db8500 design spec v3.1 and v3.3, table 10. + * But their addresses are not the same as in the + * description. The addresses in the description + * of each registers are correct. + * NODE_HIBW2_DDR_IN_3_LIMIT is only present in v1. + * + * Faulty registers addresses in table 10: + * NODE_HIBW2_DDR_IN_2_LIMIT 0xC38 + * NODE_HIBW2_DDR_IN_3_LIMIT 0xC3C + * NODE_HIBW2_DDR_OUT_0_PRIORITY 0xC40 + */ + +#define NODE_ESRAM0_IN_0_PRIORITY 0x1000 +#define NODE_ESRAM0_IN_1_PRIORITY 0x1004 +#define NODE_ESRAM0_IN_2_PRIORITY 0x1008 +#define NODE_ESRAM0_IN_3_PRIORITY 0x100C +#define NODE_ESRAM0_IN_0_LIMIT 0x1030 +#define NODE_ESRAM0_IN_1_LIMIT 0x1034 +#define NODE_ESRAM0_IN_2_LIMIT 0x1038 +#define NODE_ESRAM0_IN_3_LIMIT 0x103C +#define NODE_ESRAM0_OUT_0_PRIORITY 0x1040 + +/* common */ +#define NODE_ESRAM1_2_IN_0_PRIORITY 0x1400 +#define NODE_ESRAM1_2_IN_1_PRIORITY 0x1404 +#define NODE_ESRAM1_2_IN_2_PRIORITY 0x1408 +#define NODE_ESRAM1_2_IN_3_PRIORITY 0x140C +#define NODE_ESRAM1_2_IN_0_ARB_1_LIMIT 0x1430 +#define NODE_ESRAM1_2_IN_0_ARB_2_LIMIT 0x1434 +#define NODE_ESRAM1_2_IN_1_ARB_1_LIMIT 0x1438 +#define NODE_ESRAM1_2_IN_1_ARB_2_LIMIT 0x143C +#define NODE_ESRAM1_2_IN_2_ARB_1_LIMIT 0x1440 +#define NODE_ESRAM1_2_IN_2_ARB_2_LIMIT 0x1444 +#define NODE_ESRAM1_2_IN_3_ARB_1_LIMIT 0x1448 +#define NODE_ESRAM1_2_IN_3_ARB_2_LIMIT 0x144C + +#define NODE_ESRAM3_4_IN_0_PRIORITY 0x1800 +#define NODE_ESRAM3_4_IN_1_PRIORITY 0x1804 +#define NODE_ESRAM3_4_IN_2_PRIORITY 0x1808 +#define NODE_ESRAM3_4_IN_3_PRIORITY 0x180C +#define NODE_ESRAM3_4_IN_0_ARB_1_LIMIT 0x1830 +#define NODE_ESRAM3_4_IN_0_ARB_2_LIMIT 0x1834 +#define NODE_ESRAM3_4_IN_1_ARB_1_LIMIT 0x1838 +#define NODE_ESRAM3_4_IN_1_ARB_2_LIMIT 0x183C +#define NODE_ESRAM3_4_IN_2_ARB_1_LIMIT 0x1840 +#define NODE_ESRAM3_4_IN_2_ARB_2_LIMIT 0x1844 +#define NODE_ESRAM3_4_IN_3_ARB_1_LIMIT 0x1848 +#define NODE_ESRAM3_4_IN_3_ARB_2_LIMIT 0x184C + +#define NODE_HIBW1_DDR1_IN_0_PRIORITY_REG 0x1C00 +#define NODE_HIBW1_DDR1_IN_1_PRIORITY_REG 0x1C04 +#define NODE_HIBW1_DDR1_IN_2_PRIORITY_REG 0x1C08 +#define NODE_HIBW1_DDR1_IN_3_PRIORITY_REG 0x1C0C + +#define NODE_HIBW1_DDR1_IN_0_LIMIT_REG 0x1C30 +#define NODE_HIBW1_DDR1_IN_1_LIMIT_REG 0x1C34 +#define NODE_HIBW1_DDR1_IN_2_LIMIT_REG 0x1C38 +#define NODE_HIBW1_DDR1_IN_3_LIMIT_REG 0x1C3C + +#define NODE_HIBW1_DDR1_OUT_0_PRIORITY_REG 0x1C40 + +#define NODE_HIBW2_DDR1_IN_0_PRIORITY_REG 0x2000 +#define NODE_HIBW2_DDR1_IN_1_PRIORITY_REG 0x2004 + +#define NODE_HIBW2_DDR1_IN_0_LIMIT_REG 0x2018 +#define NODE_HIBW2_DDR1_IN_1_LIMIT_REG 0x201C +#define NODE_HIBW2_DDR1_OUT_0_PRIORITY_REG 0x2020 +#define NODE_DDR_AWQOS_DSP_DDR0_REG 0x340C +#define NODE_DDR_AWQOS_DSP_DDR1_REG 0x3400 +#define NODE_DDR_ARQOS_DSP_DDR0_REG 0x3408 +#define NODE_DDR_ARQOS_DSP_DDR1_REG 0x3404 +#define NODE_DDR_AWQOS_ARM_DDR_REG 0x3410 +#define NODE_DDR_ARQOS_ARM_DDR_REG 0x3414 +#define NODE_SGA_AWQOS_DDR0_HIBW2_REG 0x3418 +#define NODE_SGA_ARQOS_DDR0_HIBW2_REG 0x341C +#define NODE_SGA_AWQOS_SGA_HIBW2_REG 0x3420 +#define NODE_SGA_ARQOS_SGA_HIBW2_REG 0x3424 + +static struct { + void __iomem *base; + u32 hibw1_esram_in_pri[4]; + u32 hibw1_esram_in0_arb[3]; + u32 hibw1_esram_in1_arb[3]; + u32 hibw1_esram_in2_arb[3]; + u32 hibw1_esram_in3_arb[3]; + u32 hibw1_ddr0_in_prio[4]; + u32 hibw1_ddr0_in_limit[4]; + u32 hibw1_ddr0_out_prio; + u32 hibw1_ddr1_in_prio[4]; + u32 hibw1_ddr1_in_limit[4]; + u32 hibw1_ddr1_out_prio; + + /* HiBw2 node registers */ + u32 hibw2_esram_in_pri[2]; + u32 hibw2_esram_in0_arblimit[3]; + u32 hibw2_esram_in1_arblimit[3]; + u32 hibw2_ddr0_in_prio[2]; + u32 hibw2_ddr0_in_limit[2]; + u32 hibw2_ddr0_out_prio; + u32 hibw2_ddr1_in_prio[2]; + u32 hibw2_ddr1_in_limit[2]; + u32 hibw2_ddr1_out_prio; + + /* ESRAM node registers */ + u32 esram0_in_prio[4]; + u32 esram0_in_lim[4]; + u32 esram0_out_prio; + u32 esram12_in_prio[4]; + u32 esram12_in_arb_lim[8]; + u32 esram34_in_prio[4]; + u32 esram34_in_arb_lim[8]; + + u32 ddr_awqos_dsp_ddr0; + u32 ddr_awqos_dsp_ddr1; + u32 ddr_arqos_dsp_ddr0; + u32 ddr_arqos_dsp_ddr1; + u32 ddr_awqos_arm_ddr; + u32 ddr_arqos_arm_ddr; + + u32 sga_awqos_ddr0_hibw2; + u32 sga_arqos_ddr0_hibw2; + + u32 sga_awqos_sga_hibw2; + u32 sga_arqos_sga_hibw2; +} context_icn; + +/** + * u8500_context_save_icn() - save ICN context + * + */ +void u9540_context_save_icn(void) +{ + void __iomem *b = context_icn.base; + + context_icn.hibw1_esram_in_pri[0] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_0_PRIORITY); + context_icn.hibw1_esram_in_pri[1] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_1_PRIORITY); + context_icn.hibw1_esram_in_pri[2] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_2_PRIORITY); + context_icn.hibw1_esram_in_pri[3] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_3_PRIORITY); + + context_icn.hibw1_esram_in0_arb[0] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_0_ARB_1_LIMIT); + context_icn.hibw1_esram_in0_arb[1] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_0_ARB_2_LIMIT); + context_icn.hibw1_esram_in0_arb[2] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_0_ARB_3_LIMIT); + + context_icn.hibw1_esram_in1_arb[0] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_1_ARB_1_LIMIT); + context_icn.hibw1_esram_in1_arb[1] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_1_ARB_2_LIMIT); + context_icn.hibw1_esram_in1_arb[2] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_1_ARB_3_LIMIT); + + context_icn.hibw1_esram_in2_arb[0] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_2_ARB_1_LIMIT); + context_icn.hibw1_esram_in2_arb[1] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_2_ARB_2_LIMIT); + context_icn.hibw1_esram_in2_arb[2] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_2_ARB_3_LIMIT); + + context_icn.hibw1_esram_in3_arb[0] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_3_ARB_1_LIMIT); + context_icn.hibw1_esram_in3_arb[1] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_3_ARB_2_LIMIT); + context_icn.hibw1_esram_in3_arb[2] = + readl_relaxed(b + NODE_HIBW1_ESRAM_IN_3_ARB_3_LIMIT); + + context_icn.hibw1_ddr0_in_prio[0] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_0_PRIORITY); + context_icn.hibw1_ddr0_in_prio[1] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_1_PRIORITY); + context_icn.hibw1_ddr0_in_prio[2] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_2_PRIORITY); + context_icn.hibw1_ddr0_in_prio[3] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_3_PRIORITY); + + context_icn.hibw1_ddr0_in_limit[0] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_0_LIMIT); + context_icn.hibw1_ddr0_in_limit[1] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_1_LIMIT); + context_icn.hibw1_ddr0_in_limit[2] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_2_LIMIT); + context_icn.hibw1_ddr0_in_limit[3] = + readl_relaxed(b + NODE_HIBW1_DDR0_IN_3_LIMIT); + + context_icn.hibw1_ddr0_out_prio = + readl_relaxed(b + NODE_HIBW1_DDR0_OUT_0_PRIORITY); + + context_icn.hibw1_ddr1_in_prio[0] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_0_PRIORITY_REG); + context_icn.hibw1_ddr1_in_prio[1] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_1_PRIORITY_REG); + context_icn.hibw1_ddr1_in_prio[2] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_2_PRIORITY_REG); + context_icn.hibw1_ddr1_in_prio[3] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_3_PRIORITY_REG); + + context_icn.hibw1_ddr1_in_limit[0] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_0_LIMIT_REG); + context_icn.hibw1_ddr1_in_limit[1] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_1_LIMIT_REG); + context_icn.hibw1_ddr1_in_limit[2] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_2_LIMIT_REG); + context_icn.hibw1_ddr1_in_limit[3] = + readl_relaxed(b + NODE_HIBW1_DDR1_IN_3_LIMIT_REG); + + context_icn.hibw1_ddr1_out_prio = + readl_relaxed(b + NODE_HIBW1_DDR1_OUT_0_PRIORITY_REG); + + context_icn.hibw2_esram_in_pri[0] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_0_PRIORITY); + context_icn.hibw2_esram_in_pri[1] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_1_PRIORITY); + + context_icn.hibw2_esram_in0_arblimit[0] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_0_ARB_1_LIMIT); + context_icn.hibw2_esram_in0_arblimit[1] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_0_ARB_2_LIMIT); + context_icn.hibw2_esram_in0_arblimit[2] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_0_ARB_3_LIMIT); + + context_icn.hibw2_esram_in1_arblimit[0] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_1_ARB_1_LIMIT); + context_icn.hibw2_esram_in1_arblimit[1] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_1_ARB_2_LIMIT); + context_icn.hibw2_esram_in1_arblimit[2] = + readl_relaxed(b + NODE_HIBW2_ESRAM_IN_1_ARB_3_LIMIT); + + context_icn.hibw2_ddr0_in_prio[0] = + readl_relaxed(b + NODE_HIBW2_DDR0_IN_0_PRIORITY); + context_icn.hibw2_ddr0_in_prio[1] = + readl_relaxed(b + NODE_HIBW2_DDR0_IN_1_PRIORITY); + + context_icn.hibw2_ddr0_in_limit[0] = + readl_relaxed(b + NODE_HIBW2_DDR0_IN_0_LIMIT); + context_icn.hibw2_ddr0_in_limit[1] = + readl_relaxed(b + NODE_HIBW2_DDR0_IN_1_LIMIT); + + context_icn.hibw2_ddr0_out_prio = + readl_relaxed(b + NODE_HIBW2_DDR0_OUT_0_PRIORITY); + + context_icn.hibw2_ddr1_in_prio[0] = + readl_relaxed(b + NODE_HIBW2_DDR1_IN_0_PRIORITY_REG); + context_icn.hibw2_ddr1_in_prio[1] = + readl_relaxed(b + NODE_HIBW2_DDR1_IN_1_PRIORITY_REG); + + context_icn.hibw2_ddr1_in_limit[0] = + readl_relaxed(b + NODE_HIBW2_DDR1_IN_0_LIMIT_REG); + context_icn.hibw2_ddr1_in_limit[1] = + readl_relaxed(b + NODE_HIBW2_DDR1_IN_1_LIMIT_REG); + + context_icn.hibw2_ddr1_out_prio = + readl_relaxed(b + NODE_HIBW2_DDR1_OUT_0_PRIORITY_REG); + + context_icn.esram0_in_prio[0] = + readl_relaxed(b + NODE_ESRAM0_IN_0_PRIORITY); + context_icn.esram0_in_prio[1] = + readl_relaxed(b + NODE_ESRAM0_IN_1_PRIORITY); + context_icn.esram0_in_prio[2] = + readl_relaxed(b + NODE_ESRAM0_IN_2_PRIORITY); + context_icn.esram0_in_prio[3] = + readl_relaxed(b + NODE_ESRAM0_IN_3_PRIORITY); + + context_icn.esram0_in_lim[0] = + readl_relaxed(b + NODE_ESRAM0_IN_0_LIMIT); + context_icn.esram0_in_lim[1] = + readl_relaxed(b + NODE_ESRAM0_IN_1_LIMIT); + context_icn.esram0_in_lim[2] = + readl_relaxed(b + NODE_ESRAM0_IN_2_LIMIT); + context_icn.esram0_in_lim[3] = + readl_relaxed(b + NODE_ESRAM0_IN_3_LIMIT); + + context_icn.esram0_out_prio = + readl_relaxed(b + NODE_ESRAM0_OUT_0_PRIORITY); + + context_icn.esram12_in_prio[0] = + readl_relaxed(b + NODE_ESRAM1_2_IN_0_PRIORITY); + context_icn.esram12_in_prio[1] = + readl_relaxed(b + NODE_ESRAM1_2_IN_1_PRIORITY); + context_icn.esram12_in_prio[2] = + readl_relaxed(b + NODE_ESRAM1_2_IN_2_PRIORITY); + context_icn.esram12_in_prio[3] = + readl_relaxed(b + NODE_ESRAM1_2_IN_3_PRIORITY); + + context_icn.esram12_in_arb_lim[0] = + readl_relaxed(b + NODE_ESRAM1_2_IN_0_ARB_1_LIMIT); + context_icn.esram12_in_arb_lim[1] = + readl_relaxed(b + NODE_ESRAM1_2_IN_0_ARB_2_LIMIT); + context_icn.esram12_in_arb_lim[2] = + readl_relaxed(b + NODE_ESRAM1_2_IN_1_ARB_1_LIMIT); + context_icn.esram12_in_arb_lim[3] = + readl_relaxed(b + NODE_ESRAM1_2_IN_1_ARB_2_LIMIT); + context_icn.esram12_in_arb_lim[4] = + readl_relaxed(b + NODE_ESRAM1_2_IN_2_ARB_1_LIMIT); + context_icn.esram12_in_arb_lim[5] = + readl_relaxed(b + NODE_ESRAM1_2_IN_2_ARB_2_LIMIT); + context_icn.esram12_in_arb_lim[6] = + readl_relaxed(b + NODE_ESRAM1_2_IN_3_ARB_1_LIMIT); + context_icn.esram12_in_arb_lim[7] = + readl_relaxed(b + NODE_ESRAM1_2_IN_3_ARB_2_LIMIT); + + context_icn.esram34_in_prio[0] = + readl_relaxed(b + NODE_ESRAM3_4_IN_0_PRIORITY); + context_icn.esram34_in_prio[1] = + readl_relaxed(b + NODE_ESRAM3_4_IN_1_PRIORITY); + context_icn.esram34_in_prio[2] = + readl_relaxed(b + NODE_ESRAM3_4_IN_2_PRIORITY); + context_icn.esram34_in_prio[3] = + readl_relaxed(b + NODE_ESRAM3_4_IN_3_PRIORITY); + + context_icn.esram34_in_arb_lim[0] = + readl_relaxed(b + NODE_ESRAM3_4_IN_0_ARB_1_LIMIT); + context_icn.esram34_in_arb_lim[1] = + readl_relaxed(b + NODE_ESRAM3_4_IN_0_ARB_2_LIMIT); + context_icn.esram34_in_arb_lim[2] = + readl_relaxed(b + NODE_ESRAM3_4_IN_1_ARB_1_LIMIT); + context_icn.esram34_in_arb_lim[3] = + readl_relaxed(b + NODE_ESRAM3_4_IN_1_ARB_2_LIMIT); + context_icn.esram34_in_arb_lim[4] = + readl_relaxed(b + NODE_ESRAM3_4_IN_2_ARB_1_LIMIT); + context_icn.esram34_in_arb_lim[5] = + readl_relaxed(b + NODE_ESRAM3_4_IN_2_ARB_2_LIMIT); + context_icn.esram34_in_arb_lim[6] = + readl_relaxed(b + NODE_ESRAM3_4_IN_3_ARB_1_LIMIT); + context_icn.esram34_in_arb_lim[7] = + readl_relaxed(b + NODE_ESRAM3_4_IN_3_ARB_2_LIMIT); + + context_icn.ddr_awqos_dsp_ddr0 = + readl_relaxed(b + NODE_DDR_AWQOS_DSP_DDR0_REG); + context_icn.ddr_awqos_dsp_ddr1 = + readl_relaxed(b + NODE_DDR_AWQOS_DSP_DDR1_REG); + context_icn.ddr_arqos_dsp_ddr0 = + readl_relaxed(b + NODE_DDR_ARQOS_DSP_DDR0_REG); + context_icn.ddr_arqos_dsp_ddr1 = + readl_relaxed(b + NODE_DDR_ARQOS_DSP_DDR1_REG); + context_icn.ddr_awqos_arm_ddr = + readl_relaxed(b + NODE_DDR_AWQOS_ARM_DDR_REG); + context_icn.ddr_arqos_arm_ddr = + readl_relaxed(b + NODE_DDR_ARQOS_ARM_DDR_REG); + + context_icn.sga_awqos_ddr0_hibw2 = + readl_relaxed(b + NODE_SGA_AWQOS_DDR0_HIBW2_REG); + context_icn.sga_arqos_ddr0_hibw2 = + readl_relaxed(b + NODE_SGA_ARQOS_DDR0_HIBW2_REG); + + context_icn.sga_awqos_sga_hibw2 = + readl_relaxed(b + NODE_SGA_AWQOS_SGA_HIBW2_REG); + context_icn.sga_arqos_sga_hibw2 = + readl_relaxed(b + NODE_SGA_ARQOS_SGA_HIBW2_REG); +} + +/** + * u9540_context_restore_icn() - restore ICN context + * + */ +void u9540_context_restore_icn(void) +{ + void __iomem *b = context_icn.base; + + writel_relaxed(context_icn.hibw1_esram_in_pri[0], + b + NODE_HIBW1_ESRAM_IN_0_PRIORITY); + writel_relaxed(context_icn.hibw1_esram_in_pri[1], + b + NODE_HIBW1_ESRAM_IN_1_PRIORITY); + writel_relaxed(context_icn.hibw1_esram_in_pri[2], + b + NODE_HIBW1_ESRAM_IN_2_PRIORITY); + writel_relaxed(context_icn.hibw1_esram_in_pri[3], + b + NODE_HIBW1_ESRAM_IN_3_PRIORITY); + + writel_relaxed(context_icn.hibw1_esram_in0_arb[0], + b + NODE_HIBW1_ESRAM_IN_0_ARB_1_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in0_arb[1], + b + NODE_HIBW1_ESRAM_IN_0_ARB_2_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in0_arb[2], + b + NODE_HIBW1_ESRAM_IN_0_ARB_3_LIMIT); + + writel_relaxed(context_icn.hibw1_esram_in1_arb[0], + b + NODE_HIBW1_ESRAM_IN_1_ARB_1_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in1_arb[1], + b + NODE_HIBW1_ESRAM_IN_1_ARB_2_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in1_arb[2], + b + NODE_HIBW1_ESRAM_IN_1_ARB_3_LIMIT); + + writel_relaxed(context_icn.hibw1_esram_in2_arb[0], + b + NODE_HIBW1_ESRAM_IN_2_ARB_1_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in2_arb[1], + b + NODE_HIBW1_ESRAM_IN_2_ARB_2_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in2_arb[2], + b + NODE_HIBW1_ESRAM_IN_2_ARB_3_LIMIT); + + writel_relaxed(context_icn.hibw1_esram_in3_arb[0], + b + NODE_HIBW1_ESRAM_IN_3_ARB_1_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in3_arb[1], + b + NODE_HIBW1_ESRAM_IN_3_ARB_2_LIMIT); + writel_relaxed(context_icn.hibw1_esram_in3_arb[2], + b + NODE_HIBW1_ESRAM_IN_3_ARB_3_LIMIT); + + writel_relaxed(context_icn.hibw1_ddr0_in_prio[0], + b + NODE_HIBW1_DDR0_IN_0_PRIORITY); + writel_relaxed(context_icn.hibw1_ddr0_in_prio[1], + b + NODE_HIBW1_DDR0_IN_1_PRIORITY); + writel_relaxed(context_icn.hibw1_ddr0_in_prio[2], + b + NODE_HIBW1_DDR0_IN_2_PRIORITY); + writel_relaxed(context_icn.hibw1_ddr0_in_prio[3], + b + NODE_HIBW1_DDR0_IN_3_PRIORITY); + + writel_relaxed(context_icn.hibw1_ddr0_in_limit[0], + b + NODE_HIBW1_DDR0_IN_0_LIMIT); + writel_relaxed(context_icn.hibw1_ddr0_in_limit[1], + b + NODE_HIBW1_DDR0_IN_1_LIMIT); + writel_relaxed(context_icn.hibw1_ddr0_in_limit[2], + b + NODE_HIBW1_DDR0_IN_2_LIMIT); + writel_relaxed(context_icn.hibw1_ddr0_in_limit[3], + b + NODE_HIBW1_DDR0_IN_3_LIMIT); + + writel_relaxed(context_icn.hibw1_ddr0_out_prio, + b + NODE_HIBW1_DDR0_OUT_0_PRIORITY); + + writel_relaxed(context_icn.hibw1_ddr1_in_prio[0], + b + NODE_HIBW1_DDR1_IN_0_PRIORITY_REG); + writel_relaxed(context_icn.hibw1_ddr1_in_prio[1], + b + NODE_HIBW1_DDR1_IN_1_PRIORITY_REG); + writel_relaxed(context_icn.hibw1_ddr1_in_prio[2], + b + NODE_HIBW1_DDR1_IN_2_PRIORITY_REG); + writel_relaxed(context_icn.hibw1_ddr1_in_prio[3], + b + NODE_HIBW1_DDR1_IN_3_PRIORITY_REG); + + writel_relaxed(context_icn.hibw1_ddr1_in_limit[0], + b + NODE_HIBW1_DDR1_IN_0_LIMIT_REG); + writel_relaxed(context_icn.hibw1_ddr1_in_limit[1], + b + NODE_HIBW1_DDR1_IN_1_LIMIT_REG); + writel_relaxed(context_icn.hibw1_ddr1_in_limit[2], + b + NODE_HIBW1_DDR1_IN_2_LIMIT_REG); + writel_relaxed(context_icn.hibw1_ddr1_in_limit[3], + b + NODE_HIBW1_DDR1_IN_3_LIMIT_REG); + + writel_relaxed(context_icn.hibw1_ddr1_out_prio, + b + NODE_HIBW1_DDR1_OUT_0_PRIORITY_REG); + + writel_relaxed(context_icn.hibw2_esram_in_pri[0], + b + NODE_HIBW2_ESRAM_IN_0_PRIORITY); + writel_relaxed(context_icn.hibw2_esram_in_pri[1], + b + NODE_HIBW2_ESRAM_IN_1_PRIORITY); + + writel_relaxed(context_icn.hibw2_esram_in0_arblimit[0], + b + NODE_HIBW2_ESRAM_IN_0_ARB_1_LIMIT); + writel_relaxed(context_icn.hibw2_esram_in0_arblimit[1], + b + NODE_HIBW2_ESRAM_IN_0_ARB_2_LIMIT); + writel_relaxed(context_icn.hibw2_esram_in0_arblimit[2], + b + NODE_HIBW2_ESRAM_IN_0_ARB_3_LIMIT); + + writel_relaxed(context_icn.hibw2_esram_in1_arblimit[0], + b + NODE_HIBW2_ESRAM_IN_1_ARB_1_LIMIT); + writel_relaxed(context_icn.hibw2_esram_in1_arblimit[1], + b + NODE_HIBW2_ESRAM_IN_1_ARB_2_LIMIT); + writel_relaxed(context_icn.hibw2_esram_in1_arblimit[2], + b + NODE_HIBW2_ESRAM_IN_1_ARB_3_LIMIT); + + writel_relaxed(context_icn.hibw2_ddr0_in_prio[0], + b + NODE_HIBW2_DDR0_IN_0_PRIORITY); + writel_relaxed(context_icn.hibw2_ddr0_in_prio[1], + b + NODE_HIBW2_DDR0_IN_1_PRIORITY); + + writel_relaxed(context_icn.hibw2_ddr0_in_limit[0], + b + NODE_HIBW2_DDR0_IN_0_LIMIT); + writel_relaxed(context_icn.hibw2_ddr0_in_limit[1], + b + NODE_HIBW2_DDR0_IN_1_LIMIT); + + writel_relaxed(context_icn.hibw2_ddr0_out_prio, + b + NODE_HIBW2_DDR0_OUT_0_PRIORITY); + + writel_relaxed(context_icn.hibw2_ddr1_in_prio[0], + b + NODE_HIBW2_DDR1_IN_0_PRIORITY_REG); + writel_relaxed(context_icn.hibw2_ddr1_in_prio[1], + b + NODE_HIBW2_DDR1_IN_1_PRIORITY_REG); + + writel_relaxed(context_icn.hibw2_ddr1_in_limit[0], + b + NODE_HIBW2_DDR1_IN_0_LIMIT_REG); + writel_relaxed(context_icn.hibw2_ddr1_in_limit[1], + b + NODE_HIBW2_DDR1_IN_1_LIMIT_REG); + + writel_relaxed(context_icn.hibw2_ddr1_out_prio, + b + NODE_HIBW2_DDR1_OUT_0_PRIORITY_REG); + + writel_relaxed(context_icn.esram0_in_prio[0], + b + NODE_ESRAM0_IN_0_PRIORITY); + writel_relaxed(context_icn.esram0_in_prio[1], + b + NODE_ESRAM0_IN_1_PRIORITY); + writel_relaxed(context_icn.esram0_in_prio[2], + b + NODE_ESRAM0_IN_2_PRIORITY); + writel_relaxed(context_icn.esram0_in_prio[3], + b + NODE_ESRAM0_IN_3_PRIORITY); + + writel_relaxed(context_icn.esram0_in_lim[0], + b + NODE_ESRAM0_IN_0_LIMIT); + writel_relaxed(context_icn.esram0_in_lim[1], + b + NODE_ESRAM0_IN_1_LIMIT); + writel_relaxed(context_icn.esram0_in_lim[2], + b + NODE_ESRAM0_IN_2_LIMIT); + writel_relaxed(context_icn.esram0_in_lim[3], + b + NODE_ESRAM0_IN_3_LIMIT); + + writel_relaxed(context_icn.esram0_out_prio, + b + NODE_ESRAM0_OUT_0_PRIORITY); + + writel_relaxed(context_icn.esram12_in_prio[0], + b + NODE_ESRAM1_2_IN_0_PRIORITY); + writel_relaxed(context_icn.esram12_in_prio[1], + b + NODE_ESRAM1_2_IN_1_PRIORITY); + writel_relaxed(context_icn.esram12_in_prio[2], + b + NODE_ESRAM1_2_IN_2_PRIORITY); + writel_relaxed(context_icn.esram12_in_prio[3], + b + NODE_ESRAM1_2_IN_3_PRIORITY); + + writel_relaxed(context_icn.esram12_in_arb_lim[0], + b + NODE_ESRAM1_2_IN_0_ARB_1_LIMIT); + writel_relaxed(context_icn.esram12_in_arb_lim[1], + b + NODE_ESRAM1_2_IN_0_ARB_2_LIMIT); + writel_relaxed(context_icn.esram12_in_arb_lim[2], + b + NODE_ESRAM1_2_IN_1_ARB_1_LIMIT); + writel_relaxed(context_icn.esram12_in_arb_lim[3], + b + NODE_ESRAM1_2_IN_1_ARB_2_LIMIT); + writel_relaxed(context_icn.esram12_in_arb_lim[4], + b + NODE_ESRAM1_2_IN_2_ARB_1_LIMIT); + writel_relaxed(context_icn.esram12_in_arb_lim[5], + b + NODE_ESRAM1_2_IN_2_ARB_2_LIMIT); + writel_relaxed(context_icn.esram12_in_arb_lim[6], + b + NODE_ESRAM1_2_IN_3_ARB_1_LIMIT); + writel_relaxed(context_icn.esram12_in_arb_lim[7], + b + NODE_ESRAM1_2_IN_3_ARB_2_LIMIT); + + writel_relaxed(context_icn.esram34_in_prio[0], + b + NODE_ESRAM3_4_IN_0_PRIORITY); + writel_relaxed(context_icn.esram34_in_prio[1], + b + NODE_ESRAM3_4_IN_1_PRIORITY); + writel_relaxed(context_icn.esram34_in_prio[2], + b + NODE_ESRAM3_4_IN_2_PRIORITY); + writel_relaxed(context_icn.esram34_in_prio[3], + b + NODE_ESRAM3_4_IN_3_PRIORITY); + + writel_relaxed(context_icn.esram34_in_arb_lim[0], + b + NODE_ESRAM3_4_IN_0_ARB_1_LIMIT); + writel_relaxed(context_icn.esram34_in_arb_lim[1], + b + NODE_ESRAM3_4_IN_0_ARB_2_LIMIT); + writel_relaxed(context_icn.esram34_in_arb_lim[2], + b + NODE_ESRAM3_4_IN_1_ARB_1_LIMIT); + writel_relaxed(context_icn.esram34_in_arb_lim[3], + b + NODE_ESRAM3_4_IN_1_ARB_2_LIMIT); + writel_relaxed(context_icn.esram34_in_arb_lim[4], + b + NODE_ESRAM3_4_IN_2_ARB_1_LIMIT); + writel_relaxed(context_icn.esram34_in_arb_lim[5], + b + NODE_ESRAM3_4_IN_2_ARB_2_LIMIT); + writel_relaxed(context_icn.esram34_in_arb_lim[6], + b + NODE_ESRAM3_4_IN_3_ARB_1_LIMIT); + writel_relaxed(context_icn.esram34_in_arb_lim[7], + b + NODE_ESRAM3_4_IN_3_ARB_2_LIMIT); + + writel_relaxed(context_icn.ddr_awqos_dsp_ddr0, + b + NODE_DDR_AWQOS_DSP_DDR0_REG); + writel_relaxed(context_icn.ddr_awqos_dsp_ddr1, + b + NODE_DDR_AWQOS_DSP_DDR1_REG); + writel_relaxed(context_icn.ddr_arqos_dsp_ddr0, + b + NODE_DDR_ARQOS_DSP_DDR0_REG); + writel_relaxed(context_icn.ddr_arqos_dsp_ddr1, + b + NODE_DDR_ARQOS_DSP_DDR1_REG); + writel_relaxed(context_icn.ddr_awqos_arm_ddr, + b + NODE_DDR_AWQOS_ARM_DDR_REG); + writel_relaxed(context_icn.ddr_arqos_arm_ddr, + b + NODE_DDR_ARQOS_ARM_DDR_REG); + + writel_relaxed(context_icn.sga_awqos_ddr0_hibw2, + b + NODE_SGA_AWQOS_DDR0_HIBW2_REG); + writel_relaxed(context_icn.sga_arqos_ddr0_hibw2, + b + NODE_SGA_ARQOS_DDR0_HIBW2_REG); + + writel_relaxed(context_icn.sga_awqos_sga_hibw2, + b + NODE_SGA_AWQOS_SGA_HIBW2_REG); + writel_relaxed(context_icn.sga_arqos_sga_hibw2, + b + NODE_SGA_ARQOS_SGA_HIBW2_REG); +} + +void u9540_context_init(void) +{ + context_icn.base = ioremap(U8500_ICN_BASE, SZ_16K); +} diff --git a/arch/arm/mach-ux500/pm/context.c b/arch/arm/mach-ux500/pm/context.c index ffd73f3ed52..e63fd4fbe8c 100644 --- a/arch/arm/mach-ux500/pm/context.c +++ b/arch/arm/mach-ux500/pm/context.c @@ -43,6 +43,7 @@ #define U8500_BACKUPRAM_SIZE SZ_64K #define U8500_PUBLIC_BOOT_ROM_BASE (U8500_BOOT_ROM_BASE + 0x17000) +#define U9540_PUBLIC_BOOT_ROM_BASE (U9540_BOOT_ROM_BASE + 0x17000) #define U5500_PUBLIC_BOOT_ROM_BASE (U5500_BOOT_ROM_BASE + 0x18000) /* @@ -598,6 +599,8 @@ void context_vape_save(void) u5500_context_save_icn(); if (cpu_is_u8500()) u8500_context_save_icn(); + if (cpu_is_u9540()) + u9540_context_save_icn(); save_stm_ape(); @@ -621,6 +624,8 @@ void context_vape_restore(void) u5500_context_restore_icn(); if (cpu_is_u8500()) u8500_context_restore_icn(); + if (cpu_is_u9540()) + u9540_context_restore_icn(); atomic_notifier_call_chain(&context_ape_notifier_list, CONTEXT_APE_RESTORE, NULL); @@ -906,13 +911,21 @@ static int __init context_init(void) context_gic_dist_common.base = ioremap(U5500_GIC_DIST_BASE, SZ_4K); per_cpu(context_gic_cpu, 0).base = ioremap(U5500_GIC_CPU_BASE, SZ_4K); - } else if (cpu_is_u8500()) { + } else if (cpu_is_u8500() || cpu_is_u9540()) { /* Give logical address to backup RAM. For both CPUs */ - writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE), - IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); - - writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE), - IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); + if (cpu_is_u9540()) { + writel(IO_ADDRESS_DB9540_ROM(U9540_PUBLIC_BOOT_ROM_BASE), + IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); + + writel(IO_ADDRESS_DB9540_ROM(U9540_PUBLIC_BOOT_ROM_BASE), + IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); + } else { + writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE), + IO_ADDRESS(U8500_CPU0_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); + + writel(IO_ADDRESS(U8500_PUBLIC_BOOT_ROM_BASE), + IO_ADDRESS(U8500_CPU1_BACKUPRAM_ADDR_PUBLIC_BOOT_ROM_LOG_ADDR)); + } context_tpiu.base = ioremap(U8500_TPIU_BASE, SZ_4K); context_stm_ape.base = ioremap(U8500_STM_REG_BASE, SZ_4K); @@ -952,6 +965,8 @@ static int __init context_init(void) u8500_context_init(); } else if (cpu_is_u5500()) { u5500_context_init(); + } else if (cpu_is_u9540()) { + u9540_context_init(); } else { printk(KERN_ERR "context: unknown hardware!\n"); return -EINVAL; -- cgit v1.2.3