From 3eb3e1775ead27876884f5119342cdd8ffb091b9 Mon Sep 17 00:00:00 2001 From: Pawel Szyszuk Date: Thu, 6 Oct 2011 11:04:12 +0100 Subject: ARM: U9500: HSI RX PIPELINE buffer flush ST-Ericsson Linux next: NA ST-Ericsson ID: 365683 ST-Ericsson FOSS-OUT ID: NA Change-Id: I25b92d815447d2746ba25a9db132b242b3da9d9c Signed-off-by: Pawel Szyszuk Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/33223 Reviewed-by: Christopher BLAIR Reviewed-by: Derek MORTON Reviewed-by: Andrew LYNN --- drivers/hsi/controllers/ste_hsi.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/hsi/controllers/ste_hsi.c b/drivers/hsi/controllers/ste_hsi.c index a2cbb2108f7..fe43d7b2133 100644 --- a/drivers/hsi/controllers/ste_hsi.c +++ b/drivers/hsi/controllers/ste_hsi.c @@ -1353,17 +1353,13 @@ static int ste_hsi_flush(struct hsi_client *cl) writel(0, ste_hsi->rx_base + STE_HSI_RX_DMAEN); ste_hsi_terminate_dma(ste_port); - /* Flush all HSIR and HSIT buffers */ + /* Flush HSIT buffers */ writel(0, ste_hsi->tx_base + STE_HSI_TX_STATE); writel(0, ste_hsi->tx_base + STE_HSI_TX_BUFSTATE); + + /* Flush HSIR pipeline and channel buffers */ writel(0, ste_hsi->rx_base + STE_HSI_RX_STATE); - /* - * BUFSTATE is cleared twice on purpose: - * first time all fifos are cleared - * second time to clear data that was in pipline buffer - * and was transfered to fifos - */ - writel(0, ste_hsi->rx_base + STE_HSI_RX_BUFSTATE); + writel(0, ste_hsi->rx_base + STE_HSI_RX_PIPEGAUGE); writel(0, ste_hsi->rx_base + STE_HSI_RX_BUFSTATE); /* Flush all errors */ -- cgit v1.2.3