From 8a0f1f858cb7e2e92257ed2f6b1f4ea444796fcb Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Wed, 15 Feb 2012 13:23:16 +0100 Subject: arm: u8500: prcmu: remove write only registers from dump list ST-Ericsson Linux next: - ST-Ericsson ID: 417413 ST-Ericsson FOSS-OUT ID: Trivial Change-Id: I33bc3a5eb0ca20d6cf9adeb3dbfb84e9c3f12538 Signed-off-by: Mian Yousaf Kaukab Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/49037 Reviewed-by: QABUILD Reviewed-by: QATEST Reviewed-by: Jonas ABERG --- arch/arm/mach-ux500/prcmu-debug.c | 127 ++++++++++++++++++-------------------- 1 file changed, 59 insertions(+), 68 deletions(-) diff --git a/arch/arm/mach-ux500/prcmu-debug.c b/arch/arm/mach-ux500/prcmu-debug.c index 372756b5301..749bcef85b7 100644 --- a/arch/arm/mach-ux500/prcmu-debug.c +++ b/arch/arm/mach-ux500/prcmu-debug.c @@ -90,68 +90,61 @@ static const u16 u8500_prcmu_dump_regs[] = { /*TIMER_1_DOWNCOUNT*/ 0xc4, /*TIMER_1_MODE*/ 0xc8, /*TIMER_2_REF*/ 0xcc, /*TIMER_2_DOWNCOUNT*/ 0xd0, /*TIMER_2_MODE*/ 0xd4, /*CLK009_MGT*/ 0xe4, - /*MODECLK*/ 0xe8, /*ARM_IT_SET*/ 0xf0, - /*4500_CLK_REQ*/ 0xf8, /*MBOX_CPU_VAL*/ 0xfc, - /*PLL32K_ENABLE*/ 0x10c, /*PLL32K_LOCKP*/ 0x110, - /*ARM_CHGCLKREQ*/ 0x114, /*ARM_PLLDIVPS*/ 0x118, - /*ARMITMSK31TO0*/ 0x11c, /*ARMITMSK63TO32*/ 0x120, - /*ARMITMSK95TO64*/ 0x124, /*ARMITMSK127TO96*/ 0x128, - /*ARMSTANDBY_STATUS*/ 0x130, /*CGATING_BYPASS*/ 0x134, - /*GPIOCR*/ 0x138, /*LEMI*/ 0x13c, - /*COMPCR*/ 0x140, /*COMPSTA*/ 0x144, - /*ITSTATUS0*/ 0x148, /*ITSTATUS1*/ 0x150, - /*ITSTATUS2*/ 0x158, /*ITSTATUS3*/ 0x160, - /*ITSTATUS4*/ 0x168, /*LINE_VALUE*/ 0x170, - /*HOLD_EVT*/ 0x174, /*EDGE_SENS_L*/ 0x178, - /*EDGE_SENS_H*/ 0x17c, /*DEBUG_CTRL_VAL*/ 0x190, - /*DEBUG_NOPWRDOWN_VAL*/ 0x194, /*DEBUG_CTRL_ACK*/ 0x198, - /*A9PL_FORCE_CLKEN*/ 0x19c, /*TPIU_FLUSHIN_REQ*/ 0x1a0, - /*TPIU_FLUSHIN_ACK*/ 0x1a4, /*STP_FLUSHIN_REQ*/ 0x1a8, - /*STP_FLUSHIN_ACK*/ 0x1ac, /*HWI2C_DIV*/ 0x1b0, - /*HWI2C_GO*/ 0x1b4, /*HWI2C_CMD*/ 0x1b8, + /*MODECLK*/ 0xe8, /*4500_CLK_REQ*/ 0xf8, + /*MBOX_CPU_VAL*/ 0xfc, /*PLL32K_ENABLE*/ 0x10c, + /*PLL32K_LOCKP*/ 0x110, /*ARM_CHGCLKREQ*/ 0x114, + /*ARM_PLLDIVPS*/ 0x118, /*ARMITMSK31TO0*/ 0x11c, + /*ARMITMSK63TO32*/ 0x120, /*ARMITMSK95TO64*/ 0x124, + /*ARMITMSK127TO96*/ 0x128, /*ARMSTANDBY_STATUS*/ 0x130, + /*CGATING_BYPASS*/ 0x134, /*GPIOCR*/ 0x138, + /*LEMI*/ 0x13c, /*COMPCR*/ 0x140, + /*COMPSTA*/ 0x144, /*ITSTATUS0*/ 0x148, + /*ITSTATUS1*/ 0x150, /*ITSTATUS2*/ 0x158, + /*ITSTATUS3*/ 0x160, /*ITSTATUS4*/ 0x168, + /*LINE_VALUE*/ 0x170, /*HOLD_EVT*/ 0x174, + /*EDGE_SENS_L*/ 0x178, /*EDGE_SENS_H*/ 0x17c, + /*DEBUG_CTRL_VAL*/ 0x190, /*DEBUG_NOPWRDOWN_VAL*/ 0x194, + /*DEBUG_CTRL_ACK*/ 0x198, /*A9PL_FORCE_CLKEN*/ 0x19c, + /*TPIU_FLUSHIN_REQ*/ 0x1a0, /*TPIU_FLUSHIN_ACK*/ 0x1a4, + /*STP_FLUSHIN_REQ*/ 0x1a8, /*STP_FLUSHIN_ACK*/ 0x1ac, + /*HWI2C_DIV*/ 0x1b0, /*HWI2C_CMD*/ 0x1b8, /*HWI2C_DATA123*/ 0x1bc, /*HWI2C_SR*/ 0x1c0, /*REMAPCR*/ 0x1c4, /*TCR*/ 0x1c8, /*CLKOCR*/ 0x1cc, /*ITSTATUS_DBG*/ 0x1d0, /*LINE_VALUE_DBG*/ 0x1d8, /*DBG_HOLD*/ 0x1dc, - /*EDGE_SENS_DBG*/ 0x1e0, /*APE_RESETN_SET*/ 0x1e4, - /*APE_RESETN_VAL*/ 0x1ec, /*A9_RESETN_SET*/ 0x1f0, - /*A9_RESETN_VAL*/ 0x1f8, /*MOD_RESETN_SET*/ 0x1fc, - /*MOD_RESETN_VAL*/ 0x204, /*GPIO_RESETN_SET*/ 0x208, - /*GPIO_RESETN_VAL*/ 0x210, /*4500_RESETN_SET*/ 0x214, - /*4500_RESETN_VAL*/ 0x21c, /*HSI_SOFTRST*/ 0x224, - /*APE_SOFTRST*/ 0x228, /*SWD_RST_TEMPO*/ 0x238, + /*EDGE_SENS_DBG*/ 0x1e0, /*APE_RESETN_VAL*/ 0x1ec, + /*A9_RESETN_SET*/ 0x1f0, /*A9_RESETN_VAL*/ 0x1f8, + /*MOD_RESETN_VAL*/ 0x204, /*GPIO_RESETN_VAL*/ 0x210, + /*4500_RESETN_VAL*/ 0x21c, /*SWD_RST_TEMPO*/ 0x238, /*RST_4500_TEMPO*/ 0x23c, /*SVAMMDSP_IT*/ 0x240, - /*SIAMMDSP_IT*/ 0x248, /*POWER_STATE_SET*/ 0x254, - /*POWER_STATE_VAL*/ 0x25c, /*ARMITVALUE31TO0*/ 0x260, - /*ARMITVALUE63TO32*/ 0x264, /*ARMITVALUE95TO64*/ 0x268, - /*ARMITVALUE127TO96*/ 0x26c, /*REDUN_LOAD*/ 0x270, - /*REDUN_STATUS*/ 0x274, /*UNIPROCLK_MGT*/ 0x278, - /*UICCCLK_MGT*/ 0x27c, /*SSPCLK_MGT*/ 0x280, - /*RNGCLK_MGT*/ 0x284, /*MSP1CLK_MGT*/ 0x288, - /*DAP_RESETN_SET*/ 0x2a0, /*DAP_RESETN_VAL*/ 0x2a8, - /*SRAM_DEDCSTOV*/ 0x300, /*SRAM_LS_SLEEP*/ 0x304, - /*SRAM_A9*/ 0x308, /*ARM_LS_CLAMP*/ 0x30c, - /*IOCR*/ 0x310, /*MODEM_SYSCLKOK*/ 0x314, - /*SYSCLKOK_DELAY*/ 0x318, /*SYSCLKSTATUS*/ 0x31c, - /*DSI_SW_RESET*/ 0x324, /*A9_MASK_REQ*/ 0x328, - /*A9_MASK_ACK*/ 0x32c, /*HOSTACCESS_REQ*/ 0x334, - /*TIMER_3_REF*/ 0x338, /*TIMER_3_DOWNCOUNT*/ 0x33c, - /*TIMER_3_MODE*/ 0x340, /*PMB_SENS_CTRL*/ 0x344, - /*PMB_REF_COUNTER*/ 0x348, /*PMB_SENSOR_STATUS*/ 0x34c, - /*APE_EPOD_CFG*/ 0x404, /*DDR_EPOD_CFG*/ 0x408, - /*EPOD_C_SET*/ 0x410, /*EPOD_C_VAL*/ 0x418, - /*EPOD_VOK*/ 0x41c, /*MMIP_LS_CLAMP_SET*/ 0x420, - /*MMIP_LS_CLAMP_VAL*/ 0x428, /*VSAFE_LS_CLAMP_SET*/ 0x42c, + /*SIAMMDSP_IT*/ 0x248, /*POWER_STATE_VAL*/ 0x25c, + /*ARMITVALUE31TO0*/ 0x260, /*ARMITVALUE63TO32*/ 0x264, + /*ARMITVALUE95TO64*/ 0x268, /*ARMITVALUE127TO96*/ 0x26c, + /*REDUN_LOAD*/ 0x270, /*REDUN_STATUS*/ 0x274, + /*UNIPROCLK_MGT*/ 0x278, /*UICCCLK_MGT*/ 0x27c, + /*SSPCLK_MGT*/ 0x280, /*RNGCLK_MGT*/ 0x284, + /*MSP1CLK_MGT*/ 0x288, /*DAP_RESETN_SET*/ 0x2a0, + /*DAP_RESETN_VAL*/ 0x2a8, /*SRAM_DEDCSTOV*/ 0x300, + /*SRAM_LS_SLEEP*/ 0x304, /*SRAM_A9*/ 0x308, + /*ARM_LS_CLAMP*/ 0x30c, /*IOCR*/ 0x310, + /*MODEM_SYSCLKOK*/ 0x314, /*SYSCLKOK_DELAY*/ 0x318, + /*SYSCLKSTATUS*/ 0x31c, /*DSI_SW_RESET*/ 0x324, + /*A9_MASK_REQ*/ 0x328, /*A9_MASK_ACK*/ 0x32c, + /*HOSTACCESS_REQ*/ 0x334, /*TIMER_3_REF*/ 0x338, + /*TIMER_3_DOWNCOUNT*/ 0x33c, /*TIMER_3_MODE*/ 0x340, + /*PMB_SENS_CTRL*/ 0x344, /*PMB_REF_COUNTER*/ 0x348, + /*PMB_SENSOR_STATUS*/ 0x34c, /*APE_EPOD_CFG*/ 0x404, + /*DDR_EPOD_CFG*/ 0x408, /*EPOD_C_VAL*/ 0x418, + /*EPOD_VOK*/ 0x41c, /*MMIP_LS_CLAMP_VAL*/ 0x428, /*VSAFE_LS_CLAMP_VAL*/ 0x434, /*DDRSUBSYS_APE_MINBW*/ 0x438, /*DDRSUBSYS_STATUS*/ 0x43c, /*DDRSUBSYS_CONTROL*/ 0x440, /*DDRSUBSYS_HIGH_LEAK_COND*/ 0x444, /*DDRSUBSYS_CONFIG*/ 0x448, - /*DDRSUBSYS_CONFIG_ACK*/ 0x44c, /*TIMER_4_REF*/ 0x450, - /*TIMER_4_DOWNCOUNT*/ 0x454, /*TIMER_4_MODE*/ 0x458, - /*TIMER_5_REF*/ 0x45c, /*TIMER_5_DOWNCOUNT*/ 0x460, - /*TIMER_5_MODE*/ 0x464, /*APE_MEM_REQ*/ 0x470, - /*DBG_FORCES_APE_MEM_REQ*/ 0x474, /*APE_MEM_WFX_EN*/ 0x478, - /*APE_MEM_LATENCY*/ 0x47c, /*APE_MEM_ACK*/ 0x480, - /*ITSTATUS5*/ 0x484, /*ARM_IT1_SET*/ 0x490, + /*TIMER_4_REF*/ 0x450, /*TIMER_4_DOWNCOUNT*/ 0x454, + /*TIMER_4_MODE*/ 0x458, /*TIMER_5_REF*/ 0x45c, + /*TIMER_5_DOWNCOUNT*/ 0x460, /*TIMER_5_MODE*/ 0x464, + /*APE_MEM_REQ*/ 0x470, /*DBG_FRCS_APE_MEM_REQ*/ 0x474, + /*APE_MEM_WFX_EN*/ 0x478, /*APE_MEM_LATENCY*/ 0x47c, + /*APE_MEM_ACK*/ 0x480, /*ITSTATUS5*/ 0x484, /*ARM_IT1_VAL*/ 0x494, /*MOD_PWR_OK*/ 0x498, /*MOD_AUXCLKOK*/ 0x49c, /*MOD_AWAKE_STATUS*/ 0x4a0, /*MOD_SWRESET_IRQ_ACK*/ 0x4a4, /*MOD_SWRESET_ACK*/ 0x4a8, @@ -159,16 +152,15 @@ static const u16 u8500_prcmu_dump_regs[] = { /*HWOBS_L*/ 0x4b4, /*PLLDSI_FREQ*/ 0x500, /*PLLDSI_ENABLE*/ 0x504, /*PLLDSI_LOCKP*/ 0x508, /*RNG_ENABLE*/ 0x50c, /*YYCLKEN0_MGT_SET*/ 0x510, - /*YYCLKEN1_MGT_SET*/ 0x514, /*YYCLKEN0_MGT_VAL*/ 0x520, - /*YYCLKEN1_MGT_VAL*/ 0x524, /*XP70CLK_MGT2*/ 0x528, - /*DSITVCLK_DIV*/ 0x52c, /*DSI_PLLOUT_SEL*/ 0x530, - /*DSI_GLITCHFREE_EN*/ 0x534, /*CLKACTIV*/ 0x538, - /*SIA_MMDSP_MEM_MGT*/ 0x53c, /*SVA_MMDSP_MEM_MGT*/ 0x540, - /*SXAMMDSP_FORCE_CLKEN*/ 0x544, /*UICC_NANDTREE*/ 0x570, - /*GPIOCR2*/ 0x574, /*MDM_ACWAKE*/ 0x578, - /*MOD_MEM_REQ*/ 0x5a4, /*MOD_MEM_ACK*/ 0x5a8, - /*ARM_PLLDIVPS_REQ*/ 0x5b0, /*ARM_PLLDIVPS_ACK*/ 0x5b4, - /*SRPTIMER_VAL*/ 0x5d0, + /*YYCLKEN0_MGT_VAL*/ 0x520, /*YYCLKEN1_MGT_VAL*/ 0x524, + /*XP70CLK_MGT2*/ 0x528, /*DSITVCLK_DIV*/ 0x52c, + /*DSI_PLLOUT_SEL*/ 0x530, /*DSI_GLITCHFREE_EN*/ 0x534, + /*CLKACTIV*/ 0x538, /*SIA_MMDSP_MEM_MGT*/ 0x53c, + /*SVA_MMDSP_MEM_MGT*/ 0x540, /*SXAMMDSP_FORCE_CLKEN*/ 0x544, + /*UICC_NANDTREE*/ 0x570, /*GPIOCR2*/ 0x574, + /*MDM_ACWAKE*/ 0x578, /*MOD_MEM_REQ*/ 0x5a4, + /*MOD_MEM_ACK*/ 0x5a8, /*ARM_PLLDIVPS_REQ*/ 0x5b0, + /*ARM_PLLDIVPS_ACK*/ 0x5b4, /*SRPTIMER_VAL*/ 0x5d0, }; /* Offsets from secure base which is U8500_PRCMU_BASE + SZ_4K */ @@ -177,10 +169,9 @@ static const u16 u8500_prcmu_dump_secure_regs[] = { /*ARMITMSKSEC_31TO0*/ 0x08, /*ARMITMSKSEC_63TO32*/ 0x0C, /*ARMITMSKSEC_95TO64*/ 0x10, /*ARMITMSKSEC_127TO96*/ 0x14, /*ARMIT_MASKXP70_IT*/ 0x18, /*ESRAM0_EPOD_CFG*/ 0x1C, - /*ESRAM0_EPOD_C_VAL*/ 0x20, /*ESRAM0_EPOD_C_SET*/ 0x24, - /*ESRAM0_EPOD_VOK*/ 0x2C, /*ESRAM0_LS_SLEEP*/ 0x30, - /*SECURE_ONGOING*/ 0x34, /*I2C_SECURE*/ 0x38, - /*RESET_STATUS*/ 0x3C, /*PERIPH4_RESETN_SET*/ 0x40, + /*ESRAM0_EPOD_C_VAL*/ 0x20, /*ESRAM0_EPOD_VOK*/ 0x2C, + /*ESRAM0_LS_SLEEP*/ 0x30, /*SECURE_ONGOING*/ 0x34, + /*I2C_SECURE*/ 0x38, /*RESET_STATUS*/ 0x3C, /*PERIPH4_RESETN_VAL*/ 0x48, /*SPAREOUT_SEC*/ 0x4C, /*PIPELINEDCR*/ 0xD8, }; -- cgit v1.2.3