From 2839e06c95d12ada034cf9b63da60334c7c6358b Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Tue, 8 Mar 2011 06:59:54 +0100 Subject: ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation. Workaround: Disable Write-Back and Cache Linefill (Debug Control Register) Clean & Invalidate by Way (0x7FC) Re-enable Write-Back and Cache Linefill (Debug Control Register) This patch also removes any OMAP dependency on PL310 Errata's Signed-off-by: Santosh Shilimkar Acked-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/Kconfig | 15 ++++++++++++--- arch/arm/include/asm/outercache.h | 1 + arch/arm/mm/cache-l2x0.c | 32 ++++++++++++++++++-------------- 3 files changed, 31 insertions(+), 17 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 65ea7bb57c4..ef41f7e39f6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1135,7 +1135,7 @@ config ARM_ERRATA_742231 config PL310_ERRATA_588369 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" - depends on CACHE_L2X0 && ARCH_OMAP4 + depends on CACHE_L2X0 help The PL310 L2 cache controller implements three types of Clean & Invalidate maintenance operations: by Physical Address @@ -1144,8 +1144,7 @@ config PL310_ERRATA_588369 clean operation followed immediately by an invalidate operation, both performing to the same memory location. This functionality is not correctly implemented in PL310 as clean lines are not - invalidated as a result of these operations. Note that this errata - uses Texas Instrument's secure monitor api. + invalidated as a result of these operations. config ARM_ERRATA_720789 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" @@ -1172,6 +1171,16 @@ config ARM_ERRATA_743622 visible impact on the overall performance or power consumption of the processor. +config PL310_ERRATA_727915 + bool "Background Clean & Invalidate by Way operation can cause data corruption" + depends on CACHE_L2X0 + help + PL310 implements the Clean & Invalidate by Way L2 cache maintenance + operation (offset 0x7FC). This operation runs in background so that + PL310 can handle normal accesses while it is in progress. Under very + rare circumstances, due to this erratum, write data can be lost when + PL310 treats a cacheable write transaction during a Clean & + Invalidate by Way operation. endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index fc190092527..348d513afa9 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h @@ -31,6 +31,7 @@ struct outer_cache_fns { #ifdef CONFIG_OUTER_CACHE_SYNC void (*sync)(void); #endif + void (*set_debug)(unsigned long); }; #ifdef CONFIG_OUTER_CACHE diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 170c9bb9586..803bce8845a 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -67,18 +67,24 @@ static inline void l2x0_inv_line(unsigned long addr) writel_relaxed(addr, base + L2X0_INV_LINE_PA); } -#ifdef CONFIG_PL310_ERRATA_588369 -static void debug_writel(unsigned long val) -{ - extern void omap_smc1(u32 fn, u32 arg); +#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) - /* - * Texas Instrument secure monitor api to modify the - * PL310 Debug Control Register. - */ - omap_smc1(0x100, val); +#define debug_writel(val) outer_cache.set_debug(val) + +static void l2x0_set_debug(unsigned long val) +{ + writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); } +#else +/* Optimised out for non-errata case */ +static inline void debug_writel(unsigned long val) +{ +} + +#define l2x0_set_debug NULL +#endif +#ifdef CONFIG_PL310_ERRATA_588369 static inline void l2x0_flush_line(unsigned long addr) { void __iomem *base = l2x0_base; @@ -91,11 +97,6 @@ static inline void l2x0_flush_line(unsigned long addr) } #else -/* Optimised out for non-errata case */ -static inline void debug_writel(unsigned long val) -{ -} - static inline void l2x0_flush_line(unsigned long addr) { void __iomem *base = l2x0_base; @@ -119,9 +120,11 @@ static void l2x0_flush_all(void) /* clean all ways */ spin_lock_irqsave(&l2x0_lock, flags); + debug_writel(0x03); writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY); cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask); cache_sync(); + debug_writel(0x00); spin_unlock_irqrestore(&l2x0_lock, flags); } @@ -329,6 +332,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.flush_all = l2x0_flush_all; outer_cache.inv_all = l2x0_inv_all; outer_cache.disable = l2x0_disable; + outer_cache.set_debug = l2x0_set_debug; printk(KERN_INFO "%s cache controller enabled\n", type); printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", -- cgit v1.2.3 From 4bdb157749a0da065e532f2f46040c178075b06f Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Tue, 22 Feb 2011 10:00:44 +0100 Subject: ARM: 6755/1: omap4: l2x0: Populate set_debug() function and enable Errata 727915 Populate the l2x0 set_debug function pointer with OMAP secure call and enable the PL310 Errata 727915 This patch has dependency on the earlier patch ARM: l2x0: Errata fix for flush by Way operation can cause data corruption Signed-off-by: Santosh Shilimkar Reviewed-by: Catalin Marinas Signed-off-by: Russell King --- arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/omap4-common.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 1a2cf6226a5..b69fa0a0299 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -45,6 +45,7 @@ config ARCH_OMAP4 select CPU_V7 select ARM_GIC select PL310_ERRATA_588369 + select PL310_ERRATA_727915 select ARM_ERRATA_720789 select ARCH_HAS_OPP select PM_OPP if PM diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 19268647ce3..9ef8c29dd81 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -52,6 +52,12 @@ static void omap4_l2x0_disable(void) omap_smc1(0x102, 0x0); } +static void omap4_l2x0_set_debug(unsigned long val) +{ + /* Program PL310 L2 Cache controller debug register */ + omap_smc1(0x100, val); +} + static int __init omap_l2_cache_init(void) { u32 aux_ctrl = 0; @@ -99,6 +105,7 @@ static int __init omap_l2_cache_init(void) * specific one */ outer_cache.disable = omap4_l2x0_disable; + outer_cache.set_debug = omap4_l2x0_set_debug; return 0; } -- cgit v1.2.3 From d7ed36a4ea84e3a850f9932e2058ceef987d1acd Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Wed, 2 Mar 2011 08:03:22 +0100 Subject: ARM: 6777/1: gic: Add hooks for architecture specific extensions Few architectures combine the GIC with an external interrupt controller. On such systems it may be necessary to update both the GIC registers and the external controller's registers to control IRQ behavior. This can be addressed in couple of possible methods. 1. Export common GIC routines along with 'struct irq_chip gic_chip' and allow architectures to have custom function by override. 2. Provide architecture specific function pointer hooks within GIC library and leave platforms to add the necessary code as part of these hooks. First one might be non-intrusive but have few shortcomings like arch needs to have there own custom gic library. Locks used should be common since it caters to same IRQs etc. Maintenance point of view also it leads to multiple file fixes. The second probably is cleaner and portable. It ensures that all the common GIC infrastructure is not touched and also provides archs to address their specific issue. Cc: Russell King Signed-off-by: Santosh Shilimkar Acked-by: Colin Cross Tested-by: Colin Cross Signed-off-by: Russell King --- arch/arm/common/gic.c | 47 +++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/hardware/gic.h | 1 + 2 files changed, 48 insertions(+) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index e21c1f4218d..cb6b041c39d 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -44,6 +44,19 @@ struct gic_chip_data { void __iomem *cpu_base; }; +/* + * Supported arch specific GIC irq extension. + * Default make them NULL. + */ +struct irq_chip gic_arch_extn = { + .irq_ack = NULL, + .irq_mask = NULL, + .irq_unmask = NULL, + .irq_retrigger = NULL, + .irq_set_type = NULL, + .irq_set_wake = NULL, +}; + #ifndef MAX_GIC_NR #define MAX_GIC_NR 1 #endif @@ -74,6 +87,8 @@ static inline unsigned int gic_irq(struct irq_data *d) static void gic_ack_irq(struct irq_data *d) { spin_lock(&irq_controller_lock); + if (gic_arch_extn.irq_ack) + gic_arch_extn.irq_ack(d); writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); spin_unlock(&irq_controller_lock); } @@ -84,6 +99,8 @@ static void gic_mask_irq(struct irq_data *d) spin_lock(&irq_controller_lock); writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); + if (gic_arch_extn.irq_mask) + gic_arch_extn.irq_mask(d); spin_unlock(&irq_controller_lock); } @@ -92,6 +109,8 @@ static void gic_unmask_irq(struct irq_data *d) u32 mask = 1 << (d->irq % 32); spin_lock(&irq_controller_lock); + if (gic_arch_extn.irq_unmask) + gic_arch_extn.irq_unmask(d); writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); spin_unlock(&irq_controller_lock); } @@ -116,6 +135,9 @@ static int gic_set_type(struct irq_data *d, unsigned int type) spin_lock(&irq_controller_lock); + if (gic_arch_extn.irq_set_type) + gic_arch_extn.irq_set_type(d, type); + val = readl(base + GIC_DIST_CONFIG + confoff); if (type == IRQ_TYPE_LEVEL_HIGH) val &= ~confmask; @@ -141,6 +163,14 @@ static int gic_set_type(struct irq_data *d, unsigned int type) return 0; } +static int gic_retrigger(struct irq_data *d) +{ + if (gic_arch_extn.irq_retrigger) + return gic_arch_extn.irq_retrigger(d); + + return -ENXIO; +} + #ifdef CONFIG_SMP static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) @@ -166,6 +196,21 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, } #endif +#ifdef CONFIG_PM +static int gic_set_wake(struct irq_data *d, unsigned int on) +{ + int ret = -ENXIO; + + if (gic_arch_extn.irq_set_wake) + ret = gic_arch_extn.irq_set_wake(d, on); + + return ret; +} + +#else +#define gic_set_wake NULL +#endif + static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) { struct gic_chip_data *chip_data = get_irq_data(irq); @@ -201,9 +246,11 @@ static struct irq_chip gic_chip = { .irq_mask = gic_mask_irq, .irq_unmask = gic_unmask_irq, .irq_set_type = gic_set_type, + .irq_retrigger = gic_retrigger, #ifdef CONFIG_SMP .irq_set_affinity = gic_set_affinity, #endif + .irq_set_wake = gic_set_wake, }; void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 84557d32100..0691f9dcc50 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h @@ -34,6 +34,7 @@ #ifndef __ASSEMBLY__ extern void __iomem *gic_cpu_base_addr; +extern struct irq_chip gic_arch_extn; void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); void gic_secondary_init(unsigned int); -- cgit v1.2.3 From 1cf7cf06c92ba46ac0e0654ad8aad4c93ae412db Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 2 Mar 2011 18:08:55 +0100 Subject: ARM: 6778/1: compressed/head.S: make LDFLAGS_vmlinux into a recursively expanded variable The simply expanded variable may be evaluated before the target file for the stat command is up to date or even exists. Switching to a recursively expanded variable move the execution of the stat command to the location where LDFLAGS_vmlinux is actually used, fixing the dependency issue introduced by patch #6746/1. Signed-off-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/boot/compressed/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 9d328be6e5e..3c0c68ff6a8 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -84,7 +84,7 @@ EXTRA_CFLAGS := -fpic -fno-builtin EXTRA_AFLAGS := -Wa,-march=all # Provide size of uncompressed kernel to the decompressor via a linker symbol. -LDFLAGS_vmlinux := --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) +LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image) # Supply ZRELADDR to the decompressor via a linker symbol. ifneq ($(CONFIG_AUTO_ZRELADDR),y) LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) -- cgit v1.2.3 From bf9dd36091695f1138a98b6ae85d565e60635545 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 4 Mar 2011 23:51:59 +0100 Subject: ARM: 6786/1: enable CONFIG_KTIME_SCALAR Use straight 64-bit values as 64-bit operations are fairly efficient on ARM. Comparing the asm output with and without KTIME_SCALAR, using 64-bit math generates clearly better code. Comparing kernel/hrtimer.c .text size, it goes from 0x1414 to 0x119c with this change. Signed-off-by: Rob Herring Signed-off-by: Russell King --- arch/arm/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ef41f7e39f6..2fec7073f68 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -63,6 +63,10 @@ config GENERIC_CLOCKEVENTS_BROADCAST depends on GENERIC_CLOCKEVENTS default y if SMP +config KTIME_SCALAR + bool + default y + config HAVE_TCM bool select GENERIC_ALLOCATOR -- cgit v1.2.3 From 6fa85e5ce311a8c57fe32cb6403961f7a897112d Mon Sep 17 00:00:00 2001 From: Stepan Moskovchenko Date: Thu, 10 Mar 2011 05:12:25 +0100 Subject: ARM: 6796/1: Footbridge: Fix I/O mappings for NOMMU mode Use the correct I/O address definitions for Footbridge peripherals when the kernel is compiled without MMU support. Signed-off-by: Stepan Moskovchenko Signed-off-by: Russell King --- arch/arm/mach-footbridge/include/mach/hardware.h | 21 ++++++++++++++------- arch/arm/mach-footbridge/include/mach/io.h | 10 ++++++++-- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index 51dd902043a..b6fdf23ecf6 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -23,26 +23,33 @@ * 0xf9000000 0x50000000 1MB Cache flush * 0xf0000000 0x80000000 16MB ISA memory */ + +#ifdef CONFIG_MMU +#define MMU_IO(a, b) (a) +#else +#define MMU_IO(a, b) (b) +#endif + #define XBUS_SIZE 0x00100000 -#define XBUS_BASE 0xff800000 +#define XBUS_BASE MMU_IO(0xff800000, 0x40000000) #define ARMCSR_SIZE 0x00100000 -#define ARMCSR_BASE 0xfe000000 +#define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) #define WFLUSH_SIZE 0x00100000 -#define WFLUSH_BASE 0xfd000000 +#define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) #define PCIIACK_SIZE 0x00100000 -#define PCIIACK_BASE 0xfc000000 +#define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) #define PCICFG1_SIZE 0x01000000 -#define PCICFG1_BASE 0xfb000000 +#define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) #define PCICFG0_SIZE 0x01000000 -#define PCICFG0_BASE 0xfa000000 +#define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) #define PCIMEM_SIZE 0x01000000 -#define PCIMEM_BASE 0xf0000000 +#define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) #define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) #define XBUS_LED_AMBER (1 << 0) diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h index 101a4fe90bd..32e4cc397c2 100644 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ b/arch/arm/mach-footbridge/include/mach/io.h @@ -14,8 +14,14 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H -#define PCIO_SIZE 0x00100000 -#define PCIO_BASE 0xff000000 +#ifdef CONFIG_MMU +#define MMU_IO(a, b) (a) +#else +#define MMU_IO(a, b) (b) +#endif + +#define PCIO_SIZE 0x00100000 +#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) #define IO_SPACE_LIMIT 0xffff -- cgit v1.2.3 From 23bfdacf4eb525ff3404161429cedaa281c23e47 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 10 Mar 2011 14:03:01 +0100 Subject: ARM: 6798/1: aout-core: zero thread debug registers in a.out core dump The removal of the single-step emulation from ptrace on ARM means that thread_struct no longer has software breakpoint fields in its debug member. This patch fixes the a.out core dump code so that the debug registers are zeroed rather than trying to copy from non-existent fields. Cc: Nicolas Pitre Signed-off-by: Bryan Wu Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/a.out-core.h | 6 +----- arch/arm/include/asm/user.h | 2 +- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/a.out-core.h b/arch/arm/include/asm/a.out-core.h index 93d04acaa31..92f10cb5c70 100644 --- a/arch/arm/include/asm/a.out-core.h +++ b/arch/arm/include/asm/a.out-core.h @@ -32,11 +32,7 @@ static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT; dump->u_ssize = 0; - dump->u_debugreg[0] = tsk->thread.debug.bp[0].address; - dump->u_debugreg[1] = tsk->thread.debug.bp[1].address; - dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn.arm; - dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn.arm; - dump->u_debugreg[4] = tsk->thread.debug.nsaved; + memset(dump->u_debugreg, 0, sizeof(dump->u_debugreg)); if (dump->start_stack < 0x04000000) dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT; diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h index 05ac4b06876..35917b3a97f 100644 --- a/arch/arm/include/asm/user.h +++ b/arch/arm/include/asm/user.h @@ -71,7 +71,7 @@ struct user{ /* the registers. */ unsigned long magic; /* To uniquely identify a core file */ char u_comm[32]; /* User command that was responsible */ - int u_debugreg[8]; + int u_debugreg[8]; /* No longer used */ struct user_fp u_fp; /* FP state */ struct user_fp_struct * u_fp0;/* Used by gdb to help find the values for */ /* the FP registers. */ -- cgit v1.2.3 From 6f685c5cdd29649cf8cc8f57c72791159f936e07 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Thu, 3 Mar 2011 11:41:12 +0100 Subject: ARM: 6781/1: Thumb-2: Work around buggy Thumb-2 short branch relocations in gas Various binutils versions can resolve Thumb-2 branches to locally-defined, preemptible global symbols as short-range "b.n" branch instructions. This is a problem, because there's no guarantee the final destination of the symbol, or any candidate locations for a trampoline, are within range of the branch. For this reason, the kernel does not support fixing up the R_ARM_THM_JUMP11 (102) relocation in modules at all, and it makes little sense to add support. The symptom is that the kernel fails with an "unsupported relocation" error when loading some modules. Until fixed tools are available, passing -fno-optimize-sibling-calls to gcc should prevent gcc generating code which hits this problem, at the cost of a bit of extra runtime stack usage in some cases. The problem is described in more detail at: https://bugs.launchpad.net/binutils-linaro/+bug/725126 Only Thumb-2 kernels are affected. This patch adds a new CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11 config option which adds -fno-optimize-sibling-calls to CFLAGS_MODULE when building a Thumb-2 kernel. Signed-off-by: Dave Martin Acked-by: Nicolas Pitre Signed-off-by: Russell King --- arch/arm/Kconfig | 31 +++++++++++++++++++++++++++++++ arch/arm/Makefile | 4 ++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2fec7073f68..f871f2e1dd7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1379,6 +1379,37 @@ config THUMB2_KERNEL If unsure, say N. +config THUMB2_AVOID_R_ARM_THM_JUMP11 + bool "Work around buggy Thumb-2 short branch relocations in gas" + depends on THUMB2_KERNEL && MODULES + default y + help + Various binutils versions can resolve Thumb-2 branches to + locally-defined, preemptible global symbols as short-range "b.n" + branch instructions. + + This is a problem, because there's no guarantee the final + destination of the symbol, or any candidate locations for a + trampoline, are within range of the branch. For this reason, the + kernel does not support fixing up the R_ARM_THM_JUMP11 (102) + relocation in modules at all, and it makes little sense to add + support. + + The symptom is that the kernel fails with an "unsupported + relocation" error when loading some modules. + + Until fixed tools are available, passing + -fno-optimize-sibling-calls to gcc should prevent gcc generating + code which hits this problem, at the cost of a bit of extra runtime + stack usage in some cases. + + The problem is described in more detail at: + https://bugs.launchpad.net/binutils-linaro/+bug/725126 + + Only Thumb-2 kernels are affected. + + Unless you are sure your tools don't have this problem, say Y. + config ARM_ASM_UNIFIED bool diff --git a/arch/arm/Makefile b/arch/arm/Makefile index da525bc9614..6d611f407ce 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -105,6 +105,10 @@ AFLAGS_AUTOIT :=$(call as-option,-Wa$(comma)-mimplicit-it=always,-Wa$(comma)-mau AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W) CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN) AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb +# Work around buggy relocation from gas if requested: +ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y) +CFLAGS_MODULE +=-fno-optimize-sibling-calls +endif endif # Need -Uarm for gcc < 3.x -- cgit v1.2.3 From 10a8c3839810ac9af1aec836d61b92e7a879f5fa Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Mon, 14 Mar 2011 14:00:30 +0100 Subject: ARM: 6806/1: irq: introduce entry and exit functions for chained handlers Some chained IRQ handlers are written to cope with primary chips of potentially different flow types. Whether this a sensible thing to do is a point of contention. This patch introduces entry/exit functions for chained handlers which infer the flow type of the primary chip as fasteoi or level-type by checking whether or not the ->irq_eoi function pointer is present and calling back to the primary chip as necessary. Other methods of flow control are not considered. Acked-by: Thomas Gleixner Acked-by: Catalin Marinas Signed-off-by: Will Deacon Signed-off-by: Russell King --- arch/arm/include/asm/mach/irq.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h index 22ac140edd9..febe495d0c6 100644 --- a/arch/arm/include/asm/mach/irq.h +++ b/arch/arm/include/asm/mach/irq.h @@ -34,4 +34,35 @@ do { \ raw_spin_unlock(&desc->lock); \ } while(0) +#ifndef __ASSEMBLY__ +/* + * Entry/exit functions for chained handlers where the primary IRQ chip + * may implement either fasteoi or level-trigger flow control. + */ +static inline void chained_irq_enter(struct irq_chip *chip, + struct irq_desc *desc) +{ + /* FastEOI controllers require no action on entry. */ + if (chip->irq_eoi) + return; + + if (chip->irq_mask_ack) { + chip->irq_mask_ack(&desc->irq_data); + } else { + chip->irq_mask(&desc->irq_data); + if (chip->irq_ack) + chip->irq_ack(&desc->irq_data); + } +} + +static inline void chained_irq_exit(struct irq_chip *chip, + struct irq_desc *desc) +{ + if (chip->irq_eoi) + chip->irq_eoi(&desc->irq_data); + else + chip->irq_unmask(&desc->irq_data); +} +#endif + #endif -- cgit v1.2.3