From 76eb5567afd18aa0a61fd31cd80fb80b616aaba4 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 12 Jul 2012 17:29:54 +0900 Subject: ARM: EXYNOS: read initial state of power domain from hw registers Some bootloaders disable unused power domains to reduce power consuption. Power domain driver can easily read the actual state from the hardware registers instead of assuming that their initial state is always 'on'. Signed-off-by: Marek Szyprowski Reviewed-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/pm_domains.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index e9fafcf163d..0a952a5c45b 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -151,9 +151,12 @@ static __init int exynos4_pm_init_power_domain(void) if (of_have_populated_dt()) return exynos_pm_dt_parse_domains(); - for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) - pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL, - exynos4_pm_domains[idx]->is_off); + for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) { + struct exynos_pm_domain *pd = exynos4_pm_domains[idx]; + int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; + + pm_genpd_init(&pd->pd, NULL, !on); + } #ifdef CONFIG_S5P_DEV_FIMD0 exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0); -- cgit v1.2.3 From ebc35c726298ba3fdebba316a592735268a520bc Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Thu, 12 Jul 2012 17:29:55 +0900 Subject: ARM: EXYNOS: register devices in 'need_restore' state for pm_domains Commit ca1d72f033 ('PM / Domains: Make it possible to add devices to inactive domains') introduced possibility to add devices to inactive power domains and added pm_genpd_dev_need_restore() function which lets platform core to notify power domain core that the specified device must be restored (with its runtime_resume() callback) before first use. This patch adds the pm_genpd_dev_need_restore() call what brings back the suspend/resume behaviour for the client devices known from the previous power domain driver (removed by commit 91cfbd4ee0 - 'ARM: EXYNOS: Hook up power domains to generic power domain infrastructure'). Client device drivers relay on that suspend/resume behaviour, thus this patch fixes runtime pm operation for client devices. Signed-off-by: Marek Szyprowski Reviewed-by: Kyungmin Park Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/pm_domains.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 0a952a5c45b..373c3c00d24 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -119,7 +119,9 @@ static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, struct exynos_pm_domain *pd) { if (pdev->dev.bus) { - if (pm_genpd_add_device(&pd->pd, &pdev->dev)) + if (!pm_genpd_add_device(&pd->pd, &pdev->dev)) + pm_genpd_dev_need_restore(&pdev->dev, true); + else pr_info("%s: error in adding %s device to %s power" "domain\n", __func__, dev_name(&pdev->dev), pd->name); -- cgit v1.2.3 From bdd3cc26ba651e33780ade33f1410320cf2d0cf4 Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Thu, 12 Jul 2012 18:06:28 +0900 Subject: ARM: SAMSUNG: Update default rate for xusbxti clock The rate of xusbxti clock is set in individual machine files. The default value should be defined at the clock definition and individual machine files should modify it if required. Division by zero in kernel. [] (unwind_backtrace+0x1/0x9c) from [] (Ldiv0+0x9/0x12) [] (Ldiv0+0x9/0x12) from [] (s3c_setrate_clksrc+0x33/0x78) [] (s3c_setrate_clksrc+0x33/0x78) from [] (clk_set_rate+0x2f/0x78) Signed-off-by: Tushar Behera Cc: Stable Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/s5p-clock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c index 031a61899be..48a15991103 100644 --- a/arch/arm/plat-samsung/s5p-clock.c +++ b/arch/arm/plat-samsung/s5p-clock.c @@ -37,6 +37,7 @@ struct clk clk_ext_xtal_mux = { struct clk clk_xusbxti = { .name = "xusbxti", .id = -1, + .rate = 24000000, }; struct clk s5p_clk_27m = { -- cgit v1.2.3 From 8265981bb439f3ecc5356fb877a6c2a6636ac88a Mon Sep 17 00:00:00 2001 From: Todd Poynor Date: Fri, 13 Jul 2012 15:30:48 +0900 Subject: ARM: SAMSUNG: fix race in s3c_adc_start for ADC Checking for adc->ts_pend already claimed should be done with the lock held. Signed-off-by: Todd Poynor Acked-by: Ben Dooks Cc: Stable Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/adc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 33ecd0c9f0c..b1e05ccff3a 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -157,11 +157,13 @@ int s3c_adc_start(struct s3c_adc_client *client, return -EINVAL; } - if (client->is_ts && adc->ts_pend) - return -EAGAIN; - spin_lock_irqsave(&adc->lock, flags); + if (client->is_ts && adc->ts_pend) { + spin_unlock_irqrestore(&adc->lock, flags); + return -EAGAIN; + } + client->channel = channel; client->nr_samples = nr_samples; -- cgit v1.2.3 From bb1488024786597ffe60971645ce9097af78f972 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Fri, 13 Jul 2012 17:48:56 +0900 Subject: ARM: S3C24XX: Correct AC97 clock control bit for S3C2440 Use correct gate control bit for AC97 clock which is S3C2440_CLKCON_AC97, not S3C2440_CLKCON_CAMERA. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/mach-s3c24xx/clock-s3c2440.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c index 414364eb426..cb2883d553b 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c @@ -106,7 +106,7 @@ static struct clk s3c2440_clk_cam_upll = { static struct clk s3c2440_clk_ac97 = { .name = "ac97", .enable = s3c2410_clkcon_enable, - .ctrlbit = S3C2440_CLKCON_CAMERA, + .ctrlbit = S3C2440_CLKCON_AC97, }; static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) -- cgit v1.2.3 From 705c75e3a1785d9d3acdf1b0b3a3afb10e943b15 Mon Sep 17 00:00:00 2001 From: Sylwester Nawrocki Date: Fri, 13 Jul 2012 17:48:56 +0900 Subject: ARM: S3C24XX: Correct CAMIF interrupt definitions Properly define the CAMIF interrupt resources. This device have two interrupts - corresponding to the "codec" and "preview" data paths. IRQ_CAM is handled internally by the architecture and demultiplexed to IRQ_S3C2440_CAM_C and IRQ_S3C2440_CAM_P - these interrupts only should be handled in the driver. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/devs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 1d214cb9d77..6303974c2ee 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c @@ -126,7 +126,8 @@ struct platform_device s3c_device_adc = { #ifdef CONFIG_CPU_S3C2440 static struct resource s3c_camif_resource[] = { [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), - [1] = DEFINE_RES_IRQ(IRQ_CAM), + [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C), + [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P), }; struct platform_device s3c_device_camif = { -- cgit v1.2.3