From e840431742d3fb90b3e396204b1a03e76920e879 Mon Sep 17 00:00:00 2001 From: roger nilsson Date: Mon, 5 Dec 2011 13:08:59 +0100 Subject: misc: Remove obsolete header file The msp_i2s header file was a duplicate to: arch/arm/mach-ux500/include/mach/msp.h The asoc drivers now use the correct header file. ST-Ericsson ID: 361991 ST-Ericsson Linux next: NA ST-Ericsson FOSS-OUT ID: NA Change-Id: I8bd4e67ba149b12f9008012d98cb6d0c8481c5a4 Signed-off-by: roger nilsson Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/41032 Reviewed-by: QABUILD Reviewed-by: Ola LILJA2 --- arch/arm/mach-ux500/include/mach/msp.h | 16 +- drivers/misc/i2s/msp_i2s.c | 2 +- drivers/misc/i2s/msp_i2s.h | 362 --------------------------------- sound/soc/codecs/ab8500_audio.c | 2 +- sound/soc/codecs/av8100_audio.c | 2 +- sound/soc/codecs/cg29xx.c | 2 +- sound/soc/ux500/ux500_ab5500.c | 2 +- sound/soc/ux500/ux500_ab8500.c | 11 +- sound/soc/ux500/ux500_av8100.c | 6 +- sound/soc/ux500/ux500_cg29xx.c | 10 +- sound/soc/ux500/ux500_msp_dai.c | 30 +-- 11 files changed, 37 insertions(+), 408 deletions(-) delete mode 100755 drivers/misc/i2s/msp_i2s.h diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h index 349943f247f..09f6a98a8fc 100644 --- a/arch/arm/mach-ux500/include/mach/msp.h +++ b/arch/arm/mach-ux500/include/mach/msp.h @@ -678,9 +678,9 @@ enum msp_expand_mode { MSP_DELAY_1, \ MSP_DELAY_1, \ MSP_RISING_EDGE, \ - MSP_RISING_EDGE, \ - MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ - MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ + MSP_FALLING_EDGE, \ + MSP_FRAME_SYNC_POL_ACTIVE_LOW, \ + MSP_FRAME_SYNC_POL_ACTIVE_LOW, \ MSP_HWS_NO_SWAP, \ MSP_HWS_NO_SWAP, \ MSP_COMPRESS_MODE_LINEAR, \ @@ -711,7 +711,7 @@ enum msp_expand_mode { MSP_ELEM_LENGTH_16, \ MSP_DELAY_0, \ MSP_DELAY_0, \ - MSP_FALLING_EDGE, \ + MSP_RISING_EDGE, \ MSP_FALLING_EDGE, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ @@ -746,7 +746,7 @@ enum msp_expand_mode { MSP_ELEM_LENGTH_8, \ MSP_DELAY_0, \ MSP_DELAY_0, \ - MSP_FALLING_EDGE, \ + MSP_RISING_EDGE, \ MSP_RISING_EDGE, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ @@ -784,7 +784,7 @@ enum msp_expand_mode { MSP_ELEM_LENGTH_20, \ MSP_DELAY_1, \ MSP_DELAY_1, \ - MSP_FALLING_EDGE, \ + MSP_RISING_EDGE, \ MSP_RISING_EDGE, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ @@ -818,7 +818,7 @@ enum msp_expand_mode { MSP_ELEM_LENGTH_8, \ MSP_DELAY_1, \ MSP_DELAY_1, \ - MSP_RISING_EDGE, \ + MSP_FALLING_EDGE, \ MSP_FALLING_EDGE, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ @@ -852,7 +852,7 @@ enum msp_expand_mode { MSP_ELEM_LENGTH_8, \ MSP_DELAY_1, \ MSP_DELAY_1, \ - MSP_RISING_EDGE, \ + MSP_FALLING_EDGE, \ MSP_FALLING_EDGE, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ MSP_FRAME_SYNC_POL_ACTIVE_HIGH, \ diff --git a/drivers/misc/i2s/msp_i2s.c b/drivers/misc/i2s/msp_i2s.c index c69ee708265..f5e3e00b894 100644 --- a/drivers/misc/i2s/msp_i2s.c +++ b/drivers/misc/i2s/msp_i2s.c @@ -368,7 +368,7 @@ static int configure_protocol(struct msp *msp, * them. */ temp_reg = stm_msp_read(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; - temp_reg |= MSP_TX_CLKPOL_BIT(protocol_desc->tx_clock_pol); + temp_reg |= MSP_TX_CLKPOL_BIT(~protocol_desc->tx_clock_pol); stm_msp_write(temp_reg, msp->registers + MSP_GCR); temp_reg = stm_msp_read(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; temp_reg |= MSP_RX_CLKPOL_BIT(protocol_desc->rx_clock_pol); diff --git a/drivers/misc/i2s/msp_i2s.h b/drivers/misc/i2s/msp_i2s.h deleted file mode 100755 index 3fcb92867e2..00000000000 --- a/drivers/misc/i2s/msp_i2s.h +++ /dev/null @@ -1,362 +0,0 @@ -/*----------------------------------------------------------------------------------*/ -/* copyright STMicroelectronics, 2007. */ -/* */ -/* This program is free software; you can redistribute it and/or modify it under */ -/* the terms of the GNU General Public License as published by the Free */ -/* Software Foundation; either version 2.1 of the License, or (at your option) */ -/* any later version. */ -/* */ -/* This program is distributed in the hope that it will be useful, but WITHOUT */ -/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS */ -/* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. */ -/* */ -/* You should have received a copy of the GNU General Public License */ -/* along with this program. If not, see . */ -/*----------------------------------------------------------------------------------*/ - - -#ifndef STM_MSP_HEADER -#define STM_MSP_HEADER - -#define MSP_DR 0x00 -#define MSP_GCR 0x04 -#define MSP_TCF 0x08 -#define MSP_RCF 0x0c -#define MSP_SRG 0x10 -#define MSP_FLR 0x14 -#define MSP_DMACR 0x18 - -#define MSP_IMSC 0x20 -#define MSP_RIS 0x24 -#define MSP_MIS 0x28 -#define MSP_ICR 0x2c -#define MSP_MCR 0x30 -#define MSP_RCV 0x34 -#define MSP_RCM 0x38 - -#define MSP_TCE0 0x40 -#define MSP_TCE1 0x44 -#define MSP_TCE2 0x48 -#define MSP_TCE3 0x4c - -#define MSP_RCE0 0x60 -#define MSP_RCE1 0x64 -#define MSP_RCE2 0x68 -#define MSP_RCE3 0x6c - -#define MSP_ITCR 0x80 -#define MSP_ITIP 0x84 -#define MSP_ITOP 0x88 -#define MSP_TSTDR 0x8c - -#define MSP_PID0 0xfe0 -#define MSP_PID1 0xfe4 -#define MSP_PID2 0xfe8 -#define MSP_PID3 0xfec - -#define MSP_CID0 0xff0 -#define MSP_CID1 0xff4 -#define MSP_CID2 0xff8 -#define MSP_CID3 0xffc - - -/* Single or dual phase mode */ -enum -{ - MSP_SINGLE_PHASE, - MSP_DUAL_PHASE -}; - - -/* Transmit/Receive shifter status ------------------------------------*/ -enum -{ - MSP_SxHIFTER_IDLE = 0, - MSP_SHIFTER_WORKING = 1 -}; - - -/* Transmit/Receive FIFO status ----------------------------------*/ -enum -{ - MSP_FIFO_FULL, - MSP_FIFO_PART_FILLED, - MSP_FIFO_EMPTY -}; - - -/* Frame length -------------------*/ -enum -{ - MSP_FRAME_LENGTH_1 = 0, - MSP_FRAME_LENGTH_2 = 1, - MSP_FRAME_LENGTH_4 = 3, - MSP_FRAME_LENGTH_8 = 7, - MSP_FRAME_LENGTH_12 = 11, - MSP_FRAME_LENGTH_16 = 15, - MSP_FRAME_LENGTH_20 = 19, - MSP_FRAME_LENGTH_32 = 31, - MSP_FRAME_LENGTH_48 = 47, - MSP_FRAME_LENGTH_64 = 63 -}; - -/* Element length */ -enum -{ - MSP_ELEM_LENGTH_8 = 0, - MSP_ELEM_LENGTH_10 = 1, - MSP_ELEM_LENGTH_12 = 2, - MSP_ELEM_LENGTH_14 = 3, - MSP_ELEM_LENGTH_16 = 4, - MSP_ELEM_LENGTH_20 = 5, - MSP_ELEM_LENGTH_24 = 6, - MSP_ELEM_LENGTH_32 = 7 -}; - - -/* Data delay (in bit clock cycles) ----------------------------------------*/ -enum -{ - MSP_DELAY_0 = 0, - MSP_DELAY_1 = 1, - MSP_DELAY_2 = 2, - MSP_DELAY_3 = 3 -}; - - -/* Configurations of clocks (transmit, receive or sample rate generator) --------------------------------------------------------------------------*/ -enum -{ - MSP_RISING_EDGE = 0, - MSP_FALLING_EDGE = 1 -}; - -/* Protocol dependant parameters list */ -struct msp_protocol_desc -{ - u32 phase_mode; - u32 frame_len_1; - u32 frame_len_2; - u32 element_len_1; - u32 element_len_2; - u32 data_delay; - u32 tx_clock_edge; - u32 rx_clock_edge; -}; -#define RX_ENABLE_MASK 0x00000001 -#define RX_FIFO_ENABLE_MASK 0x00000002 -#define RX_FRAME_SYNC_MASK 0x00000004 -#define DIRECT_COMPANDING_MASK 0x00000008 -#define RX_SYNC_SEL_MASK 0x00000010 -#define RX_CLK_POL_MASK 0x00000020 -#define RX_CLK_SEL_MASK 0x00000040 -#define LOOPBACK_MASK 0x00000080 -#define TX_ENABLE_MASK 0x00000100 -#define TX_FIFO_ENABLE_MASK 0x00000200 -#define TX_FRAME_SYNC_MASK 0x00000400 -#define TX_MSP_TDR_TSR 0x00000800 -#define TX_SYNC_SEL_MASK 0x00001800 -#define TX_CLK_POL_MASK 0x00002000 -#define TX_CLK_SEL_MASK 0x00004000 -#define TX_EXTRA_DELAY_MASK 0x00008000 -#define SRG_ENABLE_MASK 0x00010000 -#define SRG_CLK_POL_MASK 0x00020000 -#define SRG_CLK_SEL_MASK 0x000C0000 -#define FRAME_GEN_EN_MASK 0x00100000 -#define SPI_CLK_MODE_MASK 0x00600000 -#define SPI_BURST_MODE_MASK 0x00800000 - -#define RXEN_BIT 0 -#define RFFEN_BIT 1 -#define RFSPOL_BIT 2 -#define DCM_BIT 3 -#define RFSSEL_BIT 4 -#define RCKPOL_BIT 5 -#define RCKSEL_BIT 6 -#define LBM_BIT 7 -#define TXEN_BIT 8 -#define TFFEN_BIT 9 -#define TFSPOL_BIT 10 -#define TFSSEL_BIT 11 -#define TCKPOL_BIT 13 -#define TCKSEL_BIT 14 -#define TXDDL_BIT 15 -#define SGEN_BIT 16 -#define SCKPOL_BIT 17 -#define SCKSEL_BIT 18 -#define FGEN_BIT 20 -#define SPICKM_BIT 21 - -#define msp_rx_clkpol_bit(n) ((n & 1) << RCKPOL_BIT) -#define msp_tx_clkpol_bit(n) ((n & 1) << TCKPOL_BIT) -#define msp_spi_clk_mode_bits(n) ((n & 3) << SPICKM_BIT) - - -/* Use this to clear the clock mode bits to non-spi */ -#define MSP_NON_SPI_CLK_MASK 0x00600000 - -#define P1ELEN_BIT 0 -#define P1FLEN_BIT 3 -#define DTYP_BIT 10 -#define ENDN_BIT 12 -#define DDLY_BIT 13 -#define FSIG_BIT 15 -#define P2ELEN_BIT 16 -#define P2FLEN_BIT 19 -#define P2SM_BIT 26 -#define P2EN_BIT 27 - -#define msp_p1_elem_len_bits(n) (n & 0x00000007) -#define msp_p2_elem_len_bits(n) (((n) << P2ELEN_BIT) & 0x00070000) -#define msp_p1_frame_len_bits(n) (((n) << P1FLEN_BIT) & 0x00000378) -#define msp_p2_frame_len_bits(n) (((n) << P2FLEN_BIT) & 0x03780000) -#define msp_data_delay_bits(n) (((n) << DDLY_BIT) & 0x00003000) -#define msp_data_type_bits(n) (((n) << DTYP_BIT) & 0x00000600) -#define msp_p2_start_mode_bit(n) (n << P2SM_BIT) -#define msp_p2_enable_bit(n) (n << P2EN_BIT) - -/* Flag register ---------------------*/ -#define RX_BUSY 0x00000001 -#define RX_FIFO_EMPTY 0x00000002 -#define RX_FIFO_FULL 0x00000004 -#define TX_BUSY 0x00000008 -#define TX_FIFO_EMPTY 0x00000010 -#define TX_FIFO_FULL 0x00000020 - -#define RBUSY_BIT 0 -#define RFE_BIT 1 -#define RFU_BIT 2 -#define TBUSY_BIT 3 -#define TFE_BIT 4 -#define TFU_BIT 5 - -/* Multichannel control register ----------------------------------*/ -#define RMCEN_BIT 0 -#define RMCSF_BIT 1 -#define RCMPM_BIT 3 -#define TMCEN_BIT 5 -#define TNCSF_BIT 6 - -/* Sample rate generator register -------------------------------------*/ -#define SCKDIV_BIT 0 -#define FRWID_BIT 10 -#define FRPER_BIT 16 - -#define SCK_DIV_MASK 0x0000003FF -#define frame_width_bits(n) (((n) << FRWID_BIT) &0x0000FC00) -#define frame_period_bits(n) (((n) << FRPER_BIT) &0x1FFF0000) - - -/* DMA controller register ----------------------------*/ -#define RX_DMA_ENABLE 0x00000001 -#define TX_DMA_ENABLE 0x00000002 - -#define RDMAE_BIT 0 -#define TDMAE_BIT 1 - -/*Interrupt Register ------------------------------------------*/ -#define RECEIVE_SERVICE_INT 0x00000001 -#define RECEIVE_OVERRUN_ERROR_INT 0x00000002 -#define RECEIVE_FRAME_SYNC_ERR_INT 0x00000004 -#define RECEIVE_FRAME_SYNC_INT 0x00000008 -#define TRANSMIT_SERVICE_INT 0x00000010 -#define TRANSMIT_UNDERRUN_ERR_INT 0x00000020 -#define TRANSMIT_FRAME_SYNC_ERR_INT 0x00000040 -#define TRANSMIT_FRAME_SYNC_INT 0x00000080 -#define ALL_INT 0x000000ff - -/* Protocol configuration values -* I2S: Single phase, 16 bits, 2 words per frame ------------------------------------------------*/ -#define I2S_PROTOCOL_DESC \ -{ \ - MSP_SINGLE_PHASE, \ - MSP_FRAME_LENGTH_1, \ - MSP_FRAME_LENGTH_1, \ - MSP_ELEM_LENGTH_32, \ - MSP_ELEM_LENGTH_32, \ - MSP_DELAY_1, \ - MSP_FALLING_EDGE, \ - MSP_FALLING_EDGE \ -} - -#define PCM_PROTOCOL_DESC \ -{ \ - MSP_SINGLE_PHASE, \ - MSP_FRAME_LENGTH_1, \ - MSP_FRAME_LENGTH_1, \ - MSP_ELEM_LENGTH_16, \ - MSP_ELEM_LENGTH_16, \ - MSP_DATA_DELAY, \ - MSP_TX_CLOCK_EDGE, \ - MSP_RX_CLOCK_EDGE \ -} - -/* Companded PCM: Single phase, 8 bits, 1 word per frame ---------------------------------------------------------*/ -#define PCM_COMPAND_PROTOCOL_DESC \ -{ \ - MSP_SINGLE_PHASE, \ - MSP_FRAME_LENGTH_1, \ - MSP_FRAME_LENGTH_1, \ - MSP_ELEM_LENGTH_8, \ - MSP_ELEM_LENGTH_8, \ - MSP_DELAY_0, \ - MSP_RISING_EDGE, \ - MSP_FALLING_EDGE \ -} - -/* AC97: Double phase, 1 element of 16 bits during first phase, -* 12 elements of 20 bits in second phase. ---------------------------------------------------------------*/ -#define AC97_PROTOCOL_DESC \ -{ \ - MSP_DUAL_PHASE, \ - MSP_FRAME_LENGTH_1, \ - MSP_FRAME_LENGTH_12, \ - MSP_ELEM_LENGTH_16, \ - MSP_ELEM_LENGTH_20, \ - MSP_DELAY_1, \ - MSP_RISING_EDGE, \ - MSP_FALLING_EDGE \ -} - -#define SPI_MASTER_PROTOCOL_DESC \ -{ \ - MSP_SINGLE_PHASE, \ - MSP_FRAME_LENGTH_1, \ - MSP_FRAME_LENGTH_1, \ - MSP_ELEM_LENGTH_8, \ - MSP_ELEM_LENGTH_8, \ - MSP_DELAY_1, \ - MSP_FALLING_EDGE, \ - MSP_RISING_EDGE \ -} -#define SPI_SLAVE_PROTOCOL_DESC \ -{ \ - MSP_SINGLE_PHASE, \ - MSP_FRAME_LENGTH_1, \ - MSP_FRAME_LENGTH_1, \ - MSP_ELEM_LENGTH_8, \ - MSP_ELEM_LENGTH_8, \ - MSP_DELAY_1, \ - MSP_FALLING_EDGE, \ - MSP_RISING_EDGE \ -} - -#define MSP_FRAME_PERIOD_IN_MONO_MODE 256 -#define MSP_FRAME_PERIOD_IN_STEREO_MODE 32 -#define MSP_FRAME_WIDTH_IN_STEREO_MODE 16 - -#endif - diff --git a/sound/soc/codecs/ab8500_audio.c b/sound/soc/codecs/ab8500_audio.c index 3bc13ef1f4e..078e068b728 100644 --- a/sound/soc/codecs/ab8500_audio.c +++ b/sound/soc/codecs/ab8500_audio.c @@ -2589,7 +2589,7 @@ static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) break; case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */ pr_debug("%s: IF0 Protocol: DSP A (TDM)\n", __func__); - set_mask |= BMASK(REG_DIGIFCONF2_IF0FORMAT1); + set_mask |= BMASK(REG_DIGIFCONF2_IF0FORMAT0); break; case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */ pr_debug("%s: IF0 Protocol: DSP B (TDM)\n", __func__); diff --git a/sound/soc/codecs/av8100_audio.c b/sound/soc/codecs/av8100_audio.c index 2b4b526cfe1..bca5b7a4329 100644 --- a/sound/soc/codecs/av8100_audio.c +++ b/sound/soc/codecs/av8100_audio.c @@ -342,7 +342,7 @@ static int av8100_codec_set_dai_fmt(struct snd_soc_dai *codec_dai, /* Set the audio input format of AV8100 */ config.audio_input_format.audio_input_if_format = - ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_B) ? + ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) ? AV8100_AUDIO_TDM_MODE : AV8100_AUDIO_I2SDELAYED_MODE; config.audio_input_format.audio_if_mode = ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM) ? diff --git a/sound/soc/codecs/cg29xx.c b/sound/soc/codecs/cg29xx.c index b5461c3e214..ec79cdae91b 100644 --- a/sound/soc/codecs/cg29xx.c +++ b/sound/soc/codecs/cg29xx.c @@ -215,7 +215,7 @@ static int cg29xx_set_dai_fmt(struct snd_soc_dai *codec_dai, dai_data->config.conf.i2s.mode = DAI_MODE_SLAVE; break; - case SND_SOC_DAIFMT_DSP_A: + case SND_SOC_DAIFMT_DSP_B: if (dai_data->config.port != PORT_1_I2S_PCM || msel == SND_SOC_DAIFMT_CBM_CFM) { pr_err("cg29xx_dai: unsupported DAI format 0x%x port=%d,msel=%d\n", diff --git a/sound/soc/ux500/ux500_ab5500.c b/sound/soc/ux500/ux500_ab5500.c index 5b4e5576cf0..6dbf72e9153 100644 --- a/sound/soc/ux500/ux500_ab5500.c +++ b/sound/soc/ux500/ux500_ab5500.c @@ -53,7 +53,7 @@ int ux500_ab5500_hw_params(struct snd_pcm_substream *substream, ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM | - SND_SOC_DAIFMT_IB_IF); + SND_SOC_DAIFMT_NB_NF); if (ret < 0) return ret; ux500_msp_dai_set_data_delay(cpu_dai, MSP_DELAY_1); diff --git a/sound/soc/ux500/ux500_ab8500.c b/sound/soc/ux500/ux500_ab8500.c index 2eef499d22e..5860e05a1dd 100644 --- a/sound/soc/ux500/ux500_ab8500.c +++ b/sound/soc/ux500/ux500_ab8500.c @@ -525,17 +525,18 @@ int ux500_ab8500_hw_params(struct snd_pcm_substream *substream, pr_debug("%s: Driver-mode: %s.\n", __func__, (driver_mode == DRIVERMODE_NORMAL) ? "NORMAL" : "CODEC_ONLY"); + + ab8500_audio_set_bit_delay(codec_dai, 1); + if (driver_mode == DRIVERMODE_NORMAL) { - ab8500_audio_set_bit_delay(codec_dai, 0); ab8500_audio_set_word_length(codec_dai, 16); - fmt = SND_SOC_DAIFMT_DSP_B | + fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CONT; } else { - ab8500_audio_set_bit_delay(codec_dai, 1); ab8500_audio_set_word_length(codec_dai, 20); - fmt = SND_SOC_DAIFMT_DSP_B | + fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_GATED; @@ -557,6 +558,8 @@ int ux500_ab8500_hw_params(struct snd_pcm_substream *substream, return ret; } + ux500_msp_dai_set_data_delay(cpu_dai, MSP_DELAY_1); + /* Setup TDM-slots */ streamIsPlayback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); diff --git a/sound/soc/ux500/ux500_av8100.c b/sound/soc/ux500/ux500_av8100.c index a1be8d15c72..becf81a07e0 100644 --- a/sound/soc/ux500/ux500_av8100.c +++ b/sound/soc/ux500/ux500_av8100.c @@ -112,7 +112,7 @@ static int ux500_av8100_hw_params(struct snd_pcm_substream *substream, } /* Set format for codec-DAI */ - fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBM_CFM; + fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM; pr_debug("%s: Setting format for codec-DAI (fmt = %d).\n", __func__, fmt); @@ -139,7 +139,7 @@ static int ux500_av8100_hw_params(struct snd_pcm_substream *substream, } /* Set format for CPU-DAI */ - fmt = SND_SOC_DAIFMT_DSP_B | + fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_IF; pr_debug("%s: Setting DAI-format for Ux500-platform (fmt = %d).\n", @@ -154,8 +154,6 @@ static int ux500_av8100_hw_params(struct snd_pcm_substream *substream, return ret; } - ux500_msp_dai_set_data_delay(cpu_dai, MSP_DELAY_1); - return ret; } diff --git a/sound/soc/ux500/ux500_cg29xx.c b/sound/soc/ux500/ux500_cg29xx.c index 8301a80f54d..bb95bc2c306 100644 --- a/sound/soc/ux500/ux500_cg29xx.c +++ b/sound/soc/ux500/ux500_cg29xx.c @@ -19,7 +19,7 @@ #define UX500_CG29XX_MSP_CLOCK_FREQ 18900000 #define UX500_CG29XX_DAI_SLOT_WIDTH 16 #define UX500_CG29XX_DAI_SLOTS 2 -#define UX500_CG29XX_DAI_ACTIVE_SLOTS 0x01 +#define UX500_CG29XX_DAI_ACTIVE_SLOTS 0x02 int ux500_cg29xx_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) @@ -40,7 +40,7 @@ int ux500_cg29xx_hw_params(struct snd_pcm_substream *substream, pr_debug("%s: DAI-index (Platform): %d\n", __func__, cpu_dai->id); err = snd_soc_dai_set_fmt(codec_dai, - SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS); + SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS); if (err) { pr_err("%s: snd_soc_dai_set_fmt(codec) failed with %d.\n", @@ -63,7 +63,7 @@ int ux500_cg29xx_hw_params(struct snd_pcm_substream *substream, } err = snd_soc_dai_set_fmt(cpu_dai, - SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS | + SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_NB_NF); if (err) { @@ -148,7 +148,7 @@ int u5500_cg29xx_hw_params(struct snd_pcm_substream *substream, } } else { err = snd_soc_dai_set_fmt(codec_dai, - SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS); + SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS); if (err) { pr_err("%s: snd_soc_dai_set_fmt(codec) failed with %d.\n", __func__, @@ -170,7 +170,7 @@ int u5500_cg29xx_hw_params(struct snd_pcm_substream *substream, } err = snd_soc_dai_set_fmt(cpu_dai, - SND_SOC_DAIFMT_DSP_A | + SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_CBS_CFS | SND_SOC_DAIFMT_NB_NF); diff --git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c index 1eb8cf88323..6cdc96734ed 100644 --- a/sound/soc/ux500/ux500_msp_dai.c +++ b/sound/soc/ux500/ux500_msp_dai.c @@ -339,32 +339,18 @@ static void ux500_msp_dai_setup_clocking(unsigned int fmt, switch (fmt & SND_SOC_DAIFMT_INV_MASK) { default: case SND_SOC_DAIFMT_NB_NF: - msp_config->tx_frame_sync_pol = - MSP_FRAME_SYNC_POL(MSP_FRAME_SYNC_POL_ACTIVE_HIGH); - msp_config->rx_frame_sync_pol = - MSP_FRAME_SYNC_POL_ACTIVE_HIGH << RFSPOL_SHIFT; break; case SND_SOC_DAIFMT_NB_IF: - msp_config->tx_frame_sync_pol = - MSP_FRAME_SYNC_POL(MSP_FRAME_SYNC_POL_ACTIVE_LOW); - msp_config->rx_frame_sync_pol = - MSP_FRAME_SYNC_POL_ACTIVE_LOW << RFSPOL_SHIFT; - break; - - case SND_SOC_DAIFMT_IB_IF: - msp_config->iodelay = 0x20; - msp_config->protocol_desc.tx_clock_pol = 1; - msp_config->tx_frame_sync_pol = 1 << TFSPOL_SHIFT; - msp_config->protocol_desc.rx_clock_pol = 1; - msp_config->rx_frame_sync_pol = 1 << RFSPOL_SHIFT; + msp_config->tx_frame_sync_pol ^= 1 << TFSPOL_SHIFT; + msp_config->rx_frame_sync_pol ^= 1 << RFSPOL_SHIFT; break; } if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM) { pr_debug("%s: Codec is MASTER.\n", __func__); - + msp_config->iodelay = 0x20; msp_config->rx_frame_sync_sel = 0; msp_config->tx_frame_sync_sel = 1 << TFSSEL_SHIFT; msp_config->tx_clock_sel = 0; @@ -392,17 +378,19 @@ static void ux500_msp_dai_compile_prot_desc_pcm(unsigned int fmt, prot_desc->tx_phase2_start_mode = MSP_PHASE2_START_MODE_IMEDIATE; prot_desc->rx_bit_transfer_format = MSP_BTF_MS_BIT_FIRST; prot_desc->tx_bit_transfer_format = MSP_BTF_MS_BIT_FIRST; + prot_desc->tx_frame_sync_pol = MSP_FRAME_SYNC_POL(MSP_FRAME_SYNC_POL_ACTIVE_HIGH); + prot_desc->rx_frame_sync_pol = MSP_FRAME_SYNC_POL_ACTIVE_HIGH << RFSPOL_SHIFT; if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) { pr_debug("%s: DSP_A.\n", __func__); + prot_desc->rx_clock_pol = MSP_RISING_EDGE; prot_desc->tx_clock_pol = MSP_FALLING_EDGE; - prot_desc->rx_clock_pol = MSP_FALLING_EDGE; } else { pr_debug("%s: DSP_B.\n", __func__); + prot_desc->rx_clock_pol = MSP_FALLING_EDGE; prot_desc->tx_clock_pol = MSP_RISING_EDGE; - prot_desc->rx_clock_pol = MSP_RISING_EDGE; } prot_desc->rx_half_word_swap = MSP_HWS_NO_SWAP; @@ -424,6 +412,8 @@ static void ux500_msp_dai_compile_prot_desc_i2s(struct msp_protocol_desc *prot_d MSP_PHASE2_START_MODE_FRAME_SYNC; prot_desc->rx_bit_transfer_format = MSP_BTF_MS_BIT_FIRST; prot_desc->tx_bit_transfer_format = MSP_BTF_MS_BIT_FIRST; + prot_desc->tx_frame_sync_pol = MSP_FRAME_SYNC_POL(MSP_FRAME_SYNC_POL_ACTIVE_LOW); + prot_desc->rx_frame_sync_pol = MSP_FRAME_SYNC_POL_ACTIVE_LOW << RFSPOL_SHIFT; prot_desc->rx_frame_length_1 = MSP_FRAME_LENGTH_1; prot_desc->rx_frame_length_2 = MSP_FRAME_LENGTH_1; @@ -435,7 +425,7 @@ static void ux500_msp_dai_compile_prot_desc_i2s(struct msp_protocol_desc *prot_d prot_desc->tx_element_length_2 = MSP_ELEM_LENGTH_16; prot_desc->rx_clock_pol = MSP_RISING_EDGE; - prot_desc->tx_clock_pol = MSP_RISING_EDGE; + prot_desc->tx_clock_pol = MSP_FALLING_EDGE; prot_desc->tx_half_word_swap = MSP_HWS_NO_SWAP; prot_desc->rx_half_word_swap = MSP_HWS_NO_SWAP; -- cgit v1.2.3