From 4330971889149f064e9af8e020fe098c628b627e Mon Sep 17 00:00:00 2001 From: Carlos Chinea Date: Tue, 14 Dec 2010 10:09:38 +0000 Subject: HSI: omap_ssi: Introducing OMAP SSI driver Introduces the OMAP SSI driver in the kernel. The Synchronous Serial Interface (SSI) is a legacy version of HSI. As in the case of HSI, it is mainly used to connect Application engines (APE) with cellular modem engines (CMT) in cellular handsets. It provides a multichannel, full-duplex, multi-core communication with no reference clock. The OMAP SSI block is capable of reaching speeds of 110 Mbit/s. Change-Id: Iea002a8f321cf66ab439552620af001206626ed6 Signed-off-by: Carlos Chinea Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/20576 Reviewed-by: Pawel SZYSZUK Tested-by: Pawel SZYSZUK Reviewed-by: Jonas ABERG --- arch/arm/mach-omap2/ssi.c | 134 ++++++++++++++++++++++ arch/arm/plat-omap/include/plat/ssi.h | 204 ++++++++++++++++++++++++++++++++++ 2 files changed, 338 insertions(+) create mode 100644 arch/arm/mach-omap2/ssi.c create mode 100644 arch/arm/plat-omap/include/plat/ssi.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/ssi.c b/arch/arm/mach-omap2/ssi.c new file mode 100644 index 00000000000..e822a77f5ca --- /dev/null +++ b/arch/arm/mach-omap2/ssi.c @@ -0,0 +1,134 @@ +/* + * linux/arch/arm/mach-omap2/ssi.c + * + * Copyright (C) 2010 Nokia Corporation. All rights reserved. + * + * Contact: Carlos Chinea + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +static struct omap_ssi_platform_data ssi_pdata = { + .num_ports = SSI_NUM_PORTS, + .get_dev_context_loss_count = omap_pm_get_dev_context_loss_count, +}; + +static struct resource ssi_resources[] = { + /* SSI controller */ + [0] = { + .start = 0x48058000, + .end = 0x48058fff, + .name = "omap_ssi_sys", + .flags = IORESOURCE_MEM, + }, + /* GDD */ + [1] = { + .start = 0x48059000, + .end = 0x48059fff, + .name = "omap_ssi_gdd", + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = 71, + .end = 71, + .name = "ssi_gdd", + .flags = IORESOURCE_IRQ, + }, + /* SSI port 1 */ + [3] = { + .start = 0x4805a000, + .end = 0x4805a7ff, + .name = "omap_ssi_sst1", + .flags = IORESOURCE_MEM, + }, + [4] = { + .start = 0x4805a800, + .end = 0x4805afff, + .name = "omap_ssi_ssr1", + .flags = IORESOURCE_MEM, + }, + [5] = { + .start = 67, + .end = 67, + .name = "ssi_p1_mpu_irq0", + .flags = IORESOURCE_IRQ, + }, + [6] = { + .start = 68, + .end = 68, + .name = "ssi_p1_mpu_irq1", + .flags = IORESOURCE_IRQ, + }, + [7] = { + .start = 0, + .end = 0, + .name = "ssi_p1_cawake", + .flags = IORESOURCE_IRQ | IORESOURCE_UNSET, + }, +}; + +static struct platform_device ssi_pdev = { + .name = "omap_ssi", + .id = 0, + .num_resources = ARRAY_SIZE(ssi_resources), + .resource = ssi_resources, + .dev = { + .platform_data = &ssi_pdata, + }, +}; + +int __init omap_ssi_config(struct omap_ssi_board_config *ssi_config) +{ + unsigned int port, offset, cawake_gpio; + int err; + + ssi_pdata.num_ports = ssi_config->num_ports; + for (port = 0, offset = 7; port < ssi_config->num_ports; + port++, offset += 5) { + cawake_gpio = ssi_config->cawake_gpio[port]; + if (!cawake_gpio) + continue; /* Nothing to do */ + err = gpio_request(cawake_gpio, "cawake"); + if (err < 0) + goto rback; + gpio_direction_input(cawake_gpio); + ssi_resources[offset].start = gpio_to_irq(cawake_gpio); + ssi_resources[offset].flags &= ~IORESOURCE_UNSET; + ssi_resources[offset].flags |= IORESOURCE_IRQ_HIGHEDGE | + IORESOURCE_IRQ_LOWEDGE; + } + + return 0; +rback: + dev_err(&ssi_pdev.dev, "Request cawake (gpio%d) failed\n", cawake_gpio); + while (port > 0) + gpio_free(ssi_config->cawake_gpio[--port]); + + return err; +} + +static int __init ssi_init(void) +{ + return platform_device_register(&ssi_pdev); +} +subsys_initcall(ssi_init); diff --git a/arch/arm/plat-omap/include/plat/ssi.h b/arch/arm/plat-omap/include/plat/ssi.h new file mode 100644 index 00000000000..eb84c3a69f7 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/ssi.h @@ -0,0 +1,204 @@ +/* + * plat/ssi.h + * + * Hardware definitions for SSI. + * + * Copyright (C) 2010 Nokia Corporation. All rights reserved. + * + * Contact: Carlos Chinea + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + */ + +#ifndef __OMAP_SSI_REGS_H__ +#define __OMAP_SSI_REGS_H__ + +#define SSI_NUM_PORTS 1 +/* + * SSI SYS registers + */ +#define SSI_REVISION_REG 0 +# define SSI_REV_MAJOR 0xf0 +# define SSI_REV_MINOR 0xf +#define SSI_SYSCONFIG_REG 0x10 +# define SSI_AUTOIDLE (1 << 0) +# define SSI_SOFTRESET (1 << 1) +# define SSI_SIDLEMODE_FORCE 0 +# define SSI_SIDLEMODE_NO (1 << 3) +# define SSI_SIDLEMODE_SMART (1 << 4) +# define SSI_SIDLEMODE_MASK 0x18 +# define SSI_MIDLEMODE_FORCE 0 +# define SSI_MIDLEMODE_NO (1 << 12) +# define SSI_MIDLEMODE_SMART (1 << 13) +# define SSI_MIDLEMODE_MASK 0x3000 +#define SSI_SYSSTATUS_REG 0x14 +# define SSI_RESETDONE 1 +#define SSI_MPU_STATUS_REG(port, irq) (0x808 + ((port) * 0x10) + ((irq) * 2)) +#define SSI_MPU_ENABLE_REG(port, irq) (0x80c + ((port) * 0x10) + ((irq) * 8)) +# define SSI_DATAACCEPT(channel) (1 << (channel)) +# define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) +# define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) +# define SSI_ERROROCCURED (1 << 24) +# define SSI_BREAKDETECTED (1 << 25) +#define SSI_GDD_MPU_IRQ_STATUS_REG 0x0800 +#define SSI_GDD_MPU_IRQ_ENABLE_REG 0x0804 +# define SSI_GDD_LCH(channel) (1 << (channel)) +#define SSI_WAKE_REG(port) (0xc00 + ((port) * 0x10)) +#define SSI_CLEAR_WAKE_REG(port) (0xc04 + ((port) * 0x10)) +#define SSI_SET_WAKE_REG(port) (0xc08 + ((port) * 0x10)) +# define SSI_WAKE(channel) (1 << (channel)) +# define SSI_WAKE_MASK 0xff + +/* + * SSI SST registers + */ +#define SSI_SST_ID_REG 0 +#define SSI_SST_MODE_REG 4 +# define SSI_MODE_VAL_MASK 3 +# define SSI_MODE_SLEEP 0 +# define SSI_MODE_STREAM 1 +# define SSI_MODE_FRAME 2 +# define SSI_MODE_MULTIPOINTS 3 +#define SSI_SST_FRAMESIZE_REG 8 +# define SSI_FRAMESIZE_DEFAULT 31 +#define SSI_SST_TXSTATE_REG 0xc +# define SSI_TXSTATE_IDLE 0 +#define SSI_SST_BUFSTATE_REG 0x10 +# define SSI_FULL(channel) (1 << (channel)) +#define SSI_SST_DIVISOR_REG 0x18 +# define SSI_MAX_DIVISOR 127 +#define SSI_SST_BREAK_REG 0x20 +#define SSI_SST_CHANNELS_REG 0x24 +# define SSI_CHANNELS_DEFAULT 4 +#define SSI_SST_ARBMODE_REG 0x28 +# define SSI_ARBMODE_ROUNDROBIN 0 +# define SSI_ARBMODE_PRIORITY 1 +#define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) +#define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) + +/* + * SSI SSR registers + */ +#define SSI_SSR_ID_REG 0 +#define SSI_SSR_MODE_REG 4 +#define SSI_SSR_FRAMESIZE_REG 8 +#define SSI_SSR_RXSTATE_REG 0xc +#define SSI_SSR_BUFSTATE_REG 0x10 +# define SSI_NOTEMPTY(channel) (1 << (channel)) +#define SSI_SSR_BREAK_REG 0x1c +#define SSI_SSR_ERROR_REG 0x20 +#define SSI_SSR_ERRORACK_REG 0x24 +#define SSI_SSR_OVERRUN_REG 0x2c +#define SSI_SSR_OVERRUNACK_REG 0x30 +#define SSI_SSR_TIMEOUT_REG 0x34 +# define SSI_TIMEOUT_DEFAULT 0 +#define SSI_SSR_CHANNELS_REG 0x28 +#define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) +#define SSI_SSR_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) + +/* + * SSI GDD registers + */ +#define SSI_GDD_HW_ID_REG 0 +#define SSI_GDD_PPORT_ID_REG 0x10 +#define SSI_GDD_MPORT_ID_REG 0x14 +#define SSI_GDD_PPORT_SR_REG 0x20 +#define SSI_GDD_MPORT_SR_REG 0x24 +# define SSI_ACTIVE_LCH_NUM_MASK 0xff +#define SSI_GDD_TEST_REG 0x40 +# define SSI_TEST 1 +#define SSI_GDD_GCR_REG 0x100 +# define SSI_CLK_AUTOGATING_ON (1 << 3) +# define SSI_FREE (1 << 2) +# define SSI_SWITCH_OFF (1 << 0) +#define SSI_GDD_GRST_REG 0x200 +# define SSI_SWRESET 1 +#define SSI_GDD_CSDP_REG(channel) (0x800 + ((channel) * 0x40)) +# define SSI_DST_BURST_EN_MASK 0xc000 +# define SSI_DST_SINGLE_ACCESS0 0 +# define SSI_DST_SINGLE_ACCESS (1 << 14) +# define SSI_DST_BURST_4x32_BIT (2 << 14) +# define SSI_DST_BURST_8x32_BIT (3 << 14) +# define SSI_DST_MASK 0x1e00 +# define SSI_DST_MEMORY_PORT (8 << 9) +# define SSI_DST_PERIPHERAL_PORT (9 << 9) +# define SSI_SRC_BURST_EN_MASK 0x180 +# define SSI_SRC_SINGLE_ACCESS0 0 +# define SSI_SRC_SINGLE_ACCESS (1 << 7) +# define SSI_SRC_BURST_4x32_BIT (2 << 7) +# define SSI_SRC_BURST_8x32_BIT (3 << 7) +# define SSI_SRC_MASK 0x3c +# define SSI_SRC_MEMORY_PORT (8 << 2) +# define SSI_SRC_PERIPHERAL_PORT (9 << 2) +# define SSI_DATA_TYPE_MASK 3 +# define SSI_DATA_TYPE_S32 2 +#define SSI_GDD_CCR_REG(channel) (0x802 + ((channel) * 0x40)) +# define SSI_DST_AMODE_MASK (3 << 14) +# define SSI_DST_AMODE_CONST 0 +# define SSI_DST_AMODE_POSTINC (1 << 12) +# define SSI_SRC_AMODE_MASK (3 << 12) +# define SSI_SRC_AMODE_CONST 0 +# define SSI_SRC_AMODE_POSTINC (1 << 12) +# define SSI_CCR_ENABLE (1 << 7) +# define SSI_CCR_SYNC_MASK 0x1f +#define SSI_GDD_CICR_REG(channel) (0x804 + ((channel) * 0x40)) +# define SSI_BLOCK_IE (1 << 5) +# define SSI_HALF_IE (1 << 2) +# define SSI_TOUT_IE (1 << 0) +#define SSI_GDD_CSR_REG(channel) (0x806 + ((channel) * 0x40)) +# define SSI_CSR_SYNC (1 << 6) +# define SSI_CSR_BLOCK (1 << 5) +# define SSI_CSR_HALF (1 << 2) +# define SSI_CSR_TOUR (1 << 0) +#define SSI_GDD_CSSA_REG(channel) (0x808 + ((channel) * 0x40)) +#define SSI_GDD_CDSA_REG(channel) (0x80c + ((channel) * 0x40)) +#define SSI_GDD_CEN_REG(channel) (0x810 + ((channel) * 0x40)) +#define SSI_GDD_CSAC_REG(channel) (0x818 + ((channel) * 0x40)) +#define SSI_GDD_CDAC_REG(channel) (0x81a + ((channel) * 0x40)) +#define SSI_GDD_CLNK_CTRL_REG(channel) (0x828 + ((channel) * 0x40)) +# define SSI_ENABLE_LNK (1 << 15) +# define SSI_STOP_LNK (1 << 14) +# define SSI_NEXT_CH_ID_MASK 0xf + +/** + * struct omap_ssi_platform_data - OMAP SSI platform data + * @num_ports: Number of ports on the controller + * @ctxt_loss_count: Pointer to omap_pm_get_dev_context_loss_count + */ +struct omap_ssi_platform_data { + unsigned int num_ports; + int (*get_dev_context_loss_count)(struct device *dev); +}; + +/** + * struct omap_ssi_config - SSI board configuration + * @num_ports: Number of ports in use + * @cawake_line: Array of cawake gpio lines + */ +struct omap_ssi_board_config { + unsigned int num_ports; + int cawake_gpio[SSI_NUM_PORTS]; +}; + +#ifdef CONFIG_OMAP_SSI_CONFIG +extern int omap_ssi_config(struct omap_ssi_board_config *ssi_config); +#else +static inline int omap_ssi_config(struct omap_ssi_board_config *ssi_config) +{ + return 0; +} +#endif /* CONFIG_OMAP_SSI_CONFIG */ + +#endif /* __OMAP_SSI_REGS_H__ */ -- cgit v1.2.3 From 8999e34d81e7949139cbabca57cde5429ed530fb Mon Sep 17 00:00:00 2001 From: Philippe Langlais Date: Tue, 19 Apr 2011 09:39:21 +0200 Subject: HSI: omap_ssi: Add OMAP SSI to the kernel configuration Add OMAP SSI device and driver to the kernel configuration Change-Id: I7f21d4016a98db6f53efcd03f9ffd176b8845d7c Signed-off-by: Carlos Chinea Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/20577 Reviewed-by: Pawel SZYSZUK Tested-by: Pawel SZYSZUK Reviewed-by: Jonas ABERG Conflicts: arch/arm/mach-omap2/Makefile --- arch/arm/mach-omap2/Makefile | 3 +++ drivers/hsi/Kconfig | 1 + drivers/hsi/Makefile | 1 + drivers/hsi/controllers/Kconfig | 23 +++++++++++++++++++++++ drivers/hsi/controllers/Makefile | 5 +++++ 5 files changed, 33 insertions(+) create mode 100644 drivers/hsi/controllers/Kconfig create mode 100644 drivers/hsi/controllers/Makefile (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 49f92bc1c31..95578bb571d 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -187,6 +187,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),) obj-y += dsp.o endif +omap-ssi-$(CONFIG_OMAP_SSI) := ssi.o +obj-y += $(omap-ssi-m) $(omap-ssi-y) + # Specific board support obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o diff --git a/drivers/hsi/Kconfig b/drivers/hsi/Kconfig index d94e38dd80c..f053858683c 100644 --- a/drivers/hsi/Kconfig +++ b/drivers/hsi/Kconfig @@ -15,5 +15,6 @@ config HSI_BOARDINFO default y source "drivers/hsi/clients/Kconfig" +source "drivers/hsi/controllers/Kconfig" endif # HSI diff --git a/drivers/hsi/Makefile b/drivers/hsi/Makefile index 9d5d33f90de..586e5e0729e 100644 --- a/drivers/hsi/Makefile +++ b/drivers/hsi/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_HSI_BOARDINFO) += hsi_boardinfo.o obj-$(CONFIG_HSI) += hsi.o obj-y += clients/ +obj-y += controllers/ diff --git a/drivers/hsi/controllers/Kconfig b/drivers/hsi/controllers/Kconfig new file mode 100644 index 00000000000..3efe0f027c7 --- /dev/null +++ b/drivers/hsi/controllers/Kconfig @@ -0,0 +1,23 @@ +# +# HSI controllers configuration +# +comment "HSI controllers" + +config OMAP_SSI + tristate "OMAP SSI hardware driver" + depends on ARCH_OMAP && HSI + default n + ---help--- + SSI is a legacy version of HSI. It is usually used to connect + an application engine with a cellular modem. + If you say Y here, you will enable the OMAP SSI hardware driver. + + If unsure, say N. + +if OMAP_SSI + +config OMAP_SSI_CONFIG + boolean + default y + +endif # OMAP_SSI diff --git a/drivers/hsi/controllers/Makefile b/drivers/hsi/controllers/Makefile new file mode 100644 index 00000000000..c4ba2c2c2bd --- /dev/null +++ b/drivers/hsi/controllers/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for HSI controllers drivers +# + +obj-$(CONFIG_OMAP_SSI) += omap_ssi.o -- cgit v1.2.3 From 1bd12ef5ea3f63f6a2002a7574d022ca7d2529ae Mon Sep 17 00:00:00 2001 From: Philippe Langlais Date: Wed, 19 Oct 2011 10:22:22 +0200 Subject: arch: arm: ST-E HSI controller Change-Id: Ibe70431ede8a9707b37e3394c22beb9acc42d8cb Signed-off-by: Pawel Szyszuk --- arch/arm/mach-ux500/include/mach/hsi.h | 122 +++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 arch/arm/mach-ux500/include/mach/hsi.h (limited to 'arch') diff --git a/arch/arm/mach-ux500/include/mach/hsi.h b/arch/arm/mach-ux500/include/mach/hsi.h new file mode 100644 index 00000000000..030e35e729b --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/hsi.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + */ + +#ifndef __MACH_HSI_H +#define __MACH_HSI_H + +#include + +/* HSIT register offsets */ +#define STE_HSI_TX_ID 0x000 +#define STE_HSI_TX_MODE 0x004 +#define STE_HSI_TX_STATE 0x008 +#define STE_HSI_TX_IOSTATE 0x00C +#define STE_HSI_TX_BUFSTATE 0x010 +#define STE_HSI_TX_DIVISOR 0x014 +#define STE_HSI_TX_PARITY 0x018 +#define STE_HSI_TX_BREAK 0x01C +#define STE_HSI_TX_CHANNELS 0x020 +#define STE_HSI_TX_FLUSHBITS 0x024 +#define STE_HSI_TX_PRIORITY 0x028 +#define STE_HSI_TX_BURSTLEN 0x02C +#define STE_HSI_TX_PREAMBLE 0x030 +#define STE_HSI_TX_DATASWAP 0x034 +#define STE_HSI_TX_FRAMELENX 0x080 +#define STE_HSI_TX_BUFFERX 0x0C0 +#define STE_HSI_TX_BASEX 0x100 +#define STE_HSI_TX_SPANX 0x140 +#define STE_HSI_TX_GAUGEX 0x180 +#define STE_HSI_TX_WATERMARKX 0x1C0 +#define STE_HSI_TX_DMAEN 0x200 +#define STE_HSI_TX_WATERMARKIS 0x204 +#define STE_HSI_TX_WATERMARKIM 0x208 +#define STE_HSI_TX_WATERMARKIC 0x20C +#define STE_HSI_TX_WATERMARKID 0x210 +#define STE_HSI_TX_PERIPHID0 0xFE0 +#define STE_HSI_TX_PERIPHID1 0xFE4 +#define STE_HSI_TX_PERIPHID2 0xFE8 +#define STE_HSI_TX_PERIPHID3 0xFEC + +/* HSIR register offsets */ +#define STE_HSI_RX_ID 0x000 +#define STE_HSI_RX_MODE 0x004 +#define STE_HSI_RX_STATE 0x008 +#define STE_HSI_RX_BUFSTATE 0x00C +#define STE_HSI_RX_THRESHOLD 0x010 +#define STE_HSI_RX_PARITY 0x014 +#define STE_HSI_RX_DETECTOR 0x018 +#define STE_HSI_RX_EXCEP 0x01C +#define STE_HSI_RX_ACK 0x020 +#define STE_HSI_RX_CHANNELS 0x024 +#define STE_HSI_RX_REALTIME 0x028 +#define STE_HSI_RX_OVERRUN 0x02C +#define STE_HSI_RX_OVERRUNACK 0x030 +#define STE_HSI_RX_PREAMBLE 0x034 +#define STE_HSI_RX_PIPEGAUGE 0x038 +#define STE_HSI_RX_STATICCONFID 0x03C +#define STE_HSI_RX_BUFFERX 0x080 +#define STE_HSI_RX_FRAMELENX 0x0C0 +#define STE_HSI_RX_BASEX 0x100 +#define STE_HSI_RX_SPANX 0x140 +#define STE_HSI_RX_GAUGEX 0x180 +#define STE_HSI_RX_WATERMARKX 0x1C0 +#define STE_HSI_RX_DMAEN 0x200 +#define STE_HSI_RX_WATERMARKIS 0x204 +#define STE_HSI_RX_WATERMARKIM 0x208 +#define STE_HSI_RX_WATERMARKIC 0x20C +#define STE_HSI_RX_WATERMARKID 0x210 +#define STE_HSI_RX_OVERRUNMIS 0x214 +#define STE_HSI_RX_OVERRUNIM 0x218 +#define STE_HSI_RX_EXCEPMIS 0x21C +#define STE_HSI_RX_EXCEPIM 0x220 +#define STE_HSI_RX_PERIPHID0 0xFE0 +#define STE_HSI_RX_PERIPHID1 0xFE4 +#define STE_HSI_RX_PERIPHID2 0xFE8 +#define STE_HSI_RX_PERIPHID3 0xFEC + +/* HSI states */ +#define STE_HSI_STATE_IDLE 0x00 +#define STE_HSI_STATE_START 0x01 +#define STE_HSI_STATE_TRANSMIT 0x02 +#define STE_HSI_STATE_BREAK 0x03 +#define STE_HSI_STATE_FLUSH 0x04 +#define STE_HSI_STATE_HALT 0x05 + +/* HSI exceptions */ +#define STE_HSI_EXCEP_TIMEOUT 0x01 +#define STE_HSI_EXCEP_OVERRUN 0x02 +#define STE_HSI_EXCEP_BREAK 0x04 +#define STE_HSI_EXCEP_PARITY 0x08 + +/* HSI modes */ +#define STE_HSI_MODE_SLEEP 0x00 +#define STE_HSI_MODE_STREAM 0x01 +#define STE_HSI_MODE_FRAME 0x02 +#define STE_HSI_MODE_PIPELINED 0x03 +#define STE_HSI_MODE_FAILSAFE 0x04 + +#define STE_HSI_MAX_BUFFERS 32 + +/* Max channels of STE HSI controller */ +#define STE_HSI_MAX_CHANNELS 4 + +struct stedma40_chan_cfg; + +struct ste_hsi_port_cfg { +#ifdef CONFIG_STE_DMA40 + bool (*dma_filter)(struct dma_chan *chan, void *filter_param); + struct stedma40_chan_cfg *dma_tx_cfg; + struct stedma40_chan_cfg *dma_rx_cfg; +#endif +}; + +struct ste_hsi_platform_data { + int num_ports; + int use_dma; + struct ste_hsi_port_cfg *port_cfg; +}; + +#endif -- cgit v1.2.3 From 34b45698157f41b89227c4043e97f05aeb520bb7 Mon Sep 17 00:00:00 2001 From: Pawel Szyszuk Date: Thu, 7 Jul 2011 15:16:33 +0100 Subject: ARM: U8500: ST-E HSI: DMA burst and PIPE support Added support for HSIR PIPELINED mode (also in drivers/hsi) Added DMA max burst (in DMA words) as a parameter in hsi.h DMA channel high priority set to TRUE for HSI ST-Ericsson ID: 356625 ST-Ericsson Linux next: NA ST-Ericsson FOSS-OUT ID: Trivial Change-Id: Id842e61343ce5013992337db085fcbe91dd5b9f7 Signed-off-by: Pawel Szyszuk Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/32180 Reviewed-by: Yann GAUTIER Reviewed-by: Andrew LYNN --- arch/arm/mach-ux500/include/mach/hsi.h | 5 +++- drivers/hsi/controllers/ste_hsi.c | 51 ++++++++++++++++++++++++++++------ 2 files changed, 47 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/include/mach/hsi.h b/arch/arm/mach-ux500/include/mach/hsi.h index 030e35e729b..1d2ab206e27 100644 --- a/arch/arm/mach-ux500/include/mach/hsi.h +++ b/arch/arm/mach-ux500/include/mach/hsi.h @@ -63,6 +63,7 @@ #define STE_HSI_RX_SPANX 0x140 #define STE_HSI_RX_GAUGEX 0x180 #define STE_HSI_RX_WATERMARKX 0x1C0 +#define STE_HSI_RX_FRAMEBURSTCNT 0x1E0 #define STE_HSI_RX_DMAEN 0x200 #define STE_HSI_RX_WATERMARKIS 0x204 #define STE_HSI_RX_WATERMARKIM 0x208 @@ -101,7 +102,9 @@ #define STE_HSI_MAX_BUFFERS 32 /* Max channels of STE HSI controller */ -#define STE_HSI_MAX_CHANNELS 4 +#define STE_HSI_MAX_CHANNELS 2 + +#define STE_HSI_DMA_MAX_BURST 1 struct stedma40_chan_cfg; diff --git a/drivers/hsi/controllers/ste_hsi.c b/drivers/hsi/controllers/ste_hsi.c index 8ac1363c14c..a9cd343fd53 100644 --- a/drivers/hsi/controllers/ste_hsi.c +++ b/drivers/hsi/controllers/ste_hsi.c @@ -198,9 +198,19 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) ste_hsi->tx_base + STE_HSI_TX_BASEX + 4 * i); writel(buffers - 1, ste_hsi->tx_base + STE_HSI_TX_SPANX + 4 * i); - writel(buffers - 1, - ste_hsi->tx_base + STE_HSI_TX_WATERMARKX + 4 * i); + + /* + * The DMA burst request and the buffer occupation interrupt are + * asserted when the free space in the corresponding channel buffer + * is greater than the value programmed in TX_WATERMARKX field. + * The field value must be less than the corresponding SPAN value. + */ +#ifdef CONFIG_STE_DMA40 + writel(STE_HSI_DMA_MAX_BURST-1, + ste_hsi->tx_base + STE_HSI_TX_WATERMARKX + 4 * i); +#else /* IRQ mode */ writel(0, ste_hsi->tx_base + STE_HSI_TX_WATERMARKX + 4 * i); +#endif } /* @@ -215,7 +225,16 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) * Configure RX */ writel(pcontext->rx_mode, ste_hsi->rx_base + STE_HSI_RX_MODE); - writel(0, ste_hsi->rx_base + STE_HSI_RX_PARITY); + + if (STE_HSI_MODE_PIPELINED == pcontext->rx_mode) + /* + * 0x0F: The READY line is negated after the start of the + * 16th frame reception in PIPELINED mode. + */ + writel(0x0F, ste_hsi->rx_base + STE_HSI_RX_FRAMEBURSTCNT); + else + writel(0, ste_hsi->rx_base + STE_HSI_RX_FRAMEBURSTCNT); + writel(pcontext->rx_channels, ste_hsi->rx_base + STE_HSI_RX_CHANNELS); /* Calculate buffers number per channel */ buffers = STE_HSI_MAX_BUFFERS / pcontext->rx_channels; @@ -226,9 +245,19 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) ste_hsi->rx_base + STE_HSI_RX_BASEX + 4 * i); writel(buffers - 1, ste_hsi->rx_base + STE_HSI_RX_SPANX + 4 * i); - writel(buffers - 1, - ste_hsi->rx_base + STE_HSI_RX_WATERMARKX + 4 * i); + + /* + * The DMA burst request and the buffer occupation interrupt are + * asserted when the busy space in the corresponding channel buffer + * is greater than the value programmed in RX_WATERMARKX field. + * The field value must be less than the corresponding SPAN value. + */ +#ifdef CONFIG_STE_DMA40 + writel(STE_HSI_DMA_MAX_BURST-1, + ste_hsi->rx_base + STE_HSI_RX_WATERMARKX + 4 * i); +#else /* IRQ mode */ writel(0, ste_hsi->rx_base + STE_HSI_RX_WATERMARKX + 4 * i); +#endif } /* @@ -642,13 +671,13 @@ static int ste_hsi_setup_dma(struct hsi_client *cl) .src_addr = 0, /* dynamic data */ .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, .direction = DMA_FROM_DEVICE, - .src_maxburst = 1, + .src_maxburst = STE_HSI_DMA_MAX_BURST, }; struct dma_slave_config tx_conf = { .dst_addr = 0, /* dynamic data */ .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, .direction = DMA_TO_DEVICE, - .dst_maxburst = 1, + .dst_maxburst = STE_HSI_DMA_MAX_BURST, }; if (!ste_hsi->use_dma) @@ -1279,7 +1308,13 @@ static int ste_hsi_setup(struct hsi_client *cl) ste_hsi->context->tx_mode = cl->tx_cfg.mode; ste_hsi->context->tx_divisor = div; ste_hsi->context->tx_channels = cl->tx_cfg.channels; - ste_hsi->context->rx_mode = cl->rx_cfg.mode; + + if ((HSI_FLOW_PIPE == cl->rx_cfg.flow) && + (HSI_MODE_FRAME == cl->rx_cfg.mode)) + ste_hsi->context->rx_mode = STE_HSI_MODE_PIPELINED; + else + ste_hsi->context->rx_mode = cl->rx_cfg.mode; + ste_hsi->context->rx_channels = cl->rx_cfg.channels; } -- cgit v1.2.3 From ecc25025b1584b32fd0d51895dde1e9265803d24 Mon Sep 17 00:00:00 2001 From: Pawel Szyszuk Date: Thu, 6 Oct 2011 12:35:01 +0100 Subject: ARM: U9500: HSI registers update to DB8500 V2 spec ST-Ericsson Linux next: NA ST-Ericsson ID: 365681 ST-Ericsson FOSS-OUT ID: NA Change-Id: I396c2a4d44ded438308e358aa0ad976a397d4dd6 Signed-off-by: Pawel Szyszuk Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/33224 Reviewed-by: Christopher BLAIR Reviewed-by: Derek MORTON Reviewed-by: Andrew LYNN --- arch/arm/mach-ux500/include/mach/hsi.h | 11 +++++------ drivers/hsi/controllers/ste_hsi.c | 7 ++----- 2 files changed, 7 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/include/mach/hsi.h b/arch/arm/mach-ux500/include/mach/hsi.h index 1d2ab206e27..58d33249cae 100644 --- a/arch/arm/mach-ux500/include/mach/hsi.h +++ b/arch/arm/mach-ux500/include/mach/hsi.h @@ -16,13 +16,11 @@ #define STE_HSI_TX_IOSTATE 0x00C #define STE_HSI_TX_BUFSTATE 0x010 #define STE_HSI_TX_DIVISOR 0x014 -#define STE_HSI_TX_PARITY 0x018 #define STE_HSI_TX_BREAK 0x01C #define STE_HSI_TX_CHANNELS 0x020 #define STE_HSI_TX_FLUSHBITS 0x024 #define STE_HSI_TX_PRIORITY 0x028 -#define STE_HSI_TX_BURSTLEN 0x02C -#define STE_HSI_TX_PREAMBLE 0x030 +#define STE_HSI_TX_STATICCONFID 0x02C #define STE_HSI_TX_DATASWAP 0x034 #define STE_HSI_TX_FRAMELENX 0x080 #define STE_HSI_TX_BUFFERX 0x0C0 @@ -31,10 +29,11 @@ #define STE_HSI_TX_GAUGEX 0x180 #define STE_HSI_TX_WATERMARKX 0x1C0 #define STE_HSI_TX_DMAEN 0x200 -#define STE_HSI_TX_WATERMARKIS 0x204 +#define STE_HSI_TX_WATERMARKMIS 0x204 #define STE_HSI_TX_WATERMARKIM 0x208 #define STE_HSI_TX_WATERMARKIC 0x20C #define STE_HSI_TX_WATERMARKID 0x210 +#define STE_HSI_TX_WATERMARKIS 0x214 #define STE_HSI_TX_PERIPHID0 0xFE0 #define STE_HSI_TX_PERIPHID1 0xFE4 #define STE_HSI_TX_PERIPHID2 0xFE8 @@ -46,7 +45,6 @@ #define STE_HSI_RX_STATE 0x008 #define STE_HSI_RX_BUFSTATE 0x00C #define STE_HSI_RX_THRESHOLD 0x010 -#define STE_HSI_RX_PARITY 0x014 #define STE_HSI_RX_DETECTOR 0x018 #define STE_HSI_RX_EXCEP 0x01C #define STE_HSI_RX_ACK 0x020 @@ -65,7 +63,7 @@ #define STE_HSI_RX_WATERMARKX 0x1C0 #define STE_HSI_RX_FRAMEBURSTCNT 0x1E0 #define STE_HSI_RX_DMAEN 0x200 -#define STE_HSI_RX_WATERMARKIS 0x204 +#define STE_HSI_RX_WATERMARKMIS 0x204 #define STE_HSI_RX_WATERMARKIM 0x208 #define STE_HSI_RX_WATERMARKIC 0x20C #define STE_HSI_RX_WATERMARKID 0x210 @@ -73,6 +71,7 @@ #define STE_HSI_RX_OVERRUNIM 0x218 #define STE_HSI_RX_EXCEPMIS 0x21C #define STE_HSI_RX_EXCEPIM 0x220 +#define STE_HSI_RX_WATERMARKIS 0x224 #define STE_HSI_RX_PERIPHID0 0xFE0 #define STE_HSI_RX_PERIPHID1 0xFE4 #define STE_HSI_RX_PERIPHID2 0xFE8 diff --git a/drivers/hsi/controllers/ste_hsi.c b/drivers/hsi/controllers/ste_hsi.c index fe43d7b2133..8348a66697d 100644 --- a/drivers/hsi/controllers/ste_hsi.c +++ b/drivers/hsi/controllers/ste_hsi.c @@ -141,8 +141,6 @@ static void ste_hsi_init_registers(struct ste_hsi_controller *ste_hsi) writel(0, ste_hsi->tx_base + STE_HSI_TX_FLUSHBITS); /* TO DO: TX channel priorities will be implemented later */ writel(0, ste_hsi->tx_base + STE_HSI_TX_PRIORITY); - writel(0, ste_hsi->tx_base + STE_HSI_TX_BURSTLEN); - writel(0, ste_hsi->tx_base + STE_HSI_TX_PREAMBLE); writel(0, ste_hsi->tx_base + STE_HSI_TX_DATASWAP); writel(0, ste_hsi->tx_base + STE_HSI_TX_DMAEN); writel(0, ste_hsi->tx_base + STE_HSI_TX_WATERMARKID); @@ -187,7 +185,6 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) */ writel(pcontext->tx_mode, ste_hsi->tx_base + STE_HSI_TX_MODE); writel(pcontext->tx_divisor, ste_hsi->tx_base + STE_HSI_TX_DIVISOR); - writel(0, ste_hsi->tx_base + STE_HSI_TX_PARITY); writel(pcontext->tx_channels, ste_hsi->tx_base + STE_HSI_TX_CHANNELS); /* Calculate buffers number per channel */ buffers = STE_HSI_MAX_BUFFERS / pcontext->tx_channels; @@ -879,7 +876,7 @@ static void ste_hsi_rx_tasklet(unsigned long data) u32 irq_status, irq_mask; unsigned int i; - irq_status = readl(ste_hsi->rx_base + STE_HSI_RX_WATERMARKIS); + irq_status = readl(ste_hsi->rx_base + STE_HSI_RX_WATERMARKMIS); if (!irq_status) goto out; @@ -927,7 +924,7 @@ static void ste_hsi_tx_tasklet(unsigned long data) u32 irq_status, irq_mask; unsigned int i; - irq_status = readl(ste_hsi->tx_base + STE_HSI_TX_WATERMARKIS); + irq_status = readl(ste_hsi->tx_base + STE_HSI_TX_WATERMARKMIS); if (!irq_status) goto out; -- cgit v1.2.3