diff options
| author | Jonas Aaberg <jonas.aberg@stericsson.com> | 2011-09-26 07:56:26 +0200 |
|---|---|---|
| committer | Robert Marklund <robert.marklund@stericsson.com> | 2011-10-05 13:01:15 +0200 |
| commit | 7c6316bcc8d108acf1a260aa9d869cb736eb318d (patch) | |
| tree | 6706147d02608de4d3d1ba6beecebc1db0ec6d4b /arch | |
| parent | b9a3c9344d92dd1979b69c2f7730195e920c2281 (diff) | |
ARM: u5500: prcmu-qos: Add DDR limits
Change-Id: Icf6d6c68909c9e16f83c1d0d72ad6bc15459cb62
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/32135
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-ux500/pm/prcmu-qos-power.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/arch/arm/mach-ux500/pm/prcmu-qos-power.c b/arch/arm/mach-ux500/pm/prcmu-qos-power.c index 8eb21c533c5..e095eed4b70 100644 --- a/arch/arm/mach-ux500/pm/prcmu-qos-power.c +++ b/arch/arm/mach-ux500/pm/prcmu-qos-power.c @@ -245,10 +245,6 @@ static void update_target(int target) switch (target) { case PRCMU_QOS_DDR_OPP: switch (extreme_value) { - case 25: - op = DDR_25_OPP; - pr_debug("prcmu qos: set ddr opp to 25%%\n"); - break; case 50: op = DDR_50_OPP; pr_debug("prcmu qos: set ddr opp to 50%%\n"); @@ -257,6 +253,13 @@ static void update_target(int target) op = DDR_100_OPP; pr_debug("prcmu qos: set ddr opp to 100%%\n"); break; + case 25: + /* 25% DDR OPP is not supported on 5500 */ + if (!cpu_is_u5500()) { + op = DDR_25_OPP; + pr_debug("prcmu qos: set ddr opp to 25%%\n"); + break; + } default: pr_err("prcmu qos: Incorrect ddr target value (%d)", extreme_value); @@ -665,7 +668,11 @@ static int qos_delayed_cpufreq_notifier(struct notifier_block *nb, static int __init prcmu_qos_power_init(void) { - int ret = 0; + int ret; + + /* 25% DDR OPP is not supported on u5500 */ + if (cpu_is_u5500()) + ddr_opp_qos.default_value = 50; ret = register_prcmu_qos_misc(&ape_opp_qos, &prcmu_qos_ape_power_fops); if (ret < 0) { |