From c648fa58260b2537acfbe4bcec0e78c027ce7d75 Mon Sep 17 00:00:00 2001 From: Mattias Nilsson Date: Mon, 17 Oct 2011 17:26:10 +0200 Subject: arm: ux500: add plldsi and dsi{0,1}clk This patch adds the PLLDSI and the two subclocks dsi{0,1}clk to the U8500 clock tree. ST Ericsson ID: 343004, 359227 ST Ericsson FOSS-OUT ID: trivial Change-Id: I36b5a9b741da293b58ecd0bbeaf5678832104b34 Signed-off-by: Mattias Nilsson Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/34372 Reviewed-by: Jonas ABERG --- arch/arm/mach-ux500/clock-db8500.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-ux500/clock-db8500.c b/arch/arm/mach-ux500/clock-db8500.c index cf9fd4e5d10..3fd5a777ac7 100644 --- a/arch/arm/mach-ux500/clock-db8500.c +++ b/arch/arm/mach-ux500/clock-db8500.c @@ -38,6 +38,7 @@ static DEFINE_MUTEX(sysclk_mutex); static DEFINE_MUTEX(ab_ulpclk_mutex); static DEFINE_MUTEX(ab_intclk_mutex); static DEFINE_MUTEX(clkout0_mutex); +static DEFINE_MUTEX(dsi_pll_mutex); static struct delayed_work sysclk_disable_work; @@ -529,6 +530,30 @@ static DEF_PRCMU_CLK(uiccclk, PRCMU_UICCCLK, 48000000); static DEF_PRCMU_CLK(timclk, PRCMU_TIMCLK, 2400000); static DEF_PRCMU_CLK(sdmmcclk, PRCMU_SDMMCCLK, 50000000); +static struct clk dsi_pll = { + .name = "dsi_pll", + .ops = &prcmu_scalable_clk_ops, + .cg_sel = PRCMU_PLLDSI, + .parent = &hdmiclk, + .mutex = &dsi_pll_mutex, +}; + +static struct clk dsi0clk = { + .name = "dsi0clk", + .ops = &prcmu_scalable_clk_ops, + .cg_sel = PRCMU_DSI0CLK, + .parent = &dsi_pll, + .mutex = &dsi_pll_mutex, +}; + +static struct clk dsi1clk = { + .name = "dsi1clk", + .ops = &prcmu_scalable_clk_ops, + .cg_sel = PRCMU_DSI1CLK, + .parent = &dsi_pll, + .mutex = &dsi_pll_mutex, +}; + static struct clk dsi0escclk = { .name = "dsi0escclk", .ops = &prcmu_scalable_clk_ops, -- cgit v1.2.3