added clkinfo, clkmaja and build for SRAM config

clkinfo command shows current PLL and clock settings.
clkmaja changes certain clocks to be more U5500 (Maja) alike.

With make u8500_SRAM_config a U-Boot suitable to run from SRAM can be
compiled.

Signed-off-by: Michael Brandt <Michael.Brandt@stericsson.com>

4 files changed, 263 insertions, 68 deletions

diff --git a/Makefile b/Makefile
index 35f64122d..b105d745e 100755
--- a/Makefile
+++ b/Makefile
@@ -3172,9 +3172,11 @@ smdkc100_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
 
 u8500_def_config \
+u8500_SRAM_config \
 u8500_noconsole_config \
 u8500_auto_config: unconfig
 	@mkdir -p $(obj)include
+	@mkdir -p $(obj)board/st/u8500
 	@ > $(obj)include/config.h
 	@if [ "$(findstring _def, $@)" ] ; then \
 		echo "#ifndef  CONFIG_SKIP_LOWLEVEL_INIT " >> $(obj)include/config.h ; \
@@ -3186,6 +3188,10 @@ u8500_auto_config: unconfig
                 echo "#define CONFIG_SKIP_LOWLEVEL_INIT 1" >> $(obj)include/config.h ; \
                 echo "#endif"  >> $(obj)include/config.h ; \
                 echo "#define CONFIG_SILENT_CONSOLE 1" >>  $(obj)include/config.h ; \
+	fi; \
+	if [ "$(findstring _SRAM, $@)" ] ; then \
+		echo "#define CONFIG_BOOT_SRAM" >>  $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x40030000" >$(obj)board/st/u8500/config.tmp ; \
 	fi;
 	@$(MKCONFIG) -a u8500 arm arm_cortexa9 u8500 st stw8500
 
diff --git a/board/st/u8500/config.mk b/board/st/u8500/config.mk
index a75eda429..a7b5c846c 100755
--- a/board/st/u8500/config.mk
+++ b/board/st/u8500/config.mk
@@ -1,5 +1,18 @@
+# mop500/href:
 #
-# image should be loaded at 0x01000000
+#	Valid values for TEXT_BASE are:
 #
+#       Standard configuration - all models
+#       0x07F8_0000	run from SDRAM
+#
+#	Test configuraton
+#	0x4001_0000	run from eSRAM
+
 
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
 TEXT_BASE = 0x07F80000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c
index 4bb94e2b9..3b8c82a96 100755
--- a/board/st/u8500/u8500.c
+++ b/board/st/u8500/u8500.c
@@ -31,11 +31,75 @@
 #define NOMADIK_BACKUPRAM0_BASE (NOMADIK_PER4_BASE + 0x00000)
 #define NOMADIK_BACKUPRAM1_BASE (NOMADIK_PER4_BASE + 0x01000)
 
-extern void	(*handler)(); 
-extern unsigned volatile long magic_num;
+/* Power, Reset, Clock Management Unit */
+#define PRCMU_BASE	CFG_PRCMU_BASE
+#define PRCM_ARMCLKFIX_MGT_REG		(PRCMU_BASE + 0x000)
+#define PRCM_ACLK_MGT_REG		(PRCMU_BASE + 0x004)
+#define PRCM_SVAMMDSPCLK_MGT_REG	(PRCMU_BASE + 0x008)
+#define PRCM_SIAMMDSPCLK_MGT_REG	(PRCMU_BASE + 0x00C)
+#define PRCM_SAAMMDSPCLK_MGT_REG	(PRCMU_BASE + 0x010)
+#define PRCM_SGACLK_MGT_REG		(PRCMU_BASE + 0x014)
+#define PRCM_UARTCLK_MGT_REG		(PRCMU_BASE + 0x018)
+#define PRCM_MSPCLK_MGT_REG		(PRCMU_BASE + 0x01C)
+#define PRCM_I2CCLK_MGT_REG		(PRCMU_BASE + 0x020)
+#define PRCM_SDMMCCLK_MGT_REG		(PRCMU_BASE + 0x024)
+#define PRCM_SLIMCLK_MGT_REG		(PRCMU_BASE + 0x028)
+#define PRCM_PER1CLK_MGT_REG		(PRCMU_BASE + 0x02C)
+#define PRCM_PER2CLK_MGT_REG		(PRCMU_BASE + 0x030)
+#define PRCM_PER3CLK_MGT_REG		(PRCMU_BASE + 0x034)
+#define PRCM_PER5CLK_MGT_REG		(PRCMU_BASE + 0x038)
+#define PRCM_PER6CLK_MGT_REG		(PRCMU_BASE + 0x03C)
+#define PRCM_PER7CLK_MGT_REG		(PRCMU_BASE + 0x040)
+#define PRCM_DMACLK_MGT_REG		(PRCMU_BASE + 0x074)
+
+enum {
+	GATED = 0,
+	PLLSOC0,	/* pllsw = 001 */
+	PLLSOC1,	/* pllsw = 010 */
+	PLLDDR,		/* pllsw = 100 */
+};
+
+static const char *pll_name[4] = {"GATED", "SOC0", "SOC1", "DDR"};
+static uint32_t pll_khz[4];	/* use ffs(pllsw(reg)) as index */
+
+static struct clk_mgt_regs {
+	uint32_t addr;
+	uint32_t val;
+	const char *descr;
+} clk_mgt_regs[] = {
+	/* register content taken from bootrom settings */
+	{PRCM_ARMCLKFIX_MGT_REG, 0x0120, "ARMCLKFIX"}, /* ena, SOC0/0, ??? */
+	{PRCM_ACLK_MGT_REG, 0x0125, "ACLK"},	/* ena, SOC0/5, 160 MHz */
+	{PRCM_SVAMMDSPCLK_MGT_REG, 0x1122, "SVA"}, /* ena, SOC0/2, 400 MHz */
+	{PRCM_SIAMMDSPCLK_MGT_REG, 0x0022, "SIA"}, /* dis, SOC0/2, 400 MHz */
+	{PRCM_SAAMMDSPCLK_MGT_REG, 0x0822, "SAA"}, /* dis, SOC0/4, 200 MHz */
+	{PRCM_SGACLK_MGT_REG, 0x0024, "SGA"},	/* dis, SOC0/4, 200 MHz */
+	{PRCM_UARTCLK_MGT_REG, 0x0300, "UART"},	/* ena, GATED, CLK38 */
+	{PRCM_MSPCLK_MGT_REG, 0x0200, "MSP"},	/* dis, GATED, CLK38 */
+	{PRCM_I2CCLK_MGT_REG, 0x0130, "I2C"},	/* ena, SOC0/16, 50 MHz */
+	{PRCM_SDMMCCLK_MGT_REG, 0x0130, "SDMMC"}, /* ena, SOC0/16, 50 MHz */
+	{PRCM_PER1CLK_MGT_REG, 0x126, "PER1"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER2CLK_MGT_REG, 0x126, "PER2"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER3CLK_MGT_REG, 0x126, "PER3"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER5CLK_MGT_REG, 0x126, "PER5"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER6CLK_MGT_REG, 0x126, "PER6"},	/* ena, SOC0/6, 133 MHz */
+	{PRCM_PER7CLK_MGT_REG, 0x128, "PER7"},	/* ena, SOC0/8, 100 MHz */
+	{PRCM_DMACLK_MGT_REG, 0x125, "DMA"},	/* ena, SOC0/5, 160 MHz */
+	{0, 0, NULL},
+};
+
+/* U5500 (Maja) alike clock settings */
+static struct clk_mgt_regs maja_clk_regs[] = {
+	{PRCM_SVAMMDSPCLK_MGT_REG, 0x1124, "SVA"},	/* SOC0/4, 200 MHz */
+	{PRCM_SIAMMDSPCLK_MGT_REG, 0x0024, "SIA"},	/* SOC0/6, 133 MHz */
+	{PRCM_SGACLK_MGT_REG, 0x0025, "SGA"},		/* SOC0/5, 160 MHz */
+	{0, 0, NULL},
+};
+
+extern void (*handler)();
 extern void secondary_wfe();
 
-void wake_up_other_cores()
+void wake_up_other_cores(void)
 {
 	handler = secondary_wfe;
 	*((volatile unsigned int *)(NOMADIK_BACKUPRAM0_BASE+0x1FF4))= handler;
@@ -44,7 +108,7 @@ void wake_up_other_cores()
 	return;
 }
 
-void init_regs(void);
+static void init_regs(void);
 
 DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
@@ -54,18 +118,12 @@ void show_boot_progress(int progress)
 }
 #endif
 
-static inline void delay(unsigned long loops)
-{
-    __asm__ volatile ("1:\n"
-              "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0"(loops));
-}
-
 /*
-* Miscellaneous platform dependent initialisations
-*/
+ * Miscellaneous platform dependent initialisations
+ */
 
 int board_init(void)
-{    
+{
     gd->bd->bi_arch_number = 0x1A4;
     gd->bd->bi_boot_params = 0x00000100;
     //enable the timers in PRCMU reg
@@ -85,10 +143,6 @@ int misc_init_r(void)
 }
 #endif
 
-/******************************
-Routine:
-Description:
-******************************/
 int dram_init(void)
 {
     gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
@@ -101,7 +155,6 @@ int dram_init(void)
     return 0;
 }
 
-#define ARRAY_SIZE(x)		(sizeof(x) / sizeof((x)[0]))
 unsigned int addr_vall_arr[] = {
 0x8011F000, 0x0000FFFF, // Clocks for HSI  TODO Enable reqd only
 0x8011F008, 0x00001C44, // Clocks for HSI  TODO Enable reqd only
@@ -129,19 +182,144 @@ unsigned int addr_vall_arr[] = {
 0xA03FE020, 0x00000FFF, // USB
 0xA03FE024, 0x00000000  // USB
 };
+
 #ifdef BOARD_LATE_INIT
 int board_late_init(void)
 {
 	return (0);
 }
 #endif
-void init_regs(void)
-{    
+
+static void init_regs(void)
+{
     int i;
     for(i = 0; i < ARRAY_SIZE(addr_vall_arr)/2; i++)
     {
-        
+
         *((volatile unsigned int *)(addr_vall_arr[2 * i]))
                                 = addr_vall_arr[(2 * i) + 1];
-    }    
+    }
+}
+
+/*
+ * get_pll_freq_khz - return PLL frequency in kHz
+ */
+static get_pll_freq_khz(uint32_t inclk_khz, uint32_t freq_reg)
+{
+	uint32_t idf, ldf, odf, seldiv, phi;
+
+	/*
+	 * PLLOUTCLK = PHI = (INCLK*LDF)/(2*ODF*IDF) if SELDIV2=0
+	 * PLLOUTCLK = PHI = (INCLK*LDF)/(4*ODF*IDF) if SELDIV2=1
+	 * where:
+	 * IDF=R(2:0) (when R=000, IDF=1d)
+	 * LDF = 2*D(7:0) (D must be greater than or equal to 6)
+	 * ODF = N(5:0) (when N=000000, 0DF=1d)
+	 */
+
+	idf = (freq_reg & 0x70000) >> 16;
+	ldf = (freq_reg & 0xff) * 2;
+	odf = (freq_reg & 0x3f00) >> 8;
+	seldiv = (freq_reg & 0x01000000) >> 24;
+	phi = (inclk_khz * ldf) / (2 * odf * idf);
+	if (seldiv)
+		phi = phi/2;
+
+	return phi;
+}
+
+int do_clkinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	uint32_t inclk_khz = 38400;	/* 38.4 MHz */
+	uint32_t reg, phi;
+	uint32_t val;
+	uint32_t clk_khz;
+	unsigned int clk_sel;
+	struct clk_mgt_regs *regs = clk_mgt_regs;
+
+	/* DDR PLL */
+	reg =  *(uint32_t *)0x8015708C;
+	phi = get_pll_freq_khz(inclk_khz, reg);
+	pll_khz[PLLDDR] = phi;
+	printf("\nDDR PLL out frequency: %d.%d Mhz\n",
+			phi/1000, phi % 1000);
+	/* ARM PLL */
+	reg =  *(uint32_t *)0x80157088;
+	phi = get_pll_freq_khz(inclk_khz, reg);
+	printf("ARM PLL out frequency: %d.%d Mhz\n",
+			phi/1000, phi % 1000);
+	reg =  *(uint32_t *)0x80157114; /* PRCM_ARM_CHGCLKREQ_REG */
+	printf("A9 running on ");
+	if (reg & 1)
+		printf("external clock");
+	else
+		printf("ARM PLL");
+	printf("\n");
+
+	/* SOC0 Pll */
+	reg =  *(uint32_t *)0x80157080;
+	phi = get_pll_freq_khz(inclk_khz, reg);
+	pll_khz[PLLSOC0] = phi;
+	printf("SOC0 PLL out frequency: %d.%d Mhz\n",
+			phi/1000, phi % 1000);
+
+	/* SOC1 Pll */
+	reg =  *(uint32_t *)0x80157084;
+	phi = get_pll_freq_khz(inclk_khz, reg);
+	pll_khz[PLLSOC1] = phi;
+	printf("SOC1 PLL out frequency: %d.%d Mhz\n",
+			phi/1000, phi % 1000);
+	printf("\n");
+
+	/* go through list of clk_mgt_reg */
+	while (regs->addr) {
+		val = readl(regs->addr);
+		/* convert bit position into array index */
+		clk_sel = ffs((val >> 5) & 0x7);	/* PLLSW[2:0] */
+		printf("%s(%08x): %08x", regs->descr, regs->addr, val);
+		printf(", PLL %s", pll_name[clk_sel]);
+		if (val & 0x200)
+			clk_khz = 38400;	/* CLK38 is set */
+		else if ((val & 0x1f) == 0)
+			/* ARMCLKFIX_MGT is 0x120, e.g. div = 0 ! */
+			clk_khz = 0;
+		else
+			clk_khz = pll_khz[clk_sel] / (val & 0x1f);
+		printf(", CLK %d.%d MHz", clk_khz / 1000, clk_khz % 1000);
+		printf(", %s", (val & 0x100) ? "ena" : "dis");
+		printf("\n");
+		regs++;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clkinfo,	1,	1,	do_clkinfo,
+	"print clock info",
+	""
+);
+
+/*
+ * do_clkmaja - change certain register to imitate Maja performance
+ */
+int do_clkmaja(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	uint32_t val;
+	struct clk_mgt_regs *regs = maja_clk_regs;
+
+	while (regs->addr) {
+		val = readl(regs->addr);
+		printf("%s(%08x): %08x -> %08x\n", regs->descr, regs->addr,
+				val, regs->val);
+		writel(regs->val, regs->addr);
+		regs++;
+	}
 }
+
+U_BOOT_CMD(
+	clkmaja,	1,	1,	do_clkmaja,
+	"set some clocks maja alike",
+	""
+);
+
diff --git a/include/configs/u8500.h b/include/configs/u8500.h
index 9a24bc242..91fd37f00 100755
--- a/include/configs/u8500.h
+++ b/include/configs/u8500.h
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2009
- * STEricsson, <www.stericsson.com>
+ * ST-Ericsson, <www.stericsson.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -28,35 +28,35 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_U8500			1
-#define CONFIG_U8500_ED			1
-#define CONFIG_L2_OFF			1
-
-// XXX: nomadik left over?
-// #define PCI_IO_VADDR            	0xee000000
-
-// #define __io(a)                 	((void __iomem *)(PCI_IO_VADDR + (a)))
+#define CONFIG_U8500		1
+#define CONFIG_U8500_ED		1
+#define CONFIG_L2_OFF		1
 
 #define CONFIG_SYS_MEMTEST_START	0x00000000
-#define CONFIG_SYS_MEMTEST_END		0x1FFFFFFF
-#define CONFIG_SYS_HZ			1000//(2400000 / 128)	/* Timer0 is clocked at 2.4Mhz  with 256 divider */
+#define CONFIG_SYS_MEMTEST_END	0x1FFFFFFF
+#define CONFIG_SYS_HZ		1000		/* must be 1000 */
 
 #ifndef CONFIG_U8500_V1
-#define CONFIG_SYS_TIMERBASE		0xA03DA000      /* MTU0 timer */
+#define CONFIG_SYS_TIMERBASE	0xA03DA000      /* MTU0 timer */
 #else
-#define CONFIG_SYS_TIMERBASE		0xA03C6000      /* MTU0 timer */
+#define CONFIG_SYS_TIMERBASE	0xA03C6000      /* MTU0 timer */
 #endif
 
-#define CONFIG_MISC_INIT_R		1	/* call misc_init_r during start up */
-	
-#define BOARD_LATE_INIT			1
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
+
+#define BOARD_LATE_INIT		1
 
 /*-----------------------------------------------------------------------
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE            	128*1024
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#ifdef CONFIG_BOOT_SRAM
+#define CONFIG_ENV_SIZE		32*1024
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 64*1024)
+#else
+#define CONFIG_ENV_SIZE		128*1024
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 256*1024)
+#endif
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* for initial data */
 
 /*-----------------------------------------------------------------------
  * PL011 Configuration
@@ -66,21 +66,21 @@
 /*
  * U8500 UART registers base for 3 serial devices
  */
-#define CFG_UART0_BASE			0x80120000
-#define CFG_UART1_BASE			0x80121000
-#define CFG_UART2_BASE			0x80007000
-#define CFG_SERIAL0			CFG_UART0_BASE	
-#define CFG_SERIAL1			CFG_UART1_BASE	
-#define CFG_SERIAL2   			CFG_UART2_BASE
-#define CONFIG_PL011_CLOCK 		38400000
-#define CONFIG_PL01x_PORTS      	{ (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1), (void *) (CFG_SERIAL2) }
-#define CONFIG_CONS_INDEX		2
-#define CONFIG_BAUDRATE        		115200
-#define CONFIG_SYS_BAUDRATE_TABLE      	{ 9600, 19200, 38400, 57600, 115200 }
- 
-// do_fat_read will loop (insane timeout), e.g. fail, if this is defined
-#define CONFIG_MMC			1
-#define CONFIG_DOS_PARTITION		1
+#define CFG_UART0_BASE		0x80120000
+#define CFG_UART1_BASE		0x80121000
+#define CFG_UART2_BASE		0x80007000
+#define CFG_SERIAL0		CFG_UART0_BASE
+#define CFG_SERIAL1		CFG_UART1_BASE
+#define CFG_SERIAL2		CFG_UART2_BASE
+#define CONFIG_PL011_CLOCK	38400000
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
+				  (void *)CFG_SERIAL2 }
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_MMC		1
+#define CONFIG_DOS_PARTITION	1
 
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_BOOTD
@@ -99,9 +99,9 @@
 #define CONFIG_CMD_SOURCE
 
 #ifdef CONFIG_USB_TTY
-#define CONFIG_BOOTDELAY		-1	/* disable autoboot */
+#define CONFIG_BOOTDELAY	-1	/* disable autoboot */
 #else
-#define CONFIG_BOOTDELAY		5
+#define CONFIG_BOOTDELAY	5
 #endif /* CONFIG_USB_TTY */
 
 #define CONFIG_BOOTARGS	"cachepolicy=writealloc root=/dev/mmcblk0p2 noinitrd rootfstype=ext3 rootdelay=1 init=/linuxrc console=ttyAMA2,115200n8 board_id=1 mem=96M@0 mem=128M@128M"
@@ -118,7 +118,7 @@
 	"stderr=serial,usbtty\0"
 
 #ifndef CONFIG_USB_TTY
-#define CONFIG_PREBOOT 			"mmc init 1;mmc_read_cmd_file"
+#define CONFIG_PREBOOT			"mmc init 1;mmc_read_cmd_file"
 #endif
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
@@ -126,7 +126,7 @@
 
 #define CONFIG_SYS_LONGHELP			/* undef to save memory     */
 #define CONFIG_SYS_PROMPT	"U8500 $ "	/* Monitor Command Prompt   */
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
 
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
@@ -136,15 +136,14 @@
 
 #undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 #define CONFIG_SYS_LOAD_ADDR		0x00100000 /* default load address */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 	1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
 
-#define CONFIG_SYS_HUSH_PARSER 		1
-#define CONFIG_SYS_PROMPT_HUSH_PS2 	"> "
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMDLINE_EDITING
 
-
-#define CONFIG_SETUP_MEMORY_TAGS 	2
-#define CONFIG_INITRD_TAG 		1
+#define CONFIG_SETUP_MEMORY_TAGS	2
+#define CONFIG_INITRD_TAG		1
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
 
 /*-----------------------------------------------------------------------
@@ -153,7 +152,6 @@
  * The stack sizes are set up in start.S using the settings below
  */
 
-#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
 #ifdef CONFIG_USE_IRQ
 #define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
 #define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */