diff options
| author | Gregory Hermant <gregory.hermant@calao-systems.com> | 2011-11-10 22:14:13 +0200 |
|---|---|---|
| committer | Kalle Vahlman <kalle.vahlman@movial.com> | 2011-11-17 21:43:43 +0200 |
| commit | e0198035a245378312f372573f67356521addebd (patch) | |
| tree | b9abcf882d6ef0d8bd2731b046805ee6b7f85de9 | |
| parent | f035234e805d73eca1bdcb1091d9277a946d9ca3 (diff) | |
Increase FSMC data-phase timing for ethernet controller SRAM transfers
The ethernet controller reportedly suffers data corruption of transfers from
SRAM through the Flexible Smart Memory Controller on some PDK boards.
Increasing the data-phase timing for the transfers fixes these problems.
| -rw-r--r-- | board/st/u8500/u8500.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c index cf6c73d58..70f5dc955 100644 --- a/board/st/u8500/u8500.c +++ b/board/st/u8500/u8500.c @@ -646,8 +646,11 @@ int board_late_init(void) /* setup FSMC for LAN controler */ writel(0x305b, 0x80000000); - /* the default is too slow */ - writel(0x01010110, 0x80000004); + /* + * the default is too slow + * NOTE: below this some boards corrupt data in SRAM transfers + */ + writel(0x01010210, 0x80000004); } /* enable 3V6 for GBF chip */ |