diff options
| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /board | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'board')
1386 files changed, 18891 insertions, 21810 deletions
diff --git a/board/AtmarkTechno/suzaku/flash.c b/board/AtmarkTechno/suzaku/flash.c index 49a06733a..ce6fae01b 100644 --- a/board/AtmarkTechno/suzaku/flash.c +++ b/board/AtmarkTechno/suzaku/flash.c @@ -24,7 +24,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned long flash_init(void) { diff --git a/board/AtmarkTechno/suzaku/u-boot.lds b/board/AtmarkTechno/suzaku/u-boot.lds index cb90854a3..b38f64877 100644 --- a/board/AtmarkTechno/suzaku/u-boot.lds +++ b/board/AtmarkTechno/suzaku/u-boot.lds @@ -61,6 +61,7 @@ SECTIONS { __bss_start = .; *(.bss) + . = ALIGN(4); __bss_end = .; } __end = . ; diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c index 39c97b1f5..d509a8fdb 100644 --- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c +++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c @@ -32,7 +32,7 @@ int checkboard (void) { puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n"); -#if (TEXT_BASE == CFG_INT_FLASH_BASE) +#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) puts (" Boot from Internal FLASH\n"); #endif @@ -45,10 +45,10 @@ phys_size_t initdram (int board_type) size = 0; MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 - | MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4); -#ifdef CFG_SDRAM_BASE0 + | MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4); +#ifdef CONFIG_SYS_SDRAM_BASE0 - MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0) + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; @@ -57,17 +57,17 @@ phys_size_t initdram (int board_type) MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5; + *(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5; MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; for (i = 0; i < 2000; i++) asm (" nop"); mbar_writeLong (MCFSDRAMC_DACR0, mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS); - *(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5; - size += CFG_SDRAM_SIZE * 1024 * 1024; + *(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5; + size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif -#ifdef CFG_SDRAM_BASE1 - MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1) +#ifdef CONFIG_SYS_SDRAM_BASE1 + MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) | MCFSDRAMC_DACR_PS_16; @@ -76,25 +76,25 @@ phys_size_t initdram (int board_type) MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP; - *(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5; + *(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5; MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE; for (i = 0; i < 2000; i++) asm (" nop"); MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS; - *(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5; - size += CFG_SDRAM_SIZE1 * 1024 * 1024; + *(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5; + size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024; #endif return size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); diff --git a/board/BuS/EB+MCF-EV123/Makefile b/board/BuS/EB+MCF-EV123/Makefile index ceeffa775..ed3ac0755 100644 --- a/board/BuS/EB+MCF-EV123/Makefile +++ b/board/BuS/EB+MCF-EV123/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o mii.o +COBJS = $(BOARD).o cfm_flash.o flash.o VCxK.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c index 4b46b7c9a..f2fe353db 100644 --- a/board/BuS/EB+MCF-EV123/VCxK.c +++ b/board/BuS/EB+MCF-EV123/VCxK.c @@ -25,7 +25,7 @@ #include <asm/m5282.h> #include "VCxK.h" -vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE); +vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE); #define VCXK_BWS vcxk_bws static ulong vcxk_driver; diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c index 98e563fc5..fe03b1758 100644 --- a/board/BuS/EB+MCF-EV123/cfm_flash.c +++ b/board/BuS/EB+MCF-EV123/cfm_flash.c @@ -28,14 +28,14 @@ #if defined(CONFIG_M5281) || defined(CONFIG_M5282) -#if (CFG_CLK>20000000) - #define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40) +#if (CONFIG_SYS_CLK>20000000) + #define CFM_CLK (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40) #else - #define CFM_CLK ((long) CFG_CLK / 400000 + 1) + #define CFM_CLK ((long) CONFIG_SYS_CLK / 400000 + 1) #endif #define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \ - (CFG_MBAR & 0xC0000000)) + (CONFIG_SYS_MBAR & 0xC0000000)) void cfm_flash_print_info (flash_info_t * info) { @@ -60,8 +60,8 @@ void cfm_flash_init (flash_info_t * info) MCFCFM_MCR = 0; MCFCFM_CLKD = CFM_CLK; debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\ - CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ - CFG_CLK); + CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ + CONFIG_SYS_CLK); MCFCFM_SACC = 0; MCFCFM_DACC = 0; @@ -86,7 +86,7 @@ void cfm_flash_init (flash_info_t * info) { if (sector == 0) { - info->start[sector] = CFG_INT_FLASH_BASE; + info->start[sector] = CONFIG_SYS_INT_FLASH_BASE; } else { @@ -187,7 +187,7 @@ int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cn return rc; } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION int cfm_flash_protect(flash_info_t * info,long sector,int prot) { diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.h b/board/BuS/EB+MCF-EV123/cfm_flash.h index cc8cdbd1e..ed4e7943e 100644 --- a/board/BuS/EB+MCF-EV123/cfm_flash.h +++ b/board/BuS/EB+MCF-EV123/cfm_flash.h @@ -33,7 +33,7 @@ extern void cfm_flash_print_info (flash_info_t * info); extern int cfm_flash_erase_sector (flash_info_t * info, int sector); extern void cfm_flash_init (flash_info_t * info); extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION extern int cfm_flash_protect(flash_info_t * info,long sector,int prot); #endif diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c index c2a1b6ff6..3c36367d7 100644 --- a/board/BuS/EB+MCF-EV123/flash.c +++ b/board/BuS/EB+MCF-EV123/flash.c @@ -27,10 +27,10 @@ #include <common.h> #include "cfm_flash.h" -#define PHYS_FLASH_1 CFG_FLASH_BASE +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; void flash_print_info (flash_info_t * info) { @@ -83,7 +83,7 @@ unsigned long flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; switch (i) @@ -93,8 +93,8 @@ unsigned long flash_init (void) (AMD_MANUFACT & FLASH_VENDMASK) | (AMD_ID_LV160B & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); flashbase = PHYS_FLASH_1; for (j = 0; j < flash_info[i].sector_count; j++) { if (j == 0) { @@ -128,8 +128,8 @@ unsigned long flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0xffff, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]); return size; } @@ -177,7 +177,7 @@ int amd_flash_erase_sector(flash_info_t * info, int sector) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; state = ERR_TIMOUT; } @@ -303,7 +303,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { state = ERR_TIMOUT; } if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK))) @@ -390,7 +390,7 @@ int amd_flash_protect(flash_info_t * info,long sector,int prot) return rc; } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION int flash_real_protect(flash_info_t * info,long sector,int prot) { diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c deleted file mode 100644 index 8ae2ec69c..000000000 --- a/board/BuS/EB+MCF-EV123/mii.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CFG_PEHLPAR; - } else { - MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_AMD79C874VC "AMD79C874VC" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - strcpy(info->phy_name, - STR_ID_AMD79C874VC); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - printf(STR_ID_AMD79C874VC); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/BuS/EB+MCF-EV123/u-boot.lds b/board/BuS/EB+MCF-EV123/u-boot.lds index 4a880e689..b22b332c4 100644 --- a/board/BuS/EB+MCF-EV123/u-boot.lds +++ b/board/BuS/EB+MCF-EV123/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/LEOX/elpt860/README.LEOX b/board/LEOX/elpt860/README.LEOX index 9052b097b..25524af69 100644 --- a/board/LEOX/elpt860/README.LEOX +++ b/board/LEOX/elpt860/README.LEOX @@ -106,7 +106,7 @@ version - print monitor version ? - alias for 'help' ################################################## -# Environment Variables (CFG_ENV_IS_IN_NVRAM) +# Environment Variables (CONFIG_ENV_IS_IN_NVRAM) ############################## LEOX_elpt860: printenv diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c index 5f506314c..905df92b1 100644 --- a/board/LEOX/elpt860/elpt860.c +++ b/board/LEOX/elpt860/elpt860.c @@ -138,23 +138,23 @@ const uint sdram_table[] = { /* ------------------------------------------------------------------------- */ -#define CFG_PC4 0x0800 +#define CONFIG_SYS_PC4 0x0800 -#define CFG_DS1 CFG_PC4 +#define CONFIG_SYS_DS1 CONFIG_SYS_PC4 /* * Very early board init code (fpga boot, etc.) */ int board_early_init_f (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* * Light up the red led on ELPT860 pcb (DS1) (PCDAT) */ - immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */ - immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */ - immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */ + immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */ + immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */ + immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */ return (0); /* success */ } @@ -181,7 +181,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size_b0 = 0; @@ -207,7 +207,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; /* * The following value is used as an address (i.e. opcode) for @@ -229,10 +229,10 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -252,7 +252,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -260,7 +260,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -269,7 +269,7 @@ phys_size_t initdram (int board_type) } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -282,22 +282,22 @@ phys_size_t initdram (int board_type) */ if (size_b0 < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping: map bigger bank first */ - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; { unsigned long reg; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } @@ -319,7 +319,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -329,20 +329,20 @@ dram_size (long int mamr_value, long int *base, long int maxsize) /* ------------------------------------------------------------------------- */ -#define CFG_PA1 0x4000 -#define CFG_PA2 0x2000 +#define CONFIG_SYS_PA1 0x4000 +#define CONFIG_SYS_PA2 0x2000 -#define CFG_LBKs (CFG_PA2 | CFG_PA1) +#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 | CONFIG_SYS_PA1) void reset_phy (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect * and no AUI loopback */ - immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */ - immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */ - immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */ + immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */ + immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */ + immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */ } diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c index c1b3b8513..9a75aad18 100644 --- a/board/LEOX/elpt860/flash.c +++ b/board/LEOX/elpt860/flash.c @@ -33,7 +33,7 @@ /* ** Note 1: In this file, you have to provide the following variable: ** ------ -** flash_info_t flash_info[CFG_MAX_FLASH_BANKS] +** flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS] ** 'flash_info_t' structure is defined into 'include/flash.h' ** and defined as extern into 'common/cmd_flash.c' ** @@ -61,11 +61,11 @@ #include <mpc8xx.h> -#ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Internal Functions @@ -82,13 +82,13 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -105,28 +105,28 @@ flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE, + size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE-1, &flash_info[0]); #endif @@ -383,7 +383,7 @@ flash_erase (flash_info_t *info, addr = (volatile unsigned char *)(info->start[l_sect]); while ( (addr[0] & 0x80) != 0x80 ) { - if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT ) + if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT ) { printf ("Timeout\n"); return ( 1 ); @@ -556,7 +556,7 @@ write_word (flash_info_t *info, start = get_timer (0); while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) ) { - if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { return (1); } @@ -602,7 +602,7 @@ write_byte (flash_info_t *info, start = get_timer (0); while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) ) { - if ( get_timer(start) > CFG_FLASH_WRITE_TOUT ) + if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { return (1); } diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index 7b1440b36..9b9b980f4 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -77,7 +77,7 @@ SECTIONS lib_ppc/ticks.o (.text) . = env_offset; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -147,6 +147,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug index 357867054..434c9b71d 100644 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -70,7 +70,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c index e118563fc..4d44001ff 100644 --- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c +++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c @@ -26,6 +26,7 @@ #include <common.h> #include <command.h> #include <pci.h> +#include <netdev.h> #include "articiaS.h" #include "memio.h" #include "via686.h" @@ -111,3 +112,11 @@ void pci_init_board (void) articiaS_pci_init (); #endif } + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_3COM) + eth_3com_initialize(bis); +#endif + return 0; +} diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c index 40c951d06..949af1802 100644 --- a/board/MAI/AmigaOneG3SE/cmd_boota.c +++ b/board/MAI/AmigaOneG3SE/cmd_boota.c @@ -27,7 +27,7 @@ struct bootcode_block bblk; int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR; + unsigned char *load_address = (unsigned char *) CONFIG_SYS_LOAD_ADDR; unsigned char *base_address; unsigned long offset; diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c index 5a90cc57d..0b4dfe6aa 100644 --- a/board/MAI/AmigaOneG3SE/enet.c +++ b/board/MAI/AmigaOneG3SE/enet.c @@ -28,6 +28,7 @@ #include <common.h> #include <malloc.h> #include <net.h> +#include <netdev.h> #include <asm/io.h> #include <pci.h> diff --git a/board/MAI/AmigaOneG3SE/flash.c b/board/MAI/AmigaOneG3SE/flash.c index 409b955fd..a96d5bae2 100644 --- a/board/MAI/AmigaOneG3SE/flash.c +++ b/board/MAI/AmigaOneG3SE/flash.c @@ -1,14 +1,14 @@ #include <common.h> #include <flash.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned long flash_init(void) { int i; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; diff --git a/board/MAI/AmigaOneG3SE/flash_new.c b/board/MAI/AmigaOneG3SE/flash_new.c index d46bf4646..7b7ea1697 100644 --- a/board/MAI/AmigaOneG3SE/flash_new.c +++ b/board/MAI/AmigaOneG3SE/flash_new.c @@ -39,7 +39,7 @@ #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static ulong flash_get_size (ulong addr, flash_info_t *info); static int flash_get_offsets (ulong base, flash_info_t *info); @@ -80,7 +80,7 @@ unsigned long flash_init_old(void) { int i; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; @@ -101,33 +101,33 @@ unsigned long flash_init (void) flash_to_xd(); /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; flash_info[i].size = 0; } - DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE); + DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE); - flash_size = flash_get_size (CFG_FLASH_BASE, flash_info); + flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info); DEBUGF("## Flash bank size: %08lx\n", flash_size); if (flash_size) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \ - CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \ + CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif @@ -286,10 +286,10 @@ static ulong flash_get_size (ulong addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } if (! flash_get_offsets (addr, info)) { @@ -418,10 +418,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = info->start[l_sect]; - DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); + DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT); while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); flash_reset (info->start[0]); flash_to_mem(); @@ -562,7 +562,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flash_reset (addr); flash_to_mem(); return (1); diff --git a/board/MAI/AmigaOneG3SE/i8259.h b/board/MAI/AmigaOneG3SE/i8259.h index 05c40522d..eb08e13d4 100644 --- a/board/MAI/AmigaOneG3SE/i8259.h +++ b/board/MAI/AmigaOneG3SE/i8259.h @@ -21,20 +21,20 @@ * MA 02111-1307 USA */ -#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1 -#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1 -#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2 -#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2 -#define ICW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3 -#define ICW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3 -#define ICW4_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4 -#define ICW4_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4 -#define OCW1_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1 -#define OCW1_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1 -#define OCW2_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2 -#define OCW2_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2 -#define OCW3_1 CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3 -#define OCW3_2 CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3 +#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1 +#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1 +#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2 +#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2 +#define ICW3_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3 +#define ICW3_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3 +#define ICW4_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4 +#define ICW4_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4 +#define OCW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1 +#define OCW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1 +#define OCW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2 +#define OCW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2 +#define OCW3_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3 +#define OCW3_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3 #define IMR_1 OCW1_1 #define IMR_2 OCW1_2 diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c index 86b44150d..de46d6e37 100644 --- a/board/MAI/AmigaOneG3SE/interrupts.c +++ b/board/MAI/AmigaOneG3SE/interrupts.c @@ -119,12 +119,12 @@ int interrupt_init (void) #ifdef DEBUG puts("interrupt_init: setting decrementer_count\n"); #endif - decrementer_count = get_tbclk() / CFG_HZ; + decrementer_count = get_tbclk() / CONFIG_SYS_HZ; #ifdef DEBUG puts("interrupt_init: setting actual decremter\n"); #endif - set_dec (get_tbclk() / CFG_HZ); + set_dec (get_tbclk() / CONFIG_SYS_HZ); #ifdef DEBUG puts("interrupt_init: clearing external interrupt table\n"); diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c index 724a44db7..a297005ed 100644 --- a/board/MAI/AmigaOneG3SE/ps2kbd.c +++ b/board/MAI/AmigaOneG3SE/ps2kbd.c @@ -214,7 +214,7 @@ int isa_kbd_init (void) } } -#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE extern int overwrite_console (void); #else int overwrite_console (void) @@ -492,22 +492,22 @@ unsigned char handle_kbd_event (void) */ unsigned char kbd_read_status(void) { - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); + return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); } unsigned char kbd_read_input(void) { - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); + return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); } void kbd_write_command(unsigned char cmd) { - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); } void kbd_write_output(unsigned char data) { - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); } int kbd_read_data(void) diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c index b6f57c724..88039f3d0 100644 --- a/board/MAI/AmigaOneG3SE/serial.c +++ b/board/MAI/AmigaOneG3SE/serial.c @@ -6,7 +6,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_NS16550 +#ifndef CONFIG_SYS_NS16550 static uint32 ComPort1; uint16 SerialEcho = 1; @@ -147,8 +147,8 @@ void serial_debug_putc (int c) #else -const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1; -const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2; +const NS16550_t Com0 = (NS16550_t) CONFIG_SYS_NS16550_COM1; +const NS16550_t Com1 = (NS16550_t) CONFIG_SYS_NS16550_COM2; int serial_init (void) { diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds index 7386ea7a2..e107b479c 100644 --- a/board/MAI/AmigaOneG3SE/u-boot.lds +++ b/board/MAI/AmigaOneG3SE/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS cpu/74xx_7xx/start.o (.text) /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c index 26cdcdf76..857ab3edc 100644 --- a/board/MAI/AmigaOneG3SE/usb_uhci.c +++ b/board/MAI/AmigaOneG3SE/usb_uhci.c @@ -627,7 +627,7 @@ int usb_lowlevel_init(void) pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); usb_base_addr&=0xFFFFFFF0; - usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; + usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS; rh.devnum = 0; usb_init_skel(); reset_hc(); @@ -801,7 +801,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, unsigned short wIndex; unsigned short wLength; - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + if (usb_pipeint(pipe)) { printf("Root-Hub submit IRQ: NOT implemented\n"); #if 0 uhci->rh.urb = urb; diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt index 290aed90a..e4fefb31d 100644 --- a/board/Marvell/common/bootseq.txt +++ b/board/Marvell/common/bootseq.txt @@ -88,7 +88,7 @@ in_flash: nothing mem_malloc_init malloc_bin_reloc - spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) env_relocated misc_init_r(bd): (board/evb64260/evb64260.c) mpsc_init2 diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c index 3603372d0..21eae0e94 100644 --- a/board/Marvell/common/flash.c +++ b/board/Marvell/common/flash.c @@ -48,7 +48,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last); int write_word_intel (bank_addr_t addr, bank_word_t value); -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -68,14 +68,14 @@ unsigned long flash_init (void) unsigned long base, flash_size; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* the boot flash */ - base = CFG_FLASH_BASE; + base = CONFIG_SYS_FLASH_BASE; size_b0 = - flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base, + flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base, &flash_info[0]); printf ("[%ldkB@%lx] ", size_b0 / 1024, base); @@ -84,11 +84,11 @@ unsigned long flash_init (void) printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20); } - base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE); + base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE); /* base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/ - for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { unsigned long size = - flash_get_size (CFG_EXTRA_FLASH_WIDTH, + flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *) base, &flash_info[i]); printf ("[%ldMB@%lx] ", size >> 20, base); @@ -617,7 +617,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* has the timeout limit been reached? */ if (get_timer (start) > - CFG_FLASH_ERASE_TOUT) + CONFIG_SYS_FLASH_ERASE_TOUT) { /* timeout limit reached */ printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]); @@ -776,7 +776,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr = (volatile unsigned char *) (info->start[l_sect]); /* broken for 2x16: TODO */ while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -956,7 +956,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) { /* has the timeout limit been reached? */ if (get_timer (start) > - CFG_FLASH_WRITE_TOUT) { + CONFIG_SYS_FLASH_WRITE_TOUT) { /* timeout limit reached */ printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data); /* reset the flash */ @@ -1064,7 +1064,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c index 32b2b30a4..d42604439 100644 --- a/board/Marvell/common/i2c.c +++ b/board/Marvell/common/i2c.c @@ -48,7 +48,7 @@ static void i2c_init (int speed, int slaveaddr) unsigned int actualN = 0, actualM = 0; unsigned int control, status; unsigned int minMargin = 0xffffffff; - unsigned int tclk = CFG_TCLK; + unsigned int tclk = CONFIG_SYS_TCLK; unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ DP (puts ("i2c_init\n")); @@ -372,7 +372,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_read\n")); @@ -447,7 +447,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_write\n")); @@ -500,7 +500,7 @@ int i2c_probe (uchar chip) unsigned int i2c_status; #endif uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_probe\n")); diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c index d26f883ad..42b3ee154 100644 --- a/board/Marvell/common/intel_flash.c +++ b/board/Marvell/common/intel_flash.c @@ -152,7 +152,7 @@ int write_word_intel (bank_addr_t addr, bank_word_t value) /* data polling for D7 */ start = get_timer (0); do { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { retval = 1; goto done; } @@ -227,7 +227,7 @@ int flash_erase_intel (flash_info_t * info, int s_first, int s_last) do { now = get_timer (start); - if (now - estart > CFG_FLASH_ERASE_TOUT) { + if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (sect %d)\n", sect); haderr = 1; break; diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h index 666a4cdca..bd8941ea5 100644 --- a/board/Marvell/common/intel_flash.h +++ b/board/Marvell/common/intel_flash.h @@ -68,7 +68,7 @@ /* ID and Lock Configuration */ #define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ #define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CFG_FLASH_ID +#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID /* dimensions */ #define CHIP_WIDTH 2 /* chips are in 16 bit mode */ diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S index 41c3a9508..b3a089803 100644 --- a/board/Marvell/common/misc.S +++ b/board/Marvell/common/misc.S @@ -16,7 +16,7 @@ board_relocate_rom: mflr r7 /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h + lis r11, CONFIG_SYS_GT_REGS@h /* if we're using ECC, we must use the DMA engine to copy ourselves */ bl start_idma_transfer_0 bl wait_for_idma_0 @@ -29,12 +29,12 @@ board_relocate_rom: board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ /* now that we're running from ram, init the rest of main memory * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l + lis r8, CONFIG_SYS_MONITOR_LEN@h + ori r8, r8, CONFIG_SYS_MONITOR_LEN@l divw r3, r10, r8 @@ -120,15 +120,15 @@ stop_idma_engine_0: blr #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* NOTE: trashes r3-r7 */ .globl board_asm_init board_asm_init: /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r3, CONFIG_SYS_DFL_GT_REGS@h + ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTERNAL_SPACE_DECODE /* test to see if we've already moved */ diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c index 475445b78..7fbf28a60 100644 --- a/board/Marvell/common/ns16550.c +++ b/board/Marvell/common/ns16550.c @@ -1,7 +1,7 @@ /* * COM1 NS16550 support * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines + * modified to use CONFIG_SYS_ISA_MEM and new defines * * further modified by Josh Huber <huber@mclx.com> to support * the DUART on the Galileo Eval board. (db64360) @@ -13,8 +13,8 @@ #ifdef ZUMA_NTL /* no 16550 device */ #else -const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0), - (NS16550_t) (CFG_DUART_IO + 0x20) +const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0), + (NS16550_t) (CONFIG_SYS_DUART_IO + 0x20) }; volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h index f2ed2abc9..b9691ab5a 100644 --- a/board/Marvell/common/ns16550.h +++ b/board/Marvell/common/ns16550.h @@ -2,7 +2,7 @@ * NS16550 Serial Port * originally from linux source (arch/ppc/boot/ns16550.h) * modified slightly to - * have addresses as offsets from CFG_ISA_BASE + * have addresses as offsets from CONFIG_SYS_ISA_BASE * added a few more definitions * added prototypes for ns16550.c * reduced no of com ports to 2 diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c index 01efbea77..3e7f406ff 100644 --- a/board/Marvell/common/serial.c +++ b/board/Marvell/common/serial.c @@ -52,17 +52,17 @@ DECLARE_GLOBAL_DATA_PTR; int serial_init (void) { -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) int clock_divisor = 230400 / gd->baudrate; #endif mpsc_init (gd->baudrate); /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif return (0); @@ -97,10 +97,10 @@ int serial_init (void) { int clock_divisor = 230400 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 (void) NS16550_init (0, clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 (void) NS16550_init (1, clock_divisor); #endif return (0); @@ -109,29 +109,29 @@ int serial_init (void) void serial_putc (const char c) { if (c == '\n') - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } int serial_getc (void) { - return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } int serial_tstc (void) { - return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } void serial_setbrg (void) { int clock_divisor = 230400 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif } diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c index 2a810a618..35b695e86 100644 --- a/board/Marvell/db64360/db64360.c +++ b/board/Marvell/db64360/db64360.c @@ -33,6 +33,7 @@ #include "../include/pci.h" #include "../include/mv_gen_reg.h" #include <net.h> +#include <netdev.h> #include "eth.h" #include "mpsc.h" @@ -54,7 +55,7 @@ /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -63,7 +64,7 @@ */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -126,7 +127,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ @@ -135,7 +136,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -153,21 +154,21 @@ static void gt_pci_config (void) /* ronen- add write to pci remap registers for 64460. in 64360 when writing to pci base go and overide remap automaticaly, in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -183,7 +184,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -199,7 +200,7 @@ static void gt_cpu_config (void) tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif @@ -250,7 +251,7 @@ int board_early_init_f (void) * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); /* No PCI in first release of Port To_do: enable it. */ #ifdef CONFIG_PCI @@ -296,56 +297,56 @@ int board_early_init_f (void) * on-board sram on the eval board, and updates the correct * registers to boot from the sram. (device0) */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) sram_boot = 1; if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ -#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ +#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); #endif -#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); #endif -#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); #endif -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ /* detect if we are booting from the 32 bit flash */ if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); + CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ #endif gt_cpu_config (); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); DEBUG_LED0_ON (); DEBUG_LED1_ON (); DEBUG_LED2_ON (); @@ -358,7 +359,7 @@ int board_early_init_f (void) int misc_init_r () { icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd) /* check to see if we booted from the sram. If so, move things * back to the way they should be. (we're running from main * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); } display_mem_map (); /* now, jump to the main ppcboot board init code */ @@ -401,7 +402,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -414,34 +415,34 @@ void debug_led (int led, int mode) if (mode == 1) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x08000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x0c000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x10000); break; } } else if (mode == 0) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x14000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x18000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x1c000); break; } @@ -512,7 +513,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaULL, @@ -606,7 +607,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -633,9 +634,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -660,8 +661,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -678,9 +679,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -770,8 +771,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -847,9 +848,9 @@ int testdram (void) /* runwalk = 0; */ if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -859,7 +860,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -869,7 +870,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -885,7 +886,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ @@ -924,8 +925,13 @@ void board_prebootm_init () /* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */ /* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); + my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); icache_disable (); dcache_disable (); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c index 923d95555..7ad6ae8c0 100644 --- a/board/Marvell/db64360/mpsc.c +++ b/board/Marvell/db64360/mpsc.c @@ -426,7 +426,7 @@ void mpsc_sdma_init (void) (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c index 563728412..499809514 100644 --- a/board/Marvell/db64360/pci.c +++ b/board/Marvell/db64360/pci.c @@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); @@ -859,14 +859,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -901,14 +901,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c index ecadaf271..d0817d7e2 100644 --- a/board/Marvell/db64360/sdram_init.c +++ b/board/Marvell/db64360/sdram_init.c @@ -312,7 +312,7 @@ return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT +#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT for (i = 0; i <= 127; i++) { printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], @@ -690,16 +690,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP < - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP < - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { dimmInfo-> maxClSupported_DDR @@ -714,16 +714,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP > - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP > - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { printf ("*********************************************************\n"); printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); @@ -1290,37 +1290,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) case 0x0: case 0x80: /* refresh period is 15.625 usec */ sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) + (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x1: case 0x81: /* refresh period is 3.9 usec */ sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x2: case 0x82: /* refresh period is 7.8 usec */ sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x3: case 0x83: /* refresh period is 31.3 usec */ sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x4: case 0x84: /* refresh period is 62.5 usec */ sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x5: case 0x85: /* refresh period is 125 usec */ sdram_config_reg = - (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; default: /* refresh period undefined */ @@ -1807,7 +1807,7 @@ phys_size_t initdram (int board_type) printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (!checkbank[bank_no]) continue; diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds index 1a95755ab..ff2d8b7fe 100644 --- a/board/Marvell/db64360/u-boot.lds +++ b/board/Marvell/db64360/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c index 1ae898d1e..14e635592 100644 --- a/board/Marvell/db64460/db64460.c +++ b/board/Marvell/db64460/db64460.c @@ -33,6 +33,7 @@ #include "../include/pci.h" #include "../include/mv_gen_reg.h" #include <net.h> +#include <netdev.h> #include "eth.h" #include "mpsc.h" @@ -54,7 +55,7 @@ /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -63,7 +64,7 @@ */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -126,7 +127,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ @@ -135,7 +136,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -153,21 +154,21 @@ static void gt_pci_config (void) /* ronen- add write to pci remap registers for 64460. in 64360 when writing to pci base go and overide remap automaticaly, in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -183,7 +184,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -199,7 +200,7 @@ static void gt_cpu_config (void) tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64460 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif @@ -250,7 +251,7 @@ int board_early_init_f (void) * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); /* No PCI in first release of Port To_do: enable it. */ #ifdef CONFIG_PCI @@ -296,56 +297,56 @@ int board_early_init_f (void) * on-board sram on the eval board, and updates the correct * registers to boot from the sram. (device0) */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) sram_boot = 1; if (!sram_boot) - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ -#ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */ +#ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */ if (!sram_boot) - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); #endif -#ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */ - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */ + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); #endif -#ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */ - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */ + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); #endif -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ /* detect if we are booting from the 32 bit flash */ if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); + CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ #endif gt_cpu_config (); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); DEBUG_LED0_ON (); DEBUG_LED1_ON (); DEBUG_LED2_ON (); @@ -358,7 +359,7 @@ int board_early_init_f (void) int misc_init_r () { icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -379,9 +380,9 @@ void after_reloc (ulong dest_addr, gd_t * gd) /* check to see if we booted from the sram. If so, move things * back to the way they should be. (we're running from main * memory at this point now */ - if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) { - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M); + if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) { + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M); } display_mem_map (); /* now, jump to the main ppcboot board init code */ @@ -401,7 +402,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -414,34 +415,34 @@ void debug_led (int led, int mode) if (mode == 1) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x08000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x0c000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x10000); break; } } else if (mode == 0) { switch (led) { case 0: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x14000); break; case 1: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x18000); break; case 2: - addr = (int *) ((unsigned int) CFG_DEV1_SPACE | + addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE | 0x1c000); break; } @@ -512,7 +513,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -543,7 +544,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaULL, @@ -606,7 +607,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -633,9 +634,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -660,8 +661,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -678,9 +679,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -738,7 +739,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -770,8 +771,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -847,9 +848,9 @@ int testdram (void) /* runwalk = 0; */ if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -859,7 +860,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -869,7 +870,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -885,7 +886,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ @@ -924,8 +925,13 @@ void board_prebootm_init () GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); /* Relocate MV64460 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM); + my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM); icache_disable (); dcache_disable (); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c index 359b83140..303a63615 100644 --- a/board/Marvell/db64460/mpsc.c +++ b/board/Marvell/db64460/mpsc.c @@ -426,7 +426,7 @@ void mpsc_sdma_init (void) (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -516,9 +516,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c index 563728412..499809514 100644 --- a/board/Marvell/db64460/pci.c +++ b/board/Marvell/db64460/pci.c @@ -52,13 +52,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); @@ -859,14 +859,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -901,14 +901,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c index f36f3484a..6d6b12644 100644 --- a/board/Marvell/db64460/sdram_init.c +++ b/board/Marvell/db64460/sdram_init.c @@ -312,7 +312,7 @@ return 0; } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT +#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT for (i = 0; i <= 127; i++) { printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], @@ -690,16 +690,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP < - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP < - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { dimmInfo-> maxClSupported_DDR @@ -714,16 +714,16 @@ return 0; if ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP > - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) || ((dimmInfo-> minimumCycleTimeAtMaxCasLatancy_LoP == - CFG_DDR_SDRAM_CYCLE_COUNT_LOP) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) && (dimmInfo-> minimumCycleTimeAtMaxCasLatancy_RoP > - CFG_DDR_SDRAM_CYCLE_COUNT_ROP))) + CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) { printf ("*********************************************************\n"); printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); @@ -1289,37 +1289,37 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) case 0x0: case 0x80: /* refresh period is 15.625 usec */ sdram_config_reg = - (unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ) + (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x1: case 0x81: /* refresh period is 3.9 usec */ sdram_config_reg = - (unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x2: case 0x82: /* refresh period is 7.8 usec */ sdram_config_reg = - (unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x3: case 0x83: /* refresh period is 31.3 usec */ sdram_config_reg = - (unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x4: case 0x84: /* refresh period is 62.5 usec */ sdram_config_reg = - (unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; case 0x5: case 0x85: /* refresh period is 125 usec */ sdram_config_reg = - (unsigned int) (((float) 125 * (float) CFG_BUS_HZ) / + (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) / (float) 1000000.0); break; default: /* refresh period undefined */ @@ -1816,7 +1816,7 @@ phys_size_t initdram (int board_type) printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (!checkbank[bank_no]) continue; diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds index 1a95755ab..ff2d8b7fe 100644 --- a/board/Marvell/db64460/u-boot.lds +++ b/board/Marvell/db64460/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c index 804635a4a..9fdf700ff 100644 --- a/board/RPXClassic/RPXClassic.c +++ b/board/RPXClassic/RPXClassic.c @@ -111,7 +111,7 @@ void board_get_enetaddr (uchar * enet) char buff[256], *cp; /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Read 256 bytes in EEPROM */ i2c_read (0x54, 0, 1, (uchar *)buff, 128); @@ -167,7 +167,7 @@ void rpxclassic_init (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size10; @@ -175,15 +175,15 @@ phys_size_t initdram (int board_type) sizeof (sdram_table) / sizeof (uint)); /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000000; /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -200,7 +200,7 @@ phys_size_t initdram (int board_type) * try 10 column mode */ - size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM, + size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); return (size10); @@ -218,7 +218,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c index cc76bbdfa..e1f3f9d07 100644 --- a/board/RPXClassic/eccx.c +++ b/board/RPXClassic/eccx.c @@ -299,7 +299,7 @@ void video_get_info_str (int line_number, char *info) */ unsigned int board_video_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* Program ECCX registers */ diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c index 2e0b8f958..f07d96052 100644 --- a/board/RPXClassic/flash.c +++ b/board/RPXClassic/flash.c @@ -33,7 +33,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -51,20 +51,20 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif @@ -313,7 +313,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long *)(info->start[l_sect]); while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -436,7 +436,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index 1f9a191d4..55cb5eca3 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS /* XXX ? . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -135,6 +135,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index c33581d25..ea8538900 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c index bca31e4c8..dca53a468 100644 --- a/board/RPXlite/RPXlite.c +++ b/board/RPXlite/RPXlite.c @@ -104,7 +104,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size10; @@ -112,15 +112,15 @@ phys_size_t initdram (int board_type) sizeof (sdram_table) / sizeof (uint)); /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000000; /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -137,7 +137,7 @@ phys_size_t initdram (int board_type) * try 10 column mode */ - size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM, + size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); return (size10); @@ -156,7 +156,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c index 659d60a2d..788fcdf29 100644 --- a/board/RPXlite/flash.c +++ b/board/RPXlite/flash.c @@ -38,7 +38,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -52,13 +52,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { -/* volatile immap_t *immap = (immap_t *)CFG_IMMR; */ +/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */ /* volatile memctl8xx_t *memctl = &immap->im_memctl; */ unsigned long size_b0 ; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -73,19 +73,19 @@ unsigned long flash_init (void) */ /* Remap FLASH according to real size */ /*%%% - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; %%%*/ /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif @@ -390,7 +390,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long *)(info->start[l_sect]); while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -513,7 +513,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index 1f9a191d4..55cb5eca3 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS /* XXX ? . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -135,6 +135,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index c33581d25..ea8538900 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/RPXlite_dw/README b/board/RPXlite_dw/README index 28bcb318e..14296b2ab 100644 --- a/board/RPXlite_dw/README +++ b/board/RPXlite_dw/README @@ -21,7 +21,7 @@ make distclean make RPXlite_DW_64_config make all -2. CFG_ENV_IS_IN_FLASH/CFG_ENV_IS_IN_NVRAM +2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM The default environment parameter is stored in FLASH because it is a common choice for environment parameter.So I make NVRAM as backup parameter storeage.The reason why I diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c index d6fabf04e..364a3165c 100644 --- a/board/RPXlite_dw/RPXlite_dw.c +++ b/board/RPXlite_dw/RPXlite_dw.c @@ -106,22 +106,22 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size9; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR ; + memctl->memc_mptpr = CONFIG_SYS_MPTPR ; memctl->memc_mar = 0x00000088; /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ /*Disable Periodic timer A. */ udelay(200); @@ -142,13 +142,13 @@ phys_size_t initdram (int board_type) * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); /* * Final mapping: */ - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; udelay (1000); @@ -171,7 +171,7 @@ void rpxlite_init (void) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c index 41cb036bb..91788af20 100644 --- a/board/RPXlite_dw/flash.c +++ b/board/RPXlite_dw/flash.c @@ -49,7 +49,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions vu_long : volatile unsigned long IN include/common.h @@ -64,22 +64,22 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* If Monitor is in the cope of FLASH,then * protect this area by default in case for * other occupation. [SAM] */ /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); #endif flash_info[0].size = size_b0; @@ -360,7 +360,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long *)(info->start[l_sect]); while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -482,7 +482,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index 2ee12069d..8d178940e 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS /* XXX ? . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -135,6 +135,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index f6d153763..0f6ae696d 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c index c0b772d72..9d016c59d 100644 --- a/board/RRvision/RRvision.c +++ b/board/RRvision/RRvision.c @@ -112,7 +112,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long reg; long int size8, size9; @@ -126,17 +126,17 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 1 the SDRAM bank 2 at physical address 0. */ - memctl->memc_or1 = CFG_OR2_PRELIM; - memctl->memc_br1 = CFG_BR2_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -156,7 +156,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); @@ -165,7 +165,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); @@ -174,7 +174,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -187,15 +187,15 @@ phys_size_t initdram (int board_type) */ if (size < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping */ - memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* * No bank 1 @@ -206,7 +206,7 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; udelay (10000); @@ -227,7 +227,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c index d8e07e645..fdbe928fb 100644 --- a/board/RRvision/flash.c +++ b/board/RRvision/flash.c @@ -26,11 +26,11 @@ #include <common.h> #include <mpc8xx.h> -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -43,13 +43,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -63,25 +63,25 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif @@ -388,7 +388,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { puts ("Timeout\n"); return 1; } @@ -511,7 +511,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 9e767ee40..9fd77f8c0 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = env_offset; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c index c1eceaa2f..ce2cf28e3 100644 --- a/board/a3000/a3000.c +++ b/board/a3000/a3000.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc824x.h> #include <pci.h> +#include <netdev.h> int checkboard (void) { @@ -45,7 +46,7 @@ phys_size_t initdram (int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -109,3 +110,8 @@ void pci_init_board(void) { pci_mpc824x_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/a3000/flash.c b/board/a3000/flash.c index 13a5ca5b0..b671ce729 100644 --- a/board/a3000/flash.c +++ b/board/a3000/flash.c @@ -25,15 +25,15 @@ #include <common.h> #include <mpc824x.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -48,7 +48,7 @@ #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -65,13 +65,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS; - unsigned long size, size_b[CFG_MAX_FLASH_BANKS]; + unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS; + unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS]; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; @@ -99,27 +99,27 @@ unsigned long flash_init (void) } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN); +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN); /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE); + DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif size = 0; DEBUGF("## Final Flash bank sizes: "); - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { DEBUGF("%08lx ", size_b[i]); size += size_b[i]; @@ -285,10 +285,10 @@ static ulong flash_get_size (vu_char *addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = BS(0xFF); /* restore read mode */ @@ -356,7 +356,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = BS(0xB0); /* suspend erase */ *addr = BS(0xFF); /* reset to read mode */ @@ -439,7 +439,7 @@ static int write_data (flash_info_t *info, uchar *dest, uchar data) start = get_timer (0); while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = BS(0xFF); /* restore read mode */ return 1; } diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c index d1d7f6cd3..399be23e1 100644 --- a/board/actux1/actux1.c +++ b/board/actux1/actux1.c @@ -49,16 +49,16 @@ int board_init (void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); /* Setup GPIO's for PCI INTA */ - GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA); - GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA); + GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA); /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); *IXP425_GPIO_GPCLKR = 0x011001FF; /* CS5: Debug port */ @@ -69,7 +69,7 @@ int board_init (void) *IXP425_EXP_CS7 = 0x80900003; udelay (533); - GPIO_OUTPUT_SET (CFG_GPIO_IORST); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); ACTUX1_LED1 (2); ACTUX1_LED2 (2); diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h index bb3b7f953..fe454c58e 100644 --- a/board/actux1/actux1_hw.h +++ b/board/actux1/actux1_hw.h @@ -42,16 +42,16 @@ #define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) /* GPIO settings */ -#define CFG_GPIO_PCI1_INTA 2 -#define CFG_GPIO_PCI2_INTA 3 -#define CFG_GPIO_I2C_SDA 4 -#define CFG_GPIO_I2C_SCL 5 -#define CFG_GPIO_DBGJUMPER 9 -#define CFG_GPIO_BUTTON1 10 -#define CFG_GPIO_DBGSENSE 11 -#define CFG_GPIO_DTR 12 -#define CFG_GPIO_IORST 13 /* Out */ -#define CFG_GPIO_PCI_CLK 14 /* Out */ -#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ +#define CONFIG_SYS_GPIO_PCI1_INTA 2 +#define CONFIG_SYS_GPIO_PCI2_INTA 3 +#define CONFIG_SYS_GPIO_I2C_SDA 4 +#define CONFIG_SYS_GPIO_I2C_SCL 5 +#define CONFIG_SYS_GPIO_DBGJUMPER 9 +#define CONFIG_SYS_GPIO_BUTTON1 10 +#define CONFIG_SYS_GPIO_DBGSENSE 11 +#define CONFIG_SYS_GPIO_DTR 12 +#define CONFIG_SYS_GPIO_IORST 13 /* Out */ +#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ +#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ #endif diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 0de78d32a..ccdb78e9c 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -37,7 +37,7 @@ SECTIONS common/dlmalloc.o(.text) cpu/ixp/cpu.o(.text) . = env_offset; - common/environment.o(.ppcenv) + common/env_embedded.o(.ppcenv) * (.text) } @@ -64,6 +64,7 @@ SECTIONS __bss_start =.; .bss (NOLOAD): { *(.bss) + . = ALIGN(4); } _end =.; } diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c index 99daef6c5..d6aaad620 100644 --- a/board/actux2/actux2.c +++ b/board/actux2/actux2.c @@ -50,24 +50,24 @@ int board_init (void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR); - GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); - GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR); - GPIO_OUTPUT_SET (CFG_GPIO_DCD); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD); /* Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT); /* Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); *IXP425_GPIO_GPCLKR = 0x011001FF; /* CS1: IPAC-X */ @@ -80,8 +80,8 @@ int board_init (void) *IXP425_EXP_CS7 = 0x80900003; udelay (533); - GPIO_OUTPUT_SET (CFG_GPIO_IORST); - GPIO_OUTPUT_SET (CFG_GPIO_ETHRST); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST); ACTUX2_LED1 (1); ACTUX2_LED2 (0); diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h index 8ffb82a81..0f5ebcbf9 100644 --- a/board/actux2/actux2_hw.h +++ b/board/actux2/actux2_hw.h @@ -39,21 +39,21 @@ /* * GPIO settings */ -#define CFG_GPIO_DBGINT 0 -#define CFG_GPIO_ETHINT 1 -#define CFG_GPIO_ETHRST 2 /* Out */ -#define CFG_GPIO_LED5_GN 3 /* Out */ -#define CFG_GPIO_UNUSED4 4 -#define CFG_GPIO_UNUSED5 5 -#define CFG_GPIO_DSR 6 /* Out */ -#define CFG_GPIO_DCD 7 /* Out */ -#define CFG_GPIO_IPAC_INT 8 -#define CFG_GPIO_DBGJUMPER 9 -#define CFG_GPIO_BUTTON1 10 -#define CFG_GPIO_DBGSENSE 11 -#define CFG_GPIO_DTR 12 -#define CFG_GPIO_IORST 13 /* Out */ -#define CFG_GPIO_PCI_CLK 14 /* Out */ -#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ +#define CONFIG_SYS_GPIO_DBGINT 0 +#define CONFIG_SYS_GPIO_ETHINT 1 +#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ +#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ +#define CONFIG_SYS_GPIO_UNUSED4 4 +#define CONFIG_SYS_GPIO_UNUSED5 5 +#define CONFIG_SYS_GPIO_DSR 6 /* Out */ +#define CONFIG_SYS_GPIO_DCD 7 /* Out */ +#define CONFIG_SYS_GPIO_IPAC_INT 8 +#define CONFIG_SYS_GPIO_DBGJUMPER 9 +#define CONFIG_SYS_GPIO_BUTTON1 10 +#define CONFIG_SYS_GPIO_DBGSENSE 11 +#define CONFIG_SYS_GPIO_DTR 12 +#define CONFIG_SYS_GPIO_IORST 13 /* Out */ +#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ +#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ #endif diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 90cafce6c..113193619 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -38,7 +38,7 @@ SECTIONS cpu/ixp/cpu.o(.text) . = env_offset; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) * (.text) } @@ -69,6 +69,7 @@ SECTIONS __bss_start =.; .bss (NOLOAD): { *(.bss) + . = ALIGN(4); } _end =.; } diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c index 812bc2b1a..63bf365b8 100644 --- a/board/actux3/actux3.c +++ b/board/actux3/actux3.c @@ -50,35 +50,35 @@ int board_init (void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST); - GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR); - GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD); - GPIO_OUTPUT_ENABLE (CFG_GPIO_LED5_GN); - GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_RT); - GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_GN); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN); - GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); - GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST); - GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR); - GPIO_OUTPUT_SET (CFG_GPIO_DCD); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD); - GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN); - GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT); - GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN); /* * Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT); - GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT); /* * Setup GPIO's for 33MHz clock output */ - GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); *IXP425_GPIO_GPCLKR = 0x011001FF; /* CS1: IPAC-X */ @@ -91,8 +91,8 @@ int board_init (void) *IXP425_EXP_CS7 = 0x80900003; udelay (533); - GPIO_OUTPUT_SET (CFG_GPIO_IORST); - GPIO_OUTPUT_SET (CFG_GPIO_ETHRST); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST); ACTUX3_LED1_RT (1); ACTUX3_LED1_GN (0); diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h index 9b7cbce6f..c3c0cfc5d 100644 --- a/board/actux3/actux3_hw.h +++ b/board/actux3/actux3_hw.h @@ -41,20 +41,20 @@ #define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) /* GPIO settings */ -#define CFG_GPIO_DBGINT 0 -#define CFG_GPIO_ETHINT 1 -#define CFG_GPIO_ETHRST 2 /* Out */ -#define CFG_GPIO_LED5_GN 3 /* Out */ -#define CFG_GPIO_LED6_RT 4 /* Out */ -#define CFG_GPIO_LED6_GN 5 /* Out */ -#define CFG_GPIO_DSR 6 /* Out */ -#define CFG_GPIO_DCD 7 /* Out */ -#define CFG_GPIO_DBGJUMPER 9 -#define CFG_GPIO_BUTTON1 10 -#define CFG_GPIO_DBGSENSE 11 -#define CFG_GPIO_DTR 12 -#define CFG_GPIO_IORST 13 /* Out */ -#define CFG_GPIO_PCI_CLK 14 /* Out */ -#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ +#define CONFIG_SYS_GPIO_DBGINT 0 +#define CONFIG_SYS_GPIO_ETHINT 1 +#define CONFIG_SYS_GPIO_ETHRST 2 /* Out */ +#define CONFIG_SYS_GPIO_LED5_GN 3 /* Out */ +#define CONFIG_SYS_GPIO_LED6_RT 4 /* Out */ +#define CONFIG_SYS_GPIO_LED6_GN 5 /* Out */ +#define CONFIG_SYS_GPIO_DSR 6 /* Out */ +#define CONFIG_SYS_GPIO_DCD 7 /* Out */ +#define CONFIG_SYS_GPIO_DBGJUMPER 9 +#define CONFIG_SYS_GPIO_BUTTON1 10 +#define CONFIG_SYS_GPIO_DBGSENSE 11 +#define CONFIG_SYS_GPIO_DTR 12 +#define CONFIG_SYS_GPIO_IORST 13 /* Out */ +#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ +#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ #endif diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index b9a9eb9ff..e861955db 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -38,7 +38,7 @@ SECTIONS cpu/ixp/cpu.o (.text) . = env_offset; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) * (.text) } @@ -69,6 +69,7 @@ SECTIONS __bss_start =.; .bss (NOLOAD): { *(.bss) + . = ALIGN(4); } _end =.; } diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c index 84037faba..f373b5877 100644 --- a/board/actux4/actux4.c +++ b/board/actux4/actux4.c @@ -49,53 +49,53 @@ int board_init (void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_CLEAR (CFG_GPIO_nPWRON); - GPIO_OUTPUT_ENABLE (CFG_GPIO_nPWRON); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON); - GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); - GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST); /* led not populated on board*/ - GPIO_OUTPUT_ENABLE (CFG_GPIO_LED3); - GPIO_OUTPUT_SET (CFG_GPIO_LED3); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3); /* middle LED */ - GPIO_OUTPUT_ENABLE (CFG_GPIO_LED2); - GPIO_OUTPUT_SET (CFG_GPIO_LED2); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2); /* right LED */ /* weak pulldown = LED weak on */ - GPIO_OUTPUT_DISABLE (CFG_GPIO_LED1); - GPIO_OUTPUT_SET (CFG_GPIO_LED1); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1); /* Setup GPIO's for Interrupt inputs */ - GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTA); - GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTB); - GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTC); - GPIO_OUTPUT_DISABLE (CFG_GPIO_RTCINT); - GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTB); - - GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTA); - GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTB); - GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTC); - GPIO_INT_ACT_LOW_SET (CFG_GPIO_RTCINT); - GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTB); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA); + GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB); + + GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA); + GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB); + GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC); + GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT); + GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA); + GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB); /* Setup GPIO's for 33MHz clock output */ *IXP425_GPIO_GPCLKR = 0x011001FF; - GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); - GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK); *IXP425_EXP_CS1 = 0xbd113c42; udelay (10000); - GPIO_OUTPUT_SET (CFG_GPIO_IORST); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); udelay (10000); - GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST); udelay (10000); - GPIO_OUTPUT_SET (CFG_GPIO_IORST); + GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST); return 0; } diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h index 8b3ecf341..afd1c06f5 100644 --- a/board/actux4/actux4_hw.h +++ b/board/actux4/actux4_hw.h @@ -29,21 +29,21 @@ /* * GPIO settings */ -#define CFG_GPIO_USBINTA 0 -#define CFG_GPIO_USBINTB 1 -#define CFG_GPIO_USBINTC 2 -#define CFG_GPIO_nPWRON 3 /* Out */ -#define CFG_GPIO_I2C_SCL 4 -#define CFG_GPIO_I2C_SDA 5 -#define CFG_GPIO_PCI_INTB 6 -#define CFG_GPIO_BUTTON1 7 -#define CFG_GPIO_LED1 8 /* Out */ -#define CFG_GPIO_RTCINT 9 -#define CFG_GPIO_LED2 10 /* Out */ -#define CFG_GPIO_PCI_INTA 11 -#define CFG_GPIO_IORST 12 /* Out */ -#define CFG_GPIO_LED3 13 /* Out */ -#define CFG_GPIO_PCI_CLK 14 /* Out */ -#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ +#define CONFIG_SYS_GPIO_USBINTA 0 +#define CONFIG_SYS_GPIO_USBINTB 1 +#define CONFIG_SYS_GPIO_USBINTC 2 +#define CONFIG_SYS_GPIO_nPWRON 3 /* Out */ +#define CONFIG_SYS_GPIO_I2C_SCL 4 +#define CONFIG_SYS_GPIO_I2C_SDA 5 +#define CONFIG_SYS_GPIO_PCI_INTB 6 +#define CONFIG_SYS_GPIO_BUTTON1 7 +#define CONFIG_SYS_GPIO_LED1 8 /* Out */ +#define CONFIG_SYS_GPIO_RTCINT 9 +#define CONFIG_SYS_GPIO_LED2 10 /* Out */ +#define CONFIG_SYS_GPIO_PCI_INTA 11 +#define CONFIG_SYS_GPIO_IORST 12 /* Out */ +#define CONFIG_SYS_GPIO_LED3 13 /* Out */ +#define CONFIG_SYS_GPIO_PCI_CLK 14 /* Out */ +#define CONFIG_SYS_GPIO_EXTBUS_CLK 15 /* Out */ #endif diff --git a/board/actux4/u-boot.lds b/board/actux4/u-boot.lds index c8784a08b..0e1155ac7 100644 --- a/board/actux4/u-boot.lds +++ b/board/actux4/u-boot.lds @@ -60,6 +60,7 @@ SECTIONS __bss_start =.; .bss (NOLOAD): { *(.bss) + . = ALIGN(4); } _end =.; } diff --git a/board/adder/adder.c b/board/adder/adder.c index e8a5737f5..87791deb5 100644 --- a/board/adder/adder.c +++ b/board/adder/adder.c @@ -68,7 +68,7 @@ static uint sdram_table[] = { phys_size_t initdram (int board_type) { long int msize; - volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); @@ -76,7 +76,7 @@ phys_size_t initdram (int board_type) /* Configure SDRAM refresh */ memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */ + memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */ udelay(200); /* Run precharge from location 0x15 */ @@ -94,10 +94,10 @@ phys_size_t initdram (int board_type) udelay(200); memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ - memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; - memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; + memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; - msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); memctl->memc_or1 |= ~(msize - 1); return msize; diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 25aaa7d8f..d97c04918 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -118,6 +118,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index deaa292b9..06109286e 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -53,16 +53,16 @@ long int fixed_sdram(void); int board_early_init_f (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 lpcaw; /* * Initialize Local Window for the CPLD registers access (CS2 selects * the CPLD chip) */ - im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) | - CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE); - im->lpc.cs_cfg[2] = CFG_CS2_CFG; + im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) | + CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE); + im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG; /* * According to MPC5121e RM, configuring local access windows should @@ -80,21 +80,21 @@ int board_early_init_f (void) */ #ifdef CONFIG_ADS5121_REV2 - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1; #else - if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) { - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { + *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1; } else { /* running from Backup flash */ - *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32; + *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32; } #endif /* * Configure Flash Speed */ - *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG; + *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG; if (SVR_MJREV (im->sysconf.spridr) >= 2) { - *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING; + *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING; } /* * Enable clocks @@ -120,8 +120,8 @@ phys_size_t initdram (int board_type) */ long int fixed_sdram (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2 (msize); u32 i; @@ -129,7 +129,7 @@ long int fixed_sdram (void) im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR; /* Initialize DDR Local Window */ - im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; + im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000; im->sysconf.ddrlaw.ar = msize_log2 - 1; /* @@ -141,68 +141,68 @@ long int fixed_sdram (void) __asm__ __volatile__ ("isync"); /* Enable DDR */ - im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN; + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN; /* Initialize DDR Priority Manager */ - im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1; - im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2; - im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG; - im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU; - im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML; - im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU; - im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML; - im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU; - im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML; - im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU; - im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML; - im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU; - im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML; - im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU; - im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL; - im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU; - im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL; - im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; - im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL; - im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; - im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL; - im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; - im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL; + im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU; + im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU; + im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU; + im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU; + im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU; + im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL; + im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU; + im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU; + im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU; + im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU; + im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL; /* Initialize MDDRC */ - im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG; - im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0; - im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1; - im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2; + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG; + im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1; + im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2; /* Initialize DDR */ for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CFG_MICRON_NOP; - - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_EM2; - im->mddrc.ddr_command = CFG_MICRON_NOP; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_EM2; - im->mddrc.ddr_command = CFG_MICRON_EM3; - im->mddrc.ddr_command = CFG_MICRON_EN_DLL; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_RFSH; - im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; /* Start MDDRC */ - im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN; - im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN; + im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN; + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN; return msize; } @@ -292,8 +292,8 @@ static iopin_t ioregs_init[] = { int checkboard (void) { - ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); - uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c index 26628d3eb..11450aabc 100644 --- a/board/ads5121/ads5121_diu.c +++ b/board/ads5121/ads5121_diu.c @@ -43,7 +43,7 @@ static int xres, yres; void diu_set_pixel_clock(unsigned int pixclock) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile clk512x_t *clk = &immap->clk; volatile unsigned int *clkdvdr = &clk->scfr[0]; unsigned long speed_ccb, temp, pixval; @@ -100,7 +100,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, } U_BOOT_CMD( - diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp, + diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp, "diufb init | addr - Init or Display BMP file\n", "init\n - initialize DIU\n" "addr\n - display bmp at address 'addr'\n" diff --git a/board/ads5121/pci.c b/board/ads5121/pci.c index a338604f6..b747e812a 100644 --- a/board/ads5121/pci.c +++ b/board/ads5121/pci.c @@ -33,8 +33,8 @@ DECLARE_GLOBAL_DATA_PTR; /* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE static struct pci_controller pci_hose; @@ -46,7 +46,7 @@ static struct pci_controller pci_hose; void pci_init_board(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile law512x_t *pci_law; volatile pot512x_t *pci_pot; volatile pcictrl512x_t *pci_ctrl; @@ -87,10 +87,10 @@ pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; /* @@ -98,18 +98,18 @@ pci_init_board(void) */ /* PCI mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M; /* PCI IO space */ - pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; /* PCI mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; /* @@ -129,23 +129,23 @@ pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, + CONFIG_SYS_PCI_MEM_BASE, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_PHYS, - CFG_PCI_MMIO_SIZE, + CONFIG_SYS_PCI_MMIO_BASE, + CONFIG_SYS_PCI_MMIO_PHYS, + CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI_IO_BASE, - CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, + CONFIG_SYS_PCI_IO_BASE, + CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -158,8 +158,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR + 0x8300), - (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), + (CONFIG_SYS_IMMR + 0x8304)); pci_register_hose(hose); diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds index f2f6e149c..a059033b9 100644 --- a/board/ads5121/u-boot.lds +++ b/board/ads5121/u-boot.lds @@ -115,6 +115,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/afeb9260/Makefile b/board/afeb9260/Makefile new file mode 100644 index 000000000..60c4304c1 --- /dev/null +++ b/board/afeb9260/Makefile @@ -0,0 +1,56 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += afeb9260.o +COBJS-y += partition.o +COBJS-$(CONFIG_CMD_NAND) += nand.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c new file mode 100644 index 000000000..32445ab74 --- /dev/null +++ b/board/afeb9260/afeb9260.c @@ -0,0 +1,243 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <netdev.h> +#include <net.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +static void afeb9260_serial_hw_init(void) +{ +#ifdef CONFIG_USART0 + at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); +#endif + +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); +#endif + +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); +#endif + +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +} + +static void afeb9260_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_DBW_8 | + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(AT91_PIN_PC13, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(AT91_PIN_PC14, 1); +} + +static void afeb9260_spi_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ + at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */ + + at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ + at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ + at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); +} + +#ifdef CONFIG_MACB +static void afeb9260_macb_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + AT91_RSTC_ERSTL | (0x0D << 8) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + AT91_RSTC_ERSTL | (0x0 << 8) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + + at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ + at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ + at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ + at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ + at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ + at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ + at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ + at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ + at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ + at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ + at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ + at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ + at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ + at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */ + at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */ + at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ +#endif + +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of AT91SAM9260EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AFEB9260; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + afeb9260_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + afeb9260_nand_hw_init(); +#endif + afeb9260_spi_hw_init(); +#ifdef CONFIG_MACB + afeb9260_macb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/afeb9260/config.mk b/board/afeb9260/config.mk new file mode 100644 index 000000000..9ce161e55 --- /dev/null +++ b/board/afeb9260/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 diff --git a/board/afeb9260/nand.c b/board/afeb9260/nand.c new file mode 100644 index 000000000..c5ac634aa --- /dev/null +++ b/board/afeb9260/nand.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_pio.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define MASK_CLE (1 << 22) /* our CLE is AD22 */ + +static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int at91sam9260ek_nand_ready(struct mtd_info *mtd) +{ + return at91_get_gpio_value(AT91_PIN_PC13); +} + +int board_nand_init(struct nand_chip *nand) +{ + nand->ecc.mode = NAND_ECC_SOFT; +#ifdef CONFIG_SYS_NAND_DBW_16 + nand->options = NAND_BUSWIDTH_16; +#endif + nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol; + nand->dev_ready = at91sam9260ek_nand_ready; + nand->chip_delay = 20; + + return 0; +} diff --git a/board/xilinx/xupv2p/u-boot.lds b/board/afeb9260/partition.c index cb90854a3..be08f295f 100644 --- a/board/xilinx/xupv2p/u-boot.lds +++ b/board/afeb9260/partition.c @@ -1,10 +1,4 @@ /* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI <yashi@atmark-techno.com> - * - * See file CREDITS for list of people who contributed to this - * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -20,48 +14,23 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * */ +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> -OUTPUT_ARCH(microblaze) -ENTRY(_start) - -SECTIONS -{ - .text ALIGN(0x4): - { - __text_start = .; - cpu/microblaze/start.o (.text) - *(.text) - __text_end = .; - } - - .rodata ALIGN(0x4): - { - __rodata_start = .; - *(.rodata) - __rodata_end = .; - } - - .data ALIGN(0x4): - { - __data_start = .; - *(.data) - __data_end = .; - } +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - .u_boot_cmd ALIGN(0x4): - { - . = .; - __u_boot_cmd_start = .; - *(.u_boot_cmd) - __u_boot_cmd_end = .; - } +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1} +}; - .bss ALIGN(0x4): - { - __bss_start = .; - *(.bss) - __bss_end = .; - } - __end = . ; -} +/*define the area offsets*/ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"}, +}; diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c index 49a8f712b..33b4a6ee4 100644 --- a/board/alaska/alaska.c +++ b/board/alaska/alaska.c @@ -32,48 +32,48 @@ void setupBat (ulong size) int blocksize = 0; /* Flash 0 */ -#if defined (CFG_AMD_BOOT) - batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; +#if defined (CONFIG_SYS_AMD_BOOT) + batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; #else - batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; #endif - batl = CFG_FLASH0_BASE | 0x22; + batl = CONFIG_SYS_FLASH0_BASE | 0x22; write_bat (IBAT0, batu, batl); write_bat (DBAT0, batu, batl); /* Flash 1 */ -#if defined (CFG_AMD_BOOT) - batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; +#if defined (CONFIG_SYS_AMD_BOOT) + batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; #else - batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; #endif - batl = CFG_FLASH1_BASE | 0x22; + batl = CONFIG_SYS_FLASH1_BASE | 0x22; write_bat (IBAT1, batu, batl); write_bat (DBAT1, batu, batl); /* CPLD */ - batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; - batl = CFG_CPLD_BASE | 0x22; + batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batl = CONFIG_SYS_CPLD_BASE | 0x22; write_bat (IBAT2, 0, 0); write_bat (DBAT2, batu, batl); /* FPGA */ - batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; - batl = CFG_FPGA_BASE | 0x22; + batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batl = CONFIG_SYS_FPGA_BASE | 0x22; write_bat (IBAT3, 0, 0); write_bat (DBAT3, batu, batl); /* MBAR - Data only */ - batu = CFG_MBAR | BPP_RW | BPP_RX; - batl = CFG_MBAR | 0x22; + batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX; + batl = CONFIG_SYS_MBAR | 0x22; mtspr (IBAT4L, 0); mtspr (IBAT4U, 0); mtspr (DBAT4L, batl); mtspr (DBAT4U, batu); /* MBAR - SRAM */ - batu = CFG_SRAM_BASE | BPP_RW | BPP_RX; - batl = CFG_SRAM_BASE | 0x42; + batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX; + batl = CONFIG_SYS_SRAM_BASE | 0x42; mtspr (IBAT5L, batl); mtspr (IBAT5U, batu); mtspr (DBAT5L, batl); @@ -93,8 +93,8 @@ void setupBat (ulong size) blocksize = BL_256M << 2; /* Memory */ - batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; - batl = CFG_SDRAM_BASE | 0x42; + batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; + batl = CONFIG_SYS_SDRAM_BASE | 0x42; mtspr (IBAT6L, batl); mtspr (IBAT6U, batu); mtspr (DBAT6L, batl); @@ -120,9 +120,9 @@ void setupBat (ulong size) else if (size <= 0x10000000) /* 256MB */ blocksize = BL_256M << 2; - batu = (CFG_SDRAM_BASE + + batu = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | blocksize | BPP_RW | BPP_RX; - batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42; + batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42; } mtspr (IBAT7L, batl); diff --git a/board/alaska/flash.c b/board/alaska/flash.c index 715616063..aed3b6f59 100644 --- a/board/alaska/flash.c +++ b/board/alaska/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH8 @@ -86,30 +86,30 @@ unsigned long flash_init (void) ulong size = 0; ulong fsize = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { memset (&flash_info[i], 0, sizeof (flash_info_t)); switch (i) { case 0: - flash_get_size ((FPW *) CFG_FLASH1_BASE, + flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE, &flash_info[i]); - flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]); + flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]); break; case 1: - flash_get_size ((FPW *) CFG_FLASH1_BASE, + flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE, &flash_info[i]); - fsize = CFG_FLASH1_BASE + flash_info[i - 1].size; + fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size; flash_get_offsets (fsize, &flash_info[i]); break; case 2: - flash_get_size ((FPW *) CFG_FLASH0_BASE, + flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE, &flash_info[i]); - flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]); + flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]); break; case 3: - flash_get_size ((FPW *) CFG_FLASH0_BASE, + flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE, &flash_info[i]); - fsize = CFG_FLASH0_BASE + flash_info[i - 1].size; + fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size; flash_get_offsets (fsize, &flash_info[i]); break; default: @@ -124,31 +124,31 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ -#if defined (CFG_AMD_BOOT) +#if defined (CONFIG_SYS_AMD_BOOT) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[2]); flash_protect (FLAG_PROTECT_SET, - CFG_INTEL_BASE, - CFG_INTEL_BASE + monitor_flash_len - 1, + CONFIG_SYS_INTEL_BASE, + CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1, &flash_info[1]); #else flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[3]); flash_protect (FLAG_PROTECT_SET, - CFG_AMD_BASE, - CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_AMD_BASE, + CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]); #endif flash_protect (FLAG_PROTECT_SET, - CFG_ENV1_ADDR, - CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]); + CONFIG_ENV1_ADDR, + CONFIG_ENV1_ADDR + CONFIG_ENV1_SIZE - 1, &flash_info[1]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[3]); return size; } @@ -294,10 +294,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } if (value == (FPW) INTEL_ID_28F128J3A) @@ -348,7 +348,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) /* * first, wait for the WSM to be finished. The rationale for * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy * because of: (1) erase, (2) program or (3) lock bit * configuration. So we just wait for the longest timeout of * the (1)-(3), i.e. the erase timeout. @@ -361,7 +361,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) start = get_timer (0); while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = (FPW) INTEL_RESET; /* restore read mode */ printf("WSM busy too long, can't get prot status\n"); return 1; @@ -391,7 +391,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) */ static unsigned char same_chip_banks (int bank1, int bank2) { - unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = { + unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = { {1, 1, 0, 0}, {1, 1, 0, 0}, {0, 0, 1, 1}, @@ -467,7 +467,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } else { FPWV *base; /* first address in bank */ - base = (FPWV *) (CFG_AMD_BASE); + base = (FPWV *) (CONFIG_SYS_AMD_BASE); base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */ @@ -479,7 +479,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { *addr = (FPW) 0x00B000B0; /* suspend erase */ @@ -684,7 +684,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -728,7 +728,7 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) /* wait while polling the status register */ while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -746,7 +746,7 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest) /* wait while polling the status register */ while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -779,7 +779,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) return (2); } - base = (FPWV *) (CFG_AMD_BASE); + base = (FPWV *) (CONFIG_SYS_AMD_BASE); /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); @@ -799,7 +799,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ res = 1; } @@ -856,7 +856,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) start = get_timer (0); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf ("Flash lock bit operation timed out\n"); rc = 1; break; @@ -886,17 +886,17 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) */ /* find the current bank number */ - curr_bank = CFG_MAX_FLASH_BANKS + 1; - for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) { + curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1; + for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) { if (&flash_info[j] == info) { curr_bank = j; } } - if (curr_bank == CFG_MAX_FLASH_BANKS + 1) { + if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) { printf("Error: can't determine bank number!\n"); } - for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) { + for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { if (!same_chip_banks(curr_bank, bank)) { continue; } @@ -910,7 +910,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { if (get_timer (start) > - CFG_FLASH_UNLOCK_TOUT) { + CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf ("Flash lock bit operation timed out\n"); rc = 1; break; diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c index 8a7b14ee2..0fcf354cd 100644 --- a/board/altera/common/AMDLV065D.c +++ b/board/altera/common/AMDLV065D.c @@ -30,7 +30,7 @@ #endif #define SECTSZ (64 * 1024) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------*/ unsigned long flash_init (void) @@ -39,18 +39,18 @@ unsigned long flash_init (void) unsigned long addr; flash_info_t *fli = &flash_info[0]; - fli->size = CFG_FLASH_SIZE; - fli->sector_count = CFG_MAX_FLASH_SECT; + fli->size = CONFIG_SYS_FLASH_SIZE; + fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - addr = CFG_FLASH_BASE; + addr = CONFIG_SYS_FLASH_BASE; for (i = 0; i < fli->sector_count; ++i) { fli->start[i] = addr; addr += SECTSZ; fli->protect[i] = 1; } - return (CFG_FLASH_SIZE); + return (CONFIG_SYS_FLASH_SIZE); } /*--------------------------------------------------------------------*/ void flash_print_info (flash_info_t * info) @@ -135,7 +135,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ( readb (addr2) != 0xff) { udelay (1000 * 1000); putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("timeout\n"); return 1; } @@ -177,7 +177,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* Verify write */ start = get_timer (0); while (readb (dst) != b) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return 1; } } diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c index c75fe8c57..e5e770576 100644 --- a/board/altera/common/epled.c +++ b/board/altera/common/epled.c @@ -33,7 +33,7 @@ static led_id_t val = 0; void __led_init (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; @@ -44,7 +44,7 @@ void __led_init (led_id_t mask, int state) void __led_set (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; @@ -55,7 +55,7 @@ void __led_set (led_id_t mask, int state) void __led_toggle (led_id_t mask) { - nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; writel (&pio->data, val); diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c index 2638ea899..83bb7c222 100644 --- a/board/altera/common/flash.c +++ b/board/altera/common/flash.c @@ -25,7 +25,7 @@ #include <common.h> #include <nios.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*--------------------------------------------------------------------*/ void flash_print_info (flash_info_t * info) @@ -68,8 +68,8 @@ void flash_print_info (flash_info_t * info) int flash_erase (flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int prot, sect; unsigned oldpri; ulong start; @@ -112,7 +112,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); *addr = 0xaa; *addr = 0x55; *addr = 0x80; @@ -128,7 +128,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (*addr2 != 0xff) { udelay (1000 * 1000); putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("timeout\n"); return 1; } @@ -181,7 +181,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* Verify write */ start = get_timer (0); while (*dst != b) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { ipri (oldpri); return 1; } diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c index 46695bea9..11c19b7ee 100644 --- a/board/altera/dk1c20/dk1c20.c +++ b/board/altera/dk1c20/dk1c20.c @@ -58,9 +58,9 @@ phys_size_t initdram (int board_type) #if defined(CONFIG_CMD_IDE) int ide_preinit (void) { - nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT; - nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER; - nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL; + nios_pio_t *present = (nios_pio_t *) CONFIG_SYS_CF_PRESENT; + nios_pio_t *power = (nios_pio_t *) CONFIG_SYS_CF_POWER; + nios_pio_t *atasel = (nios_pio_t *) CONFIG_SYS_CF_ATASEL; /* setup data direction registers */ present->direction = NIOS_PIO_IN; diff --git a/board/altera/dk1c20/flash.c b/board/altera/dk1c20/flash.c index 1f344dd33..8bddd38e1 100644 --- a/board/altera/dk1c20/flash.c +++ b/board/altera/dk1c20/flash.c @@ -31,7 +31,7 @@ #include "../common/flash.c" /*----------------------------------------------------------------------*/ -#define BANKSZ CFG_FLASH_SIZE +#define BANKSZ CONFIG_SYS_FLASH_SIZE #define SECTSZ (64 * 1024) #define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */ @@ -43,16 +43,16 @@ unsigned long flash_init (void) flash_info_t *fli = &flash_info[0]; fli->size = BANKSZ; - fli->sector_count = CFG_MAX_FLASH_SECT; + fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - addr = CFG_FLASH_BASE; + addr = CONFIG_SYS_FLASH_BASE; for (i = 0; i < fli->sector_count; ++i) { fli->start[i] = addr; addr += SECTSZ; /* Protect all but 2 MByte user area */ - if (addr < (CFG_FLASH_BASE + USERFLASH)) + if (addr < (CONFIG_SYS_FLASH_BASE + USERFLASH)) fli->protect[i] = 0; else fli->protect[i] = 1; diff --git a/board/altera/dk1s10/flash.c b/board/altera/dk1s10/flash.c index 5c7093352..d1f2db13b 100644 --- a/board/altera/dk1s10/flash.c +++ b/board/altera/dk1s10/flash.c @@ -43,16 +43,16 @@ unsigned long flash_init (void) flash_info_t *fli = &flash_info[0]; fli->size = BANKSZ; - fli->sector_count = CFG_MAX_FLASH_SECT; + fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - addr = CFG_FLASH_BASE; + addr = CONFIG_SYS_FLASH_BASE; for (i = 0; i < fli->sector_count; ++i) { fli->start[i] = addr; addr += SECTSZ; /* Protect all but 2 MByte user area */ - if (addr < (CFG_FLASH_BASE + USERFLASH)) + if (addr < (CONFIG_SYS_FLASH_BASE + USERFLASH)) fli->protect[i] = 0; else fli->protect[i] = 1; diff --git a/board/altera/dk1s10/vectors.S b/board/altera/dk1s10/vectors.S index 2f44875dc..226f65bb5 100644 --- a/board/altera/dk1s10/vectors.S +++ b/board/altera/dk1s10/vectors.S @@ -58,12 +58,12 @@ .align 4 _vectors: -#if defined(CFG_NIOS_CPU_OCI_BASE) +#if defined(CONFIG_SYS_NIOS_CPU_OCI_BASE) /* OCI does the reset job */ .long _def_xhandler@h /* Vector 0 - NMI / Reset */ #else /* there is no OCI, so we have to do a direct reset jump here */ - .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ + .long CONFIG_SYS_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ #endif .long _cwp_lolimit@h /* Vector 1 - underflow */ .long _cwp_hilimit@h /* Vector 2 - overflow */ @@ -81,7 +81,7 @@ _vectors: .long _def_xhandler@h /* Vector 13 - future reserved */ .long _def_xhandler@h /* Vector 14 - future reserved */ .long _def_xhandler@h /* Vector 15 - future reserved */ -#if (CFG_NIOS_TMRIRQ == 16) +#if (CONFIG_SYS_NIOS_TMRIRQ == 16) .long _timebase_int@h /* Vector 16 - lopri timer*/ #else .long _def_xhandler@h /* Vector 16 */ @@ -119,7 +119,7 @@ _vectors: .long _def_xhandler@h /* Vector 47 */ .long _def_xhandler@h /* Vector 48 */ .long _def_xhandler@h /* Vector 49 */ -#if (CFG_NIOS_TMRIRQ == 50) +#if (CONFIG_SYS_NIOS_TMRIRQ == 50) .long _timebase_int@h /* Vector 50 - lopri timer*/ #else .long _def_xhandler@h /* Vector 50 */ diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 8b82ea40e..8d79be2ce 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -31,24 +31,24 @@ static void acadia_gpio_init(void) /* * GPIO0 setup (select GPIO or alternate function) */ - out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ - out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ - out32(GPIO0_TSRL, CFG_GPIO0_TSRL); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL); + out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */ + out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L); + out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */ + out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL); + out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */ /* * Ultra (405EZ) was nice enough to add another GPIO controller */ - out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */ - out32(GPIO1_OSRL, CFG_GPIO1_OSRL); - out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */ - out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L); - out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */ - out32(GPIO1_TSRL, CFG_GPIO1_TSRL); - out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */ + out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH); /* output select */ + out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL); + out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H); /* input select */ + out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L); + out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH); /* three-state select */ + out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL); + out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR); /* enable output driver for outputs */ } int board_early_init_f(void) @@ -68,7 +68,7 @@ int board_early_init_f(void) mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); mfsdr(sdrultra0, reg); reg &= ~SDR_ULTRA0_CSN_MASK; - reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) | + reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | SDR_ULTRA0_NDGPIOBP | SDR_ULTRA0_EBCRDYEN | SDR_ULTRA0_NFSRSTEN; @@ -91,7 +91,7 @@ int board_early_init_f(void) int misc_init_f(void) { /* Set EPLD to take PHY out of reset */ - out8(CFG_CPLD_BASE + 0x05, 0x00); + out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00); udelay(100000); return 0; @@ -105,7 +105,7 @@ int checkboard(void) char *s = getenv("serial#"); u8 rev; - rev = in8(CFG_CPLD_BASE + 0); + rev = in8(CONFIG_SYS_CPLD_BASE + 0); printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev); if (s != NULL) { diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c index fb7ea3595..052cf6184 100644 --- a/board/amcc/acadia/cmd_acadia.c +++ b/board/amcc/acadia/cmd_acadia.c @@ -84,7 +84,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (i2c_write(chip, 0, 1, buf, 16) != 0) printf("Error writing to EEPROM at address 0x%x\n", chip); - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0) printf("Error2 writing to EEPROM at address 0x%x\n", chip); diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 48a672574..3e5c80ea4 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -39,7 +39,7 @@ static void cram_bcr_write(u32 wr_val) wr_val <<= 2; /* set CRAM_CRE to 1 */ - gpio_write_bit(CFG_GPIO_CRAM_CRE, 1); + gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); /* Write BCR to CRAM on CS1 */ out32(wr_val + 0x00200000, 0); @@ -53,7 +53,7 @@ static void cram_bcr_write(u32 wr_val) eieio(); /* set CRAM_CRE back to 0 (normal operation) */ - gpio_write_bit(CFG_GPIO_CRAM_CRE, 0); + gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); return; } @@ -75,10 +75,10 @@ phys_size_t initdram(int board_type) u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ - gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); /* 2. EBC in Async mode */ mtebc(pb1ap, 0x078F1EC0); @@ -94,8 +94,8 @@ phys_size_t initdram(int board_type) mtebc(pb2ap, 0x9C0201C0); /* Set GPIO pins back to alternate function */ - gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); /* Config EBC to use RDY */ mfsdr(sdrultra0, val); @@ -106,5 +106,5 @@ phys_size_t initdram(int board_type) ; #endif - return (CFG_MBYTES_RAM << 20); + return (CONFIG_SYS_MBYTES_RAM << 20); } diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index cbdc0b050..799c28ffd 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -57,7 +57,7 @@ SECTIONS /* Align to next NAND block */ . = ALIGN(0x4000); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x10000); @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds index d52b51ae1..fd5f3dfd1 100644 --- a/board/amcc/acadia/u-boot.lds +++ b/board/amcc/acadia/u-boot.lds @@ -130,6 +130,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index f4157017f..febc61a08 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -462,7 +462,7 @@ phys_size_t initdram (int board_type) return dram_size; #else - return CFG_MBYTES_SDRAM << 20; + return CONFIG_SYS_MBYTES_SDRAM << 20; #endif } @@ -529,7 +529,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -543,14 +543,14 @@ void pci_target_init(struct pci_controller *hose) | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ @@ -565,8 +565,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -580,13 +580,13 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -601,7 +601,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index b46527dcc..a37636a0a 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c index 8a2e832cf..001348ac5 100644 --- a/board/amcc/bamboo/flash.c +++ b/board/amcc/bamboo/flash.c @@ -45,12 +45,12 @@ #define DEBUGF(x...) #endif /* DEBUG */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { {0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ {0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */ @@ -79,7 +79,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; unsigned long val; @@ -128,7 +128,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -150,16 +150,16 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#if defined(CONFIG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); #endif #endif diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S index f4d2ae3f4..a5c9d6d76 100644 --- a/board/amcc/bamboo/init.S +++ b/board/amcc/bamboo/init.S @@ -48,29 +48,29 @@ tlbtab: * speed up boot process. It is patched after relocation to enable SA_I */ #ifndef CONFIG_NAND_SPL - tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #else - tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) - tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) #endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) /* PCI base & peripherals */ - tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) - tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) + tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) + tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I) /* PCI */ - tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I) /* USB 2.0 Device */ - tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I) tlbtab_end @@ -79,8 +79,8 @@ tlbtab: * For NAND booting the first TLB has to be reconfigured to full size * and with caching disabled after running from RAM! */ -#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 0) +#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0) #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) .globl reconfig_tlb0 diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index cbdc0b050..799c28ffd 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -57,7 +57,7 @@ SECTIONS /* Align to next NAND block */ . = ALIGN(0x4000); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x10000); @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds index 25d917a4f..113418de9 100644 --- a/board/amcc/bamboo/u-boot.lds +++ b/board/amcc/bamboo/u-boot.lds @@ -138,6 +138,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c index e4832ebf3..a10babbf7 100644 --- a/board/amcc/bubinga/flash.c +++ b/board/amcc/bubinga/flash.c @@ -32,7 +32,7 @@ #include <ppc4xx.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #undef DEBUG #ifdef DEBUG @@ -60,7 +60,7 @@ unsigned long flash_init(void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -75,21 +75,21 @@ unsigned long flash_init(void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { + if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { /* Setup offsets */ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#ifdef CONFIG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif @@ -133,7 +133,7 @@ unsigned long flash_init(void) /* monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - base_b0 + size_b0 - CFG_MONITOR_LEN, + base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN, base_b0 + size_b0 - 1, &flash_info[0]); /* Also protect sector containing initial power-up instruction */ /* (flash_protect() checks address range - other call ignored) */ @@ -151,12 +151,12 @@ unsigned long flash_init(void) /* monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - base_b1 + size_b1 - CFG_MONITOR_LEN, + base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN, base_b1 + size_b1 - 1, &flash_info[1]); /* monitor protection OFF by default (one is enough) */ (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0 + size_b0 - CFG_MONITOR_LEN, + base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN, base_b0 + size_b0 - 1, &flash_info[0]); } else { diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds index d52b51ae1..fd5f3dfd1 100644 --- a/board/amcc/bubinga/u-boot.lds +++ b/board/amcc/bubinga/u-boot.lds @@ -130,6 +130,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c index 1d125b6e6..b1f4a213d 100644 --- a/board/amcc/canyonlands/bootstrap.c +++ b/board/amcc/canyonlands/bootstrap.c @@ -40,6 +40,8 @@ static char *config_labels[] = { "CPU: 600 PLB: 200 OPB: 100 EBC: 100", "CPU: 800 PLB: 200 OPB: 100 EBC: 100", + "CPU:1000 PLB: 200 OPB: 100 EBC: 100", + "CPU:1066 PLB: 266 OPB: 88 EBC: 88", NULL }; @@ -55,6 +57,16 @@ static u8 boot_configs[][17] = { 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 }, { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x86, 0x82, 0x96, 0x19, 0xb9, 0x80, 0x00, 0xa0, 0x40, 0x08, + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { + (NAND_COMPATIBLE | NOR_COMPATIBLE), + 0x86, 0x80, 0xb3, 0x01, 0x9d, 0x80, 0x00, 0xa0, 0x40, 0x08, + 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 + }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } @@ -168,7 +180,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); printf("Done\n"); printf("Please power-cycle the board for the changes to take effect\n"); diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index e9eba49c4..2b7468923 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -29,20 +29,61 @@ #include <asm/4xx_pcie.h> #include <asm/gpio.h> -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ DECLARE_GLOBAL_DATA_PTR; -#define CFG_BCSR3_PCIE 0x10 +#define CONFIG_SYS_BCSR3_PCIE 0x10 #define BOARD_CANYONLANDS_PCIE 1 #define BOARD_CANYONLANDS_SATA 2 #define BOARD_GLACIER 3 +#define BOARD_ARCHES 4 + +#if defined(CONFIG_ARCHES) +/* + * FPGA read/write helper macros + */ +static inline int board_fpga_read(int offset) +{ + int data; + + data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset)); + + return data; +} + +static inline void board_fpga_write(int offset, int data) +{ + out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data); +} + +/* + * CPLD read/write helper macros + */ +static inline int board_cpld_read(int offset) +{ + int data; + + out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); + data = in_8((void *)(CONFIG_SYS_CPLD_DATA)); + + return data; +} + +static inline void board_cpld_write(int offset, int data) +{ + out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset); + out_8((void *)(CONFIG_SYS_CPLD_DATA), data); +} +#endif /* defined(CONFIG_ARCHES) */ int board_early_init_f(void) { +#if !defined(CONFIG_ARCHES) u32 sdr0_cust0; u32 pvr = get_pvr(); +#endif /* * Setup the interrupt controller polarities, triggers, etc. @@ -79,6 +120,7 @@ int board_early_init_f(void) mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic3sr, 0xffffffff); /* clear all */ +#if !defined(CONFIG_ARCHES) /* SDR Setting - enable NDFC */ mfsdr(SDR0_CUST0, sdr0_cust0); sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | @@ -86,8 +128,9 @@ int board_early_init_f(void) SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_NDFC_BAC_ENCODE(3) | - (0x80000000 >> (28 + CFG_NAND_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); +#endif /* * Configure PFC (Pin Function Control) registers @@ -98,14 +141,15 @@ int board_early_init_f(void) /* Enable PCI host functionality in SDR0_PCI0 */ mtsdr(SDR0_PCI0, 0xe0000000); +#if !defined(CONFIG_ARCHES) /* Enable ethernet and take out of reset */ - out_8((void *)CFG_BCSR_BASE + 6, 0); + out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0); /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */ - out_8((void *)CFG_BCSR_BASE + 5, 0); + out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0); /* Enable USB host & USB-OTG */ - out_8((void *)CFG_BCSR_BASE + 7, 0); + out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0); mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */ @@ -123,10 +167,12 @@ int board_early_init_f(void) gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1); } +#endif return 0; } +#if !defined(CONFIG_ARCHES) static void canyonlands_sata_init(int board_type) { u32 reg; @@ -147,7 +193,26 @@ static void canyonlands_sata_init(int board_type) SDR_WRITE(SDR0_SRST1, 0x00000000); } } +#endif /* !defined(CONFIG_ARCHES) */ + +int get_cpu_num(void) +{ + int cpu = NA_OR_UNKNOWN_CPU; + +#if defined(CONFIG_ARCHES) + int cpu_num; + + cpu_num = board_fpga_read(0x3); + + /* sanity check; assume cpu numbering starts and increments from 0 */ + if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS)) + cpu = cpu_num; +#endif + + return cpu; +} +#if !defined(CONFIG_ARCHES) int checkboard(void) { char *s = getenv("serial#"); @@ -158,7 +223,7 @@ int checkboard(void) gd->board_type = BOARD_GLACIER; } else { printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board"); - if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE) + if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE) gd->board_type = BOARD_CANYONLANDS_PCIE; else gd->board_type = BOARD_CANYONLANDS_SATA; @@ -175,7 +240,7 @@ int checkboard(void) break; } - printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0))); + printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0))); if (s != NULL) { puts(", serial# "); @@ -188,6 +253,39 @@ int checkboard(void) return (0); } +#else /* defined(CONFIG_ARCHES) */ + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n"); + printf(" Revision %02x.%02x ", + board_fpga_read(0x0), board_fpga_read(0x1)); + + gd->board_type = BOARD_ARCHES; + + /* Only CPU0 has access to CPLD registers */ + if (get_cpu_num() == 0) { + u8 cfg_sw = board_cpld_read(0x1); + printf("(FPGA=%02x, CPLD=%02x)\n", + board_fpga_read(0x2), board_cpld_read(0x0)); + printf(" Configuration Switch %d%d%d%d\n", + ((cfg_sw >> 3) & 0x01), + ((cfg_sw >> 2) & 0x01), + ((cfg_sw >> 1) & 0x01), + ((cfg_sw >> 0) & 0x01)); + } else + printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2)); + + + if (s != NULL) + printf(" Serial# %s\n", s); + + return 0; +} +#endif /* !defined(CONFIG_ARCHES) */ + /* * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with * board specific values. @@ -208,7 +306,7 @@ u32 ddr_clktr(u32 default_val) { */ phys_size_t initdram(int board_type) { - return CFG_MBYTES_SDRAM << 20; + return CONFIG_SYS_MBYTES_SDRAM << 20; } #endif @@ -219,7 +317,7 @@ phys_size_t initdram(int board_type) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /* @@ -234,7 +332,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. */ - out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); out_le32((void *)PCIX0_PIM0LAH, 0); out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); out_le32((void *)PCIX0_BAR0, 0); @@ -242,12 +340,12 @@ void pci_target_init(struct pci_controller * hose ) /* * Program the board's subsystem id/vendor id */ - out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ #if defined(CONFIG_PCI) /* @@ -314,9 +412,9 @@ void pcie_setup_hoses(int busno) /* setup mem resource */ pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMSIZE, PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); @@ -362,16 +460,16 @@ int board_early_init_r (void) /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000); + mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #else - mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000); + mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #endif /* Remove TLB entry of boot EBC mapping */ - remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20); + remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20); /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */ - program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE, + program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE); /* @@ -389,6 +487,7 @@ int board_early_init_r (void) return 0; } +#if !defined(CONFIG_ARCHES) int misc_init_r(void) { u32 sdr0_srst1 = 0; @@ -427,13 +526,54 @@ int misc_init_r(void) * Disable square wave output: Batterie will be drained * quickly, when this output is not disabled */ - val = i2c_reg_read(CFG_I2C_RTC_ADDR, 0xa); + val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa); val &= ~0x40; - i2c_reg_write(CFG_I2C_RTC_ADDR, 0xa, val); + i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val); return 0; } +#else /* defined(CONFIG_ARCHES) */ + +int misc_init_r(void) +{ + u32 eth_cfg = 0; + u32 eth_pll; + u32 reg; + + /* + * Set EMAC mode/configuration (GMII, SGMII, RGMII...). + * This is board specific, so let's do it here. + */ + + /* enable SGMII mode */ + eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE | + SDR0_ETH_CFG_SGMII1_ENABLE | + SDR0_ETH_CFG_SGMII2_ENABLE); + + /* Set EMAC for MDIO */ + eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; + + /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ + eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); + + mtsdr(SDR0_ETH_CFG, eth_cfg); + + /* reset all SGMII interfaces */ + mfsdr(SDR0_SRST1, reg); + reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2); + mtsdr(SDR0_SRST1, reg); + mtsdr(SDR0_ETH_STS, 0xFFFFFFFF); + mtsdr(SDR0_SRST1, 0x00000000); + + do { + mfsdr(SDR0_ETH_PLL, eth_pll); + } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK)); + + return 0; +} +#endif /* !defined(CONFIG_ARCHES) */ + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { @@ -445,7 +585,7 @@ void ft_board_setup(void *blob, bd_t *bd) /* Fixup NOR mapping */ val[0] = 0; /* chip select number */ val[1] = 0; /* always 0 */ - val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */ + val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */ val[3] = gd->bd->bi_flashsize; rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", val, sizeof(val), 1); @@ -460,12 +600,8 @@ void ft_board_setup(void *blob, bd_t *bd) * node in the device tree, so that Linux doesn't initialize * it. */ - rc = fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCIe node, err=%s\n", - fdt_strerror(rc)); - } + fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", + "disabled", sizeof("disabled"), 1); } if (gd->board_type == BOARD_CANYONLANDS_PCIE) { @@ -474,12 +610,8 @@ void ft_board_setup(void *blob, bd_t *bd) * node in the device tree, so that Linux doesn't initialize * it. */ - rc = fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", - "disabled", sizeof("disabled"), 1); - if (rc) { - printf("Unable to update property status in PCIe node, err=%s\n", - fdt_strerror(rc)); - } + fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", + "disabled", sizeof("disabled"), 1); } } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk index 2330cae92..551a81755 100644 --- a/board/amcc/canyonlands/config.mk +++ b/board/amcc/canyonlands/config.mk @@ -37,5 +37,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index 258fb5de8..0b667968a 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -47,10 +47,10 @@ tlbtab: * enable SA_I */ #ifndef CONFIG_NAND_SPL - tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ #else - tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) - tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I) #endif @@ -60,37 +60,54 @@ tlbtab: * routine. */ -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #endif - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) /* PCIe UTL register */ - tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) +#if !defined(CONFIG_ARCHES) /* TLB-entry for NAND */ - tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) /* TLB-entry for CPLD */ - tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#else + /* TLB-entry for FPGA */ + tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I) +#endif /* TLB-entry for OCM */ - tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) /* TLB-entry for Local Configuration registers => peripherals */ - tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) /* AHB: Internal USB Peripherals (USB, SATA) */ - tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) + +#if defined(CONFIG_RAPIDIO) + /* TLB-entries for RapidIO (SRIO) */ + tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR, + 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000, + 0x4, AC_R|AC_W|SA_G|SA_I) +#endif tlbtab_end @@ -99,8 +116,8 @@ tlbtab: * For NAND booting the first TLB has to be reconfigured to full size * and with caching disabled after running from RAM! */ -#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) .globl reconfig_tlb0 diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 8a4b7f5d0..9f13d031a 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -57,7 +57,7 @@ SECTIONS /* Align to next NAND block */ . = ALIGN(0x20000); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x80000); @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/amcc/canyonlands/u-boot.lds b/board/amcc/canyonlands/u-boot.lds index 1783bc73f..f0db0b232 100644 --- a/board/amcc/canyonlands/u-boot.lds +++ b/board/amcc/canyonlands/u-boot.lds @@ -136,6 +136,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index eba0511f2..9943c744b 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -35,13 +35,13 @@ #include <ppc4xx.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions */ static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word_1(flash_info_t * info, ulong dest, ulong data); static int write_word_2(flash_info_t * info, ulong dest, ulong data); static int flash_erase_1(flash_info_t * info, int s_first, int s_last); @@ -171,7 +171,7 @@ void flash_print_info(flash_info_t * info) /* * The following code cannot be run from FLASH! */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static ulong flash_get_size(vu_long * addr, flash_info_t * info) { /* bit 0 used for big flash marking */ @@ -188,32 +188,32 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) #endif { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; default: @@ -227,67 +227,67 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 KiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 KiB */ break; - case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 KiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: info->flash_id += FLASH_AMD016; info->sector_count = 32; info->size = 0x00200000; /* => 2 MiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: info->flash_id += FLASH_AMDLV033C; info->sector_count = 64; info->size = 0x00400000; /* => 4 MiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; /* => 512 KiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; /* => 512 KiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; /* => 1 MiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; /* => 1 MiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; /* => 2 MiB */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; /* => 2 MiB */ @@ -331,14 +331,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); /* For AMD29033C flash we need to resend the command of * * reading flash protection for upper 8 Mb of flash */ if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) @@ -348,7 +348,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -356,14 +356,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_1(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -376,7 +376,7 @@ static int wait_for_DQ7_1(flash_info_t * info, int sect) return 0; } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV int flash_erase(flash_info_t * info, int s_first, int s_last) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || @@ -394,8 +394,8 @@ static int flash_erase_1(flash_info_t * info, int s_first, int s_last) int flash_erase(flash_info_t * info, int s_first, int s_last) #endif { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; int i; @@ -435,24 +435,24 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ for (i = 0; i < 50; i++) udelay(1000); /* wait 1 ms */ } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } l_sect = sect; /* @@ -474,8 +474,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); return 0; @@ -557,7 +557,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word(flash_info_t * info, ulong dest, ulong data) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || @@ -575,9 +575,9 @@ static int write_word_1(flash_info_t * info, ulong dest, ulong data) static int write_word(flash_info_t * info, ulong dest, ulong data) #endif { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i; @@ -586,15 +586,15 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) return (2); } - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { int flag; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; dest2[i] = data2[i]; @@ -604,10 +604,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -616,10 +616,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) return (0); } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -#undef CFG_FLASH_WORD_SIZE -#define CFG_FLASH_WORD_SIZE unsigned short +#undef CONFIG_SYS_FLASH_WORD_SIZE +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* * The following code cannot be run from FLASH! @@ -628,35 +628,35 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) { short i; int n; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; - case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT: info->flash_id = FLASH_MAN_MX; break; default: @@ -672,22 +672,22 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MiB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MiB */ - case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT: info->flash_id += FLASH_STMW320DT; info->sector_count = 67; info->size = 0x00400000; break; /* => 4 MiB */ - case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T: info->flash_id += FLASH_MXLV320T; info->sector_count = 71; info->size = 0x00400000; @@ -776,14 +776,14 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); /* For AMD29033C flash we need to resend the command of * * reading flash protection for upper 8 Mb of flash */ if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) @@ -793,7 +793,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -801,14 +801,14 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_2(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -823,8 +823,8 @@ static int wait_for_DQ7_2(flash_info_t * info, int sect) static int flash_erase_2(flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; int i; @@ -864,24 +864,24 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ for (i = 0; i < 50; i++) udelay(1000); /* wait 1 ms */ } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } l_sect = sect; /* @@ -903,8 +903,8 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); return 0; @@ -912,9 +912,9 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) static int write_word_2(flash_info_t * info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i; @@ -923,15 +923,15 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data) return (2); } - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { int flag; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; dest2[i] = data2[i]; @@ -941,10 +941,10 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -952,4 +952,4 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data) return (0); } -#endif /* CFG_FLASH_2ND_16BIT_DEV */ +#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk index e5722dd36..60d3bf4d2 100644 --- a/board/amcc/ebony/config.mk +++ b/board/amcc/ebony/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index 9bcdf5997..ad09e6207 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -35,7 +35,7 @@ long int fixed_sdram(void); int board_early_init_f(void) { uint reg; - unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; unsigned char status; /*-------------------------------------------------------------------- @@ -204,7 +204,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -219,7 +219,7 @@ void pci_target_init(struct pci_controller *hose) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); out32r(PCIX0_PIM0LAH, 0); out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); @@ -228,12 +228,12 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c index e8fbbc493..8fe3ba1b8 100644 --- a/board/amcc/ebony/flash.c +++ b/board/amcc/ebony/flash.c @@ -50,7 +50,7 @@ #define FLASH_ONBD_N_VAL 2 #define FLASH_SRAM_SEL_VAL 1 -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */ {0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */ {0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */ @@ -74,8 +74,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; unsigned char switch_status; unsigned short index = 0; int i; @@ -98,7 +98,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -121,15 +121,15 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[2]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#ifdef CONFIG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[2]); #endif diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S index c86076e80..811a96a1f 100644 --- a/board/amcc/ebony/init.S +++ b/board/amcc/ebony/init.S @@ -49,9 +49,9 @@ tlbtab: * routine. */ - tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) + tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds index 6be4bd102..17d1ba85f 100644 --- a/board/amcc/ebony/u-boot.lds +++ b/board/amcc/ebony/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c index 703d22560..ba71bd55c 100644 --- a/board/amcc/katmai/cmd_katmai.c +++ b/board/amcc/katmai/cmd_katmai.c @@ -57,9 +57,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) do { #ifdef CONFIG_STRESS - printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n"); #else - printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif nbytes = readline (" ? "); @@ -87,11 +87,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else { do { if (strcmp(cpuClock, "400") == 0) - printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); + printf("enter plb clock frequency 100, 133 MHz or quit to abort\n"); #ifdef CONFIG_STRESS if (strcmp(cpuClock, "667") == 0) - printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); + printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif nbytes = readline (" ? "); @@ -117,7 +117,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } do { - printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); + printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); nbytes = readline (" ? "); if (strcmp(console_buffer, "quit") == 0) @@ -133,10 +133,10 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } while (nbytes == 0); - printf("\nsys clk = %sMhz\n", sysClock); - printf("cpu clk = %sMhz\n", cpuClock); - printf("plb clk = %sMhz\n", plbClock); - printf("Pci-X clk = %sMhz\n", pcixClock); + printf("\nsys clk = %s MHz\n", sysClock); + printf("cpu clk = %s MHz\n", cpuClock); + printf("plb clk = %s MHz\n", plbClock); + printf("Pci-X clk = %s MHz\n", pcixClock); do { printf("\npress [y] to write I2C bootstrap \n"); diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk index c512b53c6..ef0cf9672 100644 --- a/board/amcc/katmai/config.mk +++ b/board/amcc/katmai/config.mk @@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index e3f3da6bd..1c74a82c3 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -59,20 +59,20 @@ tlbtabA: * routine. */ - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbtab_end /************************************************************************** @@ -99,20 +99,20 @@ tlbtabB: * routine. */ - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 08d89d779..b6c0c11ef 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -27,6 +27,7 @@ #include <i2c.h> #include <libfdt.h> #include <fdt_support.h> +#include <netdev.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/gpio.h> @@ -223,11 +224,11 @@ int board_early_init_f (void) mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ mtsdr(sdr_mfr, mfr); - mtsdr(SDR0_PFC0, CFG_PFC0); + mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); - out32(GPIO0_OR, CFG_GPIO_OR); - out32(GPIO0_ODR, CFG_GPIO_ODR); - out32(GPIO0_TCR, CFG_GPIO_TCR); + out32(GPIO0_OR, CONFIG_SYS_GPIO_OR); + out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR); + out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR); return 0; } @@ -297,7 +298,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*-------------------------------------------------------------------+ @@ -312,7 +313,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); out32r( PCIX0_BAR0, 0 ); @@ -320,12 +321,12 @@ void pci_target_init(struct pci_controller * hose ) /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ #if defined(CONFIG_PCI) /************************************************************************* @@ -356,11 +357,11 @@ static int katmai_pcie_card_present(int port) val = in32(GPIO0_IR); switch (port) { case 0: - return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0)); + return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0)); case 1: - return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1)); + return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1)); case 2: - return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2)); + return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2)); default: return 0; } @@ -403,9 +404,9 @@ void pcie_setup_hoses(int busno) /* setup mem resource */ pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMSIZE, PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); @@ -447,3 +448,8 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/amcc/katmai/u-boot.lds b/board/amcc/katmai/u-boot.lds index 36aa6de12..464bc6ecc 100644 --- a/board/amcc/katmai/u-boot.lds +++ b/board/amcc/katmai/u-boot.lds @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/kilauea/cmd_pll.c b/board/amcc/kilauea/cmd_pll.c index 0d2f27fe5..0f571fefe 100644 --- a/board/amcc/kilauea/cmd_pll.c +++ b/board/amcc/kilauea/cmd_pll.c @@ -48,7 +48,7 @@ do { \ int __i; \ for (__i = 0; __i < 2; __i++) \ - eeprom_write (CFG_I2C_EEPROM_ADDR, \ + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \ EEPROM_CONF_OFFSET + __i*BUF_STEP, \ pll_select[freq], \ BUF_STEP + __i*BUF_STEP); \ @@ -151,7 +151,7 @@ pll_debug(int off) uchar buffer[EEPROM_SDSTP_PARAM]; memset(buffer, 0, sizeof(buffer)); - eeprom_read(CFG_I2C_EEPROM_ADDR, off, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, buffer, EEPROM_SDSTP_PARAM); printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); @@ -168,9 +168,9 @@ test_write(void) /* * Write twice, 8 bytes per write */ - eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, testbuf, 8); - eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, testbuf, 16); printf("done\n"); @@ -236,7 +236,7 @@ ret: } U_BOOT_CMD( - pllalter, CFG_MAXARGS, 1, do_pll_alter, + pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, "pllalter- change pll frequence \n", "pllalter <selection> - change pll frequence \n\n\ ** New freq take effect after reset. ** \n\ diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 7b1025526..7e84a61a9 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Board early initialization function @@ -197,7 +197,7 @@ int board_early_init_f (void) SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NRB_BUSY | - (0x80000000 >> (28 + CFG_NAND_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); mtsdr(SDR0_CUST0, val); /* @@ -210,19 +210,19 @@ int board_early_init_f (void) /* * Configure FPGA register with PCIe reset */ - out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ + out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ mdelay(50); - out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ + out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ return 0; } int misc_init_r(void) { -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); #endif @@ -330,9 +330,9 @@ void pcie_setup_hoses(int busno) /* setup mem resource */ pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMSIZE, PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index cbdc0b050..799c28ffd 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -57,7 +57,7 @@ SECTIONS /* Align to next NAND block */ . = ALIGN(0x4000); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x10000); @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/amcc/kilauea/u-boot.lds b/board/amcc/kilauea/u-boot.lds index fe51ca1bf..0ac21e391 100644 --- a/board/amcc/kilauea/u-boot.lds +++ b/board/amcc/kilauea/u-boot.lds @@ -130,6 +130,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk index f52c20617..cd02aab57 100644 --- a/board/amcc/luan/config.mk +++ b/board/amcc/luan/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c index d3c3c0d05..2d3b15438 100644 --- a/board/amcc/luan/flash.c +++ b/board/amcc/luan/flash.c @@ -42,7 +42,7 @@ #define DEBUGF(x...) #endif /* DEBUG */ -static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xff900000, 0xff980000, 0xffc00000}, /* 0:000: configuraton 3 */ }; @@ -59,7 +59,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; @@ -69,7 +69,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -92,15 +92,15 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[2]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#ifdef CONFIG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[2]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[2]); #endif diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S index d5ee117df..fb54dea3a 100644 --- a/board/amcc/luan/init.S +++ b/board/amcc/luan/init.S @@ -54,7 +54,7 @@ tlbtab: tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I) /* * TLB entries for SDRAM are not needed on this platform. @@ -63,12 +63,12 @@ tlbtab: */ /* internal ram (l2 cache) */ - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I) /* peripherals at f0000000 */ - tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I) /* PCI */ - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index b14b6e1b5..de3e3d8b9 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -25,12 +25,13 @@ #include <command.h> #include <ppc4xx.h> #include <asm/processor.h> +#include <asm/ppc4xx-isram.h> #include <spd_sdram.h> #include "epld.h" DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /************************************************************************* @@ -80,7 +81,7 @@ int board_early_init_f(void) ************************************************************************/ int misc_init_r(void) { - volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; + volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE; /* set modes of operation */ x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | @@ -166,7 +167,7 @@ int pci_pre_init( struct pci_controller *hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -181,7 +182,7 @@ void pci_target_init(struct pci_controller *hose) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -190,12 +191,12 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* @@ -255,7 +256,7 @@ static int on_off( const char *s ) ************************************************************************/ static void l2cache_disable(void) { - mtdcr( l2_cache_cfg, 0 ); + mtdcr( L2_CACHE_CFG, 0 ); } @@ -265,24 +266,24 @@ static void l2cache_disable(void) ************************************************************************/ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ { - mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ + mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ - mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */ + mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */ - mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ + mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ - while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */ + while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */ - mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ + mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ - mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ + mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ - mtdcr( l2_cache_snp0, 0 ); /* snoop registers */ - mtdcr( l2_cache_snp1, 0 ); + mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */ + mtdcr( L2_CACHE_SNP1, 0 ); __asm__ volatile ("sync"); /* msync */ - mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */ + mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */ __asm__ volatile ("sync"); } @@ -294,7 +295,7 @@ static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ ************************************************************************/ static int l2cache_status(void) { - return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0; + return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0; } diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds index 791178517..b66c768b4 100644 --- a/board/amcc/luan/u-boot.lds +++ b/board/amcc/luan/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c index 0d2f27fe5..0f571fefe 100644 --- a/board/amcc/makalu/cmd_pll.c +++ b/board/amcc/makalu/cmd_pll.c @@ -48,7 +48,7 @@ do { \ int __i; \ for (__i = 0; __i < 2; __i++) \ - eeprom_write (CFG_I2C_EEPROM_ADDR, \ + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, \ EEPROM_CONF_OFFSET + __i*BUF_STEP, \ pll_select[freq], \ BUF_STEP + __i*BUF_STEP); \ @@ -151,7 +151,7 @@ pll_debug(int off) uchar buffer[EEPROM_SDSTP_PARAM]; memset(buffer, 0, sizeof(buffer)); - eeprom_read(CFG_I2C_EEPROM_ADDR, off, + eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off, buffer, EEPROM_SDSTP_PARAM); printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); @@ -168,9 +168,9 @@ test_write(void) /* * Write twice, 8 bytes per write */ - eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, testbuf, 8); - eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, testbuf, 16); printf("done\n"); @@ -236,7 +236,7 @@ ret: } U_BOOT_CMD( - pllalter, CFG_MAXARGS, 1, do_pll_alter, + pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, "pllalter- change pll frequence \n", "pllalter <selection> - change pll frequence \n\n\ ** New freq take effect after reset. ** \n\ diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index 2b4d3d4b7..9fc0ec666 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Board early initialization function @@ -194,9 +194,9 @@ int board_early_init_f (void) mtsdr(SDR0_SRST, 0); /* Reset PCIe slots */ - gpio_write_bit(CFG_GPIO_PCIE_RST, 0); + gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0); udelay(100); - gpio_write_bit(CFG_GPIO_PCIE_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1); /* * Configure PFC (Pin Function Control) registers @@ -210,10 +210,10 @@ int board_early_init_f (void) int misc_init_r(void) { -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); #endif @@ -286,9 +286,9 @@ void pcie_setup_hoses(int busno) /* setup mem resource */ pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMSIZE, PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); diff --git a/board/amcc/makalu/u-boot.lds b/board/amcc/makalu/u-boot.lds index fe51ca1bf..0ac21e391 100644 --- a/board/amcc/makalu/u-boot.lds +++ b/board/amcc/makalu/u-boot.lds @@ -130,6 +130,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk index 9e1833591..b62e776d3 100644 --- a/board/amcc/ocotea/config.mk +++ b/board/amcc/ocotea/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c index 5614e2078..a83f93afa 100644 --- a/board/amcc/ocotea/flash.c +++ b/board/amcc/ocotea/flash.c @@ -53,9 +53,9 @@ #define FLASH_ONBD_N_VAL 2 #define FLASH_SRAM_SEL_VAL 1 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */ {0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */ {0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */ @@ -83,8 +83,8 @@ static int write_word(flash_info_t * info, ulong dest, ulong data); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; - unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; + unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; unsigned char switch_status; unsigned short index = 0; int i; @@ -107,7 +107,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -131,15 +131,15 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[i]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#ifdef CONFIG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); #endif diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S index d211c710b..8bcfbb197 100644 --- a/board/amcc/ocotea/init.S +++ b/board/amcc/ocotea/init.S @@ -49,9 +49,9 @@ tlbtab: * routine. */ - tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X) + tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 4d1d09321..fe4540849 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -42,7 +42,7 @@ void fpga_init (void); int board_early_init_f (void) { unsigned long mfr; - unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; + unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE; unsigned char switch_status; unsigned long cs0_base; unsigned long cs0_size; @@ -315,7 +315,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -330,7 +330,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -339,12 +339,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h index 95ce1fd35..400852ab7 100644 --- a/board/amcc/ocotea/ocotea.h +++ b/board/amcc/ocotea/ocotea.h @@ -22,7 +22,7 @@ */ /* Board specific FPGA stuff ... */ -#define FPGA_REG0 (CFG_FPGA_BASE + 0x00) +#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00) #define FPGA_REG0_SSCG_MASK 0x80 #define FPGA_REG0_SSCG_DISABLE 0x00 #define FPGA_REG0_SSCG_ENABLE 0x80 @@ -48,7 +48,7 @@ #define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 #define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 #define FPGA_REG0_FLASH 0x01 -#define FPGA_REG1 (CFG_FPGA_BASE + 0x01) +#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01) #define FPGA_REG1_9772_FSELFBX_MASK 0x80 #define FPGA_REG1_9772_FSELFBX_6 0x00 #define FPGA_REG1_9772_FSELFBX_10 0x80 @@ -71,7 +71,7 @@ #define FPGA_REG1_SOURCE_SSDIV1 0x05 #define FPGA_REG1_SOURCE_SSDIV2 0x06 #define FPGA_REG1_SOURCE_SSDIV4 0x07 -#define FPGA_REG2 (CFG_FPGA_BASE + 0x02) +#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02) #define FPGA_REG2_TC0 0x80 #define FPGA_REG2_TC1 0x40 #define FPGA_REG2_TC2 0x20 @@ -82,7 +82,7 @@ #define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 #define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ #define FPGA_REG2_DEFAULT_UART1_N 0x01 -#define FPGA_REG3 (CFG_FPGA_BASE + 0x03) +#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03) #define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ #define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ #define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ @@ -108,7 +108,7 @@ #define FPGA_REG3_STAT_LED4_DISAB 0x00 #define FPGA_REG3_STAT_LED2_DISAB 0x00 #define FPGA_REG3_STAT_LED1_DISAB 0x00 -#define FPGA_REG4 (CFG_FPGA_BASE + 0x04) +#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04) #define FPGA_REG4_GPHY_MODE10 0x80 #define FPGA_REG4_GPHY_MODE100 0x40 #define FPGA_REG4_GPHY_MODE1000 0x20 diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds index 298aba82d..8f6187313 100644 --- a/board/amcc/ocotea/u-boot.lds +++ b/board/amcc/ocotea/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk index f33336d93..381f2b23d 100644 --- a/board/amcc/redwood/config.mk +++ b/board/amcc/redwood/config.mk @@ -38,5 +38,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S index fcffada30..363d7932a 100644 --- a/board/amcc/redwood/init.S +++ b/board/amcc/redwood/init.S @@ -54,24 +54,24 @@ tlbtab: */ /* Although 512 KB, map 256k at a time */ - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) /* * Peripheral base */ - tlbentry(CFG_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/redwood/u-boot.lds b/board/amcc/redwood/u-boot.lds index 2104cc2a3..8362c9b8a 100644 --- a/board/amcc/redwood/u-boot.lds +++ b/board/amcc/redwood/u-boot.lds @@ -70,7 +70,7 @@ SECTIONS board/amcc/redwood/init.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -141,6 +141,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index 6b9043a05..3402f84a3 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -46,7 +46,7 @@ #define NAND_COMPATIBLE 0x01 #define NOR_COMPATIBLE 0x02 -/* check with Stefan on CFG_I2C_EEPROM_ADDR */ +/* check with Stefan on CONFIG_SYS_I2C_EEPROM_ADDR */ #define I2C_EEPROM_ADDR 0x52 static char *config_labels[] = { @@ -207,7 +207,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } /* check CPLD register +5 for PCI 66MHz flag */ - if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0) + if ((in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN) == 0) /* * PLB-to-PCI divisor = 3 for 33MHz sync PCI * instead of 2 for 66MHz systems @@ -216,7 +216,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); printf("Done\n"); printf("Please power-cycle the board for the changes to take effect\n"); diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk index 5e04ee4e3..6c748c914 100644 --- a/board/amcc/sequoia/config.mk +++ b/board/amcc/sequoia/config.mk @@ -41,5 +41,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 46a37c6a2..bd346bf04 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -45,36 +45,36 @@ tlbtab: /* TLB-entry for DDR SDRAM (Up to 2GB) */ #ifdef CONFIG_4xx_DCACHE - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) #else - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) #endif /* TLB-entry for EBC */ - tlbentry( CFG_BCSR_BASE, SZ_256M, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ #ifndef CONFIG_NAND_SPL - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) #else - tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for NAND */ - tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) @@ -95,8 +95,8 @@ tlbtab: * For NAND booting the first TLB has to be reconfigured to full size * and with caching disabled after running from RAM! */ -#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) .globl reconfig_tlb0 diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 77e6c7b4d..64eb06308 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -113,5 +113,5 @@ phys_size_t initdram (int board_type) */ set_mcsr(get_mcsr()); - return (CFG_MBYTES_SDRAM << 20); + return (CONFIG_SYS_MBYTES_SDRAM << 20); } diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 176d5cf0d..d6668e29b 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size (ulong base, int banknum); @@ -74,16 +74,16 @@ int board_early_init_f(void) mtdcr(uic2sr, 0xffffffff); /* clear all */ /* 50MHz tmrclk */ - out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00); + out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); /* clear write protects */ - out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00); + out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00); /* enable Ethernet */ - out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00); + out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00); /* enable USB device */ - out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20); + out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20); /* select Ethernet (and optionally IIC1) pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -113,7 +113,7 @@ int board_early_init_f(void) SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CFG_NAND_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); return 0; @@ -157,17 +157,17 @@ int misc_init_r(void) */ flash_get_size(gd->bd->bi_flashstart, 0); -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif @@ -320,8 +320,8 @@ int checkboard(void) printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); #endif - rev = in_8((void *)(CFG_BCSR_BASE + 0)); - val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; + rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); + val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { @@ -407,7 +407,7 @@ int pci_pre_init(struct pci_controller *hose) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /* @@ -423,16 +423,16 @@ void pci_target_init(struct pci_controller *hose) */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ @@ -448,8 +448,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -463,9 +463,9 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -480,7 +480,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /* * is_pci_host diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index ae2e18de4..6e1e16997 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -57,7 +57,7 @@ SECTIONS /* Align to next NAND block */ . = ALIGN(0x4000); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x10000); @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/amcc/sequoia/u-boot.lds b/board/amcc/sequoia/u-boot.lds index b20fb1c0a..05152b7f7 100644 --- a/board/amcc/sequoia/u-boot.lds +++ b/board/amcc/sequoia/u-boot.lds @@ -135,9 +135,10 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c index 290259e73..110cbe5e9 100644 --- a/board/amcc/taihu/flash.c +++ b/board/amcc/taihu/flash.c @@ -32,7 +32,7 @@ #include <ppc4xx.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #undef DEBUG #ifdef DEBUG @@ -41,9 +41,9 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define DEBUGF(x...) #endif /* DEBUG */ -#define CFG_FLASH_CHAR_SIZE unsigned char -#define CFG_FLASH_CHAR_ADDR0 (0x0aaa) -#define CFG_FLASH_CHAR_ADDR1 (0x0555) +#define CONFIG_SYS_FLASH_CHAR_SIZE unsigned char +#define CONFIG_SYS_FLASH_CHAR_ADDR0 (0x0aaa) +#define CONFIG_SYS_FLASH_CHAR_ADDR1 (0x0555) /*----------------------------------------------------------------------- * Functions */ @@ -65,7 +65,7 @@ unsigned long flash_init(void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -84,15 +84,15 @@ unsigned long flash_init(void) flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#ifdef CONFIG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif /* Also protect sector containing initial power-up instruction */ @@ -299,32 +299,32 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) #endif { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; default: @@ -338,67 +338,67 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: info->flash_id += FLASH_AMD016; info->sector_count = 32; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: info->flash_id += FLASH_AMDLV033C; info->sector_count = 64; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; @@ -445,14 +445,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); /* For AMD29033C flash we need to resend the command of * * reading flash protection for upper 8 Mb of flash */ if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) @@ -462,7 +462,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return info->size; } @@ -470,14 +470,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_1(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -509,8 +509,8 @@ static int flash_erase_1(flash_info_t * info, int s_first, int s_last) int flash_erase(flash_info_t * info, int s_first, int s_last) #endif { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; int i; @@ -550,24 +550,24 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ for (i = 0; i < 50; i++) udelay(1000); /* wait 1 ms */ } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } l_sect = sect; /* @@ -589,8 +589,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); return 0; @@ -691,9 +691,9 @@ static int write_word_1(flash_info_t * info, ulong dest, ulong data) static int write_word(flash_info_t * info, ulong dest, ulong data) #endif { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i; @@ -702,15 +702,15 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) return 2; } - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { int flag; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; dest2[i] = data2[i]; @@ -720,10 +720,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return 1; } } @@ -740,32 +740,32 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) { short i; - CFG_FLASH_CHAR_SIZE value; + CONFIG_SYS_FLASH_CHAR_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; udelay(1000); - value = (CFG_FLASH_CHAR_SIZE)addr2[0]; + value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_CHAR_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT: + case (CONFIG_SYS_FLASH_CHAR_SIZE) SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT: + case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; default: @@ -775,83 +775,83 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) return 0; /* no or unknown flash */ } - value = (CFG_FLASH_CHAR_SIZE)addr2[2]; /* device ID */ + value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[2]; /* device ID */ DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B: + case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_ID_M29W040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F016D: info->flash_id += FLASH_AMD016; info->sector_count = 32; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV033C: info->flash_id += FLASH_AMDLV033C; info->sector_count = 64; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR: - if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2 - && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) { + case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_MIRROR: + if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_2 + && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) { info->flash_id += FLASH_AMLV128U; info->sector_count = 256; info->size = 0x01000000; - } else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2 - && (CFG_FLASH_CHAR_SIZE)addr2[0x1e] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) { + } else if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_2 + && (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) { info->flash_id += FLASH_S29GL128N; info->sector_count = 128; info->size = 0x01000000; @@ -904,38 +904,38 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); /* For AMD29033C flash we need to resend the command of * * reading flash protection for upper 8 Mb of flash */ if (i == 32) { - addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) info->protect[i] = 0; else - info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1; + info->protect[i] = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[4] & 1; } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; return info->size; } static int wait_for_DQ7_2(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) != - (CFG_FLASH_WORD_SIZE) 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while (((CONFIG_SYS_FLASH_WORD_SIZE)addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -950,8 +950,8 @@ static int wait_for_DQ7_2(flash_info_t * info, int sect) static int flash_erase_2(flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; int i; @@ -991,24 +991,24 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080; - addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050; /* block erase */ + addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; + addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x50505050; /* block erase */ for (i = 0; i < 50; i++) udelay(1000); /* wait 1 ms */ } else { - addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080; - addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ + addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080; + addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030; /* sector erase */ } l_sect = sect; /* @@ -1030,8 +1030,8 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */ printf(" done\n"); return 0; @@ -1039,9 +1039,9 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) static int write_word_2(flash_info_t * info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i; @@ -1050,15 +1050,15 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data) return 2; } - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { int flag; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA0A0A0A0; dest2[i] = data2[i]; @@ -1068,10 +1068,10 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return 1; } } diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index 254e3eb83..6e9330f68 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -28,6 +28,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <spi.h> +#include <netdev.h> #include <asm/gpio.h> extern int lcd_init(void); @@ -47,8 +48,8 @@ int board_early_init_f(void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ - mtebc(pb3cr, CFG_EBC_PB3CR); + mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ + mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); /* * Configure CPC0_PCI to enable PerWE as output @@ -77,15 +78,6 @@ int checkboard(void) return 0; } -/************************************************************************* - * phys_size_t initdram - * - ************************************************************************/ -phys_size_t initdram(int board) -{ - return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */ -} - static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) { char stat; @@ -200,3 +192,8 @@ int pci_pre_init(struct pci_controller *hose) return 1; } #endif /* CONFIG_PCI */ + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds index d52b51ae1..fd5f3dfd1 100644 --- a/board/amcc/taihu/u-boot.lds +++ b/board/amcc/taihu/u-boot.lds @@ -130,6 +130,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c index 55ad535c8..52bad56bf 100644 --- a/board/amcc/taihu/update.c +++ b/board/amcc/taihu/update.c @@ -101,7 +101,7 @@ static uchar buf_66[] = static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[]) { ulong len = 0x20; - uchar chip = CFG_I2C_EEPROM_ADDR; + uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR; uchar *pbuf; uchar base; int i; diff --git a/board/amcc/taishan/config.mk b/board/amcc/taishan/config.mk index 4eefff21d..ee5eb1ba6 100644 --- a/board/amcc/taishan/config.mk +++ b/board/amcc/taishan/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S index 8db043ba1..748ec0ab5 100644 --- a/board/amcc/taishan/init.S +++ b/board/amcc/taishan/init.S @@ -89,9 +89,9 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c index 8d2dce35c..624ae40f6 100644 --- a/board/amcc/taishan/lcd.c +++ b/board/amcc/taishan/lcd.c @@ -31,9 +31,9 @@ #define LCD_DELAY_NORMAL_US 100 #define LCD_DELAY_NORMAL_MS 2 -#define LCD_CMD_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE)) -#define LCD_DATA_ADDR ((volatile char *)(CFG_EBC2_LCM_BASE+1)) -#define LCD_BLK_CTRL ((volatile char *)(CFG_EBC1_FPGA_BASE+0x2)) +#define LCD_CMD_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE)) +#define LCD_DATA_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1)) +#define LCD_BLK_CTRL ((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2)) #define mdelay(t) ({unsigned long msec=(t); while (msec--) { udelay(1000);}}) @@ -359,7 +359,7 @@ void set_phy_normal_mode(void) static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { volatile unsigned int *GpioOr = - (volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700); + (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700); *GpioOr |= 0x00300000; return 0; } @@ -367,7 +367,7 @@ static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { volatile unsigned int *GpioOr = - (volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700); + (volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700); *GpioOr &= ~0x00300000; return 0; } diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index fdd82e7cc..28bdab5db 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -27,8 +27,9 @@ #include <asm/processor.h> #include <spd_sdram.h> #include <ppc4xx_enet.h> +#include <netdev.h> -#ifdef CFG_INIT_SHOW_RESET_REG +#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG void show_reset_reg(void); #endif @@ -62,7 +63,7 @@ int board_early_init_f (void) EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ @@ -172,9 +173,9 @@ int board_early_init_f (void) mtsdr(sdr_pfc1,reg); /* Set GPIO 10 and 11 as output */ - GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718); - GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704); - GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700); + GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718); + GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704); + GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700); *GpioOdr &= ~(0x00300000); *GpioTcr |= 0x00300000; @@ -201,7 +202,7 @@ int checkboard (void) } putc ('\n'); -#ifdef CFG_INIT_SHOW_RESET_REG +#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG show_reset_reg(); #endif @@ -247,7 +248,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -262,7 +263,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -271,12 +272,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host @@ -311,3 +312,8 @@ int post_hotkeys_pressed(void) return (ctrlc()); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/amcc/taishan/u-boot.lds b/board/amcc/taishan/u-boot.lds index 85d375938..e62080839 100644 --- a/board/amcc/taishan/u-boot.lds +++ b/board/amcc/taishan/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c index ed2c196dc..96b918be0 100644 --- a/board/amcc/taishan/update.c +++ b/board/amcc/taishan/update.c @@ -51,7 +51,7 @@ const uchar bootstrap_buf[16] = { static int update_boot_eeprom(void) { ulong len = 0x10; - uchar chip = CFG_BOOTSTRAP_IIC_ADDR; + uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR; uchar *pbuf = (uchar *)bootstrap_buf; int ii, jj; diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c index 056f9b936..d363564d5 100644 --- a/board/amcc/walnut/flash.c +++ b/board/amcc/walnut/flash.c @@ -58,7 +58,7 @@ unsigned long flash_init(void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -73,21 +73,21 @@ unsigned long flash_init(void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { + if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { /* Setup offsets */ flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#ifdef CONFIG_ENV_IS_IN_FLASH + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds index 5d07e4438..c9472f934 100644 --- a/board/amcc/walnut/u-boot.lds +++ b/board/amcc/walnut/u-boot.lds @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk index 4ab0ea008..df5466e2c 100644 --- a/board/amcc/yosemite/config.mk +++ b/board/amcc/yosemite/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S index 425ad0868..f9382365c 100644 --- a/board/amcc/yosemite/init.S +++ b/board/amcc/yosemite/init.S @@ -91,22 +91,22 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I ) /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) /* USB 2.0 Device */ - tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds index c12aad7e3..ccb510e7e 100644 --- a/board/amcc/yosemite/u-boot.lds +++ b/board/amcc/yosemite/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 05be40acd..3982896cb 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ int board_early_init_f(void) { @@ -107,18 +107,18 @@ int board_early_init_f(void) mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ /*clear tmrclk divisor */ - *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; + *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00; /*enable ethernet */ - *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0; + *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0; #ifdef CONFIG_440EP /*enable usb 1.1 fs device and remove usb 2.0 reset */ - *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00; + *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00; #endif /*get rid of flash write protect */ - *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; + *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00; return 0; } @@ -167,7 +167,7 @@ int misc_init_r (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); @@ -186,8 +186,8 @@ int checkboard(void) printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board"); #endif - rev = in_8((void *)(CFG_BCSR_BASE + 0)); - val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN; + rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); + val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN; printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33); if (s != NULL) { @@ -329,7 +329,7 @@ phys_size_t initdram(int board) sdram_tr1_set(0x08000000, &tr1_bank2); mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800)); - return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */ + return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */ } /************************************************************************* @@ -395,7 +395,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -409,14 +409,14 @@ void pci_target_init(struct pci_controller *hose) | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ @@ -431,8 +431,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -446,13 +446,13 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -467,7 +467,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host @@ -508,5 +508,5 @@ void hw_watchdog_reset(void) void board_reset(void) { /* give reset to BCSR */ - *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09; + *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09; } diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index e698b201f..d9698602b 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -33,8 +33,6 @@ extern void print_evb440spe_info(void); static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]); -extern int cmd_get_data_size(char* arg, int default_size); - /* ------------------------------------------------------------------------- */ int do_evb440spe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -71,7 +69,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, chip = IIC0_ALT_BOOTPROM_ADDR; do { - printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n"); + printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n"); nbytes = readline (" ? "); if (strcmp(console_buffer, "quit") == 0) @@ -87,12 +85,12 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, do { if (strcmp(sysClock, "66") == 0) { - printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 533 MHz or quit to abort\n"); } else { #ifdef CONFIG_STRESS - printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533, 667 MHz or quit to abort\n"); #else - printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n"); + printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n"); #endif } nbytes = readline (" ? "); @@ -132,11 +130,11 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, } else { do { if (strcmp(cpuClock, "400") == 0) - printf("enter plb clock frequency 100, 133 Mhz or quit to abort\n"); + printf("enter plb clock frequency 100, 133 MHz or quit to abort\n"); #ifdef CONFIG_STRESS if (strcmp(cpuClock, "667") == 0) - printf("enter plb clock frequency 133, 166 Mhz or quit to abort\n"); + printf("enter plb clock frequency 133, 166 MHz or quit to abort\n"); #endif nbytes = readline (" ? "); @@ -162,7 +160,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, } do { - printf("enter Pci-X clock frequency 33, 66, 100 or 133 Mhz or quit to abort\n"); + printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n"); nbytes = readline (" ? "); if (strcmp(console_buffer, "quit") == 0) @@ -178,10 +176,10 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, } while (nbytes == 0); - printf("\nsys clk = %sMhz\n", sysClock); - printf("cpu clk = %sMhz\n", cpuClock); - printf("plb clk = %sMhz\n", plbClock); - printf("Pci-X clk = %sMhz\n", pcixClock); + printf("\nsys clk = %s MHz\n", sysClock); + printf("cpu clk = %s MHz\n", cpuClock); + printf("plb clk = %s MHz\n", plbClock); + printf("Pci-X clk = %s MHz\n", pcixClock); do { printf("\npress [y] to write I2C bootstrap \n"); diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk index ff454ebf1..3ce3cc171 100644 --- a/board/amcc/yucca/config.mk +++ b/board/amcc/yucca/config.mk @@ -38,5 +38,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c index 15b8a462b..eda49eb17 100644 --- a/board/amcc/yucca/flash.c +++ b/board/amcc/yucca/flash.c @@ -43,12 +43,12 @@ #define DEBUGF(x...) #endif /* DEBUG */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */ {0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */ {0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */ @@ -67,7 +67,7 @@ static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { * Functions */ static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word_1(flash_info_t * info, ulong dest, ulong data); static int write_word_2(flash_info_t * info, ulong dest, ulong data); static int flash_erase_1(flash_info_t * info, int s_first, int s_last); @@ -198,7 +198,7 @@ void flash_print_info(flash_info_t * info) /* * The following code cannot be run from FLASH! */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static ulong flash_get_size(vu_long * addr, flash_info_t * info) { /* bit 0 used for big flash marking */ @@ -214,32 +214,32 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) #endif { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; default: @@ -253,67 +253,67 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ break; - case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D: info->flash_id += FLASH_AMD016; info->sector_count = 32; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C: info->flash_id += FLASH_AMDLV033C; info->sector_count = 64; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; @@ -357,14 +357,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); /* For AMD29033C flash we need to resend the command of * * reading flash protection for upper 8 Mb of flash */ if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) @@ -374,7 +374,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -382,14 +382,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_1(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -402,7 +402,7 @@ static int wait_for_DQ7_1(flash_info_t * info, int sect) return 0; } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV int flash_erase(flash_info_t * info, int s_first, int s_last) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || @@ -420,8 +420,8 @@ static int flash_erase_1(flash_info_t * info, int s_first, int s_last) int flash_erase(flash_info_t * info, int s_first, int s_last) #endif { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; int i; @@ -457,24 +457,24 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ for (i = 0; i < 50; i++) udelay(1000); /* wait 1 ms */ } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } l_sect = sect; /* @@ -496,8 +496,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); return 0; @@ -577,7 +577,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word(flash_info_t * info, ulong dest, ulong data) { if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || @@ -595,9 +595,9 @@ static int write_word_1(flash_info_t * info, ulong dest, ulong data) static int write_word(flash_info_t * info, ulong dest, ulong data) #endif { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i, flag; @@ -605,13 +605,13 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) if ((*((vu_long *)dest) & data) != data) return (2); - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; dest2[i] = data2[i]; @@ -621,10 +621,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } @@ -632,10 +632,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) return (0); } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -#undef CFG_FLASH_WORD_SIZE -#define CFG_FLASH_WORD_SIZE unsigned short +#undef CONFIG_SYS_FLASH_WORD_SIZE +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* * The following code cannot be run from FLASH! @@ -644,37 +644,37 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) { short i; int n; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; - case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT: info->flash_id = FLASH_MAN_MX; break; default: @@ -688,22 +688,22 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT: info->flash_id += FLASH_STMW320DT; info->sector_count = 67; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T: info->flash_id += FLASH_MXLV320T; info->sector_count = 71; info->size = 0x00400000; @@ -782,14 +782,14 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); /* For AMD29033C flash we need to resend the command of * * reading flash protection for upper 8 Mb of flash */ if (i == 32) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) @@ -799,7 +799,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -807,14 +807,14 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_2(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -829,8 +829,8 @@ static int wait_for_DQ7_2(flash_info_t * info, int sect) static int flash_erase_2(flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; int i; @@ -866,24 +866,24 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050; /* block erase */ for (i = 0; i < 50; i++) udelay(1000); /* wait 1 ms */ } else { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ } l_sect = sect; /* @@ -905,8 +905,8 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); return 0; @@ -914,9 +914,9 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) static int write_word_2(flash_info_t * info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i; @@ -924,15 +924,15 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data) if ((*((vu_long *)dest) & data) != data) return (2); - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { int flag; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; dest2[i] = data2[i]; @@ -942,17 +942,17 @@ static int write_word_2(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } return (0); } -#endif /* CFG_FLASH_2ND_16BIT_DEV */ +#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ /*----------------------------------------------------------------------- * Functions @@ -966,7 +966,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; unsigned long val; @@ -1011,7 +1011,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -1034,16 +1034,16 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#if defined(CONFIG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); -#if defined(CFG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, +#if defined(CONFIG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); #endif #endif diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index 67e8f8f3a..9308fdac2 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -59,23 +59,23 @@ tlbtabA: * routine. */ - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) - - tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) - - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) + + tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) + + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I) tlbtab_end /************************************************************************** @@ -102,20 +102,20 @@ tlbtabB: * routine. */ - tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) - tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) + tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I) + tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I) - tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I) tlbtab_end diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds index 4477cd8a8..adfa28b0e 100644 --- a/board/amcc/yucca/u-boot.lds +++ b/board/amcc/yucca/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 84c3938d7..c8055689f 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -28,6 +28,7 @@ #include <common.h> #include <ppc4xx.h> #include <i2c.h> +#include <netdev.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/4xx_pcie.h> @@ -625,7 +626,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*-------------------------------------------------------------------+ @@ -640,7 +641,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); out32r( PCIX0_BAR0, 0 ); @@ -648,12 +649,12 @@ void pci_target_init(struct pci_controller * hose ) /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ #if defined(CONFIG_PCI) /************************************************************************* @@ -842,9 +843,9 @@ void pcie_setup_hoses(int busno) /* setup mem resource */ pci_set_region(hose->regions + 0, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, - CFG_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, + CONFIG_SYS_PCIE_MEMSIZE, PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); @@ -952,3 +953,8 @@ int onboard_pci_arbiter_selected(int core_pci) #endif return (BOARD_OPTION_NOT_SELECTED); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index 55277e72d..e9f80ff5c 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> +#include <netdev.h> #include <asm/processor.h> #include "powerspan.h" @@ -697,3 +698,8 @@ U_BOOT_CMD (swrecon, 1, 0, do_swreconfig, "swrecon - trigger a board reconfigure to the software selected configuration\n", "\n" " - trigger a board reconfigure to the software selected configuration\n"); + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c index 1a3b25218..1e742e527 100644 --- a/board/amirix/ap1000/flash.c +++ b/board/amirix/ap1000/flash.c @@ -110,7 +110,7 @@ typedef union { #define NUM_ERASE_REGIONS 4 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -130,7 +130,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword); static int flash_full_status_check (flash_info_t * info, ulong sector, ulong tout, char *prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len); #endif @@ -270,7 +270,7 @@ unsigned long flash_init (void) flash_info[0].flash_id = FLASH_UNKNOWN; flash_info[0].portwidth = FLASH_CFI_16BIT; flash_info[0].chipwidth = FLASH_CFI_16BIT; - size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0); + size += flash_info[0].size = flash_get_size (CONFIG_SYS_PROGFLASH_BASE, 0); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20); }; @@ -278,7 +278,7 @@ unsigned long flash_init (void) flash_info[1].flash_id = FLASH_UNKNOWN; flash_info[1].portwidth = FLASH_CFI_8BIT; flash_info[1].chipwidth = FLASH_CFI_16BIT; - size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1); + size += flash_info[1].size = flash_get_size (CONFIG_SYS_CONFFLASH_BASE, 1); if (flash_info[1].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20); }; @@ -398,7 +398,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return rc; wp = cp; } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE while (cnt >= info->portwidth) { i = info->buffer_size > cnt ? cnt : info->buffer_size; if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) @@ -419,7 +419,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) wp += info->portwidth; cnt -= info->portwidth; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); } @@ -824,7 +824,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, return flash_full_status_check (info, 0, info->write_tout, "write"); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* loop through the sectors from the highest address * when the passed address is greater or equal to the sector address @@ -900,4 +900,4 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c index a6436ac5b..a9b3fd89f 100644 --- a/board/amirix/ap1000/pci.c +++ b/board/amirix/ap1000/pci.c @@ -267,10 +267,10 @@ static int psII_write_config_dword (struct pci_controller *hose, static struct pci_config_table ap1000_config_table[] = { #ifdef CONFIG_AP1000 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN), - PCI_FUNC (CFG_ETH_DEV_FN), + PCI_BUS (CONFIG_SYS_ETH_DEV_FN), PCI_DEV (CONFIG_SYS_ETH_DEV_FN), + PCI_FUNC (CONFIG_SYS_ETH_DEV_FN), pci_cfgfunc_config_device, - {CFG_ETH_IOBASE, CFG_ETH_MEMBASE, + {CONFIG_SYS_ETH_IOBASE, CONFIG_SYS_ETH_MEMBASE, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, #endif {} diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c index 508e88040..87003be9c 100644 --- a/board/amirix/ap1000/serial.c +++ b/board/amirix/ap1000/serial.c @@ -30,15 +30,15 @@ DECLARE_GLOBAL_DATA_PTR; const NS16550_t COM_PORTS[] = - { (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 }; + { (NS16550_t) CONFIG_SYS_NS16550_COM1, (NS16550_t) CONFIG_SYS_NS16550_COM2 }; -#undef CFG_DUART_CHAN -#define CFG_DUART_CHAN gComPort +#undef CONFIG_SYS_DUART_CHAN +#define CONFIG_SYS_DUART_CHAN gComPort static int gComPort = 0; int serial_init (void) { - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; (void) NS16550_init (COM_PORTS[0], clock_divisor); gComPort = 0; @@ -49,30 +49,30 @@ int serial_init (void) void serial_putc (const char c) { if (c == '\n') { - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); } - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } int serial_getc (void) { - return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } int serial_tstc (void) { - return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } void serial_setbrg (void) { - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif } diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds index a939e0331..27a6f8b06 100644 --- a/board/amirix/ap1000/u-boot.lds +++ b/board/amirix/ap1000/u-boot.lds @@ -69,7 +69,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -138,6 +138,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/apollon/Makefile b/board/apollon/Makefile index 9bac9a6c0..f20de3c93 100644 --- a/board/apollon/Makefile +++ b/board/apollon/Makefile @@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := apollon.o mem.o sys_info.o +COBJS-y := apollon.o mem.o sys_info.o SOBJS := lowlevel_init.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c index 8efa70395..8964eba7f 100644 --- a/board/apollon/apollon.c +++ b/board/apollon/apollon.c @@ -245,7 +245,7 @@ void peripheral_enable(void) __raw_writel(v, CM_CLKSEL2_CORE); __raw_writel(0x1, CM_CLKSEL_WKUP); -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 /* Enable UART1 clock */ func_clks |= BIT21; if_clks |= BIT21; diff --git a/board/apollon/config.mk b/board/apollon/config.mk index 417b954a7..2b464e787 100644 --- a/board/apollon/config.mk +++ b/board/apollon/config.mk @@ -13,7 +13,7 @@ # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 # (mem base + reserved) # For use with external or internal boots. -TEXT_BASE = 0x80e80000 +TEXT_BASE = 0x83e80000 # Used with full SRAM boot. # This is either with a GP system or a signed boot image. diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S index 8381feae0..64550f61e 100644 --- a/board/apollon/lowlevel_init.S +++ b/board/apollon/lowlevel_init.S @@ -51,7 +51,7 @@ _TEXT_BASE: .globl lowlevel_init lowlevel_init: -#ifdef CFG_NOR_BOOT +#ifdef CONFIG_SYS_NOR_BOOT /* Check running in SDRAM */ mov r0, pc, lsr #28 cmp r0, #8 diff --git a/board/apollon/mem.c b/board/apollon/mem.c index 0211c6ad2..36bf6e922 100644 --- a/board/apollon/mem.c +++ b/board/apollon/mem.c @@ -146,7 +146,7 @@ void gpmc_init(void) __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */ -#ifdef CFG_NAND_BOOT +#ifdef CONFIG_SYS_NAND_BOOT /* set nWP, disable limited addr */ __raw_writel(0x001, GPMC_CONFIG); #else @@ -164,7 +164,7 @@ void gpmc_init(void) __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ sdelay(1000); -#ifdef CFG_NOR_BOOT +#ifdef CONFIG_SYS_NOR_BOOT __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0); __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0); __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0); @@ -208,13 +208,13 @@ void gpmc_init(void) __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2); __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2); __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2); -#ifdef CFG_NOR_BOOT +#ifdef CONFIG_SYS_NOR_BOOT __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2); #else __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2); #endif -#ifndef CFG_NOR_BOOT +#ifndef CONFIG_SYS_NOR_BOOT /* setup cs3 */ __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */ sdelay(1000); diff --git a/board/apollon/mem.h b/board/apollon/mem.h index d4636f405..09c4ea43c 100644 --- a/board/apollon/mem.h +++ b/board/apollon/mem.h @@ -142,7 +142,7 @@ #endif /* endif PRCM_CONFIG_II */ #ifdef PRCM_CONFIG_III /* L3 at 133MHz */ -# ifdef CFG_NAND_BOOT +# ifdef CONFIG_SYS_NAND_BOOT # define APOLLON_24XX_GPMC_CONFIG1_0 0x0 # define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400 # define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400 @@ -156,7 +156,7 @@ # define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008 # define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F # define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4 -# endif /* endif CFG_NAND_BOOT */ +# endif /* endif CONFIG_SYS_NAND_BOOT */ # define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24)) # define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000 # define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01 @@ -165,6 +165,6 @@ # define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F # define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4 # define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24)) -#endif /* endif CFG_PRCM_III */ +#endif /* endif CONFIG_SYS_PRCM_III */ #endif /* endif _APOLLON_OMAP24XX_MEM_H_ */ diff --git a/board/apollon/u-boot.lds b/board/apollon/u-boot.lds index 7b29a5b79..0aeb4373d 100644 --- a/board/apollon/u-boot.lds +++ b/board/apollon/u-boot.lds @@ -58,6 +58,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c index 8518856cb..cdbbfd01c 100644 --- a/board/armadillo/flash.c +++ b/board/armadillo/flash.c @@ -37,7 +37,7 @@ #define FL_WORD(addr) (*(volatile unsigned short*)(addr)) #define FLASH_TIMEOUT 20000000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ @@ -47,14 +47,14 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK); /*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */ flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -69,13 +69,13 @@ ulong flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } diff --git a/board/armadillo/u-boot.lds b/board/armadillo/u-boot.lds index 418101ff8..49d18f7d6 100644 --- a/board/armadillo/u-boot.lds +++ b/board/armadillo/u-boot.lds @@ -50,6 +50,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/assabet/u-boot.lds b/board/assabet/u-boot.lds index 3f52f0431..5507dd3eb 100644 --- a/board/assabet/u-boot.lds +++ b/board/assabet/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/atc/atc.c b/board/atc/atc.c index 79527f438..936c031c6 100644 --- a/board/atc/atc.c +++ b/board/atc/atc.c @@ -281,7 +281,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = &memctl->memc_psdmr; @@ -306,7 +306,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -317,7 +317,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -331,7 +331,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, int misc_init_r(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint)); @@ -342,37 +342,37 @@ int misc_init_r(void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong size8, size9; #endif long psize; psize = 8 * 1024 * 1024; - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL) "); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL) "); } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -380,10 +380,9 @@ phys_size_t initdram (int board_type) } #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif diff --git a/board/atc/config.mk b/board/atc/config.mk index eee7a60e3..dd854e7e4 100644 --- a/board/atc/config.mk +++ b/board/atc/config.mk @@ -25,7 +25,7 @@ # ATC boards # -# This should be equal to the CFG_FLASH_BASE define in config_atc.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_atc.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/atc/flash.c b/board/atc/flash.c index 2ab60e866..fd76723e8 100644 --- a/board/atc/flash.c +++ b/board/atc/flash.c @@ -23,7 +23,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -67,11 +67,11 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { #if 0 ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; #else - ulong flashbase = CFG_FLASH_BASE; + ulong flashbase = CONFIG_SYS_FLASH_BASE; #endif memset(&flash_info[i], 0, sizeof(flash_info_t)); @@ -87,20 +87,20 @@ unsigned long flash_init (void) size += flash_info[i].size; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif @@ -164,13 +164,13 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->start[0] <= base && base < info->start[0] + info->size) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -476,7 +476,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -490,14 +490,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ putc ('.'); last = get_timer(0); } } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = get_timer(0); } @@ -601,7 +601,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00F000F0; /* reset bank */ res = 1; } @@ -647,7 +647,7 @@ static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) start = get_timer (0); while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00B000B0; /* Suspend program */ res = 1; } diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c index e112eca85..473bb10af 100644 --- a/board/atc/ti113x.c +++ b/board/atc/ti113x.c @@ -526,8 +526,8 @@ int i82365_init (void) mem.map = 0; mem.flags = MAP_ATTRIB | MAP_ACTIVE; mem.speed = 300; - mem.sys_start = CFG_PCMCIA_MEM_ADDR; - mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1; + mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; + mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; mem.card_start = 0; i365_set_mem_map (&socket, &mem); @@ -613,8 +613,8 @@ static void i82365_dump_regions (pci_dev_t dev) { u_int tmp[2]; u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET); + u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; + u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); pci_read_config_dword (dev, 0x00, tmp + 0); pci_read_config_dword (dev, 0x80, tmp + 1); diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index c5082a092..f7d68b705 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -30,11 +30,13 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> +#include <asm/arch/hardware.h> #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif +#include <netdev.h> #define MP_BLOCK_3_BASE 0xFDF00000 @@ -50,19 +52,19 @@ static void at91cap9_serial_hw_init(void) #ifdef CONFIG_USART0 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); #endif #ifdef CONFIG_USART1 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); #endif #ifdef CONFIG_USART2 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); #endif #ifdef CONFIG_USART3 /* DBGU */ @@ -145,9 +147,9 @@ static void at91cap9_nand_hw_init(void) at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_DBW_16 | -#else /* CFG_NAND_DBW_8 */ +#else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_DBW_8 | #endif AT91_SMC_TDF_(1)); @@ -324,6 +326,35 @@ static void at91cap9_lcd_hw_init(void) gd->fb_base = 0; } + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + AT91_CPU_NAME, + strmhz(temp, AT91_CPU_CLOCK)); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ #endif int board_init(void) @@ -376,3 +407,12 @@ void reset_phy(void) #endif } #endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c index 1dec5582f..cc2263b02 100644 --- a/board/atmel/at91cap9adk/nand.c +++ b/board/atmel/at91cap9adk/nand.c @@ -62,7 +62,7 @@ static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int board_nand_init(struct nand_chip *nand) { nand->ecc.mode = NAND_ECC_SOFT; -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91cap9adk_nand_hwcontrol; diff --git a/board/atmel/at91cap9adk/partition.c b/board/atmel/at91cap9adk/partition.c index eb1a724ab..7e1d46f53 100644 --- a/board/atmel/at91cap9adk/partition.c +++ b/board/atmel/at91cap9adk/partition.c @@ -23,10 +23,10 @@ #include <asm/hardware.h> #include <dataflash.h> -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; -struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ }; /*define the area offsets*/ diff --git a/board/atmel/at91rm9200dk/at91rm9200dk.c b/board/atmel/at91rm9200dk/at91rm9200dk.c index c564f73a5..b89a3fd54 100644 --- a/board/atmel/at91rm9200dk/at91rm9200dk.c +++ b/board/atmel/at91rm9200dk/at91rm9200dk.c @@ -47,7 +47,7 @@ int board_init (void) /* so we do _nothing_ here */ /* arch number of AT91RM9200DK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200; + gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK; /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; diff --git a/board/atmel/at91rm9200dk/flash.c b/board/atmel/at91rm9200dk/flash.c index 0513d61d7..902c3c41c 100644 --- a/board/atmel/at91rm9200dk/flash.c +++ b/board/atmel/at91rm9200dk/flash.c @@ -59,7 +59,7 @@ OrgDef OrgAT49BV6416[] = { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ }; -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* AT49BV1614A Codes */ #define FLASH_CODE1 0xAA @@ -77,8 +77,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define CMD_UNLOCK_BYPASS 0x0020 #define CMD_SECTOR_UNLOCK 0x0070 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00005555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00002AAA<<1))) #define BIT_ERASE_DONE 0x0080 #define BIT_RDY_MASK 0x0080 @@ -99,9 +99,9 @@ void flash_identification (flash_info_t * info) MEM_FLASH_ADDR2 = FLASH_CODE2; MEM_FLASH_ADDR1 = ID_IN_CODE; - manuf_code = *(volatile u16 *) CFG_FLASH_BASE; - device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); - add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); + manuf_code = *(volatile u16 *) CONFIG_SYS_FLASH_BASE; + device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + 2); + add_device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + (3 << 1)); MEM_FLASH_ADDR1 = FLASH_CODE1; MEM_FLASH_ADDR2 = FLASH_CODE2; @@ -157,7 +157,7 @@ ulong flash_init (void) ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_identification (&flash_info[i]); @@ -216,18 +216,18 @@ ulong flash_init (void) /* Protect binary boot image */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + CONFIG_SYS_BOOT_SIZE - 1, &flash_info[0]); /* Protect environment variables */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); /* Protect U-Boot gzipped image */ flash_protect (FLAG_PROTECT_SET, - CFG_U_BOOT_BASE, - CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1, &flash_info[0]); + CONFIG_SYS_U_BOOT_BASE, + CONFIG_SYS_U_BOOT_BASE + CONFIG_SYS_U_BOOT_SIZE - 1, &flash_info[0]); return size; } @@ -345,7 +345,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -433,7 +433,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; } diff --git a/board/atmel/at91rm9200dk/partition.c b/board/atmel/at91rm9200dk/partition.c index 975be1746..c739b116b 100644 --- a/board/atmel/at91rm9200dk/partition.c +++ b/board/atmel/at91rm9200dk/partition.c @@ -23,11 +23,11 @@ #include <asm/hardware.h> #include <dataflash.h> -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; -struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3} }; /*define the area offsets*/ diff --git a/board/atmel/at91rm9200dk/u-boot.lds b/board/atmel/at91rm9200dk/u-boot.lds index 14cd22800..987b07d94 100644 --- a/board/atmel/at91rm9200dk/u-boot.lds +++ b/board/atmel/at91rm9200dk/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 06d8512cc..ef99b8b0d 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -30,9 +30,11 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> +#include <asm/arch/hardware.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -46,19 +48,19 @@ static void at91sam9260ek_serial_hw_init(void) #ifdef CONFIG_USART0 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); #endif #ifdef CONFIG_USART1 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); #endif #ifdef CONFIG_USART2 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); #endif #ifdef CONFIG_USART3 /* DBGU */ @@ -90,9 +92,9 @@ static void at91sam9260ek_nand_hw_init(void) at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_DBW_16 | -#else /* CFG_NAND_DBW_8 */ +#else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_DBW_8 | #endif AT91_SMC_TDF_(2)); @@ -248,3 +250,12 @@ void reset_phy(void) #endif } #endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c index 665e35c54..c5ac634aa 100644 --- a/board/atmel/at91sam9260ek/nand.c +++ b/board/atmel/at91sam9260ek/nand.c @@ -67,7 +67,7 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { nand->ecc.mode = NAND_ECC_SOFT; -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol; diff --git a/board/atmel/at91sam9260ek/partition.c b/board/atmel/at91sam9260ek/partition.c index 557d6954f..2629c6718 100644 --- a/board/atmel/at91sam9260ek/partition.c +++ b/board/atmel/at91sam9260ek/partition.c @@ -23,11 +23,11 @@ #include <asm/hardware.h> #include <dataflash.h> -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; -struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CFG_DATAFLASH_LOGIC_ADDR_CS1, 1} +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1} }; /*define the area offsets*/ diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 647aab525..14f236da2 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -48,19 +48,19 @@ static void at91sam9261ek_serial_hw_init(void) #ifdef CONFIG_USART0 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); #endif #ifdef CONFIG_USART1 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); #endif #ifdef CONFIG_USART2 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); #endif #ifdef CONFIG_USART3 /* DBGU */ @@ -92,9 +92,9 @@ static void at91sam9261ek_nand_hw_init(void) at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_DBW_16 | -#else /* CFG_NAND_DBW_8 */ +#else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_DBW_8 | #endif AT91_SMC_TDF_(2)); @@ -209,6 +209,35 @@ static void at91sam9261ek_lcd_hw_init(void) gd->fb_base = AT91SAM9261_SRAM_BASE; } + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + AT91_CPU_NAME, + strmhz(temp, AT91_CPU_CLOCK)); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ #endif int board_init(void) diff --git a/board/atmel/at91sam9261ek/nand.c b/board/atmel/at91sam9261ek/nand.c index fccb9d78d..06395ee21 100644 --- a/board/atmel/at91sam9261ek/nand.c +++ b/board/atmel/at91sam9261ek/nand.c @@ -67,7 +67,7 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { nand->ecc.mode = NAND_ECC_SOFT; -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol; diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c index 975be1746..c739b116b 100644 --- a/board/atmel/at91sam9261ek/partition.c +++ b/board/atmel/at91sam9261ek/partition.c @@ -23,11 +23,11 @@ #include <asm/hardware.h> #include <dataflash.h> -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; -struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CFG_DATAFLASH_LOGIC_ADDR_CS3, 3} +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3} }; /*define the area offsets*/ diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 927fc912c..ebd464976 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -31,11 +31,13 @@ #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> +#include <asm/arch/hardware.h> #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -49,19 +51,19 @@ static void at91sam9263ek_serial_hw_init(void) #ifdef CONFIG_USART0 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); #endif #ifdef CONFIG_USART1 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); #endif #ifdef CONFIG_USART2 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); #endif #ifdef CONFIG_USART3 /* DBGU */ @@ -93,9 +95,9 @@ static void at91sam9263ek_nand_hw_init(void) at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_DBW_16 | -#else /* CFG_NAND_DBW_8 */ +#else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_DBW_8 | #endif AT91_SMC_TDF_(2)); @@ -258,6 +260,35 @@ static void at91sam9263ek_lcd_hw_init(void) gd->fb_base = AT91SAM9263_SRAM0_BASE; } + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + AT91_CPU_NAME, + strmhz(temp, AT91_CPU_CLOCK)); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ #endif int board_init(void) @@ -308,3 +339,12 @@ void reset_phy(void) #endif } #endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/atmel/at91sam9263ek/nand.c b/board/atmel/at91sam9263ek/nand.c index 250ec7f39..3c247f6e5 100644 --- a/board/atmel/at91sam9263ek/nand.c +++ b/board/atmel/at91sam9263ek/nand.c @@ -67,7 +67,7 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { nand->ecc.mode = NAND_ECC_SOFT; -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol; diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c index eb1a724ab..7e1d46f53 100644 --- a/board/atmel/at91sam9263ek/partition.c +++ b/board/atmel/at91sam9263ek/partition.c @@ -23,10 +23,10 @@ #include <asm/hardware.h> #include <dataflash.h> -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; -struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ }; /*define the area offsets*/ diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 509e7c38e..b6fef9d6f 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -48,19 +48,19 @@ static void at91sam9rlek_serial_hw_init(void) #ifdef CONFIG_USART0 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); #endif #ifdef CONFIG_USART1 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); #endif #ifdef CONFIG_USART2 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); #endif #ifdef CONFIG_USART3 /* DBGU */ @@ -92,9 +92,9 @@ static void at91sam9rlek_nand_hw_init(void) at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 AT91_SMC_DBW_16 | -#else /* CFG_NAND_DBW_8 */ +#else /* CONFIG_SYS_NAND_DBW_8 */ AT91_SMC_DBW_8 | #endif AT91_SMC_TDF_(2)); @@ -181,6 +181,35 @@ static void at91sam9rlek_lcd_hw_init(void) gd->fb_base = 0; } + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2008 ATMEL Corp\n"); + lcd_printf ("at91support@atmel.com\n"); + lcd_printf ("%s CPU at %s MHz\n", + AT91_CPU_NAME, + strmhz(temp, AT91_CPU_CLOCK)); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, + nand_size >> 20 ); +} +#endif /* CONFIG_LCD_INFO */ #endif diff --git a/board/atmel/at91sam9rlek/nand.c b/board/atmel/at91sam9rlek/nand.c index eb342b842..625f6ec9b 100644 --- a/board/atmel/at91sam9rlek/nand.c +++ b/board/atmel/at91sam9rlek/nand.c @@ -67,7 +67,7 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { nand->ecc.mode = NAND_ECC_SOFT; -#ifdef CFG_NAND_DBW_16 +#ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol; diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c index eb1a724ab..7e1d46f53 100644 --- a/board/atmel/at91sam9rlek/partition.c +++ b/board/atmel/at91sam9rlek/partition.c @@ -23,10 +23,10 @@ #include <asm/hardware.h> #include <dataflash.h> -AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS]; +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; -struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = { - {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ }; /*define the area offsets*/ diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index 480d5255f..004d8daa9 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -27,6 +27,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/hmatrix.h> #include <asm/arch/portmux.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -95,8 +96,6 @@ int board_early_init_r(void) return 0; } -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bi) { diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 7be39931e..c36cb5717 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -26,6 +26,7 @@ #include <asm/arch/clk.h> #include <asm/arch/hmatrix.h> #include <asm/arch/portmux.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -117,8 +118,6 @@ int board_early_init_r(void) return 0; } -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bi) { diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index e2bfd4aff..4d380f3fa 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -55,17 +55,17 @@ unsigned long flash_init(void) unsigned long addr; unsigned int i; - flash_info[0].size = CFG_FLASH_SIZE; + flash_info[0].size = CONFIG_SYS_FLASH_SIZE; flash_info[0].sector_count = 135; - flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]); + flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) flash_info[0].start[i] = addr; for (; i < flash_info[0].sector_count; i++, addr += 0x10000) flash_info[0].start[i] = addr; - return CFG_FLASH_SIZE; + return CONFIG_SYS_FLASH_SIZE; } void flash_print_info(flash_info_t *info) diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 337cf31ad..6ef663eeb 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -37,10 +37,6 @@ #include <libfdt.h> #include <fdt_support.h> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - long int fixed_sdram(void); int board_early_init_f (void) @@ -50,9 +46,9 @@ int board_early_init_f (void) int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %lx\n",(ulong)&gur->porpllsr); @@ -73,15 +69,15 @@ int checkboard (void) ************************************************************************/ long int fixed_sdram (void) { - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000000D; ddr->err_sbe = 0x00ff0000; @@ -90,13 +86,13 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ @@ -117,27 +113,21 @@ initdram(int board_type) dram_size = fixed_sdram (); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); + CONFIG_SYS_MEMTEST_START, + CONFIG_SYS_MEMTEST_END); printf("DRAM test phase 1:\n"); for (p = pstart; p < pend; p++) { @@ -182,10 +172,13 @@ static struct pci_controller pcie1_hose; int first_free_busno=0; +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; @@ -210,11 +203,11 @@ pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); int pcie_configured = io_sel & 6; + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE1 connected to slot as %s (base address %x)", @@ -227,36 +220,31 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCIE1_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCIE1_MEM_BASE2, - CFG_PCIE1_MEM_PHYS2, - CFG_PCIE1_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE2, + CONFIG_SYS_PCIE1_MEM_PHYS2, + CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -278,9 +266,9 @@ pci_init_board(void) #ifdef CONFIG_PCI1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; uint pci_agent = (host_agent == 6); uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ @@ -300,26 +288,22 @@ pci_init_board(void) ); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -337,29 +321,26 @@ pci_init_board(void) #ifdef CONFIG_PCI2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pci2_hose; + struct pci_region *r = hose->regions; if (!(devdisr & MPC85xx_DEVDISR_PCI2)) { - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - pci_set_region(hose->regions + 1, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, + r += fsl_pci_setup_inbound_windows(r); + + pci_set_region(r++, + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -385,39 +366,21 @@ int last_stage_init(void) } #if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); -void -ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - ft_cpu_setup(blob, bd); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCI2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pci2_hose); #endif #ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci2", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif - } } #endif diff --git a/board/atum8548/ddr.c b/board/atum8548/ddr.c index f07d746c2..ab64fa88f 100644 --- a/board/atum8548/ddr.c +++ b/board/atum8548/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/atum8548/law.c b/board/atum8548/law.c index b66fd7b29..b70b0910d 100644 --- a/board/atum8548/law.c +++ b/board/atum8548/law.c @@ -48,14 +48,14 @@ */ struct law_entry law_table[] = { - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), - SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c index 1ef4de41e..ef7942cb1 100644 --- a/board/atum8548/tlb.c +++ b/board/atum8548/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -47,11 +47,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf8000000 128M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, CONFIG_SYS_FLASH_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), @@ -59,7 +59,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 1G Non-cacheable, guarded * 0x80000000 1G PCI1/PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1), @@ -67,11 +67,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3, 4: 512M Non-cacheable, guarded * 0xc0000000 1G PCI2 */ - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), }; diff --git a/board/atum8548/u-boot.lds b/board/atum8548/u-boot.lds index 46c45d771..650cb9ec9 100644 --- a/board/atum8548/u-boot.lds +++ b/board/atum8548/u-boot.lds @@ -138,6 +138,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/avnet/fx12mm/.gitignore b/board/avnet/fx12mm/.gitignore new file mode 100644 index 000000000..b644f5994 --- /dev/null +++ b/board/avnet/fx12mm/.gitignore @@ -0,0 +1 @@ +config.tmp diff --git a/board/avnet/fx12mm/Makefile b/board/avnet/fx12mm/Makefile new file mode 100644 index 000000000..f9437817b --- /dev/null +++ b/board/avnet/fx12mm/Makefile @@ -0,0 +1,27 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es +# This work has been supported by: Qtechnology http://qtec.com/ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +COBJS += $(BOARD).o + +include $(SRCTREE)/board/xilinx/ppc405-generic/Makefile diff --git a/board/xilinx/xupv2p/config.mk b/board/avnet/fx12mm/config.mk index c07b0b35b..f5a603950 100644 --- a/board/xilinx/xupv2p/config.mk +++ b/board/avnet/fx12mm/config.mk @@ -1,7 +1,7 @@ # -# (C) Copyright 2007 Michal Simek -# -# Michal SIMEK <monstr@monstr.eu> +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com # # See file CREDITS for list of people who contributed to this # project. @@ -13,7 +13,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -21,12 +21,6 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -# CAUTION: This file is automatically generated by libgen. -# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 # -TEXT_BASE = 0x38000000 - -PLATFORM_CPPFLAGS += -mno-xl-soft-mul -PLATFORM_CPPFLAGS += -mno-xl-soft-div -PLATFORM_CPPFLAGS += -mxl-barrel-shift +sinclude $(SRCTREE)/board/xilinx/ppc405-generic/config.mk diff --git a/board/xilinx/xupv2p/xupv2p.c b/board/avnet/fx12mm/fx12mm.c index b48103fdc..485864591 100644 --- a/board/xilinx/xupv2p/xupv2p.c +++ b/board/avnet/fx12mm/fx12mm.c @@ -1,7 +1,10 @@ /* - * (C) Copyright 2007 Michal Simek + * (C) Copyright 2008 * - * Michal SIMEK <monstr@monstr.eu> + * Author: Xilinx Inc. + * + * Modified by: + * Georg Schardt <schardt@team-ctech.de> * * See file CREDITS for list of people who contributed to this * project. @@ -13,37 +16,37 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * */ -/* This is a board specific file. It's OK to include board specific - * header files */ - -#include <common.h> #include <config.h> +#include <common.h> +#include <asm/processor.h> -void do_reset (void) +int checkboard(void) { -#ifdef CFG_GPIO_0 - *((unsigned long *)(CFG_GPIO_0_ADDR)) = - ++(*((unsigned long *)(CFG_GPIO_0_ADDR))); -#endif -#ifdef CFG_RESET_ADDRESS - puts ("Reseting board\n"); - asm ("bra r0"); -#endif -} + char tmp[64]; + char *s, *e; + int i = getenv_r("serial", tmp, sizeof(tmp)); -int gpio_init (void) -{ -#ifdef CFG_GPIO_0 - *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0; -#endif + if (i < 0) { + printf("Avnet Virtex4 FX12 with no serial #"); + } else { + for (e = tmp; *e; ++e) { + if (*e == ' ') + break; + } + printf("Avnet Virtex4 FX12 Minimodul # "); + for (s = tmp; s < e; ++s) + putc(*s); + } + putc('\n'); return 0; } diff --git a/board/avnet/fx12mm/xparameters.h b/board/avnet/fx12mm/xparameters.h new file mode 100644 index 000000000..4410f19b7 --- /dev/null +++ b/board/avnet/fx12mm/xparameters.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2008 + * + * Georg Schardt <schardt@team-ctech.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * CAUTION: This file is based on the xparameters.h automatically + * generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5 + */ + +#ifndef __XPARAMETER_H__ +#define __XPARAMETER_H__ + +/* RS232 */ +#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 +#define XPAR_UARTNS550_0_BASEADDR 0x83E00000 + + +/* INT_C */ +#define XPAR_XPS_INTC_0_DEVICE_ID 0 +#define XPAR_XPS_INTC_0_BASEADDR 0x81800000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2 + +/* CPU core clock */ +#define XPAR_CORE_CLOCK_FREQ_HZ 300000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 + +/* RAM */ +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 + +/* FLASH */ +#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000 + +#endif diff --git a/board/avnet/v5fx30teval/.gitignore b/board/avnet/v5fx30teval/.gitignore new file mode 100644 index 000000000..f6418a0c5 --- /dev/null +++ b/board/avnet/v5fx30teval/.gitignore @@ -0,0 +1 @@ +/config.tmp diff --git a/board/avnet/v5fx30teval/Makefile b/board/avnet/v5fx30teval/Makefile new file mode 100644 index 000000000..de23f296c --- /dev/null +++ b/board/avnet/v5fx30teval/Makefile @@ -0,0 +1,27 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es +# This work has been supported by: Qtechnology http://qtec.com/ +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +COBJS += $(BOARD).o + +include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile diff --git a/board/avnet/v5fx30teval/config.mk b/board/avnet/v5fx30teval/config.mk new file mode 100644 index 000000000..51448ce7f --- /dev/null +++ b/board/avnet/v5fx30teval/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# + +sinclude $(SRCTREE)/board/xilinx/ppc440-generic/config.mk diff --git a/board/avnet/v5fx30teval/v5fx30teval.c b/board/avnet/v5fx30teval/v5fx30teval.c new file mode 100644 index 000000000..14a1d5d52 --- /dev/null +++ b/board/avnet/v5fx30teval/v5fx30teval.c @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + + +int checkboard(void) +{ + puts("Avnet Virtex 5 FX30 Evaluation Board\n"); + return 0; +} diff --git a/board/avnet/v5fx30teval/xparameters.h b/board/avnet/v5fx30teval/xparameters.h new file mode 100644 index 000000000..bb657fcf2 --- /dev/null +++ b/board/avnet/v5fx30teval/xparameters.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters.h by Xilinx + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif diff --git a/board/barco/barco.c b/board/barco/barco.c index f8b2084c4..ed3557219 100644 --- a/board/barco/barco.c +++ b/board/barco/barco.c @@ -90,7 +90,7 @@ phys_size_t initdram (int board_type) long mear1; long emear1; - size = get_ram_size (CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size (CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg (MEAR1); @@ -188,14 +188,14 @@ unsigned update_flash (unsigned char *buf) unsigned scan_flash (void) { char section[] = "kernel"; - int cfgFileLen = (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1); + int cfgFileLen = (CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH >> 1); int sectionPtr = 0; int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */ int bufPtr; unsigned char *buf; - buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \ - - CFG_FLASH_ERASE_SECTOR_LENGTH); + buf = (unsigned char*)(CONFIG_SYS_FLASH_RANGE_BASE + CONFIG_SYS_FLASH_RANGE_SIZE \ + - CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH); for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) { if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) { return BOOT_DEFAULT; @@ -236,14 +236,14 @@ TSBootInfo* find_boot_info (void) switch (bootimage) { case TRY_WORKING: - info->address = CFG_WORKING_KERNEL_ADDRESS; + info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS; break; case BOOT_WORKING : - info->address = CFG_WORKING_KERNEL_ADDRESS; + info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS; break; case BOOT_DEFAULT: default: - info->address= CFG_DEFAULT_KERNEL_ADDRESS; + info->address= CONFIG_SYS_DEFAULT_KERNEL_ADDRESS; } info->size = *((unsigned int *)(info->address )); diff --git a/board/barco/barco_svc.h b/board/barco/barco_svc.h index bd924f2b1..e1032609c 100644 --- a/board/barco/barco_svc.h +++ b/board/barco/barco_svc.h @@ -38,16 +38,16 @@ #include <asm/io.h> /* Defines for the barcohydra board */ -#ifndef CFG_FLASH_ERASE_SECTOR_LENGTH -#define CFG_FLASH_ERASE_SECTOR_LENGTH (0x10000) +#ifndef CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH +#define CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH (0x10000) #endif -#ifndef CFG_DEFAULT_KERNEL_ADDRESS -#define CFG_DEFAULT_KERNEL_ADDRESS (CFG_FLASH_BASE + 0x30000) +#ifndef CONFIG_SYS_DEFAULT_KERNEL_ADDRESS +#define CONFIG_SYS_DEFAULT_KERNEL_ADDRESS (CONFIG_SYS_FLASH_BASE + 0x30000) #endif -#ifndef CFG_WORKING_KERNEL_ADDRESS -#define CFG_WORKING_KERNEL_ADDRESS (0xFFE00000) +#ifndef CONFIG_SYS_WORKING_KERNEL_ADDRESS +#define CONFIG_SYS_WORKING_KERNEL_ADDRESS (0xFFE00000) #endif diff --git a/board/barco/early_init.S b/board/barco/early_init.S index 07dafb716..531dcdf4a 100644 --- a/board/barco/early_init.S +++ b/board/barco/early_init.S @@ -32,68 +32,68 @@ #if defined(USE_DINK32) /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) + #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) #else - #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) + #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) #endif .text /* Values to program into memory controller registers */ tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT + .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT .long MCCR3 - .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ - (CFG_RDLAT << MCCR3_RDLAT_SHIFT) + .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ + (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \ + (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT) .long MCCR4 - .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CFG_REGISTERD_TYPE_BUFFER << 20) | \ - (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ - (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) + .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ + (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \ + (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ + ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \ + (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ + (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ + ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) .long MSAR1 - .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMSAR1 - .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MSAR2 - .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMSAR2 - .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MEAR1 - .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMEAR1 - .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MEAR2 - .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMEAR2 - .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long 0 @@ -123,7 +123,7 @@ loop: lwz r1, 4(r5) /* set bank enable bits */ lis r0, MBER@h ori r0, 0, MBER@l - li r1, CFG_BANK_ENABLE + li r1, CONFIG_SYS_BANK_ENABLE stwbrx r0, 0, r3 eieio stb r1, 0(r4) @@ -145,8 +145,8 @@ delay: bdnz delay eieio /* set up stack pointer */ - lis r1, CFG_INIT_SP_OFFSET@h - ori r1, r1, CFG_INIT_SP_OFFSET@l + lis r1, CONFIG_SYS_INIT_SP_OFFSET@h + ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l mtlr r10 blr diff --git a/board/barco/flash.c b/board/barco/flash.c index 6cb19b7b0..c9efb15e3 100644 --- a/board/barco/flash.c +++ b/board/barco/flash.c @@ -56,17 +56,17 @@ #define ROM_CS0_START 0xFF800000 #define ROM_CS1_START 0xFF000000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -140,10 +140,10 @@ unsigned long flash_init(void) { unsigned long i; unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; + static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++){ + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++){ flash_info_t * const pflinfo = &flash_info[i]; pflinfo->flash_id = FLASH_UNKNOWN; pflinfo->size = 0; @@ -217,17 +217,17 @@ unsigned long flash_init(void) break; } /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -458,7 +458,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) addr = (FLASH_WORD_SIZE *)(info->start[0] + ( (info->start[l_sect] - info->start[0]) << sh8b)); while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -599,7 +599,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c index a728dc64d..6fb0096be 100644 --- a/board/bc3450/bc3450.c +++ b/board/bc3450/bc3450.c @@ -33,6 +33,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <netdev.h> #ifdef CONFIG_VIDEO_SM501 #include <sm501.h> @@ -52,7 +53,7 @@ void ps2mult_early_init(void); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -99,7 +100,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -108,7 +109,7 @@ phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -129,9 +130,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -157,9 +158,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ sdram_start(0); - test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); if (test1 > test2) { sdram_start(0); dramsize2 = test1; @@ -180,7 +181,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -198,7 +199,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize; } @@ -208,7 +209,7 @@ phys_size_t initdram (int board_type) phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup and enable SDRAM chip selects */ @@ -227,9 +228,9 @@ phys_size_t initdram (int board_type) /* find RAM size */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -240,12 +241,12 @@ phys_size_t initdram (int board_type) /* set SDRAM end address according to size */ *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* Retrieve amount of SDRAM available */ dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize; } @@ -404,34 +405,34 @@ int last_stage_init (void) */ /* save original SRAM content */ - save = *(volatile u16 *)CFG_CS2_START; + save = *(volatile u16 *)CONFIG_SYS_CS2_START; restore = 1; /* write test pattern to SRAM */ - *(volatile u16 *)CFG_CS2_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in SRAM detection\n"); - if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { /* no SRAM at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; restore = 0; __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { /* make sure that we access a mirrored address */ - *(volatile u16 *)CFG_CS2_START = 0x1111; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; __asm__ volatile ("sync"); - if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, 0x80000); __asm__ volatile ("sync"); puts ("SRAM: 512 kB\n"); @@ -443,7 +444,7 @@ int last_stage_init (void) } /* restore origianl SRAM content */ if (restore) { - *(volatile u16 *)CFG_CS2_START = save; + *(volatile u16 *)CONFIG_SYS_CS2_START = save; __asm__ volatile ("sync"); } @@ -452,21 +453,21 @@ int last_stage_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; @@ -478,7 +479,7 @@ int last_stage_init (void) } /* restore origianl FB content */ if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } @@ -606,21 +607,21 @@ unsigned int board_video_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller found */ restore = 0; ret = 0; @@ -629,7 +630,7 @@ unsigned int board_video_init (void) } if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } return ret; @@ -669,3 +670,9 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SM501 */ + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +} diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c index 48bc65de2..ae5061f94 100644 --- a/board/bc3450/cmd_bc3450.c +++ b/board/bc3450/cmd_bc3450.c @@ -52,9 +52,9 @@ #define THERM_WRITE_TL 0x02 #define THERM_WRITE_TH 0x01 -#define CFG_CPU 2 -#define CFG_1SHOT 1 -#define CFG_STANDALONE 0 +#define CONFIG_SYS_CPU 2 +#define CONFIG_SYS_1SHOT 1 +#define CONFIG_SYS_STANDALONE 0 struct therm { int hi; @@ -513,7 +513,7 @@ static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) therm.hi <<= 1; therm.lo <<= 1; ds1620_write_state (&therm); - ds1620_out (THERM_WRITE_CONFIG, 8, CFG_STANDALONE); + ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE); return 0; } } @@ -538,9 +538,9 @@ int can_init (void) static int init_done = 0; int i; struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900); + (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900); struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980); + (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980); /* GPIO configuration of the CAN pins is done in BC3450.h */ @@ -686,9 +686,9 @@ int do_can (char *argv[]) { int i; struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900); + (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900); struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980); + (struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980); /* send a message on CAN1 */ can1->cantbsel = 0x01; diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 583560adb..42c4b5055 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -50,12 +50,12 @@ phys_size_t initdram(int board_type) printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); - printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); + printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); + printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); #endif - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; - return CFG_MAX_RAM_SIZE; + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return CONFIG_SYS_MAX_RAM_SIZE; } #if defined(CONFIG_MISC_INIT_R) @@ -63,10 +63,10 @@ phys_size_t initdram(int board_type) int misc_init_r(void) { /* Set direction bits for Video en/decoder reset as output */ - *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) = + *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) = PSDA_VDEC_RST | PSDA_VENC_RST; /* Deactivate Video en/decoder reset lines */ - *(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) = + *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) = PSDA_VDEC_RST | PSDA_VENC_RST; return 0; diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h index 4e043e072..1a4aa5f2f 100644 --- a/board/bf533-ezkit/flash-defines.h +++ b/board/bf533-ezkit/flash-defines.h @@ -49,10 +49,10 @@ #define FLASH_TOT_SECT 40 #define FLASH_SIZE 0x220000 #define FLASH_MAN_ST 2 -#define CFG_FLASH0_BASE 0x20000000 +#define CONFIG_SYS_FLASH0_BASE 0x20000000 #define RESET_VAL 0xF0 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; int get_codes(void); int poll_toggle_bit(long lOffset); diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index cdf4dc69b..a861e16a3 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -82,7 +82,7 @@ unsigned long flash_init(void) size_b0 = size_b1 = size_b2 = 0; #ifdef DEBUG - printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE); + printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE); printf("Memory Map for the Flash\n"); printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n"); printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n"); @@ -90,20 +90,20 @@ unsigned long flash_init(void) printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n"); printf("Please type command flinfo for information on Sectors \n"); #endif - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0); - size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1); - size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2); + size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0], 0); + size_b1 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[1], 1); + size_b2 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[2], 2); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 >> 20); } - (void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH0_BASE, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH0_BASE, (flash_info[0].start[2] - 1), &flash_info[0]); return (size_b0 + size_b1 + size_b2); @@ -180,7 +180,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) int ret; int d; if (addr % 2) { - read_flash(addr - 1 - CFG_FLASH_BASE, &d); + read_flash(addr - 1 - CONFIG_SYS_FLASH_BASE, &d); d = (int)((d & 0x00FF) | (*src++ << 8)); ret = write_data(addr - 1, 2, (uchar *) & d); if (ret == FLASH_FAIL) @@ -196,7 +196,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) int write_data(long lStart, long lCount, uchar * pnData) { long i = 0; - unsigned long ulOffset = lStart - CFG_FLASH_BASE; + unsigned long ulOffset = lStart - CONFIG_SYS_FLASH_BASE; int d; int nSector = 0; int flag = 0; @@ -285,7 +285,7 @@ int write_flash(long nOffset, int nValue) { long addr; - addr = (CFG_FLASH_BASE + nOffset); + addr = (CONFIG_SYS_FLASH_BASE + nOffset); SSYNC(); *(unsigned volatile short *)addr = nValue; SSYNC(); @@ -297,7 +297,7 @@ int write_flash(long nOffset, int nValue) int read_flash(long nOffset, int *pnValue) { int nValue = 0x0; - long addr = (CFG_FLASH_BASE + nOffset); + long addr = (CONFIG_SYS_FLASH_BASE + nOffset); if (nOffset != 0x2) reset_flash(); @@ -396,7 +396,7 @@ int erase_block_flash(int nBlock, unsigned long address) if ((nBlock < 0) || (nBlock > AFP_NumSectors)) return FALSE; - ulSectorOff = (address - CFG_FLASH_BASE); + ulSectorOff = (address - CONFIG_SYS_FLASH_BASE); write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1); write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2); diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h index cc654b895..9b381d27f 100644 --- a/board/bf533-ezkit/psd4256.h +++ b/board/bf533-ezkit/psd4256.h @@ -27,8 +27,8 @@ /* * Flash A/B Port A configuration registers. - * Addresses are offset values to CFG_FLASH1_BASE - * for Flash A and CFG_FLASH2_BASE for Flash B. + * Addresses are offset values to CONFIG_SYS_FLASH1_BASE + * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B. */ #define PSD_PORTA_DIN 0x070000 @@ -37,8 +37,8 @@ /* * Flash A/B Port B configuration registers - * Addresses are offset values to CFG_FLASH1_BASE - * for Flash A and CFG_FLASH2_BASE for Flash B. + * Addresses are offset values to CONFIG_SYS_FLASH1_BASE + * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B. */ #define PSD_PORTB_DIN 0x070001 diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S index e4b83d11d..70764acf1 100644 --- a/board/bf533-ezkit/u-boot.lds.S +++ b/board/bf533-ezkit/u-boot.lds.S @@ -36,7 +36,7 @@ * for different CPU's which may lack non-cache L1 data. */ #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CFG_MONITOR_BASE +# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE # define L1_DATA_B_SRAM_SIZE 0 #endif @@ -45,7 +45,7 @@ OUTPUT_ARCH(bfin) /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ MEMORY { - ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -71,9 +72,13 @@ SECTIONS board/bf533-ezkit/bf533-ezkit.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 7a17dfa55..0c6324b4b 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -26,7 +26,6 @@ */ #include <common.h> -#include <asm/mem_init.h> #include <asm/io.h> #include "bf533-stamp.h" @@ -56,11 +55,11 @@ phys_size_t initdram(int board_type) (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; " "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11), (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2)); - printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); + printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); printf("Bank size = %d MB\n", 128); #endif - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; return (gd->bd->bi_memsize); } diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S index 01780c570..187309f3f 100644 --- a/board/bf533-stamp/u-boot.lds.S +++ b/board/bf533-stamp/u-boot.lds.S @@ -36,7 +36,7 @@ * for different CPU's which may lack non-cache L1 data. */ #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CFG_MONITOR_BASE +# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE # define L1_DATA_B_SRAM_SIZE 0 #endif @@ -45,7 +45,7 @@ OUTPUT_ARCH(bfin) /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ MEMORY { - ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -69,9 +70,13 @@ SECTIONS lib_generic/crc32.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index a9b7a68c5..7303f1b41 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -32,6 +32,7 @@ #include <asm/io.h> #include <net.h> #include <asm/mach-common/bits/bootrom.h> +#include <netdev.h> /** * is_valid_ether_addr - Determine if the given Ethernet address is valid @@ -108,12 +109,12 @@ phys_size_t initdram(int board_type) printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); - printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); + printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); + printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); #endif - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; - return CFG_MAX_RAM_SIZE; + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return CONFIG_SYS_MAX_RAM_SIZE; } #if defined(CONFIG_MISC_INIT_R) @@ -156,8 +157,6 @@ int misc_init_r(void) #if defined(CONFIG_BFIN_MAC) -extern int bfin_EMAC_initialize(bd_t *bis); - int board_eth_init(bd_t *bis) { return bfin_EMAC_initialize(bis); @@ -237,11 +236,11 @@ int flash_post_test(int flags) erase_block_flash(n); printf("OK\r"); printf("--------Program block:%2d...", n); - write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf); + write_data(CONFIG_SYS_FLASH_BASE + offset, BLOCK_SIZE, pbuf); printf("OK\r"); printf("--------Verify block:%2d...", n); for (i = 0; i < BLOCK_SIZE; i += 2) { - if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) != + if (*(unsigned short *)(CONFIG_SYS_FLASH_BASE + offset + i) != *temp++) { value = 1; result = 1; diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c index 9800083c9..c597f2db1 100644 --- a/board/bf537-stamp/nand.c +++ b/board/bf537-stamp/nand.c @@ -44,13 +44,13 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) if (ctrl & NAND_CTRL_CHANGE) { if( ctrl & NAND_CLE ) - IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE; else - IO_ADDR_W = CFG_NAND_BASE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE; if( ctrl & NAND_ALE ) - IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE; else - IO_ADDR_W = CFG_NAND_BASE; + IO_ADDR_W = CONFIG_SYS_NAND_BASE; this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; } this->IO_ADDR_R = this->IO_ADDR_W; diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index fa119919b..889aa5c4f 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -6,7 +6,7 @@ #include <post.h> #include <watchdog.h> -#if CONFIG_POST & CFG_POST_MEMORY +#if CONFIG_POST & CONFIG_SYS_POST_MEMORY #define CLKIN 25000000 #define PATTERN1 0x5A5A5A5A #define PATTERN2 0xAAAAAAAA @@ -27,18 +27,18 @@ const int pll[CCLK_NUM][SCLK_NUM][2] = { {{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */ }; const char *const log[CCLK_NUM][SCLK_NUM] = { - {"CCLK-500Mhz SCLK-125Mhz: Writing...\0", - "CCLK-500Mhz SCLK-100Mhz: Writing...\0", - "CCLK-500Mhz SCLK- 50Mhz: Writing...\0",}, - {"CCLK-400Mhz SCLK-100Mhz: Writing...\0", - "CCLK-400Mhz SCLK- 80Mhz: Writing...\0", - "CCLK-400Mhz SCLK- 50Mhz: Writing...\0",}, - {"CCLK-200Mhz SCLK-100Mhz: Writing...\0", - "CCLK-200Mhz SCLK- 50Mhz: Writing...\0", - "CCLK-200Mhz SCLK- 40Mhz: Writing...\0",}, - {"CCLK-100Mhz SCLK-100Mhz: Writing...\0", - "CCLK-100Mhz SCLK- 50Mhz: Writing...\0", - "CCLK-100Mhz SCLK- 25Mhz: Writing...\0",}, + {"CCLK-500MHz SCLK-125MHz: Writing...\0", + "CCLK-500MHz SCLK-100MHz: Writing...\0", + "CCLK-500MHz SCLK- 50MHz: Writing...\0",}, + {"CCLK-400MHz SCLK-100MHz: Writing...\0", + "CCLK-400MHz SCLK- 80MHz: Writing...\0", + "CCLK-400MHz SCLK- 50MHz: Writing...\0",}, + {"CCLK-200MHz SCLK-100MHz: Writing...\0", + "CCLK-200MHz SCLK- 50MHz: Writing...\0", + "CCLK-200MHz SCLK- 40MHz: Writing...\0",}, + {"CCLK-100MHz SCLK-100MHz: Writing...\0", + "CCLK-100MHz SCLK- 50MHz: Writing...\0", + "CCLK-100MHz SCLK- 25MHz: Writing...\0",}, }; int memory_post_test(int flags) @@ -71,10 +71,10 @@ int memory_post_test(int flags) post_init_uart(sclk); post_out_buff("\n\r\0"); post_out_buff(log[m][n]); - for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) + for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) *(unsigned long *)addr = PATTERN1; post_out_buff("Reading...\0"); - for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) { + for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) { if ((*(unsigned long *)addr) != PATTERN1) { post_out_buff("Error\n\r\0"); ret = 0; @@ -318,5 +318,5 @@ int post_init_sdram(int sclk) return mem_SDRRC; } -#endif /* CONFIG_POST & CFG_POST_MEMORY */ +#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */ #endif /* CONFIG_POST */ diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c index 7c73ddd72..11a2803e6 100644 --- a/board/bf537-stamp/spi_flash.c +++ b/board/bf537-stamp/spi_flash.c @@ -412,7 +412,7 @@ void spi_init_f(void) */ void spi_init_r(void) { -#if defined(CONFIG_POST) && (CONFIG_POST & CFG_POST_SPI) +#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI) /* Our testing strategy here is pretty basic: * - fill src memory with an 8-bit pattern * - write the src memory to the SPI flash diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S index 01780c570..187309f3f 100644 --- a/board/bf537-stamp/u-boot.lds.S +++ b/board/bf537-stamp/u-boot.lds.S @@ -36,7 +36,7 @@ * for different CPU's which may lack non-cache L1 data. */ #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CFG_MONITOR_BASE +# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE # define L1_DATA_B_SRAM_SIZE 0 #endif @@ -45,7 +45,7 @@ OUTPUT_ARCH(bfin) /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ MEMORY { - ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -69,9 +70,13 @@ SECTIONS lib_generic/crc32.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 7345b42cb..7f8598c71 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -1,8 +1,7 @@ /* - * U-boot - ezkit561.c + * U-boot - main board file * - * Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl> - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -33,7 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; int checkboard(void) { - printf("CPU: ADSP BF561\n"); printf("Board: ADI BF561 EZ-Kit Lite board\n"); printf(" Support: http://blackfin.uclinux.org/\n"); return 0; @@ -50,25 +48,10 @@ phys_size_t initdram(int board_type) printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE); - printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20); + printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); + printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); #endif - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; - return CFG_MAX_RAM_SIZE; + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; + return CONFIG_SYS_MAX_RAM_SIZE; } - -#if defined(CONFIG_MISC_INIT_R) -/* miscellaneous platform dependent initialisations */ -int misc_init_r(void) -{ - /* Keep PF12 low to be able to drive the USB-LAN Extender */ - *pFIO0_DIR = 0x0000; - *pFIO0_FLAG_C = 0x1000; /* Clear PF12 */ - SSYNC(); - *pFIO0_POLAR = 0x0000; - SSYNC(); - - return 0; -} -#endif diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S index ddafdcb2a..99d6be634 100644 --- a/board/bf561-ezkit/u-boot.lds.S +++ b/board/bf561-ezkit/u-boot.lds.S @@ -36,7 +36,7 @@ * for different CPU's which may lack non-cache L1 data. */ #ifndef L1_DATA_B_SRAM -# define L1_DATA_B_SRAM CFG_MONITOR_BASE +# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE # define L1_DATA_B_SRAM_SIZE 0 #endif @@ -45,7 +45,7 @@ OUTPUT_ARCH(bfin) /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ MEMORY { - ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN + ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE } @@ -54,6 +54,8 @@ SECTIONS { .text : { + cpu/blackfin/start.o (.text) + #ifdef ENV_IS_EMBEDDED /* WARNING - the following is hand-optimized to fit within * the sector before the environment sector. If it throws @@ -61,7 +63,6 @@ SECTIONS * it linked after the configuration sector. */ - cpu/blackfin/start.o (.text) cpu/blackfin/traps.o (.text) cpu/blackfin/interrupt.o (.text) cpu/blackfin/serial.o (.text) @@ -71,9 +72,13 @@ SECTIONS board/bf561-ezkit/bf561-ezkit.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) #endif + __initcode_start = .; + cpu/blackfin/initcode.o (.text) + __initcode_end = .; + *(.text .text.*) } >ram diff --git a/board/bmw/README b/board/bmw/README index 1f04b1b8a..1fbef79e6 100644 --- a/board/bmw/README +++ b/board/bmw/README @@ -62,26 +62,26 @@ IO/MMU (BAT) Configuration The following Block-Address-Translation (BAT) configuration is recommended to access all I/O devices. -#define CFG_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CFG_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CFG_DBAT0L CFG_IBAT0L -#define CFG_DBAT0U CFG_IBAT0U -#define CFG_DBAT1L CFG_IBAT1L -#define CFG_DBAT1U CFG_IBAT1U -#define CFG_DBAT2L CFG_IBAT2L -#define CFG_DBAT2U CFG_IBAT2U -#define CFG_DBAT3L CFG_IBAT3L -#define CFG_DBAT3U CFG_IBAT3U +#define CONFIG_SYS_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U Interrupt Mappings diff --git a/board/bmw/bmw.c b/board/bmw/bmw.c index 043143163..41ce14f65 100644 --- a/board/bmw/bmw.c +++ b/board/bmw/bmw.c @@ -28,7 +28,7 @@ #include <malloc.h> #include <devices.h> #include <net.h> -#include <version.h> +#include <timestamp.h> #include <dtt.h> #include <mpc824x.h> #include <asm/processor.h> @@ -45,7 +45,7 @@ int checkboard(void) char buf[32]; puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n"); - printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */ printf("Local Bus at %s MHz\n", strmhz(buf, busfreq)); return 0; @@ -125,7 +125,7 @@ void doc_init (void) doc_probe(DOC_BASE_ADDR); } -#define NV_ADDR ((volatile unsigned char *) CFG_ENV_ADDR) +#define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR) /* Read from NVRAM */ void* diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S index 57a06a91f..63c29d500 100644 --- a/board/bmw/early_init.S +++ b/board/bmw/early_init.S @@ -86,10 +86,10 @@ iommu_setup: /* * Set up I/D BAT0 */ - lis r4, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - lis r3, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l + lis r4, CONFIG_SYS_DBAT0L@h + ori r4, r4, CONFIG_SYS_DBAT0L@l + lis r3, CONFIG_SYS_DBAT0U@h + ori r3, r3, CONFIG_SYS_DBAT0U@l mtdbat0l(r4) isync @@ -97,10 +97,10 @@ iommu_setup: isync sync - lis r4, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - lis r3, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l + lis r4, CONFIG_SYS_IBAT0L@h + ori r4, r4, CONFIG_SYS_IBAT0L@l + lis r3, CONFIG_SYS_IBAT0U@h + ori r3, r3, CONFIG_SYS_IBAT0U@l isync mtibat0l(r4) @@ -111,10 +111,10 @@ iommu_setup: /* * Set up I/D BAT1 */ - lis r4, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - lis r3, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l + lis r4, CONFIG_SYS_IBAT1L@h + ori r4, r4, CONFIG_SYS_IBAT1L@l + lis r3, CONFIG_SYS_IBAT1U@h + ori r3, r3, CONFIG_SYS_IBAT1U@l isync mtibat1l(r4) @@ -130,10 +130,10 @@ iommu_setup: /* * Set up I/D BAT2 */ - lis r4, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - lis r3, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l + lis r4, CONFIG_SYS_IBAT2L@h + ori r4, r4, CONFIG_SYS_IBAT2L@l + lis r3, CONFIG_SYS_IBAT2U@h + ori r3, r3, CONFIG_SYS_IBAT2U@l isync mtibat2l(r4) @@ -149,10 +149,10 @@ iommu_setup: /* * Setup I/D BAT3 */ - lis r4, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - lis r3, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l + lis r4, CONFIG_SYS_IBAT3L@h + ori r4, r4, CONFIG_SYS_IBAT3L@l + lis r3, CONFIG_SYS_IBAT3U@h + ori r3, r3, CONFIG_SYS_IBAT3U@l isync mtibat3l(r4) @@ -466,7 +466,7 @@ X4_KAHLUA_START: LOADPTR (r3, EUMBBAR) stwbrx r3,0,r5 - LOADPTR (r4, CFG_EUMB_ADDR) + LOADPTR (r4, CONFIG_SYS_EUMB_ADDR) stwbrx r4,0,r6 L1not8245: diff --git a/board/bmw/flash.c b/board/bmw/flash.c index 7fba174f4..57ffe0890 100644 --- a/board/bmw/flash.c +++ b/board/bmw/flash.c @@ -29,17 +29,17 @@ #define ROM_CS0_START 0xFF800000 #define ROM_CS1_START 0xFF000000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -141,10 +141,10 @@ unsigned long flash_init (void) { unsigned long i; unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; + static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info_t *const pflinfo = &flash_info[i]; pflinfo->flash_id = FLASH_UNKNOWN; @@ -217,17 +217,17 @@ unsigned long flash_init (void) } /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -627,7 +627,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) start[0]) << sh8b)); while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -766,7 +766,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/bmw/m48t59y.c b/board/bmw/m48t59y.c index a1a85d0fc..4e83b9076 100644 --- a/board/bmw/m48t59y.c +++ b/board/bmw/m48t59y.c @@ -299,8 +299,7 @@ rtc_get( struct rtc_time *tmp ) return 0; } -void -rtc_set( struct rtc_time *tmp ) +int rtc_set( struct rtc_time *tmp ) { m48_tod_set(tmp->tm_year, /* 1980-2079 */ tmp->tm_mon, /* 01-12 */ @@ -315,6 +314,7 @@ rtc_set( struct rtc_time *tmp ) tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif + return 0; } void diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c index 706456724..725059103 100644 --- a/board/bmw/ns16550.c +++ b/board/bmw/ns16550.c @@ -1,7 +1,7 @@ /* * COM1 NS16550 support * originally from linux source (arch/ppc/boot/ns16550.c) - * modified to use CFG_ISA_MEM and new defines + * modified to use CONFIG_SYS_ISA_MEM and new defines */ #include <config.h> @@ -10,8 +10,8 @@ typedef struct NS16550 *NS16550_t; const NS16550_t COM_PORTS[] = - { (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500), -(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) }; + { (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500), +(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) }; volatile struct NS16550 *NS16550_init (int chan, int baud_divisor) { diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h index 104f45bfb..210aea4b2 100644 --- a/board/bmw/ns16550.h +++ b/board/bmw/ns16550.h @@ -2,7 +2,7 @@ * NS16550 Serial Port * originally from linux source (arch/ppc/boot/ns16550.h) * modified slightly to - * have addresses as offsets from CFG_ISA_BASE + * have addresses as offsets from CONFIG_SYS_ISA_BASE * added a few more definitions * added prototypes for ns16550.c * reduced no of com ports to 2 diff --git a/board/bmw/serial.c b/board/bmw/serial.c index 712a95b19..0c97f1288 100644 --- a/board/bmw/serial.c +++ b/board/bmw/serial.c @@ -28,10 +28,10 @@ DECLARE_GLOBAL_DATA_PTR; #if CONFIG_CONS_INDEX == 1 static struct NS16550 *console = - (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500); + (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500); #elif CONFIG_CONS_INDEX == 2 static struct NS16550 *console = - (struct NS16550 *) (CFG_EUMB_ADDR + 0x4500); + (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500); #else #error no valid console defined #endif diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c index 7d2f746f4..717a64bb8 100644 --- a/board/c2mon/c2mon.c +++ b/board/c2mon/c2mon.c @@ -110,7 +110,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long reg; long int size8, size9; @@ -124,17 +124,17 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 2 the SDRAM bank 2 at physical address 0. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -154,7 +154,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); @@ -163,7 +163,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); @@ -172,7 +172,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -185,15 +185,15 @@ phys_size_t initdram (int board_type) */ if (size < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } /* * Final mapping */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* * No bank 1 @@ -204,7 +204,7 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; udelay (10000); @@ -225,7 +225,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c index b2be21c68..d33cb6ce4 100644 --- a/board/c2mon/flash.c +++ b/board/c2mon/flash.c @@ -24,11 +24,11 @@ #include <common.h> #include <mpc8xx.h> -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -42,13 +42,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -79,54 +79,54 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[1]); #endif } else { @@ -436,7 +436,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -559,7 +559,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c index 57846b10c..c833b20b7 100644 --- a/board/c2mon/pcmcia.c +++ b/board/c2mon/pcmcia.c @@ -22,8 +22,8 @@ static void cfg_ports (void) volatile cpm8xx_t *cp; ushort sreg; - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure Port C for TPS2211 PC-Card Power-Interface Switch @@ -69,10 +69,10 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ cfg_ports (); @@ -175,8 +175,8 @@ int pcmcia_hardware_disable(int slot) debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* Configure PCMCIA General Control Register */ debug ("Disable PCMCIA buffers and assert RESET\n"); @@ -209,9 +209,9 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) * and assert RESET signal diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds index 10b38ec35..ef9a2515c 100644 --- a/board/c2mon/u-boot.lds +++ b/board/c2mon/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug index 85072feda..dbec9860a 100644 --- a/board/c2mon/u-boot.lds.debug +++ b/board/c2mon/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index d3711d077..dce07bf78 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -34,7 +34,7 @@ #include "mt48lc16m32s2-75.h" #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -77,7 +77,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -86,7 +86,7 @@ phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -107,9 +107,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -135,10 +135,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -160,7 +160,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -178,7 +178,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize + dramsize2; } @@ -188,7 +188,7 @@ phys_size_t initdram (int board_type) phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup and enable SDRAM chip selects */ @@ -207,9 +207,9 @@ phys_size_t initdram (int board_type) /* find RAM size */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -220,12 +220,12 @@ phys_size_t initdram (int board_type) /* set SDRAM end address according to size */ *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* Retrieve amount of SDRAM available */ dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize; } @@ -244,8 +244,8 @@ int board_early_init_r (void) { *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); + *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); return 0; } diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c index ba82892dd..a4b201e01 100644 --- a/board/cerf250/flash.c +++ b/board/cerf250/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -65,7 +65,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -85,13 +85,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0] ); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); return size; } @@ -203,10 +203,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -276,7 +276,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -410,7 +410,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S index ad3c59f9f..5bfe53c72 100644 --- a/board/cerf250/lowlevel_init.S +++ b/board/cerf250/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -49,67 +49,67 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ---------------------------------------------------------------- */ @@ -147,17 +147,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -166,37 +166,37 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] @@ -212,7 +212,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field, set SDRAM clocks free running */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 @@ -243,7 +243,7 @@ mem_init: /* set MDREFR according to user define with exception of a few bits */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\ MDREFR_K2RUN |MDREFR_K2DB2) and r4, r4, r2 @@ -262,7 +262,7 @@ mem_init: /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \ MDREFR_K1FREE | MDREFR_K2FREE) and r4, r4, r2 @@ -274,7 +274,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ @@ -301,7 +301,7 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE .rept 8 str r2, [r3] .endr @@ -315,7 +315,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] diff --git a/board/cerf250/u-boot.lds b/board/cerf250/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/cerf250/u-boot.lds +++ b/board/cerf250/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 86c8e2a5f..2e6687246 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -31,7 +31,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define mb() __asm__ __volatile__ ("" : : : "memory") @@ -51,7 +51,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); @@ -71,8 +71,8 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, &flash_info[0]); return size; @@ -189,10 +189,10 @@ static ulong flash_get_size (unsigned char * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = 0xFF; /* restore read mode */ @@ -259,7 +259,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & 0x80) != 0x80) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ @@ -388,7 +388,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) /* wait while polling the status register */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0xFF; /* restore read mode */ return (1); } diff --git a/board/cm4008/u-boot.lds b/board/cm4008/u-boot.lds index 3d38f2340..e1febe19b 100644 --- a/board/cm4008/u-boot.lds +++ b/board/cm4008/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 86c8e2a5f..2e6687246 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -31,7 +31,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define mb() __asm__ __volatile__ ("" : : : "memory") @@ -51,7 +51,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); @@ -71,8 +71,8 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, &flash_info[0]); return size; @@ -189,10 +189,10 @@ static ulong flash_get_size (unsigned char * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = 0xFF; /* restore read mode */ @@ -259,7 +259,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((status = *addr) & 0x80) != 0x80) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ @@ -388,7 +388,7 @@ static int write_data (flash_info_t * info, ulong dest, unsigned char data) /* wait while polling the status register */ while (((status = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0xFF; /* restore read mode */ return (1); } diff --git a/board/cm41xx/u-boot.lds b/board/cm41xx/u-boot.lds index 3d38f2340..e1febe19b 100644 --- a/board/cm41xx/u-boot.lds +++ b/board/cm41xx/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c index 24e8db0c6..9e2f1a536 100644 --- a/board/cm5200/cm5200.c +++ b/board/cm5200/cm5200.c @@ -57,7 +57,7 @@ DECLARE_GLOBAL_DATA_PTR; static hw_id_t hw_id; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* * Helper function to initialize SDRAM controller. */ @@ -87,7 +87,7 @@ static void sdram_start(int hi_addr, mem_conf_t *mem_conf) /* normal operation */ *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* @@ -117,7 +117,7 @@ static mem_conf_t* get_mem_config(int board_type) phys_size_t initdram(int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; mem_conf_t *mem_conf; @@ -131,9 +131,9 @@ phys_size_t initdram(int board_type) *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2; sdram_start(0, mem_conf); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1, mem_conf); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0, mem_conf); dramsize = test1; @@ -150,14 +150,14 @@ phys_size_t initdram(int board_type) __builtin_ffs(dramsize >> 20) - 1; } else *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; if (dramsize >= 0x13) dramsize = (1 << (dramsize - 0x13)) << 20; else dramsize = 0; -#endif /* !CFG_RAMBOOT */ +#endif /* !CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -178,7 +178,7 @@ static void read_hw_id(hw_id_t hw_id) { int i; for (i = 0; i < HW_ID_ELEM_COUNT; ++i) - if (i2c_read(CFG_I2C_EEPROM, + if (i2c_read(CONFIG_SYS_I2C_EEPROM, hw_id_format[i].offset, 2, (uchar *)&hw_id[i][0], @@ -298,7 +298,7 @@ int checkboard(void) * also use a little trick to silence I2C-related output. */ gd->flags |= GD_FLG_SILENT; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); gd->flags &= ~GD_FLG_SILENT; read_hw_id(hw_id_tmp); @@ -363,7 +363,7 @@ int misc_init_r(void) char hostname[MODULE_NAME_MAXLEN]; /* Read ethaddr from EEPROM */ - if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); /* Check if MAC addr is owned by Schindler */ @@ -377,7 +377,7 @@ int misc_init_r(void) } } else { printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" - " device at address %02X:%04X\n", CFG_I2C_EEPROM, + " device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET); } #endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 2201bdd8c..00f0671d7 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -39,18 +39,18 @@ int do_i2c(char *argv[]) getc(); temp = 0xf0; /* set io 0-4 as output */ - i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1); + i2c_write(CONFIG_SYS_I2C_IO, 3, 1, (uchar *)&temp, 1); printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" "Press any key to stop\n\n"); while (!tstc()) { - i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1); + i2c_read(CONFIG_SYS_I2C_IO, 0, 1, (uchar *)&temp, 1); temp1 = (temp >> 4) & 0x03; temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ temp = temp1; - i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1); + i2c_write(CONFIG_SYS_I2C_IO, 1, 1, (uchar *)&temp, 1); } getc(); @@ -392,7 +392,7 @@ int do_rs232(char *argv[]) error_status = 1; break; } - gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F); + gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F); return error_status; } diff --git a/board/cm5200/u-boot.lds b/board/cm5200/u-boot.lds index 87f37de16..7bd6d4da1 100644 --- a/board/cm5200/u-boot.lds +++ b/board/cm5200/u-boot.lds @@ -116,6 +116,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c index 9983c7b78..d832e6209 100644 --- a/board/cmc_pu2/flash.c +++ b/board/cmc_pu2/flash.c @@ -29,11 +29,11 @@ #include <common.h> -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define FLASH_CYCLE1 0x0555 #define FLASH_CYCLE2 0x02AA @@ -54,7 +54,7 @@ static flash_info_t *flash_get_info(ulong base); unsigned long flash_init (void) { unsigned long size = 0; - ulong flashbase = CFG_FLASH_BASE; + ulong flashbase = CONFIG_SYS_FLASH_BASE; /* Init: no FLASHes known */ memset(&flash_info[0], 0, sizeof(flash_info_t)); @@ -63,20 +63,20 @@ unsigned long flash_init (void) size = flash_info[0].size; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif return size ? size : 1; @@ -104,14 +104,14 @@ static flash_info_t *flash_get_info(ulong base) flash_info_t * info; info = NULL; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->size && info->start[0] <= base && base <= info->start[0] + info->size - 1) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -339,7 +339,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = 0; addr = (vu_short *)(info->start[l_sect]); while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -459,7 +459,7 @@ static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) /* data polling for D7 */ while ((*dest & 0x0080) != (data & 0x0080)) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = 0x00F0; /* reset bank */ return (1); } diff --git a/board/cmc_pu2/u-boot.lds b/board/cmc_pu2/u-boot.lds index 14cd22800..987b07d94 100644 --- a/board/cmc_pu2/u-boot.lds +++ b/board/cmc_pu2/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c index 8501cae21..b78183e13 100644 --- a/board/cmi/cmi.c +++ b/board/cmi/cmi.c @@ -70,4 +70,4 @@ phys_size_t initdram(int board_type) /* * Absolute environment address for linker file. */ -GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE); +GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE); diff --git a/board/cmi/flash.c b/board/cmi/flash.c index f57d8ecfe..630c3305e 100644 --- a/board/cmi/flash.c +++ b/board/cmi/flash.c @@ -36,15 +36,15 @@ #include <common.h> #include <mpc5xx.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -62,7 +62,7 @@ #define FLASH_CMD_PROTECT_CLEAR 0x00D0 #define FLASH_STATUS_DONE 0x0080 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* * Local function prototypes @@ -81,7 +81,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -102,19 +102,19 @@ unsigned long flash_init (void) flash_info[0].size = size_b0; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif @@ -268,10 +268,10 @@ static ulong flash_get_size (vu_short *addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = FLASH_CMD_RESET; /* restore read mode */ @@ -345,7 +345,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Flash erase timeout at address %lx\n", info->start[sect]); *addr = FLASH_CMD_SUSPEND_ERASE; *addr = FLASH_CMD_RESET; @@ -473,7 +473,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) /* wait for error or finish */ while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { addr[0] = FLASH_CMD_RESET; return (1); } @@ -504,7 +504,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) /* wait for error or finish */ start = get_timer (0); while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Flash protect timeout at address %lx\n", info->start[sector]); addr[0] = FLASH_CMD_RESET; return (1); diff --git a/board/cobra5272/Makefile b/board/cobra5272/Makefile index be704b76f..cf07cf40f 100644 --- a/board/cobra5272/Makefile +++ b/board/cobra5272/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o mii.o +COBJS = $(BOARD).o flash.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c index b92855050..a62214cf5 100644 --- a/board/cobra5272/cobra5272.c +++ b/board/cobra5272/cobra5272.c @@ -42,7 +42,7 @@ phys_size_t initdram (int board_type) /* Dummy write to start SDRAM */ *((volatile unsigned long *) 0) = 0; - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; int testdram (void) diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c index 82452e2c4..33c936120 100644 --- a/board/cobra5272/flash.c +++ b/board/cobra5272/flash.c @@ -23,10 +23,10 @@ #include <common.h> -#define PHYS_FLASH_1 CFG_FLASH_BASE +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x200000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; void flash_print_info (flash_info_t * info) { @@ -74,15 +74,15 @@ unsigned long flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | (AMD_ID_PL160CB & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -113,8 +113,8 @@ unsigned long flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]); return size; } @@ -128,8 +128,8 @@ unsigned long flash_init (void) #define CMD_PROGRAM 0x00A0 #define CMD_UNLOCK_BYPASS 0x0020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) #define BIT_ERASE_DONE 0x0080 #define BIT_RDY_MASK 0x0080 @@ -211,7 +211,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -299,7 +299,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; } diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c deleted file mode 100644 index b30ba803f..000000000 --- a/board/cobra5272/mii.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; - } else { - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_AMD79C874VC "AMD79C874VC" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - strcpy(info->phy_name, - STR_ID_AMD79C874VC); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - printf(STR_ID_AMD79C874VC); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index f99a236a3..bed11777e 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/cogent/README b/board/cogent/README index e6eef662c..31ca187b5 100644 --- a/board/cogent/README +++ b/board/cogent/README @@ -80,16 +80,16 @@ To configure, perform the usual U-Boot configuration task of editing "include/config_cogent_mpc8xx.h" and reviewing all the options and settings in there. In particular, check the chip select values installed into the memory controller's various option and base -registers - these are set by the defines CFG_CMA_CSn_{BASE,SIZE} and -CFG_{B,O}Rn_PRELIM. Also be careful of the clock settings installed -into the SCCR - via the define CFG_SCCR. Finally, decide whether you +registers - these are set by the defines CONFIG_SYS_CMA_CSn_{BASE,SIZE} and +CONFIG_SYS_{B,O}Rn_PRELIM. Also be careful of the clock settings installed +into the SCCR - via the define CONFIG_SYS_SCCR. Finally, decide whether you want the serial console on motherboard serial port A or on one of the 8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly (NONE means use Cogent motherboard serial port A). Then edit the file "cogent/config.mk". Firstly, set TEXT_BASE to be the base address of the EPROM for the CPU module. This should be the -same as the value selected for CFG_MONITOR_BASE in +same as the value selected for CONFIG_SYS_MONITOR_BASE in "include/config_cogent_*.h" (in fact, I have made this automatic via the -DTEXT_BASE=... option in CPPFLAGS). diff --git a/board/cogent/flash.c b/board/cogent/flash.c index 969520d27..e6c85b6d9 100644 --- a/board/cogent/flash.c +++ b/board/cogent/flash.c @@ -24,17 +24,17 @@ #include <common.h> #include <board/cogent/flash.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -121,7 +121,7 @@ c302f_probe(flash_info_t *fip, c302f_addr_t base) fip->size += C302F_BNK_SIZE; osc = fip->sector_count; fip->sector_count += C302F_BNK_NBLOCKS; - if ((nsc = fip->sector_count) >= CFG_MAX_FLASH_SECT) + if ((nsc = fip->sector_count) >= CONFIG_SYS_MAX_FLASH_SECT) panic("Too many sectors in flash at address 0x%08lx\n", (unsigned long)base); @@ -264,7 +264,7 @@ c302f_write_word(c302f_addr_t addr, c302f_word_t value) /* data polling for D7 */ start = get_timer (0); do { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { retval = 1; goto done; } @@ -295,7 +295,7 @@ flash_init(void) flash_info_t *fip; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -303,7 +303,7 @@ flash_init(void) total = 0L; #if defined(CONFIG_CMA302) - c302f_probe(fip, (c302f_addr_t)CFG_FLASH_BASE); + c302f_probe(fip, (c302f_addr_t)CONFIG_SYS_FLASH_BASE); total += fip->size; fip++; #endif @@ -320,18 +320,18 @@ flash_init(void) * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE == CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif return total; @@ -472,7 +472,7 @@ flash_erase(flash_info_t *info, int s_first, int s_last) do { now = get_timer(start); - if (now - estart > CFG_FLASH_ERASE_TOUT) { + if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (sect %d)\n", sect); haderr = 1; break; diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c index 814b4c80a..76f5ad103 100644 --- a/board/cogent/lcd.c +++ b/board/cogent/lcd.c @@ -197,7 +197,7 @@ void lcd_printf(const char *fmt, ...) { va_list args; - char buf[CFG_PBSIZE]; + char buf[CONFIG_SYS_PBSIZE]; va_start(args, fmt); (void)vsprintf(buf, fmt, args); @@ -234,7 +234,7 @@ lcd_heartbeat(void) void board_show_activity (ulong timestamp) { #ifdef CONFIG_STATUS_LED - if ((timestamp % (CFG_HZ / 2) == 0) + if ((timestamp % (CONFIG_SYS_HZ / 2) == 0) lcd_heartbeat (); #endif } diff --git a/board/cogent/mb.h b/board/cogent/mb.h index f6eaf0ac5..b3aba48f7 100644 --- a/board/cogent/mb.h +++ b/board/cogent/mb.h @@ -69,51 +69,51 @@ * 0xA000000-0xDFFFFFF. */ -#define CMA_MB_RAM_BASE (CFG_CMA_MB_BASE+0x0000000) +#define CMA_MB_RAM_BASE (CONFIG_SYS_CMA_MB_BASE+0x0000000) #define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */ #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1) -#define CMA_MB_SLOT1_BASE (CFG_CMA_MB_BASE+0x2000000) +#define CMA_MB_SLOT1_BASE (CONFIG_SYS_CMA_MB_BASE+0x2000000) #define CMA_MB_SLOT1_SIZE 0x2000000 #endif #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#define CMA_MB_SLOT2_BASE (CFG_CMA_MB_BASE+0x4000000) +#define CMA_MB_SLOT2_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000) #define CMA_MB_SLOT2_SIZE 0x2000000 #endif #if (CMA_MB_CAPS & CMA_MB_CAP_PCI) -#define CMA_MB_STDPCI_BASE (CFG_CMA_MB_BASE+0x4000000) +#define CMA_MB_STDPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000) #define CMA_MB_STDPCI_SIZE 0x1ff0000 -#define CMA_MB_V360EPC_BASE (CFG_CMA_MB_BASE+0x5ff0000) +#define CMA_MB_V360EPC_BASE (CONFIG_SYS_CMA_MB_BASE+0x5ff0000) #define CMA_MB_V360EPC_SIZE 0x10000 #endif #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) -#define CMA_MB_SLOT3_BASE (CFG_CMA_MB_BASE+0x6000000) +#define CMA_MB_SLOT3_BASE (CONFIG_SYS_CMA_MB_BASE+0x6000000) #define CMA_MB_SLOT3_SIZE 0x2000000 #endif #if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) -#define CMA_MB_EXTPCI_BASE (CFG_CMA_MB_BASE+0xa000000) +#define CMA_MB_EXTPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0xa000000) #define CMA_MB_EXTPCI_SIZE 0x4000000 #endif -#define CMA_MB_ROMLOW_BASE (CFG_CMA_MB_BASE+0xe000000) +#define CMA_MB_ROMLOW_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000) #define CMA_MB_ROMLOW_SIZE 0x800000 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -#define CMA_MB_FLLOW_EXEC_BASE (CFG_CMA_MB_BASE+0xe000000) +#define CMA_MB_FLLOW_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000) #define CMA_MB_FLLOW_EXEC_SIZE 0x100000 -#define CMA_MB_FLLOW_RDWR_BASE (CFG_CMA_MB_BASE+0xe400000) +#define CMA_MB_FLLOW_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe400000) #define CMA_MB_FLLOW_RDWR_SIZE 0x400000 #endif #if (CMA_MB_CAPS & CMA_MB_CAP_RTC) -#define CMA_MB_RTC_BASE (CFG_CMA_MB_BASE+0xe800000) +#define CMA_MB_RTC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe800000) #define CMA_MB_RTC_SIZE 0x4000 #endif #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) -#define CMA_MB_SERPAR_BASE (CFG_CMA_MB_BASE+0xe900000) +#define CMA_MB_SERPAR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900000) #define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00) #define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40) #define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80) @@ -121,20 +121,20 @@ #endif #if (CMA_MB_CAPS & CMA_MB_CAP_KBM) -#define CMA_MB_PKBM_BASE (CFG_CMA_MB_BASE+0xe900100) +#define CMA_MB_PKBM_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900100) #define CMA_MB_PKBM_SIZE 0x10 #endif #if (CMA_MB_CAPS & CMA_MB_CAP_LCD) -#define CMA_MB_LCD_BASE (CFG_CMA_MB_BASE+0xeb00000) +#define CMA_MB_LCD_BASE (CONFIG_SYS_CMA_MB_BASE+0xeb00000) #define CMA_MB_LCD_SIZE 0x10 #endif -#define CMA_MB_DIPSW_BASE (CFG_CMA_MB_BASE+0xec00000) +#define CMA_MB_DIPSW_BASE (CONFIG_SYS_CMA_MB_BASE+0xec00000) #define CMA_MB_DIPSW_SIZE 0x10 #if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM)) -#define CMA_MB_SLOT1CFG_BASE (CFG_CMA_MB_BASE+0xf100000) +#define CMA_MB_SLOT1CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf100000) #if (CMA_MB_CAPS & CMA_MB_CAP_SER2) #define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80) #define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00) @@ -152,7 +152,7 @@ #endif #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2) -#define CMA_MB_SLOT2CFG_BASE (CFG_CMA_MB_BASE+0xf200000) +#define CMA_MB_SLOT2CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000) #if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2) #define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200) #endif @@ -160,7 +160,7 @@ #endif #if (CMA_MB_CAPS & CMA_MB_CAP_PCI) -#define CMA_MB_PCICTL_BASE (CFG_CMA_MB_BASE+0xf200000) +#define CMA_MB_PCICTL_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000) #define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100) #define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200) #define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300) @@ -171,19 +171,19 @@ #endif #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3) -#define CMA_MB_SLOT3CFG_BASE (CFG_CMA_MB_BASE+0xf300000) +#define CMA_MB_SLOT3CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf300000) #if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3) #define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200) #endif #define CMA_MB_SLOT3CFG_SIZE 0x400 #endif -#define CMA_MB_ROMHIGH_BASE (CFG_CMA_MB_BASE+0xf800000) +#define CMA_MB_ROMHIGH_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000) #define CMA_MB_ROMHIGH_SIZE 0x800000 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) -#define CMA_MB_FLHIGH_EXEC_BASE (CFG_CMA_MB_BASE+0xf800000) +#define CMA_MB_FLHIGH_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000) #define CMA_MB_FLHIGH_EXEC_SIZE 0x100000 -#define CMA_MB_FLHIGH_RDWR_BASE (CFG_CMA_MB_BASE+0xfc00000) +#define CMA_MB_FLHIGH_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xfc00000) #define CMA_MB_FLHIGH_RDWR_SIZE 0x400000 #endif diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 59d62e101..5fd9f79b7 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { *(.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.fixup) *(.got1) } @@ -122,6 +122,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index c33581d25..ea8538900 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c index f4e867ce7..1178822db 100644 --- a/board/cpc45/cpc45.c +++ b/board/cpc45/cpc45.c @@ -27,6 +27,7 @@ #include <asm/io.h> #include <pci.h> #include <i2c.h> +#include <netdev.h> int sysControlDisplay(int digit, uchar ascii_code); extern void Plx9030Init(void); @@ -71,7 +72,7 @@ phys_size_t initdram (int board_type) uint8_t mber = 0; unsigned int tmp; - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */ @@ -88,7 +89,7 @@ phys_size_t initdram (int board_type) CONFIG_READ_WORD(MCCR2, mccr2); mccr2 &= 0xffff0000; - start = CFG_SDRAM_BASE; + start = CONFIG_SYS_SDRAM_BASE; end = start + (1 << (col + row + 3) ) * bank - 1; for (i = 0; i < m; i++) { @@ -242,8 +243,8 @@ int sysControlDisplay (int digit, /* number of digit 0..7 */ #if defined(CONFIG_CMD_PCMCIA) -#ifdef CFG_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; +#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR +volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR; #endif int pcmcia_init(void) @@ -273,3 +274,8 @@ void ide_led (uchar led, uchar status) writeb(val, BCSR_BASE + 0x04); } # endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c index 37dd182ba..8fe758425 100644 --- a/board/cpc45/flash.c +++ b/board/cpc45/flash.c @@ -25,15 +25,15 @@ #include <mpc824x.h> #include <asm/processor.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -41,7 +41,7 @@ #define MAIN_SECT_SIZE 0x40000 #define PARAM_SECT_SIZE 0x8000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static int write_data (flash_info_t * info, ulong dest, ulong * data); static void write_via_fpu (vu_long * addr, ulong * data); @@ -81,8 +81,8 @@ unsigned long flash_init (void) __asm__ volatile ("sync\n eieio"); - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); addr[0] = 0x00900090; @@ -124,17 +124,17 @@ unsigned long flash_init (void) addr[0] = 0xFFFFFFFF; flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); for (j = 0; j < flash_info[i].sector_count; j++) { if (j > 30) { - flash_info[i].start[j] = CFG_FLASH_BASE + + flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + (MAIN_SECT_SIZE * 31) + (j - 31) * PARAM_SECT_SIZE; } else { - flash_info[i].start[j] = CFG_FLASH_BASE + + flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE; } @@ -162,27 +162,27 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]); #else flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); #else flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif #endif @@ -309,7 +309,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((addr[0] & 0x00800080) != 0x00800080) || ((addr[1] & 0x00800080) != 0x00800080)) { if ((now = get_timer (start)) > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); addr[0] = 0x00B000B0; /* suspend erase */ addr[0] = 0x00FF00FF; /* to read mode */ @@ -486,7 +486,7 @@ static int write_data (flash_info_t * info, ulong dest, ulong * data) while (((addr[0] & 0x00800080) != 0x00800080) || ((addr[1] & 0x00800080) != 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { addr[0] = 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c index d8f4be516..12c9c746c 100644 --- a/board/cpc45/pd67290.c +++ b/board/cpc45/pd67290.c @@ -699,16 +699,16 @@ int i82365_init (void) mem.map = 0; mem.flags = MAP_ATTRIB | MAP_ACTIVE; mem.speed = 300; - mem.sys_start = CFG_PCMCIA_MEM_ADDR; - mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1; + mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR; + mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1; mem.card_start = 0; i365_set_mem_map (&socket, &mem); mem.map = 1; mem.flags = MAP_ACTIVE; mem.speed = 300; - mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE; - mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1; + mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE; + mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1; mem.card_start = 0; i365_set_mem_map (&socket, &mem); @@ -794,8 +794,8 @@ static void i82365_dump_regions (pci_dev_t dev) { u_int tmp[2]; u_int *mem = (void *) socket.cb_phys; - u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR; - u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET); + u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR; + u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET); pci_read_config_dword (dev, 0x00, tmp + 0); pci_read_config_dword (dev, 0x80, tmp + 1); diff --git a/board/cpu86/config.mk b/board/cpu86/config.mk index 00354c46b..5fe0ca088 100644 --- a/board/cpu86/config.mk +++ b/board/cpu86/config.mk @@ -25,7 +25,7 @@ # CPU86 boards # -# This should be equal to the CFG_FLASH_BASE define in config_CPU86.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_CPU86.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c index 9e76c72d3..bc7ebfea1 100644 --- a/board/cpu86/cpu86.c +++ b/board/cpu86/cpu86.c @@ -225,7 +225,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = &memctl->memc_psdmr; @@ -250,7 +250,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -261,7 +261,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -275,37 +275,37 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong size8, size9; #endif long psize; psize = 32 * 1024 * 1024; - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL) "); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL) "); } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -313,9 +313,8 @@ phys_size_t initdram (int board_type) } #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h index cf7852cef..ca0c39f6b 100644 --- a/board/cpu86/cpu86.h +++ b/board/cpu86/cpu86.h @@ -6,19 +6,19 @@ #define REG8(x) (*(volatile unsigned char *)(x)) /* CPU86 register definitions */ -#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) -#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) -#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) -#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) -#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) -#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) -#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) -#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) -#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) -#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) -#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) +#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00) +#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01) +#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02) +#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03) +#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04) +#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05) +#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04) +#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07) +#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80) +#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81) +#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82) +#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83) +#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84) /* Board Control Register bits */ #define CPU86_BCR_FWPT 0x01 diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c index 1535a6b48..8135780c5 100644 --- a/board/cpu86/flash.c +++ b/board/cpu86/flash.c @@ -28,7 +28,7 @@ #include <mpc8xx.h> #include "cpu86.h" -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ @@ -177,7 +177,7 @@ unsigned long flash_init (void) /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -186,8 +186,8 @@ unsigned long flash_init (void) /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]); - size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]); + size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]); if (size_b0 > 0 || size_b1 > 0) { @@ -210,40 +210,40 @@ unsigned long flash_init (void) /* protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE if (size_b1) { - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE + /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE * but we shouldn't protect it. */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] ); } #else -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] ); #endif #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE +# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE if (size_b1) { flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); } # else flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); # endif #endif @@ -382,7 +382,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) last = start; addr = (vu_char *)(info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -434,7 +434,7 @@ AMD_DONE: last = start; while ((addr[0] & 0x00800080) != 0x00800080 || (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (erase suspended!)\n"); /* Suspend erase */ @@ -549,7 +549,7 @@ static int write_word (flash_info_t * info, volatile unsigned long *addr, start = get_timer (0); while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { /* Suspend program */ *addr = 0x00B000B0; @@ -604,7 +604,7 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/cpu87/config.mk b/board/cpu87/config.mk index 6384c7839..6a694a405 100644 --- a/board/cpu87/config.mk +++ b/board/cpu87/config.mk @@ -25,7 +25,7 @@ # CPU87 board # -# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in configs/cpu87.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c index f5a5de5d8..057a34c2c 100644 --- a/board/cpu87/cpu87.c +++ b/board/cpu87/cpu87.c @@ -26,6 +26,7 @@ #include <mpc8260.h> #include "cpu87.h" #include <pci.h> +#include <netdev.h> /* * I/O Port configuration table @@ -226,7 +227,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = &memctl->memc_psdmr; @@ -251,7 +252,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -262,7 +263,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -276,45 +277,45 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong size8, size9, size10; #endif long psize; psize = 32 * 1024 * 1024; - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); - size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL, - (uchar *) CFG_SDRAM_BASE); + size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); psize = max(size8,max(size9,size10)); if (psize == size8) { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL) "); } else if (psize == size9){ - psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:9COL) "); } else printf ("(60x:10COL) "); -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -322,10 +323,9 @@ phys_size_t initdram (int board_type) } #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif @@ -339,3 +339,8 @@ void pci_init_board(void) pci_mpc8250_init(&hose); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h index 5dbd4ae07..45cb853a2 100644 --- a/board/cpu87/cpu87.h +++ b/board/cpu87/cpu87.h @@ -6,19 +6,19 @@ #define REG8(x) (*(volatile unsigned char *)(x)) /* CPU86 register definitions */ -#define CPU86_VME_EAC REG8(CFG_BCRS_BASE + 0x00) -#define CPU86_VME_SAC REG8(CFG_BCRS_BASE + 0x01) -#define CPU86_VME_MAC REG8(CFG_BCRS_BASE + 0x02) -#define CPU86_BCR REG8(CFG_BCRS_BASE + 0x03) -#define CPU86_BSR REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_WDOG_RPORT REG8(CFG_BCRS_BASE + 0x05) -#define CPU86_MBOX_IRQ REG8(CFG_BCRS_BASE + 0x04) -#define CPU86_REV REG8(CFG_BCRS_BASE + 0x07) -#define CPU86_VME_IRQMASK REG8(CFG_BCRS_BASE + 0x80) -#define CPU86_VME_IRQSTATUS REG8(CFG_BCRS_BASE + 0x81) -#define CPU86_LOCAL_IRQMASK REG8(CFG_BCRS_BASE + 0x82) -#define CPU86_LOCAL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x83) -#define CPU86_PMCL_IRQSTATUS REG8(CFG_BCRS_BASE + 0x84) +#define CPU86_VME_EAC REG8(CONFIG_SYS_BCRS_BASE + 0x00) +#define CPU86_VME_SAC REG8(CONFIG_SYS_BCRS_BASE + 0x01) +#define CPU86_VME_MAC REG8(CONFIG_SYS_BCRS_BASE + 0x02) +#define CPU86_BCR REG8(CONFIG_SYS_BCRS_BASE + 0x03) +#define CPU86_BSR REG8(CONFIG_SYS_BCRS_BASE + 0x04) +#define CPU86_WDOG_RPORT REG8(CONFIG_SYS_BCRS_BASE + 0x05) +#define CPU86_MBOX_IRQ REG8(CONFIG_SYS_BCRS_BASE + 0x04) +#define CPU86_REV REG8(CONFIG_SYS_BCRS_BASE + 0x07) +#define CPU86_VME_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x80) +#define CPU86_VME_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x81) +#define CPU86_LOCAL_IRQMASK REG8(CONFIG_SYS_BCRS_BASE + 0x82) +#define CPU86_LOCAL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x83) +#define CPU86_PMCL_IRQSTATUS REG8(CONFIG_SYS_BCRS_BASE + 0x84) /* Board Control Register bits */ #define CPU86_BCR_FWPT 0x01 diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c index 076c2f919..c35757b30 100644 --- a/board/cpu87/flash.c +++ b/board/cpu87/flash.c @@ -28,7 +28,7 @@ #include <mpc8xx.h> #include "cpu87.h" -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ @@ -183,7 +183,7 @@ unsigned long flash_init (void) /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -192,8 +192,8 @@ unsigned long flash_init (void) /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]); - size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]); + size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); + size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]); if (size_b0 > 0 || size_b1 > 0) { @@ -216,40 +216,40 @@ unsigned long flash_init (void) /* protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE if (size_b1) { - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE + /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE * but we shouldn't protect it. */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1] ); } #else -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] ); #endif #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE +# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE if (size_b1) { flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); } # else flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); # endif #endif @@ -391,7 +391,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) last = start; addr = (vu_char *)(info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -443,7 +443,7 @@ AMD_DONE: last = start; while ((addr[0] & 0x00800080) != 0x00800080 || (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (erase suspended!)\n"); /* Suspend erase */ @@ -558,7 +558,7 @@ static int write_word (flash_info_t * info, volatile unsigned long *addr, start = get_timer (0); while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { /* Suspend program */ *addr = 0x00B000B0; @@ -613,7 +613,7 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/cradle/flash.c b/board/cradle/flash.c index f3f9a8cce..b5635fbc2 100644 --- a/board/cradle/flash.c +++ b/board/cradle/flash.c @@ -30,7 +30,7 @@ #define FLASH_BANK_SIZE 0x400000 #define MAIN_SECT_SIZE 0x20000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- @@ -41,15 +41,15 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F128J3 & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: flashbase = PHYS_FLASH_1; @@ -71,13 +71,13 @@ ulong flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -88,7 +88,7 @@ void flash_print_info (flash_info_t * info) { int i, j; - for (j = 0; j < CFG_MAX_FLASH_BANKS; j++) { + for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { switch (info->flash_id & FLASH_VENDMASK) { case (INTEL_MANUFACT & FLASH_VENDMASK): printf ("Intel: "); @@ -183,7 +183,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((*addr & 0x80) != 0x80) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ rc = ERR_TIMOUT; @@ -250,7 +250,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) /* wait while polling the status register */ while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0xB0; diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S index 2fd307f1d..6b5cfb922 100644 --- a/board/cradle/lowlevel_init.S +++ b/board/cradle/lowlevel_init.S @@ -24,7 +24,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -51,98 +51,98 @@ lowlevel_init: /* Set up GPIO pins first */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL + ldr r1, =CONFIG_SYS_GRER0_VAL str r1, [r0] ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL + ldr r1, =CONFIG_SYS_GRER1_VAL str r1, [r0] ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL + ldr r1, =CONFIG_SYS_GRER2_VAL str r1, [r0] ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL + ldr r1, =CONFIG_SYS_GFER0_VAL str r1, [r0] ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL + ldr r1, =CONFIG_SYS_GFER1_VAL str r1, [r0] ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL + ldr r1, =CONFIG_SYS_GFER2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] /* enable GPIO pins */ ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] SET_LED 1 ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */ - ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */ + ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */ str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */ ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */ @@ -181,47 +181,47 @@ mem_init: @ Step 2a @ write msc0, read back to ensure data latches @ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] @ write msc1 - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] @ write msc2 - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @ Step 2b @ write mecr - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] @ write mcmem0 - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] @ write mcmem1 - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] @ write mcatt0 - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] @ write mcatt1 - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] @ write mcio0 - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] @ write mcio1 - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] /*SET_LED 3 */ @@ -229,14 +229,14 @@ mem_init: @ Step 2c @ fly-by-dma is defeatured on this part @ write flycnfg - @ldr r2, =CFG_FLYCNFG_VAL + @ldr r2, =CONFIG_SYS_FLYCNFG_VAL @str r2, [r1, #FLYCNFG_OFFSET] /* FIXME Does this sequence really make sense */ #ifdef REDBOOT_WAY @ Step 2d @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL @ extract DRI field (we need a valid DRI field) @ @@ -319,7 +319,7 @@ mem_init: #else @ Step 2d @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL @ write back mdrefr @ @@ -363,7 +363,7 @@ mem_init: @ Step 4d @ fetch platform value of mdcnfg @ - ldr r2, =CFG_MDCNFG_VAL + ldr r2, =CONFIG_SYS_MDCNFG_VAL @ disable all sdram banks @ @@ -400,7 +400,7 @@ mem_init: @ Access memory *not yet enabled* for CBR refresh cycles (8) @ - CBR is generated for all banks - ldr r2, =CFG_DRAM_BASE + ldr r2, =CONFIG_SYS_DRAM_BASE str r2, [r2] str r2, [r2] str r2, [r2] @@ -430,7 +430,7 @@ mem_init: @ Step 4h @ write mdmrs @ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] @ Done Memory Init @@ -449,7 +449,7 @@ mem_init: @ Set interrupt mask register @ - ldr r1, =CFG_ICMR_VAL + ldr r1, =CONFIG_SYS_ICMR_VAL ldr r2, =ICMR str r1, [r2] @@ -465,7 +465,7 @@ mem_init: @ set core clocks @ - ldr r2, =CFG_CCCR_VAL + ldr r2, =CONFIG_SYS_CCCR_VAL ldr r1, =CCCR str r2, [r1] @@ -488,7 +488,7 @@ mem_init: @ Turn on needed clocks @ ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL + ldr r2, =CONFIG_SYS_CKEN_VAL str r2, [r1] /*SET_LED 7 */ diff --git a/board/cradle/u-boot.lds b/board/cradle/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/cradle/u-boot.lds +++ b/board/cradle/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index f0dfa07fd..1c82bdf12 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -139,7 +139,7 @@ int misc_init_r (void) struct rtc_time tm; char bootcmd[32]; - hdr = (image_header_t *) (CFG_MONITOR_BASE - image_get_header_size ()); + hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ()); #if defined(CONFIG_FIT) if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { puts ("Non legacy image format not supported\n"); @@ -181,9 +181,9 @@ int rtc_get (struct rtc_time *tmp) { return 0; } -void rtc_set (struct rtc_time *tmp) +int rtc_set (struct rtc_time *tmp) { - return; + return 0; } void rtc_reset (void) { @@ -205,13 +205,13 @@ static void init_sdram (void) /* To set the appropriate timings, we need to know the SDRAM speed. */ /* We can use the PLB speed since the SDRAM speed is the same as */ /* the PLB speed. The PLB speed is the FBK divider times the */ -/* 405GP reference clock, which on the L1 is 25Mhz. */ -/* Thus, if FBK div is 2, SDRAM is 50Mhz; if FBK div is 3, SDRAM is */ -/* 150Mhz; if FBK is 3, SDRAM is 150Mhz. */ +/* 405GP reference clock, which on the L1 is 25MHz. */ +/* Thus, if FBK div is 2, SDRAM is 50MHz; if FBK div is 3, SDRAM is */ +/* 150MHz; if FBK is 3, SDRAM is 150MHz. */ /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ -/* write SDRAM timing for 100Mhz. */ +/* write SDRAM timing for 100MHz. */ mtdcr (memcfga, mem_sdtr1); mtdcr (memcfgd, 0x0086400D); diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c index f3132740e..36d186fb9 100644 --- a/board/cray/L1/flash.c +++ b/board/cray/L1/flash.c @@ -43,7 +43,7 @@ #define FLASH_AM320B 0x0009 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -65,7 +65,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -79,7 +79,7 @@ unsigned long flash_init (void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) + if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { /* Setup offsets */ flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); @@ -253,7 +253,7 @@ int wait_for_DQ7(flash_info_t *info, int sect) start = get_timer (0); last = start; while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return -1; } @@ -457,7 +457,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds index a6bbef3dc..d278866d5 100644 --- a/board/cray/L1/u-boot.lds +++ b/board/cray/L1/u-boot.lds @@ -68,14 +68,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /*. = env_offset;*/ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -146,6 +146,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index 0552994f4..338392a07 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/csb226/flash.c b/board/csb226/flash.c index f6dfd9617..02ded1c45 100644 --- a/board/csb226/flash.c +++ b/board/csb226/flash.c @@ -37,7 +37,7 @@ #define FLASH_BANK_SIZE 0x02000000 #define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /** @@ -51,14 +51,14 @@ ulong flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F128J3 & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: @@ -76,13 +76,13 @@ ulong flash_init(void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; @@ -97,7 +97,7 @@ void flash_print_info (flash_info_t *info) { int i, j; - for (j=0; j<CFG_MAX_FLASH_BANKS; j++) { + for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) { switch (info->flash_id & FLASH_VENDMASK) { case (INTEL_MANUFACT & FLASH_VENDMASK): @@ -189,7 +189,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) *addr = 0x00D000D0; /* erase confirm */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B000B0; /* suspend erase*/ *addr = 0x00FF00FF; /* read mode */ rc = ERR_TIMOUT; @@ -251,7 +251,7 @@ static int write_long (flash_info_t *info, ulong dest, ulong data) /* wait while polling the status register */ while(((val = *addr) & 0x00800080) != 0x00800080) { - if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0x00B000B0; diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S index 4c9f10ffb..9892430a1 100644 --- a/board/csb226/lowlevel_init.S +++ b/board/csb226/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -54,71 +54,71 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ -/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ +/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */ /* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ /* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ /* */ @@ -168,17 +168,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -187,37 +187,37 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] @@ -239,7 +239,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 @@ -269,7 +269,7 @@ mem_init: /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] @@ -292,7 +292,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ @@ -325,7 +325,7 @@ mem_init: /* Jan 2003, Errata #116, page 30. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -345,7 +345,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] diff --git a/board/csb226/u-boot.lds b/board/csb226/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/csb226/u-boot.lds +++ b/board/csb226/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 5a585ae37..11596d2b7 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -51,9 +51,9 @@ uchar pll_fs6377_regs[16] = { */ int pll_init(void) { - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return i2c_write(CFG_I2C_PLL_ADDR, 0, 1, + return i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1, (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs)); } diff --git a/board/csb272/init.S b/board/csb272/init.S index e00ebf89c..ab371f20d 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -82,11 +82,11 @@ ext_bus_cntlr_init: mflr r3 /* get address of ..getAddr */ /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) + addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) mtctr r4 ..ebcloop: icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ + addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ bdnz ..ebcloop /* continue for $CTR cache lines */ /******************************************************************** diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds index 947fbd638..af871880a 100644 --- a/board/csb272/u-boot.lds +++ b/board/csb272/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) @@ -76,7 +76,7 @@ SECTIONS lib_ppc/board.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -147,6 +147,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/csb472/init.S b/board/csb472/init.S index aec42a14b..4b6958aef 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -82,11 +82,11 @@ ext_bus_cntlr_init: mflr r3 /* get address of ..getAddr */ /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) + addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) mtctr r4 ..ebcloop: icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ + addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ bdnz ..ebcloop /* continue for $CTR cache lines */ /******************************************************************** diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds index de3643eed..37363774c 100644 --- a/board/csb472/u-boot.lds +++ b/board/csb472/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) @@ -76,7 +76,7 @@ SECTIONS lib_ppc/board.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -147,6 +147,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/csb637/u-boot.lds b/board/csb637/u-boot.lds index 3b7977672..d0666ac73 100644 --- a/board/csb637/u-boot.lds +++ b/board/csb637/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c index ecf632894..720c56fc0 100644 --- a/board/cu824/cu824.c +++ b/board/cu824/cu824.c @@ -28,6 +28,7 @@ #include <mpc824x.h> #include <asm/processor.h> #include <pci.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,7 +53,7 @@ phys_size_t initdram(int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -91,3 +92,8 @@ void pci_init_board(void) { pci_mpc824x_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/cu824/flash.c b/board/cu824/flash.c index 7368176e5..bd0f8d326 100644 --- a/board/cu824/flash.c +++ b/board/cu824/flash.c @@ -25,15 +25,15 @@ #include <mpc824x.h> #include <asm/processor.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -43,7 +43,7 @@ #define BOARD_CTRL_REG 0xFE800013 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static int write_data (flash_info_t *info, ulong dest, ulong *data); static void write_via_fpu(vu_long *addr, ulong *data); @@ -75,8 +75,8 @@ unsigned long flash_init(void) *bcr |= 0x6; /* FWP0 = FWP1 = 1 */ DEBUGF("Write protect is: 0x%02X\n", *bcr); - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + vu_long *addr = (vu_long *)(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); addr[0] = 0x00900090; @@ -103,15 +103,15 @@ unsigned long flash_init(void) addr[0] = 0xFFFFFFFF; flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); for (j = 0; j < flash_info[i].sector_count; j++) { if (j <= 7) { - flash_info[i].start[j] = CFG_FLASH_BASE + + flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + j * PARAM_SECT_SIZE; } else { - flash_info[i].start[j] = CFG_FLASH_BASE + + flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + (j - 7)*MAIN_SECT_SIZE; } @@ -121,30 +121,30 @@ unsigned long flash_init(void) /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]); #else flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); #else flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif #endif @@ -268,7 +268,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while (((addr[0] & 0x00800080) != 0x00800080) || ((addr[1] & 0x00800080) != 0x00800080) ) { if ((now=get_timer(start)) > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); addr[0] = 0x00B000B0; /* suspend erase */ addr[0] = 0x00FF00FF; /* to read mode */ @@ -452,7 +452,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong *data) while (((addr[0] & 0x00800080) != 0x00800080) || ((addr[1] & 0x00800080) != 0x00800080) ) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { addr[0] = 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/dave/B2/flash.c b/board/dave/B2/flash.c index ad67e865b..bb892e670 100644 --- a/board/dave/B2/flash.c +++ b/board/dave/B2/flash.c @@ -41,19 +41,19 @@ static void flash_get_offsets (ulong base, flash_info_t * info); unsigned long flash_init (void) { #ifdef __DEBUG_START_FROM_SRAM__ - return CFG_DUMMY_FLASH_SIZE; + return CONFIG_SYS_DUMMY_FLASH_SIZE; #else unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", @@ -65,7 +65,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/dave/B2/u-boot.lds b/board/dave/B2/u-boot.lds index 8c10d47ae..a6fc6d777 100644 --- a/board/dave/B2/u-boot.lds +++ b/board/dave/B2/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index c9b288a41..a6aa6554b 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -38,8 +38,8 @@ int gunzip(void *, int, unsigned char *, unsigned long *); int board_early_init_f (void) { - out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */ - out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */ + out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */ + out32(GPIO0_OR, CONFIG_SYS_NAND1_CE); /* set initial outputs */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -85,10 +85,10 @@ int misc_init_r (void) { /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart = 0 - flash_info[0].size; - gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN; + gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN; #if 0 volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); volatile unsigned char *duart1_mcr = @@ -103,8 +103,8 @@ int misc_init_r (void) int i; unsigned long cntrl0Reg; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -168,7 +168,7 @@ int misc_init_r (void) /* * Enable power on PS/2 interface */ - *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET; /* * Enable interrupts in exar duart mcr[3] @@ -203,31 +203,6 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 /* test-only */ - for (;;) { - NAND_DISABLE_CE(1); - udelay(100); - NAND_ENABLE_CE(1); - udelay(100); - } -#endif -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - int testdram (void) { /* TODO: XXX XXX XXX */ diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c index 692d275a5..e5a0d3d17 100644 --- a/board/dave/PPChameleonEVB/flash.c +++ b/board/dave/PPChameleonEVB/flash.c @@ -42,7 +42,7 @@ static void flash_get_offsets (ulong base, flash_info_t * info); unsigned long flash_init (void) { #ifdef __DEBUG_START_FROM_SRAM__ - return CFG_DUMMY_FLASH_SIZE; + return CONFIG_SYS_DUMMY_FLASH_SIZE; #else unsigned long size; int i; @@ -54,7 +54,7 @@ unsigned long flash_init (void) debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info); /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -102,7 +102,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c index 3ccbf650d..14b61a4eb 100644 --- a/board/dave/PPChameleonEVB/nand.c +++ b/board/dave/PPChameleonEVB/nand.c @@ -67,11 +67,11 @@ static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo) /* use the base addr to find out which chip are we dealing with */ switch((ulong) this->IO_ADDR_W) { - case CFG_NAND0_BASE: - rb_gpio_pin = CFG_NAND0_RDY; + case CONFIG_SYS_NAND0_BASE: + rb_gpio_pin = CONFIG_SYS_NAND0_RDY; break; - case CFG_NAND1_BASE: - rb_gpio_pin = CFG_NAND1_RDY; + case CONFIG_SYS_NAND1_BASE: + rb_gpio_pin = CONFIG_SYS_NAND1_RDY; break; default: /* this should never happen */ return 0; diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 3037a049c..d3e6df9b3 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) @@ -141,13 +141,14 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); . = 0xFFFF8000; .ppcenv : { - common/environment.o(.ppcenv); + common/env_embedded.o(.ppcenv); } _end = . ; diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c index bf0f2bf28..b6af63b3b 100644 --- a/board/dave/common/flash.c +++ b/board/dave/common/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -162,7 +162,7 @@ void flash_print_info (flash_info_t *info) printf (" Sector Start Addresses:"); for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO /* * Check if whole sector is erased */ @@ -216,30 +216,30 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) { short i; short n; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong)addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - value = addr2[CFG_FLASH_READ0]; + value = addr2[CONFIG_SYS_FLASH_READ0]; switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; default: @@ -249,92 +249,92 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) return (0); /* no or unknown flash */ } - value = addr2[CFG_FLASH_READ1]; /* device ID */ + value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT: info->flash_id += FLASH_STMW320DT; info->sector_count = 67; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: info->flash_id += FLASH_AMDL322T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: info->flash_id += FLASH_AMDL322B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: info->flash_id += FLASH_AMDL323T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: info->flash_id += FLASH_AMDL323B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U: info->flash_id += FLASH_AM640U; info->sector_count = 128; info->size = 0x00800000; break; /* => 8 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A: info->flash_id += FLASH_SST800A; info->sector_count = 16; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A: info->flash_id += FLASH_SST160A; info->sector_count = 32; info->size = 0x00200000; @@ -432,19 +432,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) info->protect[i] = 0; else - info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; } /* * Prevent writes to uninitialized FLASH. */ if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ } return (info->size); @@ -456,8 +456,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; ulong start, now, last; int i; @@ -498,25 +498,25 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */ for (i=0; i<50; i++) udelay(1000); /* wait 1 ms */ } else { if (sect == s_first) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; } - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ } l_sect = sect; } @@ -537,9 +537,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) start = get_timer (0); last = start; - addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -552,8 +552,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) DONE: /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ printf (" done\n"); return 0; @@ -663,9 +663,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word (flash_info_t *info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; ulong start; int flag; int i; @@ -677,11 +677,11 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) + for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; dest2[i] = data2[i]; @@ -691,9 +691,9 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c index 5b5b5e9d2..30bc19626 100644 --- a/board/dave/common/fpga.c +++ b/board/dave/common/fpga.c @@ -36,12 +36,12 @@ #define MAX_ONES 226 -#ifdef CFG_FPGA_PRG -# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/ -# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ +#ifdef CONFIG_SYS_FPGA_PRG +# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/ +# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */ +# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */ +# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */ +# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */ #else # define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ # define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ @@ -74,7 +74,7 @@ static int fpga_boot (unsigned char *fpgadata, int size) int i, index, len; int count; -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 int j; #else unsigned char b; @@ -89,7 +89,7 @@ static int fpga_boot (unsigned char *fpgadata, int size) index += len + 3; } -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* search for preamble 0xFFFFFFFF */ while (1) { if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) @@ -167,7 +167,7 @@ static int fpga_boot (unsigned char *fpgadata, int size) DBG ("write configuration data into fpga\n"); /* write configuration-data into fpga... */ -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* * Load uncompressed image into fpga */ @@ -181,7 +181,7 @@ static int fpga_boot (unsigned char *fpgadata, int size) fpgadata[i] <<= 1; } } -#else /* ! CFG_FPGA_SPARTAN2 */ +#else /* ! CONFIG_SYS_FPGA_SPARTAN2 */ /* send 0xff 0x20 */ FPGA_WRITE_1; FPGA_WRITE_1; @@ -228,7 +228,7 @@ static int fpga_boot (unsigned char *fpgadata, int size) FPGA_WRITE_1; } } -#endif /* CFG_FPGA_SPARTAN2 */ +#endif /* CONFIG_SYS_FPGA_SPARTAN2 */ DBG ("%s, ", ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c index f8f180c6c..ec0d76125 100644 --- a/board/dave/common/pci.c +++ b/board/dave/common/pci.c @@ -119,24 +119,24 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d /* * Configure PLX PCI9054 */ - pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); + pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status); status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); + pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status); /* Check the latency timer for values >= 0x60. */ - pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); + pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); if (timer < 0x60) { - pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); + pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); } /* Set I/O base register. */ - pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); - pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); + pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE); + pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); + pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); if (pci9054_iobase == 0xffffffff) { @@ -149,13 +149,13 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d static struct pci_config_table pci9054_config_table[] = { #ifndef CONFIG_PCI_PNP { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), - pci_cfgfunc_config_device, { CFG_ETH_IOBASE, - CFG_ETH_IOBASE, + PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN), + pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE, + CONFIG_SYS_ETH_IOBASE, PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, #ifdef CONFIG_DASA_SIM { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), + PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN), pci_dasa_sim_config_pci9054 }, #endif #endif diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 71a3b87ac..be709bf81 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -39,7 +39,7 @@ int dram_init(void) static int dv_get_pllm_output(uint32_t pllm) { - return (pllm + 1) * (CFG_HZ_CLOCK / 1000000); + return (pllm + 1) * (CONFIG_SYS_HZ_CLOCK / 1000000); } void dv_display_clk_infos(void) @@ -54,9 +54,9 @@ void dv_display_clk_infos(void) */ int dvevm_read_mac_address(uint8_t *buf) { -#ifdef CFG_I2C_EEPROM_ADDR +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR /* Read MAC address. */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7F00, CFG_I2C_EEPROM_ADDR_LEN, + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) goto i2cerr; @@ -67,9 +67,9 @@ int dvevm_read_mac_address(uint8_t *buf) return 1; /* Found */ i2cerr: - printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); + printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR); err: -#endif /* CFG_I2C_EEPROM_ADDR */ +#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ return 0; } diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c index 00dc07c3f..d538d51f2 100644 --- a/board/davinci/common/psc.c +++ b/board/davinci/common/psc.c @@ -81,7 +81,7 @@ void lpsc_on(unsigned int id) } /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ -#if !defined(CFG_USE_DSPLINK) +#if !defined(CONFIG_SYS_USE_DSPLINK) void dsp_on(void) { int i; @@ -114,4 +114,4 @@ void dsp_on(void) REG(PSC_GBLCTL) &= ~0x1f; } -#endif /* CFG_USE_DSPLINK */ +#endif /* CONFIG_SYS_USE_DSPLINK */ diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index 151f8a900..abf60b35b 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -53,10 +53,10 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); -#if !defined(CFG_USE_DSPLINK) +#if !defined(CONFIG_SYS_USE_DSPLINK) /* Powerup the DSP */ dsp_on(); -#endif /* CFG_USE_DSPLINK */ +#endif /* CONFIG_SYS_USE_DSPLINK */ /* Bringup UART0 out of reset */ REG(UART0_PWREMU_MGMT) = 0x0000e003; diff --git a/board/davinci/dvevm/u-boot.lds b/board/davinci/dvevm/u-boot.lds index a4fcd1a9b..d86eb3621 100644 --- a/board/davinci/dvevm/u-boot.lds +++ b/board/davinci/dvevm/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c index 99fd32629..3504a2ec1 100644 --- a/board/davinci/schmoogie/schmoogie.c +++ b/board/davinci/schmoogie/schmoogie.c @@ -53,10 +53,10 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); -#if !defined(CFG_USE_DSPLINK) +#if !defined(CONFIG_SYS_USE_DSPLINK) /* Powerup the DSP */ dsp_on(); -#endif /* CFG_USE_DSPLINK */ +#endif /* CONFIG_SYS_USE_DSPLINK */ /* Bringup UART0 out of reset */ REG(UART0_PWREMU_MGMT) = 0x0000e003; @@ -125,13 +125,13 @@ int misc_init_r(void) dv_display_clk_infos(); /* Set serial number from UID chip */ - if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) { - printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) { + printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR); forceenv("serial#", "FAILED"); } else { if (buf[0] != 0x70) { /* Device Family Code */ - printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR); + printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR); forceenv("serial#", "FAILED"); } } @@ -141,7 +141,7 @@ int misc_init_r(void) tmp[0] = crc_tbl[tmp[0] ^ buf[i]]; if (tmp[0] != 0) { - printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR); + printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR); forceenv("serial#", "FAILED"); } else { /* CRC OK, set "serial" env variable */ diff --git a/board/davinci/schmoogie/u-boot.lds b/board/davinci/schmoogie/u-boot.lds index a4fcd1a9b..d86eb3621 100644 --- a/board/davinci/schmoogie/u-boot.lds +++ b/board/davinci/schmoogie/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index f47ba0f3b..9296d7b63 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -63,10 +63,10 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); -#if !defined(CFG_USE_DSPLINK) +#if !defined(CONFIG_SYS_USE_DSPLINK) /* Powerup the DSP */ dsp_on(); -#endif /* CFG_USE_DSPLINK */ +#endif /* CONFIG_SYS_USE_DSPLINK */ /* Bringup UART0 out of reset */ REG(UART0_PWREMU_MGMT) = 0x0000e003; @@ -99,35 +99,35 @@ static int sffsdr_read_mac_address(uint8_t *buf) u_int32_t value, mac[2], address; /* Read Integrity data structure checkword. */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET, - CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) goto err; if (value != INTEGRITY_CHECKWORD_VALUE) return 0; /* Read SYSCFG structure offset. */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, - CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) goto err; address = 0x800 + (int) value; /* Address of SYSCFG structure. */ /* Read NET CONFIG structure offset. */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, address, - CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) goto err; address = 0x800 + (int) value; /* Address of NET CONFIG structure. */ address += 12; /* Address of NET INTERFACE CONFIG structure. */ /* Read NET INTERFACE CONFIG 2 structure offset. */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, address, - CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4)) goto err; address = 0x800 + 16 + (int) value; /* Address of NET INTERFACE * CONFIG 2 structure. */ /* Read MAC address. */ - if (i2c_read(CFG_I2C_EEPROM_ADDR, address, - CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8)) + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8)) goto err; buf[0] = mac[0] >> 24; @@ -140,7 +140,7 @@ static int sffsdr_read_mac_address(uint8_t *buf) return 1; /* Found */ err: - printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR); + printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR); return 0; } @@ -156,10 +156,10 @@ int misc_init_r(void) dv_display_clk_infos(); /* Configure I2C switch (PCA9543) to enable channel 0. */ - i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0; - if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, - CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) { - printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); + i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0; + if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0, + CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) { + printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR); return 1; } @@ -170,9 +170,5 @@ int misc_init_r(void) if (!eth_hw_init()) printf("Ethernet init failed\n"); - /* On this platform, U-Boot is copied in RAM by the UBL, - * so we are always in the relocated state. */ - gd->flags |= GD_FLG_RELOC; - return(0); } diff --git a/board/davinci/sffsdr/u-boot.lds b/board/davinci/sffsdr/u-boot.lds index a4fcd1a9b..d86eb3621 100644 --- a/board/davinci/sffsdr/u-boot.lds +++ b/board/davinci/sffsdr/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c index a6fe82593..6de9356c7 100644 --- a/board/davinci/sonata/sonata.c +++ b/board/davinci/sonata/sonata.c @@ -52,10 +52,10 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); -#if !defined(CFG_USE_DSPLINK) +#if !defined(CONFIG_SYS_USE_DSPLINK) /* Powerup the DSP */ dsp_on(); -#endif /* CFG_USE_DSPLINK */ +#endif /* CONFIG_SYS_USE_DSPLINK */ /* Bringup UART0 out of reset */ REG(UART0_PWREMU_MGMT) = 0x0000e003; diff --git a/board/davinci/sonata/u-boot.lds b/board/davinci/sonata/u-boot.lds index a4fcd1a9b..d86eb3621 100644 --- a/board/davinci/sonata/u-boot.lds +++ b/board/davinci/sonata/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index 629dc317e..42756f5b8 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -106,19 +106,19 @@ int checkboard (void) /* We dont need theese unless we run whole pcmcia package */ write_one_tlb(20, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_IO_BASE, /* Hi */ + CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ 0x3C000017, /* Lo0 */ 0x3C200017); /* Lo1 */ write_one_tlb(21, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_ATTR_BASE, /* Hi */ + CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ 0x3D000017, /* Lo0 */ 0x3D200017); /* Lo1 */ #endif /* 0 */ write_one_tlb(22, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_MEM_ADDR, /* Hi */ + CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ 0x3E000017, /* Lo0 */ 0x3E200017); /* Lo1 */ #endif /* CONFIG_IDE_PCMCIA */ diff --git a/board/dbau1x00/flash.c b/board/dbau1x00/flash.c index 3cf29e844..a2fed1d71 100644 --- a/board/dbau1x00/flash.c +++ b/board/dbau1x00/flash.c @@ -23,7 +23,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * flash_init() diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 13e6bfcf3..842fb76e5 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -8,8 +8,8 @@ #define AU1500_SYS_ADDR 0xB1900000 #define sys_endian 0x0038 #define CP0_Config0 $16 -#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ -#define MEM_1MS ((CFG_MHZ) * 1000) +#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ +#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000) .text .set noreorder diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 1e1c5590d..da20de1ad 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -65,6 +65,6 @@ SECTIONS . = ALIGN(4); .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } uboot_end = .; } diff --git a/board/delta/delta.c b/board/delta/delta.c index 6e227748b..878416f73 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -304,8 +304,8 @@ static void init_DA9030() GPCR0 = (1<<17); /* drive GPIO17 low */ GPSR0 = (1<<17); /* drive GPIO17 high */ -#if CFG_DA9030_EXTON_DELAY - udelay((unsigned long) CFG_DA9030_EXTON_DELAY); /* wait for DA9030 */ +#if CONFIG_SYS_DA9030_EXTON_DELAY + udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */ #endif GPCR0 = (1<<17); /* drive GPIO17 low */ diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S index f059db505..eef631854 100644 --- a/board/delta/lowlevel_init.S +++ b/board/delta/lowlevel_init.S @@ -24,7 +24,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE .macro wait time ldr r2, =OSCR @@ -108,10 +108,10 @@ mem_init: orr r1, r1, #MDCNFG_DMCEN str r1, [r0] -#ifndef CFG_SKIP_DRAM_SCRUB +#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB /* scrub/init SDRAM if enabled/present */ - ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ - ldr r9, =CFG_DRAM_SIZE /* size of memory to scrub (CFG_DRAM_SIZE) */ + ldr r8, =CONFIG_SYS_DRAM_BASE /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */ + ldr r9, =CONFIG_SYS_DRAM_SIZE /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */ mov r0, #0 /* scrub with 0x0000:0000 */ mov r1, #0 mov r2, #0 @@ -125,7 +125,7 @@ mem_init: stmia r8!, {r0-r7} beq 15f b 10b -#endif /* CFG_SKIP_DRAM_SCRUB */ +#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */ 15: /* Mask all interrupts */ diff --git a/board/delta/nand.c b/board/delta/nand.c index 4ce78a1e1..aff7c54fc 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -28,26 +28,24 @@ #include <nand.h> #include <asm/arch/pxa-regs.h> -#ifdef CFG_DFC_DEBUG1 +#ifdef CONFIG_SYS_DFC_DEBUG1 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG1(fmt, args...) #endif -#ifdef CFG_DFC_DEBUG2 +#ifdef CONFIG_SYS_DFC_DEBUG2 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG2(fmt, args...) #endif -#ifdef CFG_DFC_DEBUG3 +#ifdef CONFIG_SYS_DFC_DEBUG3 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG3(fmt, args...) #endif -#define MIN(x, y) ((x < y) ? x : y) - /* These really don't belong here, as they are specific to the NAND Model */ static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; @@ -58,14 +56,12 @@ static struct nand_bbt_descr delta_bbt_descr = { .pattern = scan_ff_pattern }; -static struct nand_oobinfo delta_oob = { - .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ +static struct nand_ecclayout delta_oob = { .eccbytes = 6, .eccpos = {2, 3, 4, 5, 6, 7}, .oobfree = { {8, 2}, {12, 4} } }; - /* * not required for Monahans DFC */ @@ -208,7 +204,7 @@ static void wait_us(unsigned long us) static void dfc_clear_nddb(void) { NDCR &= ~NDCR_ND_RUN; - wait_us(CFG_NAND_OTHER_TO); + wait_us(CONFIG_SYS_NAND_OTHER_TO); } /* wait_event with timeout */ @@ -219,9 +215,9 @@ static unsigned long dfc_wait_event(unsigned long event) if(!event) return 0xff000000; else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) - timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; else - timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ; while(1) { ndsr = NDSR; @@ -244,7 +240,7 @@ static void dfc_new_cmd(void) int retry = 0; unsigned long status; - while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) { /* Clear NDSR */ NDSR = 0xFFF; @@ -435,8 +431,8 @@ int board_nand_init(struct nand_chip *nand) /* turn on the NAND Controller Clock (104 MHz @ D0) */ CKENA |= (CKENA_4_NAND | CKENA_9_SMC); -#undef CFG_TIMING_TIGHT -#ifndef CFG_TIMING_TIGHT +#undef CONFIG_SYS_TIMING_TIGHT +#ifndef CONFIG_SYS_TIMING_TIGHT tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), DFC_MAX_tCH); tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), @@ -475,7 +471,7 @@ int board_nand_init(struct nand_chip *nand) DFC_MAX_tWHR); tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), DFC_MAX_tAR); -#endif /* CFG_TIMING_TIGHT */ +#endif /* CONFIG_SYS_TIMING_TIGHT */ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); @@ -541,6 +537,7 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = dfc_hwcontrol; /* nand->dev_ready = dfc_device_ready; */ nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = &delta_oob; nand->options = NAND_BUSWIDTH_16; nand->waitfunc = dfc_wait; nand->read_byte = dfc_read_byte; @@ -549,7 +546,6 @@ int board_nand_init(struct nand_chip *nand) nand->write_buf = dfc_write_buf; nand->cmdfunc = dfc_cmdfunc; -/* nand->autooob = &delta_oob; */ nand->badblock_pattern = &delta_bbt_descr; return 0; } diff --git a/board/delta/u-boot.lds b/board/delta/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/delta/u-boot.lds +++ b/board/delta/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c index 60874ba9b..c81abc50f 100644 --- a/board/dnp1110/flash.c +++ b/board/dnp1110/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #undef FLASH_PORT_WIDTH32 @@ -65,7 +65,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { @@ -83,13 +83,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; @@ -194,10 +194,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW)0x00FF00FF; /* restore read mode */ @@ -267,7 +267,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW)0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW)0x00B000B0; /* suspend erase */ *addr = (FPW)0x00FF00FF; /* reset to read mode */ @@ -402,7 +402,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW)0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/dnp1110/u-boot.lds b/board/dnp1110/u-boot.lds index 6bd06270a..fce2533ce 100644 --- a/board/dnp1110/u-boot.lds +++ b/board/dnp1110/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c index 385b498d0..c17498f06 100644 --- a/board/eXalion/eXalion.c +++ b/board/eXalion/eXalion.c @@ -30,6 +30,8 @@ #include <asm/io.h> #include <pci.h> #include <ide.h> +#include <netdev.h> +#include <timestamp.h> #include "piix_pci.h" #include "eXalion.h" @@ -39,7 +41,7 @@ int checkboard (void) char buf[32]; printf ("Board: eXalion MPC824x - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", __DATE__, __TIME__); + printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); return 0; @@ -55,12 +57,12 @@ int checkflash (void) phys_size_t initdram (int board_type) { int i, cnt; - volatile uchar *base = CFG_SDRAM_BASE; + volatile uchar *base = CONFIG_SYS_SDRAM_BASE; volatile ulong *addr; ulong save[32]; ulong val, ret = 0; - for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0; + for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { addr = (volatile ulong *) base + cnt; save[i++] = *addr; @@ -76,7 +78,7 @@ phys_size_t initdram (int board_type) goto Done; } - for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) { + for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) { addr = (volatile ulong *) base + cnt; val = *addr; *addr = save[--i]; @@ -99,7 +101,7 @@ phys_size_t initdram (int board_type) } } - ret = CFG_MAX_RAM_SIZE; + ret = CONFIG_SYS_MAX_RAM_SIZE; Done: return ret; } @@ -290,3 +292,8 @@ void pci_init_board (void) { pci_mpc824x_init (&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c index d53ca4c13..8af680fe9 100644 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -18,6 +18,7 @@ * Place, Suite 330, Boston, MA 02111-1307 USA */ #include <common.h> +#include <netdev.h> #include <asm/io.h> #include <asm/sdram.h> @@ -88,8 +89,6 @@ int board_early_init_r(void) } #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - int board_eth_init(bd_t *bi) { return macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c index 2aa9415e8..5f73ff04d 100644 --- a/board/earthlcd/favr-32-ezkit/flash.c +++ b/board/earthlcd/favr-32-ezkit/flash.c @@ -53,17 +53,17 @@ unsigned long flash_init(void) unsigned long addr; unsigned int i; - flash_info[0].size = CFG_FLASH_SIZE; + flash_info[0].size = CONFIG_SYS_FLASH_SIZE; flash_info[0].sector_count = 135; - flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]); + flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]); for (i = 0, addr = 0; i < 8; i++, addr += 0x2000) flash_info[0].start[i] = addr; for (; i < flash_info[0].sector_count; i++, addr += 0x10000) flash_info[0].start[i] = addr; - return CFG_FLASH_SIZE; + return CONFIG_SYS_FLASH_SIZE; } void flash_print_info(flash_info_t *info) diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S index 2a9b33e12..a85fb8b89 100644 --- a/board/eltec/bab7xx/asm_init.S +++ b/board/eltec/bab7xx/asm_init.S @@ -125,7 +125,7 @@ board_asm_init: lis r2, 0xfee0 ori r2, r2, 0xcfc -#ifdef CFG_ADDRESS_MAP_A +#ifdef CONFIG_SYS_ADDRESS_MAP_A /* * Switch to address map A if necessary. */ @@ -835,17 +835,17 @@ toggleError2: /* * Get base addr of ISA I/O space */ - lis r6, CFG_ISA_IO@h - ori r6, r6, CFG_ISA_IO@l + lis r6, CONFIG_SYS_ISA_IO@h + ori r6, r6, CONFIG_SYS_ISA_IO@l /* * Set offset to base address for config registers. */ -#if defined(CFG_NS87308_BADDR_0x) +#if defined(CONFIG_SYS_NS87308_BADDR_0x) addi r4, r0, 0x0279 -#elif defined(CFG_NS87308_BADDR_10) +#elif defined(CONFIG_SYS_NS87308_BADDR_10) addi r4, r0, 0x015C -#elif defined(CFG_NS87308_BADDR_11) +#elif defined(CONFIG_SYS_NS87308_BADDR_11) addi r4, r0, 0x002E #endif add r6, r6, r4 /* add offset to base */ @@ -867,7 +867,7 @@ toggleError2: addi r5, r0, SIO_LUNENABLE bl .sio_bw - lis r8, CFG_ISA_IO@h + lis r8, CONFIG_SYS_ISA_IO@h ori r8, r8, 0x0460 li r9, 0x03 stb r9, 0(r8) /* select PMC2 register */ @@ -898,7 +898,7 @@ toggleError2: /* * Init COM1 for polled output */ - lis r8, CFG_ISA_IO@h + lis r8, CONFIG_SYS_ISA_IO@h ori r8, r8, 0x03f8 li r9, 0x00 stb r9, 1(r8) /* int disabled */ @@ -972,8 +972,8 @@ waitEmpty1: /* * Get base addr of ISA I/O space */ - lis r3, CFG_ISA_IO@h - ori r3, r3, CFG_ISA_IO@l + lis r3, CONFIG_SYS_ISA_IO@h + ori r3, r3, CONFIG_SYS_ISA_IO@l addi r3, r3, 0x015C /* adjust to superI/O 87308 base */ or r6, r3, r3 /* make a copy */ @@ -1076,7 +1076,7 @@ waitEmpty1: */ .globl Printf Printf: - lis r10, CFG_ISA_IO@h /* COM1 port */ + lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */ ori r10, r10, 0x03f8 WaitChr: @@ -1107,7 +1107,7 @@ OutHex4: OutHex: li r9, 28 /* shift reg for 8 digits */ OHstart: - lis r10, CFG_ISA_IO@h /* COM1 port */ + lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */ ori r10, r10, 0x03f8 OutDig: lbz r0, 5(r10) /* read link status */ @@ -1149,7 +1149,7 @@ OutDec: mullw r10, r0, r6 subf r7, r10, r3 - lis r10, CFG_ISA_IO@h /* COM1 port */ + lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */ ori r10, r10, 0x03f8 or. r7, r7, r7 @@ -1198,7 +1198,7 @@ OutDec6: */ .globl OutChr OutChr: - lis r10, CFG_ISA_IO@h /* COM1 port */ + lis r10, CONFIG_SYS_ISA_IO@h /* COM1 port */ ori r10, r10, 0x03f8 OutChr1: @@ -1216,7 +1216,7 @@ OutChr1: spdRead: mfspr r26, 8 /* save link register */ - lis r30, CFG_ISA_IO@h + lis r30, CONFIG_SYS_ISA_IO@h ori r30, r30, 0x220 /* GPIO Port 1 */ li r7, 0x00 li r8, 0x100 diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c index af5235237..1f78f8d16 100644 --- a/board/eltec/bab7xx/bab7xx.c +++ b/board/eltec/bab7xx/bab7xx.c @@ -30,6 +30,7 @@ #include <74xx_7xx.h> #include <ns87308.h> #include <video_fb.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,7 +44,7 @@ ulong bab7xx_get_bus_freq (void) * The GPIO Port 1 on BAB7xx reflects the bus speed. */ volatile struct GPIO *gpio = - (struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE); + (struct GPIO *) (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_GPIO_BASE); unsigned char data = gpio->dta1; @@ -86,7 +87,7 @@ int checkcpu (void) int checkboard (void) { -#ifdef CFG_ADDRESS_MAP_A +#ifdef CONFIG_SYS_ADDRESS_MAP_A puts ("Board: ELTEC BAB7xx PReP\n"); #else puts ("Board: ELTEC BAB7xx CHRP\n"); @@ -125,16 +126,16 @@ long int dram_size (int board_type) register unsigned long i, msar1, mear1, memSize; -#if defined(CFG_MEMTEST) +#if defined(CONFIG_SYS_MEMTEST) register unsigned long reg; printf ("Testing DRAM\n"); /* write each mem addr with it's address */ - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) + for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) *reg = reg; - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) { + for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) { if (*reg != reg) return -1; } @@ -244,3 +245,8 @@ void video_get_info_str (int line_number, char *info) #endif /*---------------------------------------------------------------------------*/ + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/eltec/bab7xx/flash.c b/board/eltec/bab7xx/flash.c index 442dd0051..21ae09892 100644 --- a/board/eltec/bab7xx/flash.c +++ b/board/eltec/bab7xx/flash.c @@ -34,7 +34,7 @@ #include <asm/processor.h> #include <asm/pci_io.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size (vu_long *addr, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); @@ -55,7 +55,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -96,8 +96,8 @@ unsigned long flash_init (void) if (size2 == 4*1024*1024) { (void)flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, &flash_info[1]); } @@ -370,7 +370,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -500,7 +500,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c index 1e7537745..787704f40 100644 --- a/board/eltec/bab7xx/l2cache.c +++ b/board/eltec/bab7xx/l2cache.c @@ -23,7 +23,7 @@ #include <common.h> -#if defined(CFG_L2_BAB7xx) +#if defined(CONFIG_SYS_L2_BAB7xx) #include <pci.h> #include <mpc106.h> @@ -77,7 +77,7 @@ int l2_cache_enable (int l2control) pci_write_config_dword (devbusfn, PCI_PICR2, reg32); /* cache size */ - if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04) + if (*(volatile unsigned char *) (CONFIG_SYS_ISA_IO + 0x220) & 0x04) { /* cache size is 512 KB */ picr2CacheSize = PICR2_L2_SIZE_512K; @@ -156,4 +156,4 @@ int l2_cache_enable (int l2control) /*----------------------------------------------------------------------------*/ -#endif /* (CFG_L2_BAB7xx) */ +#endif /* (CONFIG_SYS_L2_BAB7xx) */ diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c index 6a2480741..bc6eb4055 100644 --- a/board/eltec/bab7xx/misc.c +++ b/board/eltec/bab7xx/misc.c @@ -31,7 +31,7 @@ #include "srom.h" /* imports */ -extern char console_buffer[CFG_CBSIZE]; +extern char console_buffer[CONFIG_SYS_CBSIZE]; extern int l2_cache_enable (int l2control); extern void *nvram_read (void *dest, const short src, size_t count); extern void nvram_write (short dest, const void *src, size_t count); @@ -134,7 +134,7 @@ int misc_init_r (void) SECOND_DEVICE, FIRST_BLOCK); /* read out current nvram shadow image */ - nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE); + nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE); if (strcmp (eerev.magic, "ELTEC") != 0) { @@ -162,8 +162,8 @@ int misc_init_r (void) copyNv = 1; /* copy to nvram */ } - if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) != - el_srom_checksum((u_char*)buf, CFG_SROM_SIZE))) + if ((copyNv == 0) && (el_srom_checksum((u_char*)&eerev, CONFIG_SYS_SROM_SIZE) != + el_srom_checksum((u_char*)buf, CONFIG_SYS_SROM_SIZE))) { printf ("Invalid revision info copy in nvram !\n"); printf ("Press key:\n <c> to copy current revision info to nvram.\n"); @@ -304,13 +304,13 @@ int misc_init_r (void) printf("OK\n\n"); /* write new values as shadow image to nvram */ - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE); + nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE); } /*if (initSrom) */ /* copy current values as shadow image to nvram */ if (initSrom == 0 && copyNv == 1) - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE); + nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE); /* update environment */ sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", @@ -333,7 +333,7 @@ int misc_init_r (void) /* * L2 cache configuration */ -#if defined(CFG_L2_BAB7xx) +#if defined(CONFIG_SYS_L2_BAB7xx) ptr = getenv("l2cache"); if (*ptr == '0') { @@ -377,7 +377,7 @@ int misc_init_r (void) { if (pci_find_device(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C860, 0) > 0) { - /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 Mhz */ + /* BAB740 with SCSI=IRQ 11; SCC=IRQ 9; no IDE; NCR860 at 80 MHz */ scsi_dev_id = PCI_DEVICE_ID_NCR_53C860; scsi_max_scsi_id = 7; scsi_sym53c8xx_ccf = 0x15; diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c index edbd3ddf7..46e5a8bb1 100644 --- a/board/eltec/bab7xx/pci.c +++ b/board/eltec/bab7xx/pci.c @@ -43,41 +43,41 @@ void pci_init_board(void) hose->last_busno = 0xff; pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, /* * Attention: pci_hose_phys_to_bus() failes in address compare, - * so we need (CFG_PCI_MEMORY_SIZE-1) + * so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1) */ - CFG_PCI_MEMORY_SIZE-1, + CONFIG_SYS_PCI_MEMORY_SIZE-1, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI_MEM_BUS, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, + CONFIG_SYS_PCI_MEM_BUS, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); /* ISA/PCI memory space */ pci_set_region(hose->regions + 2, - CFG_ISA_MEM_BUS, - CFG_ISA_MEM_PHYS, - CFG_ISA_MEM_SIZE, + CONFIG_SYS_ISA_MEM_BUS, + CONFIG_SYS_ISA_MEM_PHYS, + CONFIG_SYS_ISA_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region(hose->regions + 3, - CFG_PCI_IO_BUS, - CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, + CONFIG_SYS_PCI_IO_BUS, + CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* ISA/PCI I/O space */ pci_set_region(hose->regions + 4, - CFG_ISA_IO_BUS, - CFG_ISA_IO_PHYS, - CFG_ISA_IO_SIZE, + CONFIG_SYS_ISA_IO_BUS, + CONFIG_SYS_ISA_IO_PHYS, + CONFIG_SYS_ISA_IO_SIZE, PCI_REGION_IO); hose->region_count = 5; diff --git a/board/eltec/bab7xx/srom.h b/board/eltec/bab7xx/srom.h index c18ab9164..504b742a6 100644 --- a/board/eltec/bab7xx/srom.h +++ b/board/eltec/bab7xx/srom.h @@ -40,8 +40,8 @@ #define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) /* bab7xx ELTEC srom */ -#define I2C_BUS_DAT (CFG_ISA_IO + 0x220) -#define I2C_BUS_DIR (CFG_ISA_IO + 0x221) +#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220) +#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221) /* srom at mpc107 */ #define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds index 1a95755ab..ff2d8b7fe 100644 --- a/board/eltec/bab7xx/u-boot.lds +++ b/board/eltec/bab7xx/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S index 1b8d399ed..8cbe9d88e 100644 --- a/board/eltec/elppc/asm_init.S +++ b/board/eltec/elppc/asm_init.S @@ -272,15 +272,15 @@ memStartWait: * set LEDs first time */ li r3, 0x1 - lis r30, CFG_USR_LED_BASE@h + lis r30, CONFIG_SYS_USR_LED_BASE@h stb r3, 2(r30) sync /* * init COM1 for polled output */ - lis r8, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r8, r8, CFG_NS16550_COM1@l + lis r8, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ + ori r8, r8, CONFIG_SYS_NS16550_COM1@l li r9, 0x00 stb r9, 1(r8) /* int disabled */ eieio @@ -290,10 +290,10 @@ memStartWait: li r9, 0x80 stb r9, 3(r8) /* link ctrl */ eieio - li r9, (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) + li r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) stb r9, 0(r8) /* baud rate (LSB)*/ eieio - li r9, ((CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8) + li r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8) stb r9, 1(r8) /* baud rate (MSB) */ eieio li r9, 0x07 @@ -589,7 +589,7 @@ memStartWait_1: * set LEDs end */ li r3, 0xf - lis r30, CFG_USR_LED_BASE@h + lis r30, CONFIG_SYS_USR_LED_BASE@h stb r3, 2(r30) sync @@ -602,8 +602,8 @@ memStartWait_1: */ Printf: - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l + lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CONFIG_SYS_NS16550_COM1@l WaitChr: lbz r0, 5(r10) /* read link status */ eieio @@ -622,8 +622,8 @@ WaitChr: * print a char to COM1 in polling mode (r10=COM1 port, r3=char) */ OutChr: - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l + lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CONFIG_SYS_NS16550_COM1@l OutChr1: lbz r0, 5(r10) /* read link status */ eieio @@ -645,8 +645,8 @@ OutHex4: OutHex: li r9, 28 /* shift reg for 8 digits */ OHstart: - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l + lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CONFIG_SYS_NS16550_COM1@l OutDig: lbz r0, 0(r29) /* slow down dummy read */ lbz r0, 5(r10) /* read link status */ @@ -685,8 +685,8 @@ OutDec: divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */ mullw r10, r0, r6 subf r7, r10, r3 - lis r10, CFG_NS16550_COM1@h /* COM1 base address*/ - ori r10, r10, CFG_NS16550_COM1@l + lis r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/ + ori r10, r10, CONFIG_SYS_NS16550_COM1@l or. r7, r7, r7 bne noblank1 li r3, 0x20 diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c index 1b70605e2..e73c712cb 100644 --- a/board/eltec/elppc/elppc.c +++ b/board/eltec/elppc/elppc.c @@ -25,6 +25,7 @@ #include <command.h> #include <mpc106.h> #include <video_fb.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -67,16 +68,16 @@ long int dram_size (int board_type) register unsigned long i, msar1, mear1, memSize; -#if defined(CFG_MEMTEST) +#if defined(CONFIG_SYS_MEMTEST) register unsigned long reg; printf ("Testing DRAM\n"); /* write each mem addr with it's address */ - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) + for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) *reg = reg; - for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) { + for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) { if (*reg != reg) return -1; } @@ -172,3 +173,8 @@ void video_get_info_str (int line_number, char *info) return; } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c index 442dd0051..21ae09892 100644 --- a/board/eltec/elppc/flash.c +++ b/board/eltec/elppc/flash.c @@ -34,7 +34,7 @@ #include <asm/processor.h> #include <asm/pci_io.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size (vu_long *addr, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); @@ -55,7 +55,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -96,8 +96,8 @@ unsigned long flash_init (void) if (size2 == 4*1024*1024) { (void)flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, &flash_info[1]); } @@ -370,7 +370,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (FLASH_WORD_SIZE *)(info->start[l_sect]); while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -500,7 +500,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c index 5fb20ae66..cbaf10b7e 100644 --- a/board/eltec/elppc/misc.c +++ b/board/eltec/elppc/misc.c @@ -29,7 +29,7 @@ #include "srom.h" /* imports */ -extern char console_buffer[CFG_CBSIZE]; +extern char console_buffer[CONFIG_SYS_CBSIZE]; extern int l2_cache_enable (int l2control); extern int eepro100_write_eeprom (struct eth_device *dev, int location, int addr_len, unsigned short data); @@ -42,7 +42,7 @@ extern int read_eeprom (struct eth_device *dev, int location, int addr_len); void *nvram_read (void *dest, const long src, size_t count) { uchar *d = (uchar *) dest; - uchar *s = (uchar *) (CFG_ENV_MAP_ADRS + src); + uchar *s = (uchar *) (CONFIG_ENV_MAP_ADRS + src); while (count--) *d++ = *s++; @@ -52,7 +52,7 @@ void *nvram_read (void *dest, const long src, size_t count) void nvram_write (long dest, const void *src, size_t count) { - uchar *d = (uchar *) (CFG_ENV_MAP_ADRS + dest); + uchar *d = (uchar *) (CONFIG_ENV_MAP_ADRS + dest); uchar *s = (uchar *) src; while (count--) @@ -95,7 +95,7 @@ int misc_init_r (void) SECOND_DEVICE, FIRST_BLOCK); /* read out current nvram shadow image */ - nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE); + nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE); if (strcmp (eerev.magic, "ELTEC") != 0) { /* srom is not initialized -> create a default revision info */ @@ -124,8 +124,8 @@ int misc_init_r (void) } if ((copyNv == 0) - && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) != - el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) { + && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) != + el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) { printf ("Invalid revision info copy in nvram !\n"); printf ("Press key:\n <c> to copy current revision info to nvram.\n"); printf (" <r> to reenter revision info.\n"); @@ -232,16 +232,16 @@ int misc_init_r (void) printf ("OK\n\n"); /* write new values as shadow image to nvram */ - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev, - CFG_SROM_SIZE); + nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev, + CONFIG_SYS_SROM_SIZE); } /*if (initSrom) */ /* copy current values as shadow image to nvram */ if (initSrom == 0 && copyNv == 1) - nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev, - CFG_SROM_SIZE); + nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev, + CONFIG_SYS_SROM_SIZE); /* update environment */ sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x", diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c index 5b115ea61..bf133b77d 100644 --- a/board/eltec/elppc/pci.c +++ b/board/eltec/elppc/pci.c @@ -42,37 +42,37 @@ void pci_init_board(void) hose->last_busno = 0xff; pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI_MEM_BUS, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, + CONFIG_SYS_PCI_MEM_BUS, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); /* ISA/PCI memory space */ pci_set_region(hose->regions + 2, - CFG_ISA_MEM_BUS, - CFG_ISA_MEM_PHYS, - CFG_ISA_MEM_SIZE, + CONFIG_SYS_ISA_MEM_BUS, + CONFIG_SYS_ISA_MEM_PHYS, + CONFIG_SYS_ISA_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region(hose->regions + 3, - CFG_PCI_IO_BUS, - CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, + CONFIG_SYS_PCI_IO_BUS, + CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* ISA/PCI I/O space */ pci_set_region(hose->regions + 4, - CFG_ISA_IO_BUS, - CFG_ISA_IO_PHYS, - CFG_ISA_IO_SIZE, + CONFIG_SYS_ISA_IO_BUS, + CONFIG_SYS_ISA_IO_PHYS, + CONFIG_SYS_ISA_IO_SIZE, PCI_REGION_IO); hose->region_count = 5; diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h index c18ab9164..504b742a6 100644 --- a/board/eltec/elppc/srom.h +++ b/board/eltec/elppc/srom.h @@ -40,8 +40,8 @@ #define SROM_SHORT(pX) (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8) /* bab7xx ELTEC srom */ -#define I2C_BUS_DAT (CFG_ISA_IO + 0x220) -#define I2C_BUS_DIR (CFG_ISA_IO + 0x221) +#define I2C_BUS_DAT (CONFIG_SYS_ISA_IO + 0x220) +#define I2C_BUS_DIR (CONFIG_SYS_ISA_IO + 0x221) /* srom at mpc107 */ #define MPC107_I2CADDR (mpc107_eumb_addr + 0x3000) /* address */ diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds index 1a95755ab..ff2d8b7fe 100644 --- a/board/eltec/elppc/u-boot.lds +++ b/board/eltec/elppc/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c index 4cc66a973..2fbdb2771 100644 --- a/board/eltec/mhpc/flash.c +++ b/board/eltec/mhpc/flash.c @@ -25,7 +25,7 @@ #include <mpc8xx.h> #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Protection Flags: @@ -62,13 +62,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -81,18 +81,18 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, &flash_info[0]); flash_info[0].size = size_b0; @@ -203,10 +203,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW)0xFF00FF00; /* restore read mode */ @@ -277,7 +277,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW)0xB000B000; /* suspend erase */ *addr = (FPW)0xFF00FF00; /* reset to read mode */ @@ -419,7 +419,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) start = get_timer (0); while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW)0xFF00FF00; /* restore read mode */ return (1); } diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c index 3666791e9..7cca6b28c 100644 --- a/board/eltec/mhpc/mhpc.c +++ b/board/eltec/mhpc/mhpc.c @@ -36,7 +36,7 @@ #include <video_fb.h> /* imports from common/main.c */ -extern char console_buffer[CFG_CBSIZE]; +extern char console_buffer[CONFIG_SYS_CBSIZE]; extern void eeprom_init (void); extern int eeprom_read (unsigned dev_addr, unsigned offset, @@ -105,7 +105,7 @@ static const unsigned int sdram_table[] = { int board_early_init_f (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(im->im_cpm); volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport); @@ -160,7 +160,7 @@ int misc_init_r (void) int i; /* check revision data */ - eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); + eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) { printf ("Enter revision number (0-9): %c ", @@ -228,7 +228,7 @@ int misc_init_r (void) } /* setup new revision data */ - eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, + eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32); } @@ -253,13 +253,13 @@ int misc_init_r (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */ memctl->memc_mptpr = MPTPR_PTP_DIV64; memctl->memc_mar = 0x00008800; @@ -267,15 +267,15 @@ phys_size_t initdram (int board_type) /* * Map controller SDRAM bank 0 */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; udelay (200); /* * Map controller SDRAM bank 1 */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + memctl->memc_or2 = CONFIG_SYS_OR2; + memctl->memc_br2 = CONFIG_SYS_BR2; /* * Perform SDRAM initializsation sequence @@ -419,7 +419,7 @@ void *video_hw_init (void) { unsigned int clut = 0; unsigned char *penv; - immap_t *immr = (immap_t *) CFG_IMMR; + immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* enable video only on CLUT value */ if ((penv = (uchar *)getenv ("clut")) != NULL) @@ -470,7 +470,7 @@ void video_set_lut (unsigned int index, unsigned char r, unsigned char g, unsigned char b) { unsigned int lum; - unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00); + unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00); /* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */ /* y = 0.299*R + 0.587*G + 0.114*B */ diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index 85117aa56..759b41290 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -124,6 +124,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index 85072feda..dbec9860a 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c index d6161bf35..330978b95 100644 --- a/board/emk/common/flash.c +++ b/board/emk/common/flash.c @@ -26,7 +26,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #if defined (CONFIG_TOP860) typedef unsigned short FLASH_PORT_WIDTH; @@ -95,7 +95,7 @@ unsigned long flash_init (void) int i = 0; extern void flash_preinit(void); extern void flash_afterinit(uint, ulong, ulong); - ulong flashbase = CFG_FLASH_BASE; + ulong flashbase = CONFIG_SYS_FLASH_BASE; flash_preinit(); @@ -105,20 +105,20 @@ unsigned long flash_init (void) flash_get_size((FPW *)flashbase, &flash_info[i]); size += flash_info[i].size; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif @@ -147,14 +147,14 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->size && info->start[0] <= base && base <= info->start[0] + info->size - 1) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -459,7 +459,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -473,14 +473,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ putc ('.'); last = get_timer(0); } } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = get_timer(0); } @@ -581,7 +581,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00F000F0; /* reset bank */ res = 1; } diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c index 8a3a12b04..c2af21952 100644 --- a/board/emk/common/vpd.c +++ b/board/emk/common/vpd.c @@ -36,8 +36,8 @@ void read_factory_r (void) uint len; /* get length first */ - addr = CFG_FACT_OFFSET; - if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) { + addr = CONFIG_SYS_FACT_OFFSET; + if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) { bailout: printf ("cannot read factory configuration\n"); printf ("be sure to set ethaddr yourself!\n"); @@ -47,14 +47,14 @@ void read_factory_r (void) addr += 2; /* sanity check */ - if (length < 20 || length > CFG_FACT_SIZE - 2) + if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2) goto bailout; /* read lines */ while (length > 0) { /* read one line */ len = length > 80 ? 80 : length; - if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len)) + if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len)) goto bailout; /* mark end of buffer */ buf[len] = 0; diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c index 27886261c..7efbcb089 100644 --- a/board/emk/top5200/top5200.c +++ b/board/emk/top5200/top5200.c @@ -35,7 +35,7 @@ phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT #if 0 ulong t; ulong tap_del; @@ -46,33 +46,33 @@ phys_size_t initdram (int board_type) #define SOFT_REF 4 /* configure SDRAM start/end */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE; + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE; *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2; + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2; /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN; + *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN; /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; -#ifdef CFG_DRAM_DDR + *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; +#ifdef CONFIG_SYS_DRAM_DDR /* set extended mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE; + *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE; #endif /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400; + *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400; /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE; + *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE; /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF; + *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF; /* set mode register */ - *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE; + *(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE; /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL; + *(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL; /* write default TAP delay */ - *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24; + *(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24; #if 0 for (tap_del = 0; tap_del < 32; tap_del++) @@ -97,7 +97,7 @@ phys_size_t initdram (int board_type) } } #endif -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20); diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c index aca4991f5..76f7a0c5f 100644 --- a/board/emk/top860/top860.c +++ b/board/emk/top860/top860.c @@ -78,7 +78,7 @@ int checkboard (void) *****************************************************************************/ phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* @@ -93,8 +93,8 @@ phys_size_t initdram (int board_type) sizeof (edo_60ns_25MHz_tbl) / sizeof (uint)); memctl->memc_mptpr = 0x0200; memctl->memc_mamr = 0x0ca20330; - memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM; - memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V; + memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM; + memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V; /* * Do 8 read accesses to DRAM */ @@ -112,7 +112,7 @@ phys_size_t initdram (int board_type) addr2[1] = 0x47110815; if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) { /* only 4MB populated */ - memctl->memc_or2 = -(CFG_DRAM_MAX / 4) | OR_CSNT_SAM; + memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM; } } diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index 97ef89a40..da23fff14 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -124,6 +124,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug index 5d97095c1..82e8dce83 100644 --- a/board/emk/top860/u-boot.lds.debug +++ b/board/emk/top860/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c index 272a9e5cc..0c2b3aedc 100644 --- a/board/ep7312/flash.c +++ b/board/ep7312/flash.c @@ -27,7 +27,7 @@ #define FLASH_BANK_SIZE 0x1000000 #define MAIN_SECT_SIZE 0x20000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- @@ -38,15 +38,15 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F128J3 & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -60,13 +60,13 @@ ulong flash_init (void) /* Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -165,7 +165,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr = 0xD0; /* erase confirm */ while ((*addr & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0xB0; /* suspend erase */ *addr = 0xFF; /* reset to read mode */ rc = ERR_TIMOUT; @@ -232,7 +232,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) /* wait while polling the status register */ while (((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0xB0; diff --git a/board/ep7312/u-boot.lds b/board/ep7312/u-boot.lds index 4a89cebaa..a79bb8cb8 100644 --- a/board/ep7312/u-boot.lds +++ b/board/ep7312/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c index 4cfb2acc8..bc20ba739 100644 --- a/board/ep8248/ep8248.c +++ b/board/ep8248/ep8248.c @@ -35,31 +35,31 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) const iop_conf_t iop_conf_tab[4][32] = { /* Port A */ { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ @@ -78,20 +78,20 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ @@ -123,11 +123,11 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ - /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ + /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */ + /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ - /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ + /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */ + /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ @@ -187,7 +187,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int board_early_init_f (void) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; bcsr[4] |= 0x30; /* Turn the LEDs off */ @@ -198,39 +198,39 @@ int board_early_init_f (void) bcsr[7] |= 0x10; #endif -#if CFG_FCC1 +#if CONFIG_SYS_FCC1 bcsr[8] |= 0xC0; -#endif /* CFG_FCC1 */ -#if CFG_FCC2 +#endif /* CONFIG_SYS_FCC1 */ +#if CONFIG_SYS_FCC2 bcsr[8] |= 0x30; -#endif /* CFG_FCC2 */ +#endif /* CONFIG_SYS_FCC2 */ return 0; } phys_size_t initdram(int board_type) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; long int msize = 16L << (bcsr[2] & 3); -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; + vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE; uchar c = 0xFF; - uint psdmr = CFG_PSDMR; + uint psdmr = CONFIG_SYS_PSDMR; int i; immap->im_siu_conf.sc_ppc_acr = 0x02; immap->im_siu_conf.sc_ppc_alrh = 0x30126745; immap->im_siu_conf.sc_tescr1 = 0x00004000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_SDRAM_OR; - memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ @@ -240,7 +240,7 @@ phys_size_t initdram(int board_type) *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ *ramaddr = c; -#endif /* !CFG_RAMBOOT */ +#endif /* !CONFIG_SYS_RAMBOOT */ /* Return total 60x bus SDRAM size */ return msize * 1024 * 1024; @@ -248,7 +248,7 @@ phys_size_t initdram(int board_type) int checkboard(void) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; puts("Board: "); switch (bcsr[0]) { diff --git a/board/ep8260/config.mk b/board/ep8260/config.mk index eaf1560e6..1225830be 100644 --- a/board/ep8260/config.mk +++ b/board/ep8260/config.mk @@ -25,7 +25,7 @@ # EP8260 boards # -# This should be equal to the CFG_FLASH_BASE define in config_ep8260.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_ep8260.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c index 0e43c6df9..90ab047f7 100644 --- a/board/ep8260/ep8260.c +++ b/board/ep8260/ep8260.c @@ -190,12 +190,12 @@ const iop_conf_t iop_conf_tab[4][32] = { */ int board_early_init_f (void) { - volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - memctl->memc_br4 = CFG_BR4_PRELIM; - memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */ regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */ return 0; @@ -203,7 +203,7 @@ int board_early_init_f (void) void reset_phy (void) { - volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; + volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; regs->bcsr4 = 0xC0; } @@ -216,7 +216,7 @@ void reset_phy (void) int checkboard (void) { - volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE; + volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE; uint major = 0, minor = 0; switch (regs->bcsr0) { @@ -245,18 +245,18 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110; + volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110; /* - ulong psdmr = CFG_PSDMR; -#ifdef CFG_LSDRAM - ulong lsdmr = CFG_LSDMR; + ulong psdmr = CONFIG_SYS_PSDMR; +#ifdef CONFIG_SYS_LSDRAM + ulong lsdmr = CONFIG_SYS_LSDMR; #endif */ - long size = CFG_SDRAM0_SIZE; + long size = CONFIG_SYS_SDRAM0_SIZE; int i; @@ -277,44 +277,44 @@ phys_size_t initdram (int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we -* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. +* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA; + memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA; *ramaddr = c; - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR; + memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW; + memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW; *ramaddr = c; - memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN; + memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; -#ifndef CFG_RAMBOOT -#ifdef CFG_LSDRAM - size += CFG_SDRAM1_SIZE; - ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c; - memctl->memc_lsrt = CFG_LSRT; +#ifndef CONFIG_SYS_RAMBOOT +#ifdef CONFIG_SYS_LSDRAM + size += CONFIG_SYS_SDRAM1_SIZE; + ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c; + memctl->memc_lsrt = CONFIG_SYS_LSRT; - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA; + memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA; *ramaddr = c; - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR; + memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW; + memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW; *ramaddr = c; - memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN; + memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; -#endif /* CFG_LSDRAM */ -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_LSDRAM */ +#endif /* CONFIG_SYS_RAMBOOT */ return (size * 1024 * 1024); } diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c index 966a34526..2a81de570 100644 --- a/board/ep8260/flash.c +++ b/board/ep8260/flash.c @@ -35,7 +35,7 @@ #define V_BYTE(a) (*(volatile unsigned char *)( a )) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- @@ -134,13 +134,13 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0>>20); @@ -150,20 +150,20 @@ unsigned long flash_init (void) * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -284,7 +284,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 || (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -403,7 +403,7 @@ static int write_dword (flash_info_t *info, ulong dest, unsigned char * pdata) start = get_timer (0); while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) || ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c index 813f020ee..c7aa2755f 100644 --- a/board/ep8260/mii_phy.c +++ b/board/ep8260/mii_phy.c @@ -54,7 +54,7 @@ mii_phy_read(unsigned short reg) { int i; unsigned short tmp, val = 0, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE; + t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE; tmp = 0x6002 | (adr << 7) | (reg << 2); regs->bcsr4 = 0xC3; @@ -83,7 +83,7 @@ mii_phy_write(unsigned short reg, unsigned short val) { int i; unsigned short tmp, adr = 0; - t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE; + t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE; tmp = 0x5002 | (adr << 7) | (reg << 2); regs->bcsr4 = 0xC3; diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c index 03baf0b59..c1d6e9100 100644 --- a/board/ep82xxm/ep82xxm.c +++ b/board/ep82xxm/ep82xxm.c @@ -39,8 +39,8 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ -#define CFG_FCC2 1 -#define CFG_FCC3 1 +#define CONFIG_SYS_FCC2 1 +#define CONFIG_SYS_FCC3 1 const iop_conf_t iop_conf_tab[4][32] = { @@ -82,34 +82,34 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */ - /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ @@ -122,7 +122,7 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */ + /* PC27 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ @@ -130,10 +130,10 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */ - /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */ - /* PC17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */ - /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */ + /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */ + /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */ + /* PC17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */ + /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */ /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */ @@ -198,7 +198,7 @@ typedef struct pci_ic_s { int board_early_init_f (void) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; bcsr[4] |= 0x30; /* Turn the LEDs off */ @@ -209,12 +209,12 @@ int board_early_init_f (void) bcsr[7] |= 0x10; #endif -#if CFG_FCC3 +#if CONFIG_SYS_FCC3 bcsr[8] |= 0xC0; -#endif /* CFG_FCC3 */ -#if CFG_FCC2 +#endif /* CONFIG_SYS_FCC3 */ +#if CONFIG_SYS_FCC2 bcsr[8] |= 0x30; -#endif /* CFG_FCC2 */ +#endif /* CONFIG_SYS_FCC2 */ return 0; } @@ -224,23 +224,23 @@ phys_size_t initdram(int board_type) /* Size in MB of SDRAM populated on board*/ long int msize = 256; -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - uint psdmr = CFG_PSDMR; + uint psdmr = CONFIG_SYS_PSDMR; int i; unsigned char ramtmp; unsigned char *ramptr1 = (unsigned char *)0x00000110; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; udelay(400); /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_SDRAM_OR; - memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; memctl->memc_psdmr = psdmr; udelay(400); @@ -255,7 +255,7 @@ udelay(400); memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */ *ramptr1 = 0xFF; memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ -#endif /* !CFG_RAMBOOT */ +#endif /* !CONFIG_SYS_RAMBOOT */ /* Return total 60x bus SDRAM size */ return msize * 1024 * 1024; @@ -263,7 +263,7 @@ udelay(400); int checkboard(void) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; puts("Board: "); switch (bcsr[0]) { diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c index 92e5f0c12..7e9500737 100644 --- a/board/ep88x/ep88x.c +++ b/board/ep88x/ep88x.c @@ -63,7 +63,7 @@ static uint sdram_table[] = { int board_early_init_f (void) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; bcsr[0] |= 0x0C; /* Turn the LEDs off */ bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for @@ -89,7 +89,7 @@ int board_early_init_f (void) phys_size_t initdram (int board_type) { long int msize; - volatile immap_t *immap = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); @@ -97,7 +97,7 @@ phys_size_t initdram (int board_type) /* Configure SDRAM refresh */ memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */ - memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */ + memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */ udelay(100); /* Run MRS pattern from location 0x36 */ @@ -106,10 +106,10 @@ phys_size_t initdram (int board_type) udelay(100); memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ - memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; - memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; + memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; - msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); memctl->memc_or1 |= ~(msize - 1); return msize; @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) int checkboard( void ) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; puts("Board: "); switch (bcsr[15]) { diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index 354514233..1b6e417be 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -115,6 +115,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/eric/eric.c b/board/eric/eric.c index 972d485b5..600b9d7a7 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -142,7 +142,7 @@ phys_size_t initdram (int board_type) * so let init.S do the init job for SDRAM * and simply return 32MByte here */ - return (CFG_SDRAM_SIZE * 1024 * 1024); + return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024); #else /* Read Serial Presence Detect Information */ diff --git a/board/eric/flash.c b/board/eric/flash.c index 2c7d2a08c..7e57513ae 100644 --- a/board/eric/flash.c +++ b/board/eric/flash.c @@ -25,10 +25,10 @@ #include <ppc4xx.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#ifdef CFG_FLASH_16BIT +#ifdef CONFIG_SYS_FLASH_16BIT #define FLASH_WORD_SIZE unsigned short #define FLASH_ID_MASK 0xFFFF #else @@ -42,7 +42,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* stolen from esteem192e/flash.c */ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT static int write_word (flash_info_t *info, ulong dest, ulong data); #else static int write_short (flash_info_t *info, ulong dest, ushort data); @@ -61,7 +61,7 @@ unsigned long flash_init (void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -75,7 +75,7 @@ unsigned long flash_init (void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) + if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { /* Setup offsets */ flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); @@ -88,8 +88,8 @@ unsigned long flash_init (void) &flash_info[0]); #else (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif size_b1 = 0 ; @@ -137,8 +137,8 @@ unsigned long flash_init (void) &flash_info[0]); #else (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif @@ -187,7 +187,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info) } else if (info->flash_id & FLASH_BTYPE) { if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; @@ -241,7 +241,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info) i = info->sector_count - 1; if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00008000; info->start[i--] = base + info->size - 0x0000C000; @@ -403,7 +403,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT /* * Note: if it is an AMD flash and the word at addr[0000] @@ -654,7 +654,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); if(info->flash_id < FLASH_AMD_COMP) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT addr[0x0555] = 0x00AA00AA; addr[0x02AA] = 0x00550055; addr[0x0555] = 0x00800080; @@ -695,7 +695,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != (0x00800080&FLASH_ID_MASK) ) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -716,7 +716,7 @@ DONE: for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ barf = 0; -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT addr = (vu_long*)(info->start[sect]); addr[0] = 0x00200020; addr[0] = 0x00D000D0; @@ -767,7 +767,7 @@ DONE: flash_info_t *info; int i; - for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) { + for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) { if ((addr >= info->start[0]) && (addr < (info->start[0] + info->size)) ) { return (info); @@ -844,7 +844,7 @@ DONE: int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT ulong cp, wp, data; int l; #else @@ -853,7 +853,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) #endif int i, rc; -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT wp = (addr & ~3); /* get lower word aligned address */ @@ -980,7 +980,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) (info->start[0]); @@ -1018,7 +1018,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -1026,7 +1026,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) } else { while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } @@ -1093,7 +1093,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) if (info->flash_id < FLASH_AMD_COMP) { /* AMD stuff */ while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -1101,7 +1101,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) } else { /* intel stuff */ while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } @@ -1120,7 +1120,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) *addr = 0x00B0; *addr = 0x0070; while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } *addr = 0x00FF; diff --git a/board/eric/init.S b/board/eric/init.S index 9d4e7ff48..2304cc7bb 100644 --- a/board/eric/init.S +++ b/board/eric/init.S @@ -219,7 +219,7 @@ sdram_init: mflr r31 -#ifdef CFG_SDRAM_MANUALLY +#ifdef CONFIG_SYS_SDRAM_MANUALLY /*------------------------------------------------------------------- */ /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */ /*------------------------------------------------------------------- */ diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds index 00e35a6b8..bf46e1842 100644 --- a/board/eric/u-boot.lds +++ b/board/eric/u-boot.lds @@ -68,14 +68,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -146,6 +146,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c index 0f655b78a..63aaf2c7a 100644 --- a/board/esd/adciop/adciop.c +++ b/board/esd/adciop/adciop.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <netdev.h> #include "adciop.h" /* ------------------------------------------------------------------------- */ @@ -95,3 +96,8 @@ int testdram (void) } /* ------------------------------------------------------------------------- */ + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c index d9eccba1e..dd578c893 100644 --- a/board/esd/adciop/flash.c +++ b/board/esd/adciop/flash.c @@ -45,7 +45,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds index db65fe69b..e91816373 100644 --- a/board/esd/adciop/u-boot.lds +++ b/board/esd/adciop/u-boot.lds @@ -132,6 +132,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 83657c8d5..ac9bbb3f4 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -41,7 +41,7 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); extern ulong flash_get_size (ulong base, int banknum); -int flash_banks = CFG_MAX_FLASH_BANKS_DETECT; +int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -140,7 +140,7 @@ int board_early_init_f (void) * First pull fpga-prg pin low, to disable fpga logic */ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ - out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ out_be32((void*)GPIO0_OR, 0); /* pull prg low */ /* @@ -178,8 +178,8 @@ int board_early_init_f (void) mtebc(pb1cr, 0); /* resize CS0 to 32MB */ - mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8); - mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8); + mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8); + mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8); } return 0; @@ -200,8 +200,8 @@ int board_early_init_r(void) int misc_init_r(void) { - u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); + u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); + u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2); u8 *duart0_mcr = (u8 *)(DUART0_BA + 4); u8 *duart1_mcr = (u8 *)(DUART1_BA + 4); unsigned char *dst; @@ -222,8 +222,8 @@ int misc_init_r(void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00300000); - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf("GUNZIP ERROR - must RESET board to recover\n"); do_reset(NULL, 0, 0, NULL); } @@ -297,11 +297,11 @@ int misc_init_r(void) /* * Enable power on PS/2 interface (with reset) */ - out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET); + out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET); for (i=0;i<100;i++) udelay(1000); udelay(1000); - out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET); + out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET); /* * Enable interrupts in exar duart mcr[3] @@ -315,15 +315,15 @@ int misc_init_r(void) str = getenv("splashimage"); if (str) { logo_addr = (uchar *)simple_strtoul(str, NULL, 16); - logo_size = CFG_VIDEO_LOGO_MAX_SIZE; + logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; } else { logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); } if (gd->board_type >= 6) { - result = lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13505_640_480_16bpp, sizeof(regs_13505_640_480_16bpp) / sizeof(regs_13505_640_480_16bpp[0]), @@ -332,16 +332,16 @@ int misc_init_r(void) /* retry with internal image */ logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13505_640_480_16bpp, sizeof(regs_13505_640_480_16bpp) / sizeof(regs_13505_640_480_16bpp[0]), logo_addr, logo_size); } } else { - result = lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp) / sizeof(regs_13806_640_480_16bpp[0]), @@ -350,8 +350,8 @@ int misc_init_r(void) /* retry with internal image */ logo_addr = logo_bmp; logo_size = sizeof(logo_bmp); - lcd_init((uchar *)CFG_LCD_BIG_REG, - (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, + (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp) / sizeof(regs_13806_640_480_16bpp[0]), @@ -389,12 +389,12 @@ int misc_init_r(void) * fix environment for field updated units */ if (getenv("altbootcmd") == NULL) { - setenv("usb_load", CFG_USB_LOAD_COMMAND); - setenv("usbargs", CFG_USB_ARGS); + setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND); + setenv("usbargs", CONFIG_SYS_USB_ARGS); setenv("bootcmd", CONFIG_BOOTCOMMAND); - setenv("usb_self", CFG_USB_SELF_COMMAND); - setenv("bootlimit", CFG_BOOTLIMIT); - setenv("altbootcmd", CFG_ALT_BOOTCOMMAND); + setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND); + setenv("bootlimit", CONFIG_SYS_BOOTLIMIT); + setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND); saveenv(); } @@ -423,30 +423,20 @@ int checkboard (void) return 0; } -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { - u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); /* * Assert or deassert CompactFlash Reset Pin */ if (on) { out_be16(fpga_mode, - in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET); + in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET); } else { out_be16(fpga_mode, - in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET); + in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET); } } #endif /* CONFIG_IDE_RESET */ @@ -459,7 +449,7 @@ void reset_phy(void) lxt971_no_sleep(); } -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) int usb_board_init(void) { return 0; @@ -490,4 +480,4 @@ int usb_board_init_fail(void) usb_board_stop(); return 0; } -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds index 21547ac27..9697cc6b3 100644 --- a/board/esd/apc405/u-boot.lds +++ b/board/esd/apc405/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/ar405/flash.c +++ b/board/esd/ar405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds index b072bbb3e..2c1cf9206 100644 --- a/board/esd/ar405/u-boot.lds +++ b/board/esd/ar405/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) @@ -79,14 +79,13 @@ SECTIONS common/cmd_mem.o (.text) common/cmd_nvedit.o (.text) common/console.o (.text) - common/lists.o (.text) common/main.o (.text) /* . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) */ - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -157,6 +156,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 25360a656..dd1e2ec2e 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -82,15 +82,6 @@ int board_early_init_f (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); @@ -103,8 +94,8 @@ int misc_init_r (void) int index; int i; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -166,9 +157,9 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); udelay(10); /* wait 10us */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); udelay(1000); /* wait 1ms */ /* @@ -205,20 +196,6 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/ash405/flash.c +++ b/board/esd/ash405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds index 644174a46..e2e2512e7 100644 --- a/board/esd/ash405/u-boot.lds +++ b/board/esd/ash405/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -142,6 +142,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c index de847f9be..56c822ec9 100644 --- a/board/esd/canbt/flash.c +++ b/board/esd/canbt/flash.c @@ -47,7 +47,7 @@ unsigned long flash_init (void) unsigned long base_b0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds index e66db5d23..74280e61d 100644 --- a/board/esd/canbt/u-boot.lds +++ b/board/esd/canbt/u-boot.lds @@ -78,12 +78,11 @@ SECTIONS common/cmd_mem.o (.text) common/cmd_nvedit.o (.text) common/console.o (.text) - common/lists.o (.text) common/main.o (.text) net/net.o (.text) /* . = env_offset; - common/environment.o (.text) + common/env_embedded.o (.text) */ *(.text) @@ -155,6 +154,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index ba27c030b..5709d4504 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -69,23 +69,14 @@ int board_early_init_f (void) /* * Reset CPLD via GPIO12 (CS3) pin */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET); udelay(1000); /* wait 1ms */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET); udelay(1000); /* wait 1ms */ return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { /* adjust flash start and offset */ @@ -95,7 +86,7 @@ int misc_init_r (void) /* * Setup and enable EEPROM write protection */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); return (0); } @@ -110,8 +101,8 @@ int checkboard (void) char str[64]; int flashcnt; int delay; - volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000); - volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001); + volatile unsigned char *led_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1000); + volatile unsigned char *ver_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1001); puts ("Board: "); @@ -141,19 +132,7 @@ int checkboard (void) /* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state * 0: disable write @@ -164,23 +143,23 @@ phys_size_t initdram (int board_type) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -194,21 +173,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -221,7 +200,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ /* ------------------------------------------------------------------------- */ diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/cms700/flash.c +++ b/board/esd/cms700/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds index 21547ac27..9697cc6b3 100644 --- a/board/esd/cms700/u-boot.lds +++ b/board/esd/cms700/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index a1e0ce5a2..633f64178 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -72,7 +72,7 @@ extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); #endif -extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; +extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE]; int au_check_cksum_valid(int i, long nbytes) { @@ -335,7 +335,7 @@ static void process_macros (const char *input, char *output) char c, prev; const char *varname_start = NULL; int inputcnt = strlen (input); - int outputcnt = CFG_CBSIZE; + int outputcnt = CONFIG_SYS_CBSIZE; int state = 0; /* 0 = waiting for '$' */ /* 1 = waiting for '(' or '{' */ /* 2 = waiting for ')' or '}' */ @@ -394,7 +394,7 @@ static void process_macros (const char *input, char *output) case 2: /* Waiting for ) */ if (c == ')' || c == '}') { int i; - char envname[CFG_CBSIZE], *envval; + char envname[CONFIG_SYS_CBSIZE], *envval; /* Varname # of chars */ int envcnt = input - varname_start - 1; diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index d88b3876d..ad490c349 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2008 * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,9 @@ #include <common.h> #include <command.h> +#if !defined(CONFIG_440) +#include <asm/4xx_pci.h> +#endif #if defined(CONFIG_CMD_BSP) @@ -36,18 +39,24 @@ extern int do_autoscript (cmd_tbl_t *, int, int, char *[]); */ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - unsigned int *ptr = 0; + u32 *ptr = 0; int count = 0; int count2 = 0; char addr[16]; char str[] = "\\|/-"; char *local_args[2]; + u32 la, ptm1la; +#if defined(CONFIG_440) + ptm1la = in32r(PCIX0_PTM1LA); +#else + ptm1la = in32r(PTM1LA); +#endif while(1) { /* * Mark sync address */ - ptr = 0; + ptr = (u32 *)ptm1la; memset(ptr, 0, 0x20); *ptr = 0xffffffff; @@ -74,7 +83,8 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf("\nGot bootcode %08x: ", *ptr); - sprintf(addr, "%08x", *ptr & ADDRMASK); + la = ptm1la + (*ptr & ADDRMASK); + sprintf(addr, "%08x", la); switch (*ptr & ~ADDRMASK) { case 0: @@ -83,8 +93,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ printf("booting image at addr 0x%s ...\n", addr); setenv("loadaddr", addr); - - do_bootm (cmdtp, 0, 0, NULL); + do_bootm(cmdtp, 0, 0, NULL); break; case 1: @@ -92,7 +101,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Boot image via autoscr */ printf("executing script at addr 0x%s ...\n", addr); - local_args[0] = addr; local_args[1] = NULL; do_autoscript(cmdtp, 0, 1, local_args); @@ -103,7 +111,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * Call run_cmd */ printf("running command at addr 0x%s ...\n", addr); - run_command ((char*)(*ptr & ADDRMASK), 0); + run_command((char*)la, 0); break; default: diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c index 40d1efb08..736176f5d 100644 --- a/board/esd/common/esd405ep_nand.c +++ b/board/esd/common/esd405ep_nand.c @@ -35,17 +35,17 @@ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int struct nand_chip *this = mtd->priv; if (ctrl & NAND_CTRL_CHANGE) { if ( ctrl & NAND_CLE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE); if ( ctrl & NAND_ALE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE); else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE); if ( ctrl & NAND_NCE ) - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE); else - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); } if (cmd != NAND_CMD_NONE) @@ -58,7 +58,7 @@ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int */ static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo) { - if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY) + if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY) return 1; return 0; } @@ -69,8 +69,8 @@ int board_nand_init(struct nand_chip *nand) /* * Set NAND-FLASH GPIO signals to defaults */ - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE); /* * Initialize nand_chip structure diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c index bda361ead..3ea053b8c 100644 --- a/board/esd/common/flash.c +++ b/board/esd/common/flash.c @@ -27,7 +27,7 @@ #endif #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -167,7 +167,7 @@ void flash_print_info (flash_info_t *info) printf (" Sector Start Addresses:"); for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO /* * Check if whole sector is erased */ @@ -221,28 +221,28 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) { short i; short n; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong)addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - value = addr2[CFG_FLASH_READ0]; + value = addr2[CONFIG_SYS_FLASH_READ0]; switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; default: @@ -252,104 +252,104 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) return (0); /* no or unknown flash */ } - value = addr2[CFG_FLASH_READ1]; /* device ID */ + value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: info->flash_id += FLASH_AMDL322T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: info->flash_id += FLASH_AMDL322B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: info->flash_id += FLASH_AMDL323T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: info->flash_id += FLASH_AMDL323B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U: info->flash_id += FLASH_AM640U; info->sector_count = 128; info->size = 0x00800000; break; /* => 8 MB */ #if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM)) - case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A: info->flash_id += FLASH_SST800A; info->sector_count = 16; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602: info->flash_id += FLASH_SST160A; info->sector_count = 32; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202: info->flash_id += FLASH_SST320; info->sector_count = 64; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401: - case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402: info->flash_id += FLASH_SST640; info->sector_count = 128; info->size = 0x00800000; @@ -424,19 +424,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) info->protect[i] = 0; else - info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; } /* * Prevent writes to uninitialized FLASH. */ if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ } return (info->size); @@ -448,8 +448,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) int flash_erase (flash_info_t *info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; ulong start, now, last; int i; @@ -490,25 +490,25 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */ for (i=0; i<50; i++) udelay(1000); /* wait 1 ms */ } else { if (sect == s_first) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; } - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ } l_sect = sect; } @@ -529,9 +529,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) start = get_timer (0); last = start; - addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -544,8 +544,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) DONE: /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ printf (" done\n"); return 0; @@ -630,9 +630,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word (flash_info_t *info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; ulong start; int flag; int i; @@ -645,11 +645,11 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) + for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; dest2[i] = data2[i]; @@ -659,9 +659,9 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c index 9e2be7eaf..5232dddc9 100644 --- a/board/esd/common/fpga.c +++ b/board/esd/common/fpga.c @@ -36,12 +36,12 @@ #define MAX_ONES 226 -#ifdef CFG_FPGA_PRG -# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output) */ -# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */ -# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */ -# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */ -# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */ +#ifdef CONFIG_SYS_FPGA_PRG +# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */ +# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */ +# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */ +# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */ +# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */ #else # define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ # define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ @@ -98,7 +98,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size) int count; unsigned char b; -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 int j; #else int bit; @@ -112,7 +112,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size) index += len + 3; } -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* search for preamble 0xFFFFFFFF */ while (1) { if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) @@ -186,7 +186,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size) DBG ("write configuration data into fpga\n"); /* write configuration-data into fpga... */ -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* * Load uncompressed image into fpga */ diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index c23dc81a2..1eea59ecb 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -37,7 +37,7 @@ int lcd_depth; unsigned char *glob_lcd_reg; unsigned char *glob_lcd_mem; -#if defined(CFG_LCD_ENDIAN) +#if defined(CONFIG_SYS_LCD_ENDIAN) void lcd_setup(int lcd, int config) { if (lcd == 0) { @@ -47,21 +47,21 @@ void lcd_setup(int lcd, int config) /* set reset to low */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST); udelay(10); /* wait 10us */ if (config == 1) { /* big-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); } else { /* little-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); } udelay(10); /* wait 10us */ /* set reset to high */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST); } else { /* * Set endianess and reset lcd controller 1 (big) @@ -69,29 +69,29 @@ void lcd_setup(int lcd, int config) /* set reset to low */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST); udelay(10); /* wait 10us */ if (config == 1) { /* big-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); } else { /* little-endian */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN); } udelay(10); /* wait 10us */ /* set reset to high */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST); } /* - * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive + * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN); } -#endif /* CFG_LCD_ENDIAN */ +#endif /* CONFIG_SYS_LCD_ENDIAN */ int lcd_bmp(uchar *logo_bmp) @@ -116,20 +116,20 @@ int lcd_bmp(uchar *logo_bmp) /* * Decompress bmp image */ - len = CFG_VIDEO_LOGO_MAX_SIZE; - dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); + len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { printf("Error: malloc for gunzip failed!\n"); return 1; } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, + if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) { free(dst); return 1; } - if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) { printf("Image could be truncated" - " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); + " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); } /* diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c index f711205ef..dcb764cd1 100644 --- a/board/esd/common/pci.c +++ b/board/esd/common/pci.c @@ -119,24 +119,24 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d /* * Configure PLX PCI9054 */ - pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status); + pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status); status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY; - pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status); + pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status); /* Check the latency timer for values >= 0x60. */ - pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); + pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer); if (timer < 0x60) { - pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); + pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60); } /* Set I/O base register. */ - pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE); - pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); + pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE); + pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase); - pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); + pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK); if (pci9054_iobase == 0xffffffff) { @@ -149,13 +149,13 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d static struct pci_config_table pci9054_config_table[] = { #ifndef CONFIG_PCI_PNP { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN), - pci_cfgfunc_config_device, { CFG_ETH_IOBASE, - CFG_ETH_IOBASE, + PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN), + pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE, + CONFIG_SYS_ETH_IOBASE, PCI_COMMAND_IO | PCI_COMMAND_MASTER }}, #ifdef CONFIG_DASA_SIM { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN), + PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN), pci_dasa_sim_config_pci9054 }, #endif #endif diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h index 0e389907f..b702fdd9a 100644 --- a/board/esd/common/xilinx_jtag/ports.h +++ b/board/esd/common/xilinx_jtag/ports.h @@ -38,12 +38,12 @@ #define TDI (short) 2 /* - * Use CFG_FPGA_xxx defines from board include file. + * Use CONFIG_SYS_FPGA_xxx defines from board include file. */ -#define JTAG_TMS CFG_FPGA_PRG /* output */ -#define JTAG_TCK CFG_FPGA_CLK /* output */ -#define JTAG_TDI CFG_FPGA_DATA /* output */ -#define JTAG_TDO CFG_FPGA_DONE /* input */ +#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */ +#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */ +#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */ +#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */ /* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */ void setPort(short p, short val); diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index 54de0b806..dcab9060b 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -36,12 +36,12 @@ int board_early_init_f (void) * Setup GPIO pins */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5)); + mtdcr(cntrl0, cntrl0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); /* set output pins to high */ - out32(GPIO0_OR, CFG_EEPROM_WP); + out32(GPIO0_OR, CONFIG_SYS_EEPROM_WP); /* setup for output (LED=off) */ - out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED); + out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED); /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -67,13 +67,6 @@ int board_early_init_f (void) return 0; } - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { unsigned long cntrl0Reg; @@ -115,21 +108,7 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state * 0: disable write @@ -139,23 +118,23 @@ phys_size_t initdram (int board_type) * 0/1: current state if <state> was -1. */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -163,7 +142,7 @@ int eeprom_write_enable (unsigned dev_addr, int state) { } #endif -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int query = argc == 1; @@ -171,21 +150,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -200,4 +179,4 @@ U_BOOT_CMD( "eepwren - Enable / disable / query EEPROM write access\n", NULL ); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c index de847f9be..56c822ec9 100644 --- a/board/esd/cpci2dp/flash.c +++ b/board/esd/cpci2dp/flash.c @@ -47,7 +47,7 @@ unsigned long flash_init (void) unsigned long base_b0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds index 21547ac27..9697cc6b3 100644 --- a/board/esd/cpci2dp/u-boot.lds +++ b/board/esd/cpci2dp/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index 0be45c70d..1bdf5e4fc 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -21,20 +21,4 @@ # MA 02111-1307 USA # -# -# esd CPCI405 boards -# - -ifeq ($(BOARD_REVISION),CPCI4052) -TEXT_BASE = 0xFFFC0000 -else -ifeq ($(BOARD_REVISION),CPCI405DT) -TEXT_BASE = 0xFFFC0000 -else -ifeq ($(BOARD_REVISION),CPCI405AB) TEXT_BASE = 0xFFFC0000 -else -TEXT_BASE = 0xFFFD0000 -endif -endif -endif diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index b856705ff..c5ccb348a 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -110,8 +110,8 @@ int board_early_init_f (void) * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) */ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ + out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ + out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ out32(GPIO0_OR, 0); /* pull prg low */ /* @@ -255,11 +255,6 @@ int cpci405_version(void) } } -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - int misc_init_r (void) { unsigned long cntrl0Reg; @@ -287,8 +282,8 @@ int misc_init_r (void) cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x00300000); - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -352,13 +347,13 @@ int misc_init_r (void) #ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { - volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; - volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; + volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; + volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR; /* * Enable outputs in fpga on version 3 board */ - *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT; + *fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT; /* * Set outputs to 0 @@ -368,9 +363,9 @@ int misc_init_r (void) /* * Reset external DUART */ - *fpga_mode |= CFG_FPGA_MODE_DUART_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET; udelay(100); - *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET); } #endif } @@ -450,9 +445,9 @@ int checkboard (void) #if 0 /* test-only */ if (ver >= 2) { - volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1; + volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1; - if (*fpga_status & CFG_FPGA_STATUS_FLASH) { + if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) { puts ("FLASH Bank B, "); } else { puts ("FLASH Bank A, "); @@ -493,18 +488,6 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP @@ -516,22 +499,20 @@ void reset_phy(void) #endif } -/* ------------------------------------------------------------------------- */ - #ifdef CONFIG_CPCI405_VER2 #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { - volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; + volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR; /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_MODE_CF_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET; } } @@ -574,12 +555,12 @@ int pci_pre_init(struct pci_controller *hose) #ifdef CONFIG_CPCI405AB -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ - |= CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ - &= ~CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ - & CFG_FPGA_MODE_1WIRE) +#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ + |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR) +#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \ + &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR) +#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \ + & CONFIG_SYS_FPGA_MODE_1WIRE) /* * Generate a 1-wire reset, return 1 if no presence detect was found, @@ -709,8 +690,8 @@ U_BOOT_CMD( NULL ); -#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ -#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ +#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ /* * Write backplane ip-address... @@ -724,11 +705,11 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *ptr; IPaddr_t ipaddr; - buf = malloc(CFG_ENV_SIZE_2); - if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) { + buf = malloc(CONFIG_ENV_SIZE_2); + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { puts("\nError reading backplane EEPROM!\n"); } else { - crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4); + crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); if (crc != *(ulong *)buf) { printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf); return -1; @@ -783,14 +764,14 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf("Setting bp_ip to %s\n", argv[1]); - buf = malloc(CFG_ENV_SIZE_2); - memset(buf, 0, CFG_ENV_SIZE_2); + buf = malloc(CONFIG_ENV_SIZE_2); + memset(buf, 0, CONFIG_ENV_SIZE_2); sprintf(str, "bp_ip=%s", argv[1]); strcpy(buf+4, str); - crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4); + crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4); *(ulong *)buf = crc; - if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) { + if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) { puts("\nError writing backplane EEPROM!\n"); } diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index e766895bb..d535924f8 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -66,7 +66,7 @@ unsigned long flash_init (void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds index 21547ac27..5d5976167 100644 --- a/board/esd/cpci405/u-boot.lds +++ b/board/esd/cpci405/u-boot.lds @@ -57,22 +57,7 @@ SECTIONS .plt : { *(.plt) } .text : { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +128,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index 20130acfe..6eedb83ff 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -32,6 +32,7 @@ #include <mpc5xxx.h> #include <pci.h> #include <command.h> +#include <netdev.h> #include "mt46v16m16-75.h" @@ -80,7 +81,7 @@ static void sdram_start(int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -105,9 +106,9 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); @@ -143,9 +144,9 @@ phys_size_t initdram(int board_type) #if 0 /* find RAM size using SDRAM CS1 only */ sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(0); #endif /* set SDRAM CS1 size according to the amount of RAM found */ @@ -179,10 +180,10 @@ void flash_afterinit(ulong size) /* adjust mapping */ *(vu_long *) MPC5XXX_BOOTCS_START = *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *) MPC5XXX_BOOTCS_STOP = *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } @@ -259,6 +260,11 @@ void init_ata_reset(void) } } +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { unsigned int addr; diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c index d76af02db..9b578b5f5 100644 --- a/board/esd/cpci5200/strataflash.c +++ b/board/esd/cpci5200/strataflash.c @@ -102,7 +102,7 @@ typedef union { #define NUM_ERASE_REGIONS 4 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -121,7 +121,7 @@ static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword); static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char *prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); #endif @@ -185,14 +185,14 @@ unsigned long flash_init(void) * */ - address = CFG_FLASH_BASE; + address = CONFIG_SYS_FLASH_BASE; size = 0; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; + address += CONFIG_SYS_FLASH_INCREMENT; if (flash_info[i].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", @@ -202,9 +202,9 @@ unsigned long flash_init(void) #if 0 /* test-only */ /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) for (i = 0; - flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1; + flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1; i++) (void)flash_real_protect(&flash_info[0], i, 1); #endif @@ -326,7 +326,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) return rc; wp = cp; } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE while (cnt >= info->portwidth) { i = info->buffer_size > cnt ? cnt : info->buffer_size; if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK) @@ -347,7 +347,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) wp += info->portwidth; cnt -= info->portwidth; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); } @@ -727,7 +727,7 @@ static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword) return flash_full_status_check(info, 0, info->write_tout, "write"); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* loop through the sectors from the highest address * when the passed address is greater or equal to the sector address @@ -801,4 +801,4 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 5ab76c6b8..70bae60c6 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -125,7 +125,7 @@ extern flash_info_t flash_info[]; /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -134,7 +134,7 @@ extern flash_info_t flash_info[]; */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); /* ------------------------------------------------------------------------- */ @@ -197,7 +197,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */ @@ -206,7 +206,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -224,21 +224,21 @@ static void gt_pci_config (void) /* ronen- add write to pci remap registers for 64460. in 64360 when writing to pci base go and overide remap automaticaly, in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -254,7 +254,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -270,7 +270,7 @@ static void gt_cpu_config (void) tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64360 P.399 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif @@ -320,7 +320,7 @@ int board_early_init_f (void) * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); /* No PCI in first release of Port To_do: enable it. */ #ifdef CONFIG_PCI @@ -364,45 +364,45 @@ int board_early_init_f (void) * registers to boot from the sram. (device0) */ - memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ - GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); - GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); - GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR); + GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); + GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); + GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR); -#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */ /* detect if we are booting from the 32 bit flash */ if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, - CFG_32BIT_BOOT_PAR); + CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ -/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/ +/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/ #endif gt_cpu_config (); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); DEBUG_LED0_ON (); DEBUG_LED1_ON (); DEBUG_LED2_ON (); @@ -415,7 +415,7 @@ int board_early_init_f (void) int misc_init_r () { icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -428,19 +428,19 @@ int misc_init_r () /* disable the dcache and MMU */ dcache_lock (); #endif - if (flash_info[3].size < CFG_FLASH_INCREMENT) { + if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) { unsigned int flash_offset; unsigned int l; - flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size; - for (l = 0; l < CFG_MAX_FLASH_SECT; l++) { + flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size; + for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) { if (flash_info[3].start[l] != 0) { flash_info[3].start[l] += flash_offset; } } flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[3]); } return 0; @@ -449,7 +449,7 @@ int misc_init_r () void after_reloc (ulong dest_addr, gd_t * gd) { - memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); display_mem_map (); /* now, jump to the main ppcboot board init code */ @@ -469,7 +469,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -540,7 +540,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -571,7 +571,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaLL, @@ -634,7 +634,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -661,9 +661,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -688,8 +688,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -706,9 +706,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -766,7 +766,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -798,8 +798,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -865,23 +865,23 @@ int testdram (void) int runaddress = 0; int runwalk = 0; -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA s = getenv ("testdramdata"); rundata = (s && (*s == 'y')) ? 1 : 0; #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS s = getenv ("testdramaddress"); runaddress = (s && (*s == 'y')) ? 1 : 0; #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK s = getenv ("testdramwalk"); runwalk = (s && (*s == 'y')) ? 1 : 0; #endif if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { - printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END); + printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -891,7 +891,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -901,7 +901,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -917,7 +917,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ @@ -956,7 +956,7 @@ void board_prebootm_init () /* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */ /* Relocate MV64360 internal regs */ - my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS); + my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS); icache_disable (); dcache_disable (); diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c index 5b1bc01c2..d95567f7d 100644 --- a/board/esd/cpci750/i2c.c +++ b/board/esd/cpci750/i2c.c @@ -46,7 +46,7 @@ static void i2c_init (int speed, int slaveaddr) unsigned int n, m, freq, margin, power; unsigned int actualN = 0, actualM = 0; unsigned int minMargin = 0xffffffff; - unsigned int tclk = CFG_TCLK; + unsigned int tclk = CONFIG_SYS_TCLK; unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */ DP (puts ("i2c_init\n")); @@ -380,7 +380,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_read\n")); @@ -428,7 +428,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_write\n")); @@ -464,7 +464,7 @@ int i2c_probe (uchar chip) unsigned int i2c_status; #endif uchar status = 0; - unsigned int i2cFreq = CFG_I2C_SPEED; + unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED; DP (puts ("i2c_probe\n")); diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 0adafe2d0..9bdc52345 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -30,7 +30,7 @@ #include <ide.h> #include <pci.h> -extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; +extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; int ide_preinit (void) { @@ -39,7 +39,7 @@ int ide_preinit (void) int l; status = 1; - for (l = 0; l < CFG_IDE_MAXBUS; l++) { + for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device (0x1103, 0x0004, 0); @@ -51,11 +51,11 @@ int ide_preinit (void) pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, (u32 *) & ide_bus_offset[0]); ide_bus_offset[0] &= 0xfffffffe; - ide_bus_offset[0] += CFG_PCI0_IO_SPACE; + ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE; pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2, (u32 *) & ide_bus_offset[1]); ide_bus_offset[1] &= 0xfffffffe; - ide_bus_offset[1] += CFG_PCI0_IO_SPACE; + ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; } return (status); } diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h index bca0e1ff5..de3758a51 100644 --- a/board/esd/cpci750/local.h +++ b/board/esd/cpci750/local.h @@ -48,7 +48,7 @@ /* #define CONFIG_BOOTCOMMAND */ /* #define CONFIG_RAMBOOTCOMMAND */ /* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CFG_AUTOLOAD */ +/* #define CONFIG_SYS_AUTOLOAD */ /* #define CONFIG_PREBOOT */ /* These don't */ diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S index 160b1d31f..233fd83bc 100644 --- a/board/esd/cpci750/misc.S +++ b/board/esd/cpci750/misc.S @@ -16,7 +16,7 @@ board_relocate_rom: mflr r7 /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h + lis r11, CONFIG_SYS_GT_REGS@h /* if we're using ECC, we must use the DMA engine to copy ourselves */ bl start_idma_transfer_0 bl wait_for_idma_0 @@ -29,12 +29,12 @@ board_relocate_rom: board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ /* now that we're running from ram, init the rest of main memory * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l + lis r8, CONFIG_SYS_MONITOR_LEN@h + ori r8, r8, CONFIG_SYS_MONITOR_LEN@l divw r3, r10, r8 @@ -120,15 +120,15 @@ stop_idma_engine_0: blr #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* NOTE: trashes r3-r7 */ .globl board_asm_init board_asm_init: /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r3, CONFIG_SYS_DFL_GT_REGS@h + ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTERNAL_SPACE_DECODE /* test to see if we've already moved */ @@ -153,11 +153,11 @@ board_asm_init: cmp cr0, r7, r6 bne 1b - lis r3, CFG_INT_SRAM_BASE@h - ori r3, r3, CFG_INT_SRAM_BASE@l + lis r3, CONFIG_SYS_INT_SRAM_BASE@h + ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l rlwinm r3, r3, 16, 16, 31 - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTEGRATED_SRAM_BASE_ADDR stwbrx r3, r5, r4 diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c index fa8d3bda9..c89426d08 100644 --- a/board/esd/cpci750/mpsc.c +++ b/board/esd/cpci750/mpsc.c @@ -427,7 +427,7 @@ void mpsc_sdma_init (void) (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -517,9 +517,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index c335ebf0b..bfc7e555b 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -66,13 +66,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); @@ -932,14 +932,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -981,14 +981,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 0291937e0..4c03630fb 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -350,7 +350,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) } else dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ -#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT +#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT for (i = 0; i <= 127; i++) { printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], @@ -1656,13 +1656,13 @@ initdram(int board_type) if (dimmInfo2.numOfModuleBanks > 2) printf("Error, SPD claims DIMM2 has >2 banks\n"); - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (! checkbank[bank_no]) continue; - if ((total + check) > CFG_GT_REGS) - check = CFG_GT_REGS - total; + if ((total + check) > CONFIG_SYS_GT_REGS) + check = CONFIG_SYS_GT_REGS - total; memory_map_bank(bank_no, total, check); realsize = dram_size((long int *)total, check); diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds index 1a95755ab..ff2d8b7fe 100644 --- a/board/esd/cpci750/u-boot.lds +++ b/board/esd/cpci750/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c index 204117edf..b5d25433f 100644 --- a/board/esd/cpciiser4/cpciiser4.c +++ b/board/esd/cpciiser4/cpciiser4.c @@ -183,22 +183,3 @@ int checkboard (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c index de847f9be..56c822ec9 100644 --- a/board/esd/cpciiser4/flash.c +++ b/board/esd/cpciiser4/flash.c @@ -47,7 +47,7 @@ unsigned long flash_init (void) unsigned long base_b0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds index 21547ac27..9697cc6b3 100644 --- a/board/esd/cpciiser4/u-boot.lds +++ b/board/esd/cpciiser4/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index 89a4aaf80..36dd58c3e 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -48,13 +48,13 @@ static unsigned int PciEepromReadLongVPD (int offs) unsigned int ret; int count; - pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c, + pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, (offs << 16) | 0x0003); count = 0; for (;;) { udelay (10 * 1000); - pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret); + pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); if ((ret & 0x80000000) != 0) { break; } else { @@ -66,7 +66,7 @@ static unsigned int PciEepromReadLongVPD (int offs) } } - pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x50, &value); + pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value); return value; } @@ -77,14 +77,14 @@ static int PciEepromWriteLongVPD (int offs, unsigned int value) unsigned int ret; int count; - pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x50, value); - pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c, + pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value); + pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, (offs << 16) | 0x80000003); count = 0; for (;;) { udelay (10 * 1000); - pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret); + pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret); if ((ret & 0x80000000) == 0) { break; } else { @@ -109,7 +109,7 @@ static void showPci9054 (void) for (l = 0; l < 6; l++) { printf ("%02x: ", l * 0x10); for (i = 0; i < 4; i++) { - pci_read_config_dword (CFG_PCI9054_DEV_FN, + pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, l * 16 + i * 4, (unsigned int *)&val); printf ("%08x ", val); diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c index fb0c77e56..47d6bb3cc 100644 --- a/board/esd/dasa_sim/dasa_sim.c +++ b/board/esd/dasa_sim/dasa_sim.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <netdev.h> #include "dasa_sim.h" /* ------------------------------------------------------------------------- */ @@ -203,22 +204,7 @@ int checkboard (void) return 0; } - -/* ------------------------------------------------------------------------- */ - phys_size_t initdram (int board_type) { return (16 * 1024 * 1024); } - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c index d2ac13fcd..9c71b043c 100644 --- a/board/esd/dasa_sim/flash.c +++ b/board/esd/dasa_sim/flash.c @@ -47,7 +47,7 @@ unsigned long flash_init (void) unsigned long base_b0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index 67d72f77f..6acf7b846 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -78,7 +78,6 @@ SECTIONS common/cmd_mem.o (.text) common/cmd_nvedit.o (.text) common/console.o (.text) - common/lists.o (.text) common/main.o (.text) board/esd/dasa_sim/flash.o (.text) @@ -87,7 +86,7 @@ SECTIONS net/bootp.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -158,6 +157,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index bb3baa477..eb001dacb 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -74,15 +74,6 @@ int board_early_init_f (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { /* adjust flash start and offset */ @@ -119,30 +110,3 @@ int checkboard (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/dp405/flash.c +++ b/board/esd/dp405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds index d70d37934..d8fbea396 100644 --- a/board/esd/dp405/u-boot.lds +++ b/board/esd/dp405/u-boot.lds @@ -66,14 +66,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -144,6 +144,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 78ae4ba67..8a87d5549 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -198,18 +198,3 @@ int checkboard (void) return 0; } - - -phys_size_t initdram (int board_type) -{ - return (16 * 1024 * 1024); -} - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c index 14549c014..240aa09f5 100644 --- a/board/esd/du405/flash.c +++ b/board/esd/du405/flash.c @@ -47,7 +47,7 @@ unsigned long flash_init (void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds index 46ef7e72a..858ae61ec 100644 --- a/board/esd/du405/u-boot.lds +++ b/board/esd/du405/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk index 516433450..91e65ec8a 100644 --- a/board/esd/du440/config.mk +++ b/board/esd/du440/config.mk @@ -33,5 +33,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 8765cc1f3..2f97a1262 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -29,7 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern ulong flash_get_size (ulong base, int banknum); int usbhub_init(void); @@ -51,31 +51,31 @@ int board_early_init_f(void) /* * Setup the GPIO pins */ - out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP); - out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP); + out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP); + out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP); out_be32((void*)GPIO0_OSRL, 0x50055400); - out_be32((void*)GPIO0_OSRH, 0x550050aa); + out_be32((void*)GPIO0_OSRH, 0x55005000); out_be32((void*)GPIO0_TSRL, 0x50055400); out_be32((void*)GPIO0_TSRH, 0x55005000); out_be32((void*)GPIO0_ISR1L, 0x50000000); out_be32((void*)GPIO0_ISR1H, 0x00000000); out_be32((void*)GPIO0_ISR2L, 0x00000000); - out_be32((void*)GPIO0_ISR2H, 0x00000100); + out_be32((void*)GPIO0_ISR2H, 0x00000000); out_be32((void*)GPIO0_ISR3L, 0x00000000); out_be32((void*)GPIO0_ISR3H, 0x00000000); out_be32((void*)GPIO1_OR, 0x00000000); out_be32((void*)GPIO1_TCR, 0xc2000000 | - CFG_GPIO1_IORSTN | - CFG_GPIO1_IORST2N | - CFG_GPIO1_LEDUSR1 | - CFG_GPIO1_LEDUSR2 | - CFG_GPIO1_LEDPOST | - CFG_GPIO1_LEDDU); - out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU); - out_be32((void*)GPIO1_OSRL, 0x5c280000); + CONFIG_SYS_GPIO1_IORSTN | + CONFIG_SYS_GPIO1_IORST2N | + CONFIG_SYS_GPIO1_LEDUSR1 | + CONFIG_SYS_GPIO1_LEDUSR2 | + CONFIG_SYS_GPIO1_LEDPOST | + CONFIG_SYS_GPIO1_LEDDU); + out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU); + out_be32((void*)GPIO1_OSRL, 0x0c280000); out_be32((void*)GPIO1_OSRH, 0x00000000); - out_be32((void*)GPIO1_TSRL, 0x0c000000); + out_be32((void*)GPIO1_TSRL, 0xcc000000); out_be32((void*)GPIO1_TSRH, 0x00000000); out_be32((void*)GPIO1_ISR1L, 0x00005550); out_be32((void*)GPIO1_ISR1H, 0x00000000); @@ -154,8 +154,8 @@ int board_early_init_f(void) SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CFG_NAND0_CS)) | - (0x80000000 >> (28 + CFG_NAND1_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) | + (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); return 0; @@ -169,6 +169,7 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; + unsigned long sdr0_srst0, sdr0_srst1; int i, j; /* adjust flash start and offset */ @@ -223,10 +224,38 @@ int misc_init_r(void) mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); - /* clear resets */ - udelay (1000); + /* + * Take USB out of reset: + * -Initial status = all cores are in reset + * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores + * -wait 1 ms + * -deassert reset to PHY + * -wait 1 ms + * -deassert reset to HOST + * -wait 4 ms + * -deassert all other resets + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ + SDR0_SRST1_P4OPB0 | \ + SDR0_SRST1_OPBA2 | \ + SDR0_SRST1_PLB42OPB1 | \ + SDR0_SRST1_OPB2PLB40); + mtsdr(SDR0_SRST1, sdr0_srst1); + udelay(1000); + + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst1); + udelay(1000); + + mfsdr(SDR0_SRST0, sdr0_srst0); + sdr0_srst0 &= ~SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst0); + udelay(4000); + + /* finally all the other resets */ mtsdr(SDR0_SRST1, 0x00000000); - udelay (1000); mtsdr(SDR0_SRST0, 0x00000000); printf("USB: Host(int phy)\n"); @@ -244,7 +273,7 @@ int misc_init_r(void) * We have to wait at least 560ms until we may call usbhub_init */ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | - CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N); + CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N); /* * flash USR1/2 LEDs (600ms) @@ -253,22 +282,22 @@ int misc_init_r(void) */ for (j = 0; j < 3; j++) { out_be32((void*)GPIO1_OR, - (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) | - CFG_GPIO1_LEDUSR1); + (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) | + CONFIG_SYS_GPIO1_LEDUSR1); for (i = 0; i < 100; i++) udelay(1000); out_be32((void*)GPIO1_OR, - (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) | - CFG_GPIO1_LEDUSR2); + (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) | + CONFIG_SYS_GPIO1_LEDUSR2); for (i = 0; i < 100; i++) udelay(1000); } out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & - ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2)); + ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2)); if (usbhub_init()) du440_post_errors++; @@ -281,14 +310,14 @@ int misc_init_r(void) int pld_revision(void) { - out8(CFG_CPLD_BASE, 0x00); - return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK); + out8(CONFIG_SYS_CPLD_BASE, 0x00); + return (int)(in8(CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK); } int board_revision(void) { - int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK) - >> CFG_GPIO1_HWVER_SHIFT); + int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK) + >> CONFIG_SYS_GPIO1_HWVER_SHIFT); return ((rpins & 1) << 3) | ((rpins & 2) << 1) | ((rpins & 4) >> 1) | ((rpins & 8) >> 3); @@ -299,7 +328,7 @@ void board_show_activity (ulong timestamp) { if ((timestamp % 100) == 0) out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1); + in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1); } void show_activity(int arg) @@ -392,7 +421,7 @@ int pci_pre_init(struct pci_controller *hose) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /* @@ -408,16 +437,16 @@ void pci_target_init(struct pci_controller *hose) */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ @@ -450,9 +479,9 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -467,7 +496,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /* * is_pci_host @@ -495,18 +524,18 @@ int last_stage_init(void) int e, i; /* everyting is ok: turn on POST-LED */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST); + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); /* slowly blink on errors and finally keep LED off */ for (e = 0; e < du440_post_errors; e++) { out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST); + in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST); for (i = 0; i < 500; i++) udelay(1000); out_be32((void*)GPIO1_OR, - in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST); + in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST); for (i = 0; i < 500; i++) udelay(1000); @@ -554,9 +583,9 @@ int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("ERROR - no signal\n"); t1 = t2 = 0; - pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77; + pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; while (!ctrlc()) { - pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77; + pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77; if (pin && !pinold) { /* bit start */ t1 = get_ticks(); if (t2 && ((unsigned int)(t1 - t2) / @@ -632,7 +661,7 @@ U_BOOT_CMD( ); #endif /* CONFIG_I2C_MULTI_BUS */ -#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 int boot_eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, @@ -642,7 +671,7 @@ int boot_eeprom_write (unsigned dev_addr, unsigned blk_off; int rcode = 0; -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 1); #endif /* @@ -671,9 +700,9 @@ int boot_eeprom_write (unsigned dev_addr, * bytes that can be ccessed with the single read or write * operation. */ -#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) -#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) maxlen = BOOT_EEPROM_PAGE_SIZE - @@ -693,11 +722,11 @@ int boot_eeprom_write (unsigned dev_addr, buffer += len; offset += len; -#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif } -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 0); #endif return rcode; @@ -733,6 +762,12 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* sdsdp[1]=0x095fa030; */ sdsdp[2] = 0x40082350; sdsdp[3] = 0x0d050000; + } else if (!strcmp(argv[1], "667-166")) { + printf("Bootstrapping for 667-166MHz\n"); + sdsdp[0] = 0x8778a252; + sdsdp[1] = 0x09d7a030; + sdsdp[2] = 0x40082350; + sdsdp[3] = 0x0d050000; } } else { printf("Bootstrapping for 533MHz (default)\n"); @@ -744,7 +779,7 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } printf("Writing boot EEPROM ...\n"); - if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR, + if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0, (uchar*)sdsdp, 16) != 0) printf("boot_eeprom_write failed\n"); else @@ -758,7 +793,7 @@ U_BOOT_CMD( NULL ); -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* * Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state @@ -770,27 +805,27 @@ U_BOOT_CMD( */ int eeprom_write_enable (unsigned dev_addr, int state) { - if ((CFG_I2C_EEPROM_ADDR != dev_addr) && - (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) + if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && + (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) return -1; else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP); + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP); + in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP); state = 0; break; default: /* Read current status back. */ state = (0 == (in_be32((void*)GPIO0_OR) & - CFG_GPIO0_EP_EEP)); + CONFIG_SYS_GPIO0_EP_EEP)); break; } } @@ -804,21 +839,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) puts ("Query of write access state failed.\n"); else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) puts ("Setup of write access state failed.\n"); @@ -830,19 +865,19 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ static int got_pldirq; static int pld_interrupt(u32 arg) { int rc = -1; /* not for us */ - u8 status = in8(CFG_CPLD_BASE); + u8 status = in8(CONFIG_SYS_CPLD_BASE); /* check for PLD interrupt */ if (status & PWR_INT_FLAG) { /* reset this int */ - out8(CFG_CPLD_BASE, 0); + out8(CONFIG_SYS_CPLD_BASE, 0); rc = 0; got_pldirq = 1; /* trigger backend */ } @@ -855,7 +890,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) got_pldirq = 0; /* clear any pending interrupt */ - out8(CFG_CPLD_BASE, 0); + out8(CONFIG_SYS_CPLD_BASE, 0); irq_install_handler(CPLD_IRQ, (interrupt_handler_t *)pld_interrupt, 0); @@ -871,7 +906,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (got_pldirq) { printf("Got interrupt!\n"); printf("Power %sready!\n", - in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT "); + in8(CONFIG_SYS_CPLD_BASE) & PWR_RDY ? "":"NOT "); } irq_free_handler(CPLD_IRQ); @@ -935,7 +970,7 @@ U_BOOT_CMD( int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { unsigned long long start, end; - char c, cmd[CFG_CBSIZE]; + char c, cmd[CONFIG_SYS_CBSIZE]; char *p, *d = cmd; int ret, i; ulong us; @@ -963,7 +998,7 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return ret; } U_BOOT_CMD( - time, CFG_MAXARGS, 1, do_time, + time, CONFIG_SYS_MAXARGS, 1, do_time, "time - run command and output execution time\n", NULL ); @@ -1013,7 +1048,7 @@ int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } U_BOOT_CMD( - gfxdemo, CFG_MAXARGS, 1, do_gfxdemo, + gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo, "gfxdemo - demo\n", NULL ); diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h index 83fdac7c6..a124a7ee9 100644 --- a/board/esd/du440/du440.h +++ b/board/esd/du440/du440.h @@ -20,18 +20,18 @@ #define SDR0_USB0 0x0320 /* USB Control Register */ -#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */ -#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */ +#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */ +#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */ -#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */ -#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */ +#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */ +#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */ -#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */ -#define CFG_GPIO1_HWVER_SHIFT 4 -#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */ -#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */ -#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */ -#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */ +#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */ +#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4 +#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */ +#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */ +#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */ +#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */ #define CPLD_VERSION_MASK 0x0f #define PWR_INT_FLAG 0x80 diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S index 4390b5074..3cac6b11b 100644 --- a/board/esd/du440/init.S +++ b/board/esd/du440/init.S @@ -44,30 +44,30 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for PCI IO */ - tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entries for EBC: CPLD, DUMEM, DUIO */ - tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for NAND */ - tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds index b20fb1c0a..05152b7f7 100644 --- a/board/esd/du440/u-boot.lds +++ b/board/esd/du440/u-boot.lds @@ -135,9 +135,10 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/hh405/flash.c +++ b/board/esd/hh405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 802491a31..efadf1646 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -345,7 +345,7 @@ int board_early_init_f (void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */ + mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */ mtdcr(uictr, 0x10000000); /* set int trigger levels */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ @@ -363,26 +363,26 @@ int cf_enable(void) int i; volatile unsigned short *fpga_ctrl = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); volatile unsigned short *fpga_status = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2); if (gd->board_type >= 2) { - if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) { - if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) { - *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN; + if (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT) { + if (!(*fpga_ctrl & CONFIG_SYS_FPGA_CTRL_CF_BUS_EN)) { + *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN; for (i=0; i<300; i++) udelay(1000); - *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; for (i=0; i<20; i++) udelay(1000); } } else { - *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN; - *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN; + *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_PWRN; } } @@ -392,11 +392,11 @@ int cf_enable(void) int misc_init_r (void) { volatile unsigned short *fpga_ctrl = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); volatile unsigned short *lcd_contrast = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4); volatile unsigned short *lcd_backlight = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6); unsigned char *dst; ulong len = sizeof(fpgadata); int status; @@ -405,8 +405,8 @@ int misc_init_r (void) char *str; unsigned long contrast0 = 0xffffffff; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -474,22 +474,22 @@ int misc_init_r (void) /* * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); /* * Reset touch-screen controller */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); udelay(1000); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_TOUCH_RST); /* * Enable power on PS/2 interface (with reset) */ - *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR); + *fpga_ctrl &= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR); for (i=0;i<500;i++) udelay(1000); - *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR); + *fpga_ctrl |= (CONFIG_SYS_FPGA_CTRL_PS2_PWR); /* * Get contrast value from environment variable @@ -512,11 +512,11 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL; *lcd_backlight = 0x0000; lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_1024_768_8bpp, sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]), logo_bmp_1024, sizeof(logo_bmp_1024)); @@ -524,11 +524,11 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL; + *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL; *lcd_backlight = 0x0000; lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), logo_bmp_640, sizeof(logo_bmp_640)); @@ -545,7 +545,7 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; /* * Set lcd clock (small epson) */ @@ -553,7 +553,7 @@ int misc_init_r (void) udelay(100); /* wait for 100 us */ lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13705_320_240_8bpp, sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]), logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp)); @@ -570,14 +570,14 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE; + *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; /* * Set lcd clock (small epson), enable 1-wire interface */ - *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE; + *fpga_ctrl |= LCD_CLK_08330 | CONFIG_SYS_FPGA_CTRL_OW_ENABLE; lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); @@ -643,48 +643,31 @@ int checkboard (void) return 0; } - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); volatile unsigned short *fpga_status = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2); - if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) || + if (((gd->board_type >= 2) && (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT)) || (gd->board_type < 2)) { /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ cf_enable(); - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; } } } #endif /* CONFIG_IDE_RESET */ -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state * 0: disable write @@ -695,23 +678,23 @@ void ide_set_reset(int on) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -725,21 +708,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -752,7 +735,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ #ifdef CONFIG_VIDEO_SM501 diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds index 21547ac27..9697cc6b3 100644 --- a/board/esd/hh405/u-boot.lds +++ b/board/esd/hh405/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/hub405/flash.c +++ b/board/esd/hub405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 03b87c9df..8785e6c84 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -101,13 +101,6 @@ int board_early_init_f (void) return 0; } - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); @@ -132,23 +125,23 @@ int misc_init_r (void) * Set RS232/RS422 control (RS232 = high on GPIO) */ val = in32(GPIO0_OR); - val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232); + val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232); str = getenv("phys0"); if (!str || (str && (str[0] == '0'))) - val |= CFG_UART2_RS232; + val |= CONFIG_SYS_UART2_RS232; str = getenv("phys1"); if (!str || (str && (str[0] == '0'))) - val |= CFG_UART3_RS232; + val |= CONFIG_SYS_UART3_RS232; str = getenv("phys2"); if (!str || (str && (str[0] == '0'))) - val |= CFG_UART4_RS232; + val |= CONFIG_SYS_UART4_RS232; str = getenv("phys3"); if (!str || (str && (str[0] == '0'))) - val |= CFG_UART5_RS232; + val |= CONFIG_SYS_UART5_RS232; out32(GPIO0_OR, val); @@ -181,9 +174,9 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* @@ -227,14 +220,3 @@ int checkboard (void) return 0; } - - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds index f21c7aad4..6908106c2 100644 --- a/board/esd/hub405/u-boot.lds +++ b/board/esd/hub405/u-boot.lds @@ -66,14 +66,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c index 6d776b7a6..31924502e 100644 --- a/board/esd/mecp5200/mecp5200.c +++ b/board/esd/mecp5200/mecp5200.c @@ -32,6 +32,7 @@ #include <mpc5xxx.h> #include <pci.h> #include <command.h> +#include <netdev.h> #include "mt46v16m16-75.h" @@ -80,7 +81,7 @@ static void sdram_start(int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -105,9 +106,9 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); @@ -142,9 +143,9 @@ phys_size_t initdram(int board_type) #if 0 /* find RAM size using SDRAM CS1 only */ sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(0); #endif /* set SDRAM CS1 size according to the amount of RAM found */ @@ -174,14 +175,14 @@ void flash_preinit(void) void flash_afterinit(ulong size) { - if (size == CFG_FLASH_SIZE) { + if (size == CONFIG_SYS_FLASH_SIZE) { /* adjust mapping */ *(vu_long *) MPC5XXX_BOOTCS_START = *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *) MPC5XXX_BOOTCS_STOP = *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } @@ -259,3 +260,8 @@ void init_power_switch(void) __asm__ volatile ("sync"); } } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c index c3d8bec91..e763a895e 100644 --- a/board/esd/ocrtc/flash.c +++ b/board/esd/ocrtc/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 7b0edd595..35bfa95f2 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -62,13 +62,6 @@ int board_early_init_f (void) return 0; } - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - /* * Check Board Identity: */ @@ -99,28 +92,3 @@ int checkboard (void) return (0); } - - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr (memcfga, mem_mb0cf); - val = mfdcr (memcfgd); - -#if 0 - printf ("\nmb0cf=%x\n", val); /* test-only */ - printf ("strap=%x\n", mfdcr (strap)); /* test-only */ -#endif - - return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17)); -} - - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds index 5fb969944..1fb754c50 100644 --- a/board/esd/ocrtc/u-boot.lds +++ b/board/esd/ocrtc/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 5c717e253..f558a2bc6 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -32,13 +32,9 @@ #include "pci405.h" - #if defined(CONFIG_CMD_BSP) extern int do_bootm (cmd_tbl_t *, int, int, char *[]); -extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); -unsigned long get_dcr(unsigned short); - /* * Command loadpci: wait for signal from host and boot image. @@ -97,33 +93,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else { sprintf(addr, "%08x", *ptr); -#if 0 - /* - * Boot image - */ - if (*ptr & 0x00000001) { - /* - * Boot VxWorks image via bootvx - */ - addr[strlen(addr)-1] = '0'; - printf("\nBooting VxWorks-Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootvx (cmdtp, 0, 1, local_args); - } else { - /* - * Boot image via bootm (normally Linux) - */ - printf("\nBooting Image at addr 0x%s ...\n", addr); - setenv("loadaddr", addr); - - local_args[0] = argv[0]; - local_args[1] = NULL; - status = do_bootm (cmdtp, 0, 1, local_args); - } -#else /* * Boot image via bootm */ @@ -133,7 +102,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) local_args[0] = argv[0]; local_args[1] = NULL; status = do_bootm (cmdtp, 0, 1, local_args); -#endif } return 0; @@ -143,843 +111,4 @@ U_BOOT_CMD( "loadpci - Wait for pci-image and boot it\n", NULL ); - -#endif - -#if 1 /* test-only */ -int do_getpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int val; - int i; - - printf("\nPCI Configuration Regs for PPC405GP:"); - for (i=0; i<0x64; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, &val); - if (!(i % 0x10)) { - printf("\n%02x: ", i); - } - printf("%08x ", val); - } - printf("\n"); - - return 0; -} -U_BOOT_CMD( - getpci, 1, 1, do_getpci, - "getpci - Print own pci configuration registers\n", - NULL -); - -int do_setpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int val; - - addr = simple_strtol (argv[1], NULL, 16); - val = simple_strtol (argv[2], NULL, 16); - - printf("\nWriting %08x to PCI reg %08x.\n", val, addr); - pci_write_config_dword(PCIDEVID_405GP, addr, val); - - return 0; -} -U_BOOT_CMD( - setpci, 3, 1, do_setpci, - "setpci - Set one pci configuration lword\n", - "<addr> <val>\n" - " - Write pci configuration lword <val> to <addr>.\n" -); - -int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int i; - - printf("\nDevice Configuration Registers (DCR's) for PPC405GP:"); - for (i=0; i<=0x1e0; i++) { - if (!(i % 0x8)) { - printf("\n%04x ", i); - } - printf("%08lx ", get_dcr(i)); - } - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpdcr, 1, 1, do_dumpdcr, - "dumpdcr - Dump all DCR registers\n", - NULL -); - - -int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:"); - printf("\n%04x %08x ", 947, mfspr(947)); - printf("\n%04x %08x ", 9, mfspr(9)); - printf("\n%04x %08x ", 1014, mfspr(1014)); - printf("\n%04x %08x ", 1015, mfspr(1015)); - printf("\n%04x %08x ", 1010, mfspr(1010)); - printf("\n%04x %08x ", 957, mfspr(957)); - printf("\n%04x %08x ", 1008, mfspr(1008)); - printf("\n%04x %08x ", 1018, mfspr(1018)); - printf("\n%04x %08x ", 954, mfspr(954)); - printf("\n%04x %08x ", 950, mfspr(950)); - printf("\n%04x %08x ", 951, mfspr(951)); - printf("\n%04x %08x ", 981, mfspr(981)); - printf("\n%04x %08x ", 980, mfspr(980)); - printf("\n%04x %08x ", 982, mfspr(982)); - printf("\n%04x %08x ", 1012, mfspr(1012)); - printf("\n%04x %08x ", 1013, mfspr(1013)); - printf("\n%04x %08x ", 948, mfspr(948)); - printf("\n%04x %08x ", 949, mfspr(949)); - printf("\n%04x %08x ", 1019, mfspr(1019)); - printf("\n%04x %08x ", 979, mfspr(979)); - printf("\n%04x %08x ", 8, mfspr(8)); - printf("\n%04x %08x ", 945, mfspr(945)); - printf("\n%04x %08x ", 987, mfspr(987)); - printf("\n%04x %08x ", 287, mfspr(287)); - printf("\n%04x %08x ", 953, mfspr(953)); - printf("\n%04x %08x ", 955, mfspr(955)); - printf("\n%04x %08x ", 272, mfspr(272)); - printf("\n%04x %08x ", 273, mfspr(273)); - printf("\n%04x %08x ", 274, mfspr(274)); - printf("\n%04x %08x ", 275, mfspr(275)); - printf("\n%04x %08x ", 260, mfspr(260)); - printf("\n%04x %08x ", 276, mfspr(276)); - printf("\n%04x %08x ", 261, mfspr(261)); - printf("\n%04x %08x ", 277, mfspr(277)); - printf("\n%04x %08x ", 262, mfspr(262)); - printf("\n%04x %08x ", 278, mfspr(278)); - printf("\n%04x %08x ", 263, mfspr(263)); - printf("\n%04x %08x ", 279, mfspr(279)); - printf("\n%04x %08x ", 26, mfspr(26)); - printf("\n%04x %08x ", 27, mfspr(27)); - printf("\n%04x %08x ", 990, mfspr(990)); - printf("\n%04x %08x ", 991, mfspr(991)); - printf("\n%04x %08x ", 956, mfspr(956)); - printf("\n%04x %08x ", 284, mfspr(284)); - printf("\n%04x %08x ", 285, mfspr(285)); - printf("\n%04x %08x ", 986, mfspr(986)); - printf("\n%04x %08x ", 984, mfspr(984)); - printf("\n%04x %08x ", 256, mfspr(256)); - printf("\n%04x %08x ", 1, mfspr(1)); - printf("\n%04x %08x ", 944, mfspr(944)); - printf("\n"); - - return 0; -} -U_BOOT_CMD( - dumpspr, 1, 1, do_dumpspr, - "dumpspr - Dump all SPR registers\n", - NULL -); - - -#define PCI0_BRDGOPT1 0x4a -#define plb0_acr 0x87 - -int do_getplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned short val; - - printf("PLB0_ACR=%08lx\n", get_dcr(0x87)); - pci_read_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, &val); - printf("PCI0_BRDGOPT1=%04x\n", val); - printf("CCR0=%08x\n", mfspr(ccr0)); - - return 0; -} -U_BOOT_CMD( - getplb, 1, 1, do_getplb, - "getplb - Dump all plb arbiter registers\n", - NULL -); - -int do_setplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int my_acr; - unsigned int my_brdgopt1; - unsigned int my_ccr0; - - my_acr = simple_strtol (argv[1], NULL, 16); - my_brdgopt1 = simple_strtol (argv[2], NULL, 16); - my_ccr0 = simple_strtol (argv[3], NULL, 16); - - mtdcr(plb0_acr, my_acr); - pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, my_brdgopt1); - mtspr(ccr0, my_ccr0); - - return 0; -} -U_BOOT_CMD( - setplb, 4, 1, do_setplb, - "setplb - Set all plb arbiter registers\n", - "PLB0_ACR PCI0_BRDGOPT1 CCR0\n" - " - Set all plb arbiter registers\n" -); - - -/*********************************************************************** - * - * The following code is only for test purposes!!!! - * Please ignore this ugly stuff!!!!!!!!!!!!!!!!!!! - * - ***********************************************************************/ - -#define PCI_ADDR 0xc0000000 - -int do_writepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int i; - int max; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - int test_pci_read = 0; - int test_pci_cfg_write = 0; - int test_sync = 0; - int test_pci_pre_read = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - max = size >> 2; - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - val = *(ulong *)0x00000000; - if (val & 0x00000008) { - test_pci_pre_read = 1; - printf("Running test with pre pci-memory-read access!\n"); - } - if (val & 0x00000004) { - test_sync = 1; - printf("Running test with sync instruction!\n"); - } - if (val & 0x00000001) { - test_pci_read = 1; - printf("Running test with pci-memory-read access!\n"); - } - if (val & 0x00000002) { - test_pci_cfg_write = 1; - printf("Running test with pci-config-write access!\n"); - } - - while (1) { - - if (test_pci_pre_read) { - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - } - - /* - * Write some values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - for (i=0; i<max; i++) { - *ptr++ = i; - } - - if (test_sync) { - /* - * Sync previous writes - */ - ppcSync(); - } - - if (test_pci_read) { - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - } - - if (test_pci_cfg_write) { - /* - * Generate IRQ to host via config regs - */ - pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); - } - - if (loopcount++ > countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci, 4, 1, do_writepci, - "writepci - Write some data to pcibus\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -#define PCI_CFGADDR 0xeec00000 -#define PCI_CFGDATA 0xeec00004 - -int ibmPciConfigWrite -( - int offset, /* offset into the configuration space */ - int width, /* data width */ - unsigned int data /* data to be written */ - ) -{ - /* - * Write config register address to the PCI config address register - * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation) - */ - out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC)); - -#if 0 /* test-only */ - ppcSync(); -#endif - - /* - * Write value to be written to the PCI config data register - */ - switch ( width ) { - case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF)); - break; - case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF)); - break; - case 4: out32r(PCI_CFGDATA | (offset & 0x3), data); - break; - } - - return (0); -} - -int do_writepci2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int max; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - max = size >> 2; - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - *ptr = 0x01234567; - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - - /* - * One pci config write - */ -/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ -/* ibmPciConfigWrite(0x44, 1, 0x00); */ - ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */ - - if (loopcount++ > countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci2, 4, 1, do_writepci2, - "writepci2- Write some data to pcibus\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax = 0; - volatile unsigned long *ptr; - volatile unsigned long val; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - *ptr = 0x01234567; - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - - /* - * One pci config write - */ - ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */ - } - - return 0; -} -U_BOOT_CMD( - writepci22, 4, 1, do_writepci22, - "writepci22- Write some data to pcibus\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -int ibmPciConfigWrite3 -( - int offset, /* offset into the configuration space */ - int width, /* data width */ - unsigned int data /* data to be written */ - ) -{ - /* - * Write config register address to the PCI config address register - * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation) - */ - out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC)); - -#if 1 /* test-only */ - ppcSync(); -#endif - - /* - * Write value to be written to the PCI config data register - */ - switch ( width ) { - case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF)); - break; - case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF)); - break; - case 4: out32r(PCI_CFGDATA | (offset & 0x3), data); - break; - } - - return (0); -} - -int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int max; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - max = size >> 2; - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - *ptr = 0x01234567; - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - - /* - * One pci config write - */ -/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ -/* ibmPciConfigWrite(0x44, 1, 0x00); */ - ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */ - - if (loopcount++ > countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci3, 4, 1, do_writepci3, - "writepci3- Write some data to pcibus\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - - -#define SECTOR_SIZE 32 /* 32 byte cache line */ -#define SECTOR_MASK 0x1F - -void my_flush_dcache(ulong lcl_addr, ulong count) -{ - unsigned int lcl_target; - - /* promote to nearest cache sector */ - lcl_target = (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK; - lcl_addr &= ~SECTOR_MASK; - while (lcl_addr != lcl_target) - { - /* ppcDcbf((void *)lcl_addr);*/ - __asm__("dcbf 0,%0": :"r" (lcl_addr)); - lcl_addr += SECTOR_SIZE; - } - __asm__("sync"); /* Always flush prefetch queue in any case */ -} - -int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int addr; - unsigned int size; - unsigned int countmax; - int i; - volatile unsigned long *ptr; - volatile unsigned long val; - int loopcount = 0; - - addr = simple_strtol (argv[1], NULL, 16); - size = simple_strtol (argv[2], NULL, 16); - countmax = simple_strtol (argv[3], NULL, 16); - if (countmax == 0) - countmax = 1000; - - do_getplb(NULL, 0, 0, NULL); - -#if 0 - out32r(PMM0LA, 0); - out32r(PMM0PCILA, 0); - out32r(PMM0PCIHA, 0); - out32r(PMM0MA, 0); - out32r(PMM1LA, PCI_ADDR); - out32r(PMM1PCILA, addr & 0xff000000); - out32r(PMM1PCIHA, 0x00000000); - out32r(PMM1MA, 0xff000001); -#endif - - printf("PMM1LA =%08lx\n", in32r(PMM1LA)); - printf("PMM1MA =%08lx\n", in32r(PMM1MA)); - printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA)); - printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA)); - - addr = PCI_ADDR | (addr & 0x00ffffff); - printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax); - - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - i = 0; - - /* - * Set pci region as cachable - */ - ppcSync(); - __asm__ volatile (" addis 4,0,0x0000 "); - __asm__ volatile (" addi 4,4,0x0080 "); - __asm__ volatile (" mtdccr 4 "); - ppcSync(); - - while (1) { - - /* - * Write one values to host via pci busmastering - */ - ptr = (volatile unsigned long *)addr; - printf("A\n"); /* test-only */ - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - *ptr++ = i++; - printf("B\n"); /* test-only */ - my_flush_dcache(addr, 32); - printf("C\n"); /* test-only */ - - /* - * Read one value back - */ - ptr = (volatile unsigned long *)addr; - val = *ptr; - printf("D\n"); /* test-only */ - - /* - * One pci config write - */ -/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */ -/* ibmPciConfigWrite(0x44, 1, 0x00); */ - ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */ - printf("E\n"); /* test-only */ - - if (loopcount++ > countmax) { - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - putc('.'); - - loopcount = 0; - } - } - - return 0; -} -U_BOOT_CMD( - writepci_cache, 4, 1, do_writepci_cache, - "writepci_cache - Write some data to pcibus\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int *ptr; - int i; - - /* - * Save own pci configuration in PRAM - */ - memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_read_config_dword(PCIDEVID_405GP, i, ptr++); - } - ptr = (unsigned int *)PCI_REGS_ADDR; - *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4); - - printf("\nStoring PCI Configuration Regs...\n"); - - return 0; -} -U_BOOT_CMD( - savepci, 4, 1, do_savepci, - "savepci - Save all pci regs\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - unsigned int *ptr; - int i; - - /* - * Rewrite pci config regs (only after soft-reset with magic set) - */ - ptr = (unsigned int *)PCI_REGS_ADDR; - if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) { - puts("Restoring PCI Configurations Regs!\n"); - ptr = (unsigned int *)PCI_REGS_ADDR + 1; - for (i=0; i<0x40; i+=4) { - pci_write_config_dword(PCIDEVID_405GP, i, *ptr++); - } - } - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - - return 0; -} -U_BOOT_CMD( - restorepci, 4, 1, do_restorepci, - "restorepci - Restore all pci regs\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - - -extern void write_without_sync(void); -extern void write_with_sync(void); -extern void write_with_less_sync(void); -extern void write_with_more_sync(void); - -/* - * code from IBM-PPCSUPP - */ -int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_without_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm1, 4, 1, do_writeibm1, - "writeibm1- Write some data to pcibus (without sync)\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_with_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm2, 4, 1, do_writeibm2, - "writeibm2- Write some data to pcibus (with sync)\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_with_less_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm22, 4, 1, do_writeibm22, - "writeibm22- Write some data to pcibus (with less sync)\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); - -int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */ - - write_with_more_sync(); - - return 0; -} -U_BOOT_CMD( - writeibm3, 4, 1, do_writeibm3, - "writeibm3- Write some data to pcibus (with more sync)\n", - "<addr> <size>\n" - " - Write some data to pcibus.\n" -); #endif diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c index 3b21781d7..905848380 100644 --- a/board/esd/pci405/flash.c +++ b/board/esd/pci405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index f740d595b..42774ad20 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -27,6 +27,7 @@ #include <malloc.h> #include <pci.h> #include <asm/4xx_pci.h> +#include <asm/io.h> #include "pci405.h" @@ -34,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Prototypes */ int gunzip(void *, int, unsigned char *, unsigned long *); -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/ +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); unsigned long fpga_done_state(void); unsigned long fpga_init_state(void); @@ -57,11 +58,11 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" -#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE) -#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12) +#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE) +#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12) -#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT) -#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12) +#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT) +#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12) int board_revision(void) @@ -78,10 +79,10 @@ int board_revision(void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00100200; /* get config bits */ + value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */ /* * Restore GPIO settings @@ -137,10 +138,10 @@ int board_early_init_f (void) /* * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ + out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ + out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */ + out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */ + out_be32((void*)GPIO0_OR, 0); /* pull prg low */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -181,15 +182,6 @@ int board_early_init_f (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { unsigned char *dst; @@ -205,8 +197,8 @@ int misc_init_r (void) * FPGA can be gzip compressed (malloc) and booted this late. */ - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -284,13 +276,11 @@ int misc_init_r (void) *magic = 0; /* clear pci reconfig magic again */ } -#if 1 /* test-only */ /* * Decrease PLB latency timeout and reduce priority of the PCI bridge master */ #define PCI0_BRDGOPT1 0x4a pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); -/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */ #define plb0_acr 0x87 /* @@ -298,14 +288,6 @@ int misc_init_r (void) */ mtdcr(plb0_acr, 0x98000000); -#if 0 /* test-only */ - printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */ -/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */ - mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000); -#endif -/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */ -#endif - free(dst); return (0); } @@ -314,7 +296,6 @@ int misc_init_r (void) /* * Check Board Identity: */ - int checkboard (void) { char str[64]; @@ -340,14 +321,14 @@ int checkboard (void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg & ~0x08000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x40000000; /* get config bits */ + value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */ if (value) { puts(", 33 MHz PCI"); } else { - puts(", 66 Mhz PCI"); + puts(", 66 MHz PCI"); } } @@ -357,37 +338,6 @@ int checkboard (void) } /* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - -#if 0 /* test-only: all PCI405 version must report 16mb */ - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -#else - return (16*1024*1024); -#endif -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ int wpeeprom(int wp) { int wp_state = wp; diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds index 21547ac27..9697cc6b3 100644 --- a/board/esd/pci405/u-boot.lds +++ b/board/esd/pci405/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c index 53afbc0b9..985044546 100644 --- a/board/esd/pf5200/flash.c +++ b/board/esd/pf5200/flash.c @@ -23,7 +23,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ typedef unsigned short FLASH_PORT_WIDTH; typedef volatile unsigned short FLASH_PORT_WIDTHV; @@ -60,7 +60,7 @@ unsigned long flash_init(void) extern void flash_preinit(void); extern void flash_afterinit(uint, ulong, ulong); - ulong flashbase = CFG_FLASH_BASE; + ulong flashbase = CONFIG_SYS_FLASH_BASE; flash_preinit(); @@ -69,18 +69,18 @@ unsigned long flash_init(void) flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]); size += flash_info[i].size; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); + flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - flash_get_info(CFG_ENV_ADDR)); + flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, + flash_get_info(CONFIG_ENV_ADDR)); #endif flash_afterinit(i, flash_info[i].start[0], flash_info[i].size); @@ -107,14 +107,14 @@ static flash_info_t *flash_get_info(ulong base) { int i; flash_info_t *info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { info = &flash_info[i]; if ((info->size) && (info->start[0] <= base) && (base <= info->start[0] + info->size - 1)) { break; } } - return (i == CFG_MAX_FLASH_BANKS ? 0 : info); + return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info); } /*----------------------------------------------------------------------- @@ -336,7 +336,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { udelay(1000); while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); if (intel) { /* suspend erase */ @@ -347,14 +347,14 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) { break; } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc('.'); last = get_timer(0); } } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc('.'); last = get_timer(0); @@ -452,7 +452,7 @@ static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) { /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ res = 1; } diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index 7970f8988..f7962afa5 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -32,6 +32,7 @@ #include <mpc5xxx.h> #include <pci.h> #include <command.h> +#include <netdev.h> #include "mt46v16m16-75.h" @@ -80,7 +81,7 @@ static void sdram_start(int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -105,9 +106,9 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); @@ -143,9 +144,9 @@ phys_size_t initdram(int board_type) #if 0 /* find RAM size using SDRAM CS1 only */ sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(0); #endif /* set SDRAM CS1 size according to the amount of RAM found */ @@ -179,10 +180,10 @@ void flash_afterinit(ulong size) /* adjust mapping */ *(vu_long *) MPC5XXX_BOOTCS_START = *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *) MPC5XXX_BOOTCS_STOP = *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } @@ -257,13 +258,18 @@ void init_power_switch(void) *(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0; __asm__ volatile ("sync"); } - *(vu_char *) CFG_CS1_START = 0x02; /* Red Power LED on */ + *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */ __asm__ volatile ("sync"); - *(vu_char *) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */ + *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */ __asm__ volatile ("sync"); } +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + void power_set_reset(int power) { debug("ide_set_reset(%d)\n", power); diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 25b210579..0fb4efab8 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -25,5 +25,4 @@ # esd PLU405 boards # -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 +TEXT_BASE = 0xFFFA0000 diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/plu405/flash.c +++ b/board/esd/plu405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index fc71e9a2a..61186a8d7 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -65,11 +65,9 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - /* Prototypes */ int gunzip(void *, int, unsigned char *, unsigned long *); - int board_early_init_f (void) { /* @@ -89,24 +87,18 @@ int board_early_init_f (void) mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + * EBC Configuration Register: set ready timeout to + * 512 ebc-clks -> ca. 15 us */ mtebc (epcr, 0xa8400000); /* ebc always driven */ return 0; } - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); @@ -121,8 +113,8 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -132,13 +124,16 @@ int misc_init_r (void) printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: INIT not low " + "after asserting PROGRAM*)\n"); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: INIT not high " + "after deasserting PROGRAM*)\n"); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); + printf("(Timeout: DONE not high " + "after programming FPGA)\n"); break; } @@ -184,22 +179,23 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ - udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ - udelay(1000); /* wait 1ms */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); + udelay(10); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); + udelay(1000); /* * Set NAND-FLASH GPIO signals to default */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); /* * Setup EEPROM write protection */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); /* * Enable interrupts in exar duart mcr[3] @@ -210,7 +206,6 @@ int misc_init_r (void) return (0); } - /* * Check Board Identity: */ @@ -231,36 +226,23 @@ int checkboard (void) return 0; } - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; } } #endif /* CONFIG_IDE_RESET */ - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP @@ -272,8 +254,7 @@ void reset_phy(void) #endif } - -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state * 0: disable write @@ -284,23 +265,26 @@ void reset_phy(void) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void*)GPIO0_OR) & + CONFIG_SYS_EEPROM_WP)); break; } } @@ -314,21 +298,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -341,4 +325,4 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds index d70d37934..fd5f3dfd1 100644 --- a/board/esd/plu405/u-boot.lds +++ b/board/esd/plu405/u-boot.lds @@ -61,19 +61,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -124,7 +111,6 @@ SECTIONS .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; - . = .; __start___ex_table = .; __ex_table : { *(__ex_table) } @@ -144,6 +130,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 326d56035..c0781dc95 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -72,23 +72,23 @@ int board_early_init_f (void) * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \ - CFG_FPGA_DONE | \ - CFG_XEREADY | \ - CFG_NONMONARCH | \ - CFG_REV1_2) << 5)); + mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \ + CONFIG_SYS_FPGA_DONE | \ + CONFIG_SYS_XEREADY | \ + CONFIG_SYS_NONMONARCH | \ + CONFIG_SYS_REV1_2) << 5)); - if (!(in32(GPIO0_IR) & CFG_REV1_2)) { + if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) { /* rev 1.2 boards */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \ - CFG_SELF_RST) << 5)); + mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \ + CONFIG_SYS_SELF_RST) << 5)); } out32(GPIO0_OR, 0); - out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */ + out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */ /* - check if rev1_2 is low, then: - * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST# + * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST# */ return 0; @@ -104,7 +104,7 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */ + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */ return (0); } @@ -112,13 +112,13 @@ ushort pmc405_pci_subsys_deviceid(void) { ulong val; val = in32(GPIO0_IR); - if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ - if (val & CFG_NONMONARCH) { /* monarch# signal */ - return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; + if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ + if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ + return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; } - return CFG_PCI_SUBSYS_DEVICEID_MONARCH; + return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH; } - return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH; + return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; } /* @@ -140,9 +140,9 @@ int checkboard (void) } val = in32(GPIO0_IR); - if (!(val & CFG_REV1_2)) { /* low=rev1.2 */ + if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ puts(" rev1.2 ("); - if (val & CFG_NONMONARCH) { /* monarch# signal */ + if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ puts("non-"); } puts("monarch)"); @@ -156,24 +156,6 @@ int checkboard (void) } /* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - - -/* ------------------------------------------------------------------------- */ void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds index 81ee614f6..ca615f509 100644 --- a/board/esd/pmc405/u-boot.lds +++ b/board/esd/pmc405/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -142,6 +142,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index ca5c177e3..16c9c7eea 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -26,6 +26,9 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/processor.h> +#if defined(CONFIG_LOGBUFFER) +#include <logbuff.h> +#endif #include "pmc440.h" @@ -323,7 +326,7 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] } printf("Writing boot EEPROM ...\n"); - if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR, + if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0, (uchar*)sdsdp, count) != 0) printf("bootstrap_eeprom_write failed\n"); else @@ -343,14 +346,11 @@ extern env_t *env_ptr; int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - u32 memsize; - u32 pram, env_base; + u32 pram, nextbase, base; char *v; u32 param; ulong *lptr; - memsize = gd->bd->bi_memsize; - v = getenv("pram"); if (v) pram = simple_strtoul(v, NULL, 10); @@ -359,21 +359,42 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - param = memsize - (pram << 10); + base = gd->bd->bi_memsize; +#if defined(CONFIG_LOGBUFFER) + base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD; +#endif + /* + * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE + */ + param = base - (pram << 10); printf("PARAM: @%08x\n", param); + debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base); + /* clear entire PA ram */ memset((void*)param, 0, (pram << 10)); - env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1)); - memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE); - lptr = (ulong*)memsize; - *(--lptr) = CFG_ENV_SIZE; - *(--lptr) = memsize - env_base; - *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08); - *(--lptr) = 0; + /* reserve 4k for pointer field */ + nextbase = base - 4096; + lptr = (ulong*)(base); + + /* + * *(--lptr) = item_size; + * *(--lptr) = base - item_base = distance from field top; + */ + + /* env is first (4k aligned) */ + nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1)); + memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE); + *(--lptr) = CONFIG_ENV_SIZE; /* size */ + *(--lptr) = base - nextbase; /* offset | type=0 */ + + /* free section */ + *(--lptr) = nextbase - param; /* size */ + *(--lptr) = (base - param) | 126; /* offset | type=126 */ - /* make sure data can be accessed through PCI */ - flush_dcache_range(param, param + (pram << 10) - 1); + /* terminate pointer field */ + *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10); + *(--lptr) = 0; /* offset=0 -> terminator */ return 0; } U_BOOT_CMD( @@ -385,28 +406,11 @@ U_BOOT_CMD( int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - if (argc > 1) { - if (argv[1][0] == '0') { - /* assert */ - printf("self-reset# asserted\n"); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST); - } else { - /* deassert */ - printf("self-reset# deasserted\n"); - out_be32((void*)GPIO0_TCR, - in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST); - } - } else { - printf("self-reset# is %s\n", - in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ? - "active" : "inactive"); - } - + in_be32((void*)CONFIG_SYS_RESET_BASE); return 0; } U_BOOT_CMD( - selfreset, 2, 1, do_selfreset, + selfreset, 1, 1, do_selfreset, "selfreset- assert self-reset# signal\n", NULL ); @@ -513,7 +517,7 @@ U_BOOT_CMD( "<pciaddr> (pciaddr will be aligned to 256MB)\n" ); -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int query = argc == 1; @@ -521,21 +525,21 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts("Query of write access state failed.\n"); } else { printf("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts("Setup of write access state failed.\n"); @@ -547,6 +551,6 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ #endif /* CONFIG_CMD_BSP */ diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk index e62b8d30e..0c4d58282 100644 --- a/board/esd/pmc440/config.mk +++ b/board/esd/pmc440/config.mk @@ -37,5 +37,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index a35f42bd5..a2eda32ac 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -220,8 +220,9 @@ int fpga_post_config_fn(int cookie) FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); - /* NGCC only: enable ledlink */ - if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) + /* NGCC/CANDES only: enable ledlink */ + if ((s = getenv("bd_type")) && + ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); return rc; diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index 148af71bb..26a8282ce 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -44,28 +44,28 @@ tlbtab: * speed up boot process. It is patched after relocation to enable SA_I */ #ifndef CONFIG_NAND_SPL - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) #else - tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for DDR SDRAM (Up to 2GB) */ #ifdef CONFIG_4xx_DCACHE - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) #else - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) #endif -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entries for EBC */ /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral @@ -76,7 +76,7 @@ tlbtab: tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for NAND */ - tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) @@ -98,8 +98,8 @@ tlbtab: * For NAND booting the first TLB has to be reconfigured to full size * and with caching disabled after running from RAM! */ -#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) +#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) +#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) .globl reconfig_tlb0 diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index 0cdaee445..382410534 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (Cg) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * Based on board/amcc/sequoia/sequoia.c * @@ -44,10 +44,12 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern void __ft_board_setup(void *blob, bd_t *bd); ulong flash_get_size(ulong base, int banknum); int pci_is_66mhz(void); +int is_monarch(void); int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt); @@ -71,7 +73,7 @@ struct serial_device *default_serial_console(void) /* mark scratchreg valid */ scratchreg = (scratchreg & 0xffffff00) | 0x80; - i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, + i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4); if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) { scratchreg |= buf[2]; @@ -103,13 +105,13 @@ int board_early_init_f(void) /* * Setup the GPIO pins - * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file + * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file */ - out32(GPIO0_OR, 0x40000002); + out32(GPIO0_OR, 0x40000102); out32(GPIO0_TCR, 0x4c90011f); - out32(GPIO0_OSRL, 0x28011400); + out32(GPIO0_OSRL, 0x28051400); out32(GPIO0_OSRH, 0x55005000); - out32(GPIO0_TSRL, 0x08011400); + out32(GPIO0_TSRL, 0x08051400); out32(GPIO0_TSRH, 0x55005000); out32(GPIO0_ISR1L, 0x54000000); out32(GPIO0_ISR1H, 0x00000000); @@ -190,12 +192,29 @@ int board_early_init_f(void) SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | - (0x80000000 >> (28 + CFG_NAND_CS)); + (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); mtsdr(SDR0_CUST0, sdr0_cust0); return 0; } +#if defined(CONFIG_MISC_INIT_F) +int misc_init_f(void) +{ + struct pci_controller hose; + hose.first_busno = 0; + hose.last_busno = 0; + hose.region_count = 0; + + if (getenv("pciearly") && (!is_monarch())) { + printf("PCI: early target init\n"); + pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA); + pci_target_init(&hose); + } + return 0; +} +#endif + /* * misc_init_r. */ @@ -207,6 +226,7 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; + unsigned long sdr0_srst0, sdr0_srst1; char *act = getenv("usbact"); /* @@ -239,24 +259,24 @@ int misc_init_r(void) */ flash_get_size(gd->bd->bi_flashstart, 0); -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif /* * USB suff... */ - if ((act == NULL || strcmp(act, "hostdev") == 0) && + if ((act == NULL || strcmp(act, "host") == 0) && !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){ /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -290,12 +310,46 @@ int misc_init_r(void) mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); - /* clear resets */ + /* + * Take USB out of reset: + * -Initial status = all cores are in reset + * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores + * -wait 1 ms + * -deassert reset to PHY + * -wait 1 ms + * -deassert reset to HOST + * -wait 4 ms + * -deassert all other resets + */ + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \ + SDR0_SRST1_P4OPB0 | \ + SDR0_SRST1_OPBA2 | \ + SDR0_SRST1_PLB42OPB1 | \ + SDR0_SRST1_OPB2PLB40); + mtsdr(SDR0_SRST1, sdr0_srst1); + udelay(1000); + + mfsdr(SDR0_SRST1, sdr0_srst1); + sdr0_srst1 &= ~SDR0_SRST1_USB20PHY; + mtsdr(SDR0_SRST1, sdr0_srst1); udelay(1000); + + mfsdr(SDR0_SRST0, sdr0_srst0); + sdr0_srst0 &= ~SDR0_SRST0_USB2H; + mtsdr(SDR0_SRST0, sdr0_srst0); + udelay(4000); + + /* finally all the other resets */ mtsdr(SDR0_SRST1, 0x00000000); - udelay(1000); mtsdr(SDR0_SRST0, 0x00000000); + if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) { + /* enable power on USB socket */ + out_be32((void*)GPIO1_OR, + in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N); + } + printf("USB: Host\n"); } else if ((strcmp(act, "dev") == 0) || @@ -498,7 +552,7 @@ int pci_pre_init(struct pci_controller *hose) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { char *ptmla_str, *ptmms_str; @@ -516,8 +570,8 @@ void pci_target_init(struct pci_controller *hose) */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ /* and enable region */ @@ -547,14 +601,14 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); } else { - /* BAR2: default: 16 MB FPGA + registers */ - out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */ + /* BAR2: default: 4MB FPGA */ + out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ } if (is_monarch()) { /* BAR2: map FPGA registers behind system memory at 1GB */ - pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008); + pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008); } /* @@ -562,8 +616,8 @@ void pci_target_init(struct pci_controller *hose) */ /* Program the board's vendor id */ - pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); /* disabled for PMC405 backward compatibility */ /* Configure command register as bus master */ @@ -571,19 +625,19 @@ void pci_target_init(struct pci_controller *hose) /* 240nS PCI clock */ - pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1); /* No error reporting */ - pci_write_config_word(0, PCI_ERREN, 0); + pci_hose_write_config_word(hose, 0, PCI_ERREN, 0); pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); if (!is_monarch()) { /* Program the board's subsystem id/classcode */ - pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CFG_PCI_SUBSYS_ID_NONMONARCH); - pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CFG_PCI_CLASSCODE_NONMONARCH); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, + CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH); + pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, + CONFIG_SYS_PCI_CLASSCODE_NONMONARCH); /* PCI configuration done: release ERREADY */ out_be32((void*)GPIO1_OR, @@ -592,18 +646,21 @@ void pci_target_init(struct pci_controller *hose) in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY); } else { /* Program the board's subsystem id/classcode */ - pci_write_config_word(0, PCI_SUBSYSTEM_ID, - CFG_PCI_SUBSYS_ID_MONARCH); - pci_write_config_word(0, PCI_CLASS_SUB_CODE, - CFG_PCI_CLASSCODE_MONARCH); + pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID, + CONFIG_SYS_PCI_SUBSYS_ID_MONARCH); + pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE, + CONFIG_SYS_PCI_CLASSCODE_MONARCH); } + + /* enable host configuration */ + pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /* * pci_master_init */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -620,12 +677,18 @@ void pci_master_init(struct pci_controller *hose) PCI_COMMAND_MEMORY); } } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ static void wait_for_pci_ready(void) { int i; char *s = getenv("pcidelay"); + /* + * We have our own handling of the pcidelay variable. + * Using CONFIG_PCI_BOOTDELAY enables pausing for host + * and adapter devices. For adapter devices we do not + * want this. + */ if (s) { int ms = simple_strtoul(s, NULL, 10); printf("PCI: Waiting for %d ms\n", ms); @@ -692,23 +755,37 @@ int post_hotkeys_pressed(void) #ifdef CONFIG_RESET_PHY_R void reset_phy(void) { + char *s; + unsigned short val_method, val_behavior; + + /* special LED setup for NGCC/CANDES */ + if ((s = getenv("bd_type")) && + ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) { + val_method = 0x0e0a; + val_behavior = 0x0cf2; + } else { + /* PMC440 standard type */ + val_method = 0x0e10; + val_behavior = 0x0cf0; + } + if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) { miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0); - miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior); + miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method); miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000); } if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) { miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0); - miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior); + miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method); miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000); } } #endif -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* * Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state @@ -720,8 +797,8 @@ void reset_phy(void) */ int eeprom_write_enable(unsigned dev_addr, int state) { - if ((CFG_I2C_EEPROM_ADDR != dev_addr) && - (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) { + if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) && + (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) { return -1; } else { switch (state) { @@ -743,9 +820,9 @@ int eeprom_write_enable(unsigned dev_addr, int state) } return state; } -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ -#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt) { @@ -753,7 +830,7 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, unsigned blk_off; int rcode = 0; -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 1); #endif /* @@ -776,7 +853,7 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, len = end - offset; -#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS) +#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS) #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1)) maxlen = BOOT_EEPROM_PAGE_SIZE - @@ -793,11 +870,11 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, buffer += len; offset += len; -#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif } -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) eeprom_write_enable(dev_addr, 0); #endif return rcode; @@ -845,13 +922,13 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, return rcode; } -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) int usb_board_init(void) { char *act = getenv("usbact"); int i; - if ((act == NULL || strcmp(act, "hostdev") == 0) && + if ((act == NULL || strcmp(act, "host") == 0) && !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) /* enable power on USB socket */ out_be32((void*)GPIO1_OR, @@ -875,4 +952,25 @@ int usb_board_init_fail(void) usb_board_stop(); return 0; } -#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int rc; + + __ft_board_setup(blob, bd); + + /* + * Disable PCI in non-monarch mode. + */ + if (!is_monarch()) { + rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) { + printf("Unable to update property status in PCI node, err=%s\n", + fdt_strerror(rc)); + } + } +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h index 7e70fd1cb..295cec1e3 100644 --- a/board/esd/pmc440/pmc440.h +++ b/board/esd/pmc440/pmc440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * * See file CREDITS for list of people who contributed to this @@ -24,8 +24,7 @@ #ifndef __PMC440_H__ #define __PMC440_H__ - -/*----------------------------------------------------------------------- +/* * GPIOs */ #define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */ @@ -41,9 +40,10 @@ #define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */ #define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */ #define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */ -#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */ -/* FPGA programming pin configuration */ +/* + * FPGA programming pin configuration + */ #define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */ #define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */ #define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */ @@ -51,10 +51,10 @@ #define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */ #define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */ -/*----------------------------------------------------------------------- +/* * FPGA interface */ -#define FPGA_BA CFG_FPGA_BASE0 +#define FPGA_BA CONFIG_SYS_FPGA_BASE0 #define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v)) #define FPGA_IN32(p) in_be32((void*)(p)) #define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v)) @@ -103,7 +103,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define RESET_OUT (1 << 19) #define IRIGB_R_OUT (1 << 14) - /* status register */ #define STATUS_VERSION_SHIFT 24 #define STATUS_VERSION_MASK 0xff000000 @@ -115,13 +114,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define STATUS_FIFO_ISF (1 << 9) #define STATUS_HOST_ISF (1 << 8) - /* inputs */ #define RESET_IN (1 << 0) #define CLOCK_IN (1 << 1) #define IRIGB_R_IN (1 << 5) - /* hostctrl register */ #define HOSTCTRL_PMCRSTOUT_GATE (1 << 17) #define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16) @@ -134,10 +131,10 @@ typedef struct pmc440_fpga_s pmc440_fpga_t; #define HOSTCTRL_HCINT_GATE (1 << 1) #define HOSTCTRL_HCINT_FLAG (1 << 0) -#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000) +#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000) #define NGCC_CTRL_FPGARST_N (1 << 2) -/*----------------------------------------------------------------------- +/* * FPGA to PPC interrupt */ #define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */ diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index c7294c994..197857ad0 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -111,5 +111,5 @@ phys_size_t initdram (int board_type) */ set_mcsr(get_mcsr()); - return (CFG_MBYTES_SDRAM << 20); + return (CONFIG_SYS_MBYTES_SDRAM << 20); } diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index ae2e18de4..6e1e16997 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -57,7 +57,7 @@ SECTIONS /* Align to next NAND block */ . = ALIGN(0x4000); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) /* Keep some space here for redundant env and potential bad env blocks */ . = ALIGN(0x10000); @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/esd/pmc440/u-boot.lds b/board/esd/pmc440/u-boot.lds index b20fb1c0a..05152b7f7 100644 --- a/board/esd/pmc440/u-boot.lds +++ b/board/esd/pmc440/u-boot.lds @@ -135,9 +135,10 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c index 13c07d2d3..ce905e94c 100644 --- a/board/esd/tasreg/flash.c +++ b/board/esd/tasreg/flash.c @@ -45,13 +45,13 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", @@ -65,8 +65,8 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+CFG_MONITOR_LEN-1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); flash_info[0].size = size_b0; diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c index fabb7464f..64e6d6329 100644 --- a/board/esd/tasreg/tasreg.c +++ b/board/esd/tasreg/tasreg.c @@ -40,8 +40,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); /* predefine these here for FPGA programming (before including fpga.c) */ #define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data) -#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_DONE) -#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_INIT) +#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE) +#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT) #define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */ #define out32(a,b) /* nothing to do (gpio already configured) */ @@ -70,7 +70,7 @@ int checkboard (void) { /* * Set LED on */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED; mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ return 0; @@ -85,13 +85,13 @@ phys_size_t initdram (int board_type) { * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 */ -#ifdef CFG_FAST_CLK +#ifdef CONFIG_SYS_FAST_CLK /* * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 */ mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CFG_PLL_BYPASS +#elif CONFIG_SYS_PLL_BYPASS /* * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 @@ -129,7 +129,7 @@ phys_size_t initdram (int board_type) { mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; @@ -150,8 +150,8 @@ int misc_init_r (void) int i; uchar buf[8]; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index afdb7202c..aec7e9bf4 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/voh405/flash.c +++ b/board/esd/voh405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds index d70d37934..d8fbea396 100644 --- a/board/esd/voh405/u-boot.lds +++ b/board/esd/voh405/u-boot.lds @@ -66,14 +66,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -144,6 +144,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 52534220a..ec65ffd43 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -104,21 +104,14 @@ int board_early_init_f (void) return 0; } - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); unsigned short *lcd_contrast = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4); unsigned short *lcd_backlight = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6); unsigned char *dst; ulong len = sizeof(fpgadata); int status; @@ -126,8 +119,8 @@ int misc_init_r (void) int i; char *str; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -190,22 +183,22 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* * Set NAND-FLASH GPIO signals to default */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE); /* * Setup EEPROM write protection */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP); /* * Enable interrupts in exar duart mcr[3] @@ -219,29 +212,29 @@ int misc_init_r (void) str = getenv("bd_type"); if (strcmp(str, "voh405_bw") == 0) { lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); } else if (strcmp(str, "voh405_bwbw") == 0) { lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); lcd_setup(1, 1); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_320_240_4bpp, sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); } else if (strcmp(str, "voh405_bwc") == 0) { lcd_setup(0, 1); - lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, regs_13704_320_240_4bpp, sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]), logo_bmp_320, sizeof(logo_bmp_320)); lcd_setup(1, 0); - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, + lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, regs_13806_640_480_16bpp, sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), logo_bmp_640, sizeof(logo_bmp_640)); @@ -253,8 +246,8 @@ int misc_init_r (void) /* * Set invert bit in small lcd controller */ - out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2), - in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01); + out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2), + in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01); /* * Set default contrast voltage on epson vga controller @@ -269,7 +262,7 @@ int misc_init_r (void) /* * Enable external I2C bus */ - out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON); return (0); } @@ -303,48 +296,19 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - -int testdram (void) -{ - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); - - return (0); -} - -/* ------------------------------------------------------------------------- */ - #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); + *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; + *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; } } #endif /* CONFIG_IDE_RESET */ @@ -362,7 +326,7 @@ void reset_phy(void) } #endif -#if defined(CFG_EEPROM_WREN) +#if defined(CONFIG_SYS_EEPROM_WREN) /* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state * 0: disable write @@ -373,23 +337,23 @@ void reset_phy(void) */ int eeprom_write_enable (unsigned dev_addr, int state) { - if (CFG_I2C_EEPROM_ADDR != dev_addr) { + if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO0. */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP); + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP)); + state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); break; } } @@ -403,21 +367,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (query) { /* Query write access state. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1); if (state < 0) { puts ("Query of write access state failed.\n"); } else { printf ("Write access for device 0x%0x is %sabled.\n", - CFG_I2C_EEPROM_ADDR, state ? "en" : "dis"); + CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis"); state = 0; } } else { if ('0' == argv[1][0]) { /* Disable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0); } else { /* Enable write access. */ - state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1); + state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1); } if (state < 0) { puts ("Setup of write access state failed.\n"); @@ -430,4 +394,4 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, "eepwren - Enable / disable / query EEPROM write access\n", NULL); -#endif /* #if defined(CFG_EEPROM_WREN) */ +#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/vom405/flash.c +++ b/board/esd/vom405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds index 21547ac27..c9472f934 100644 --- a/board/esd/vom405/u-boot.lds +++ b/board/esd/vom405/u-boot.lds @@ -61,18 +61,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index af8efcff3..1b1479f43 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -37,7 +37,6 @@ const unsigned char fpgadata[] = }; int filesize = sizeof(fpgadata); - int board_early_init_f (void) { /* @@ -76,9 +75,6 @@ int board_early_init_f (void) return 0; } - -/* ------------------------------------------------------------------------- */ - int misc_init_r (void) { /* adjust flash start and offset */ @@ -88,11 +84,9 @@ int misc_init_r (void) return (0); } - /* * Check Board Identity: */ - int checkboard (void) { char str[64]; @@ -127,25 +121,6 @@ int checkboard (void) return 0; } -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} - -/* ------------------------------------------------------------------------- */ - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c index 89af1190a..274ada9fe 100644 --- a/board/esd/wuh405/flash.c +++ b/board/esd/wuh405/flash.c @@ -48,7 +48,7 @@ unsigned long flash_init (void) int size_val = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,7 +91,7 @@ unsigned long flash_init (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds index 644174a46..e2e2512e7 100644 --- a/board/esd/wuh405/u-boot.lds +++ b/board/esd/wuh405/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -142,6 +142,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index 0590fc78f..5eca3bd38 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -80,15 +80,6 @@ int board_early_init_f (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) -{ - return 0; /* dummy implementation */ -} - - int misc_init_r (void) { volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); @@ -101,8 +92,8 @@ int misc_init_r (void) int index; int i; - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf ("GUNZIP ERROR - must RESET board to recover\n"); do_reset (NULL, 0, 0, NULL); } @@ -164,9 +155,9 @@ int misc_init_r (void) /* * Reset external DUARTs */ - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */ udelay(10); /* wait 10us */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */ udelay(1000); /* wait 1ms */ /* @@ -202,15 +193,3 @@ int checkboard (void) return 0; } - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - unsigned long val; - - mtdcr(memcfga, mem_mb0cf); - val = mfdcr(memcfgd); - - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); -} diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c index f3c8662cd..b784cbb5b 100644 --- a/board/esteem192e/esteem192e.c +++ b/board/esteem192e/esteem192e.c @@ -103,7 +103,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1; @@ -113,7 +113,7 @@ phys_size_t initdram (int board_type) memctl->memc_mptpr = 0x0200; /* divide by 32 */ - memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ + memctl->memc_mamr = 0x18003112; /*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); @@ -124,11 +124,11 @@ phys_size_t initdram (int board_type) * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */ - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */ + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; /* perform SDRAM initializsation sequence */ @@ -139,7 +139,7 @@ phys_size_t initdram (int board_type) memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */ memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ /* printf ("banks 0 and 1 are programed\n"); */ diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c index d5eb2019b..cce73fa7b 100644 --- a/board/esteem192e/flash.c +++ b/board/esteem192e/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #ifdef CONFIG_FLASH_16BIT #define FLASH_WORD_SIZE unsigned short @@ -54,13 +54,13 @@ static void flash_get_offsets (ulong base, flash_info_t * info); */ unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -91,44 +91,44 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801; /* (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */ + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = CONFIG_SYS_FLASH_BASE | 0x00000801; /* (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */ /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE, + size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif if (size_b1) { memctl->memc_or1 = - CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); memctl->memc_br1 = - (CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK); - /*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + (CONFIG_SYS_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK); + /*((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; */ /* Re-do sizing to get full correct info */ size_b1 = flash_get_size ((volatile FLASH_WORD_SIZE - *) (CFG_FLASH_BASE + size_b0), + *) (CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]); #endif } else { @@ -769,7 +769,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -1022,7 +1022,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -1030,7 +1030,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) } else { while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } @@ -1096,7 +1096,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) if (info->flash_id < FLASH_AMD_COMP) { /* AMD stuff */ while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -1104,7 +1104,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) } else { /* intel stuff */ while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } @@ -1123,7 +1123,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) *addr = 0x00B0; *addr = 0x0070; while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } *addr = 0x00FF; diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index acaf4e34f..c4e17d6ee 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c index 763760fd2..227c49a14 100644 --- a/board/etin/debris/debris.c +++ b/board/etin/debris/debris.c @@ -25,6 +25,7 @@ #include <mpc824x.h> #include <pci.h> #include <i2c.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -62,7 +63,7 @@ phys_size_t initdram (int board_type) uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0; uint8_t mber = 0; - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */ m = i2c_reg_read (0x50, 5); /* # of physical banks */ @@ -73,7 +74,7 @@ phys_size_t initdram (int board_type) CONFIG_READ_WORD(MCCR1, mccr1); mccr1 &= 0xffff0000; - start = CFG_SDRAM_BASE; + start = CONFIG_SYS_SDRAM_BASE; end = start + (1 << (col + row + 3) ) * bank - 1; for (i = 0; i < m; i++) { @@ -173,7 +174,12 @@ void nvram_write(long dest, const void *src, size_t count) int misc_init_r(void) { /* Write ethernet addr in NVRAM for VxWorks */ - nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS, + nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS, (char*)&gd->bd->bi_enetaddr[0], 6); return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c index a4100e57b..a3c813884 100644 --- a/board/etin/debris/flash.c +++ b/board/etin/debris/flash.c @@ -71,7 +71,7 @@ static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr) return (uint16_t)read32(base + addr); } -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ static void move64(uint64_t *src, uint64_t *dest) { @@ -99,7 +99,7 @@ static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data) status &= CMD(0x80); if(status == CMD(0x80)) break; - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { cfi_cmd(flash, 0xff, 0); return 1; } @@ -128,7 +128,7 @@ static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data) start = get_timer (0); status = ~data; while(status != data) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return 1; status = cfi_read(flash, dest); udelay(1); @@ -230,7 +230,7 @@ static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect) status &= CMD(0x80); if (status == CMD(0x80)) break; - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { cfi_cmd(flash, 0xff, 0); printf ("Timeout\n"); return ERR_TIMOUT; @@ -296,7 +296,7 @@ static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last) if (status == CMD(0xffff)) break; - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return ERR_TIMOUT; } @@ -581,7 +581,7 @@ unsigned long flash_init (void) mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP); set_msr(msr); - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) flash_info[i].flash_id = FLASH_UNKNOWN; size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]); if (!size) diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c index 263da6b7c..fcb4c40ea 100644 --- a/board/etin/debris/phantom.c +++ b/board/etin/debris/phantom.c @@ -20,7 +20,7 @@ #if defined(CONFIG_CMD_DATE) -#define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8) +#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8) #define RTC_YEAR ( RTC_BASE + 7 ) #define RTC_MONTH ( RTC_BASE + 6 ) @@ -254,7 +254,7 @@ int rtc_get( struct rtc_time *tmp) return 0; } -void rtc_set( struct rtc_time *tmp ) +int rtc_set( struct rtc_time *tmp ) { if (phantom_flag < 0) phantom_flag = get_phantom_flag(); @@ -307,6 +307,8 @@ void rtc_set( struct rtc_time *tmp ) /* unlock clock registers after read */ rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE )); } + + return 0; } #endif diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c index bfd6854c5..8c6afc9ca 100644 --- a/board/etin/kvme080/kvme080.c +++ b/board/etin/kvme080/kvme080.c @@ -25,6 +25,7 @@ #include <mpc824x.h> #include <pci.h> #include <i2c.h> +#include <netdev.h> #include <asm/processor.h> int checkboard(void) @@ -45,7 +46,7 @@ unsigned long setdram(int m, int row, int col, int bank) CONFIG_READ_WORD(MCCR1, mccr1); mccr1 &= 0xffff0000; - start = CFG_SDRAM_BASE; + start = CONFIG_SYS_SDRAM_BASE; end = start + (1 << (col + row + 3) ) * bank - 1; for (i = 0; i < m; i++) { @@ -100,31 +101,31 @@ phys_size_t initdram(int board_type) msr = mfmsr(); mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT2L, CFG_IBAT0L + 0x10000000); - mtspr(IBAT2U, CFG_IBAT0U + 0x10000000); - mtspr(DBAT2L, CFG_DBAT0L + 0x10000000); - mtspr(DBAT2U, CFG_DBAT0U + 0x10000000); + mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000); + mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000); + mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000); + mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000); mtmsr(msr); - if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000)) + if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000)) size = 0x20000000; /* 512MB */ - else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000)) + else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000)) size = 0x10000000; /* 256MB */ - else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000)) + else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000)) size = 0x10000000; /* 256MB */ - else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000)) + else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000)) size = 0x08000000; /* 128MB */ - else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000)) + else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000)) size = 0x08000000; /* 128MB */ - else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000)) + else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000)) size = 0x04000000; /* 64MB */ msr = mfmsr(); mtmsr(msr & ~(MSR_IR | MSR_DR)); - mtspr(IBAT2L, CFG_IBAT2L); - mtspr(IBAT2U, CFG_IBAT2U); - mtspr(DBAT2L, CFG_DBAT2L); - mtspr(DBAT2U, CFG_DBAT2U); + mtspr(IBAT2L, CONFIG_SYS_IBAT2L); + mtspr(IBAT2U, CONFIG_SYS_IBAT2U); + mtspr(DBAT2L, CONFIG_SYS_DBAT2L); + mtspr(DBAT2U, CONFIG_SYS_DBAT2U); mtmsr(msr); return size; @@ -191,3 +192,8 @@ void nvram_write(long dest, const void *src, size_t count) asm volatile("sync"); } } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c index 7806519e3..d6f638af6 100644 --- a/board/etx094/etx094.c +++ b/board/etx094/etx094.c @@ -127,7 +127,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1, size8, size9; @@ -140,7 +140,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */ + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; /* MPTPR_PTP_DIV32 0x0200 */ /* A3(SDRAM)=0 => Bursttype = Sequential * A2-A0(SDRAM)=010 => Burst length = 4 @@ -153,15 +153,15 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; if (board_type == 0) { /* "L" type boards have only one bank SDRAM */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; } - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -186,7 +186,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -194,7 +194,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -202,7 +202,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -230,7 +230,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /*DIV16 */ + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /*DIV16 */ udelay (1000); } @@ -239,18 +239,18 @@ phys_size_t initdram (int board_type) */ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br3 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* * Position Bank 0 immediately above Bank 1 */ memctl->memc_or2 = - ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { unsigned long reg; @@ -264,24 +264,24 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b1 > 0) { /* * Position Bank 1 immediately above Bank 0 */ memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br3 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b0; } else { unsigned long reg; @@ -295,7 +295,7 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } @@ -318,7 +318,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -343,7 +343,7 @@ void read_hw_vers () unsigned short rd_msk = 0x02A0; /* HW-ID pin-definition */ - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; immr->im_ioport.iop_pddir &= ~(rd_msk); immr->im_ioport.iop_pdpar &= ~(rd_msk); diff --git a/board/etx094/flash.c b/board/etx094/flash.c index 98a7c0c8d..fa51c9037 100644 --- a/board/etx094/flash.c +++ b/board/etx094/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -75,47 +75,47 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); #ifdef CONFIG_FLASH_16BIT - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */ #else - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; #endif /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); #ifdef CONFIG_FLASH_16BIT - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; #else - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; #endif /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif } else { @@ -388,10 +388,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { @@ -548,7 +548,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) #else while ((sect_addr[0] & 0x00800080) != 0x00800080) { #endif - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -693,7 +693,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -733,7 +733,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { #endif - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds index 5313bd40a..340825e81 100644 --- a/board/etx094/u-boot.lds +++ b/board/etx094/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -136,6 +136,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug index 06115ead8..28f8804dc 100644 --- a/board/etx094/u-boot.lds.debug +++ b/board/etx094/u-boot.lds.debug @@ -68,7 +68,7 @@ SECTIONS lib_generic/crc32.o (.text) common/dlmalloc.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/evb4510/flash.c b/board/evb4510/flash.c index aff92f95e..c9c6e024c 100644 --- a/board/evb4510/flash.c +++ b/board/evb4510/flash.c @@ -26,7 +26,7 @@ #include <asm/hardware.h> #include <flash.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; typedef enum { FLASH_DEV_U9_512KB = 0, @@ -327,7 +327,7 @@ unsigned long flash_init (void) s16 amd160 = -1; u32 amd160base = 0; -#if CFG_MAX_FLASH_BANKS == 2 +#if CONFIG_SYS_MAX_FLASH_BANKS == 2 s16 amd040 = -1; u32 amd040base = 0; #endif @@ -336,7 +336,7 @@ unsigned long flash_init (void) if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) { amd160 = 0; amd160base = PHYS_FLASH_1; -#if CFG_MAX_FLASH_BANKS == 1 +#if CONFIG_SYS_MAX_FLASH_BANKS == 1 } #else if (_detectFlash @@ -399,9 +399,9 @@ unsigned long flash_init (void) amd160base, amd160base + monitor_flash_len - 1, info); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, info); + CONFIG_ENV_ADDR, CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, info); -#if CFG_MAX_FLASH_BANKS == 2 +#if CONFIG_SYS_MAX_FLASH_BANKS == 2 /* Configure AMD Am29LV040B (512KB) */ info = &flash_info[amd040]; info->flash_id = FLASH_DEV_U9_512KB; @@ -421,7 +421,7 @@ unsigned long flash_init (void) #endif return flash_info[0].size -#if CFG_MAX_FLASH_BANKS == 2 +#if CONFIG_SYS_MAX_FLASH_BANKS == 2 + flash_info[1].size #endif ; @@ -478,7 +478,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) error = _flash_poll (info->flash_id, info-> start[i] | CACHE_DISABLE_MASK, - 0xFF, CFG_FLASH_ERASE_TOUT); + 0xFF, CONFIG_SYS_FLASH_ERASE_TOUT); FLASH_CMD_RESET (info->flash_id, (info-> start[0] | CACHE_DISABLE_MASK)); @@ -524,7 +524,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* Check if the write is done */ for (i = 0; i < 0xff; i++); error = _flash_poll (info->flash_id, (u32) bp, *bps, - CFG_FLASH_WRITE_TOUT); + CONFIG_SYS_FLASH_WRITE_TOUT); if (error) { return error; } diff --git a/board/evb4510/u-boot.lds b/board/evb4510/u-boot.lds index b3c2bf950..a435466d4 100644 --- a/board/evb4510/u-boot.lds +++ b/board/evb4510/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/board/evb64260/bootseq.txt b/board/evb64260/bootseq.txt index 290aed90a..e4fefb31d 100644 --- a/board/evb64260/bootseq.txt +++ b/board/evb64260/bootseq.txt @@ -88,7 +88,7 @@ in_flash: nothing mem_malloc_init malloc_bin_reloc - spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) env_relocated misc_init_r(bd): (board/evb64260/evb64260.c) mpsc_init2 diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index fa5b6d4a9..ca8bab52d 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -27,6 +27,7 @@ Skeleton NIC driver for Etherboot #include <asm/cache.h> #include <miiphy.h> #include <net.h> +#include <netdev.h> #include "eth.h" #include "eth_addrtbl.h" diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c index ab599410b..80756a5cd 100644 --- a/board/evb64260/evb64260.c +++ b/board/evb64260/evb64260.c @@ -31,6 +31,7 @@ #include <galileo/pci.h> #include <galileo/gt64260R.h> #include <net.h> +#include <netdev.h> #include <asm/io.h> #include "eth.h" @@ -56,7 +57,7 @@ extern void zuma_mbox_init(void); /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -64,7 +65,7 @@ extern void zuma_mbox_init(void); * See also my_remap_gt_regs below. (NTL) */ -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; /* ------------------------------------------------------------------------- */ @@ -99,26 +100,26 @@ gt_pci_config(void) { /* move PCI stuff out of the way - NTL */ /* map PCI Host 0 */ - pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE); + pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE); pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0); pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0); pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0); - pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE); + pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE); /* map PCI Host 1 */ - pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE); + pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE); pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0); pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0); pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0); - pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE); + pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE); /* PCI interface settings */ GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff); @@ -200,7 +201,7 @@ int board_early_init_f (void) * that if it's not at the power-on location, it's where we put * it last time. (huber) */ - my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); gt_pci_config(); @@ -217,7 +218,7 @@ int board_early_init_f (void) GT_REG_WRITE(CPU_INT_3_MASK, 0); /* now, onto the configuration */ - GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG); + GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG); /* ----- DEVICE BUS SETTINGS ------ */ @@ -244,62 +245,61 @@ int board_early_init_f (void) /* Zuma has no SRAM */ sram_boot = 0; #else - if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE) + if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE) sram_boot = 1; #endif - if (!sram_boot) - memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); + memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); - memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE); - memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE); - memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE); + memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE); + memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE); + memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE); /* configure device timing */ -#ifdef CFG_DEV0_PAR +#ifdef CONFIG_SYS_DEV0_PAR if (!sram_boot) - GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR); + GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR); #endif -#ifdef CFG_DEV1_PAR - GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR); +#ifdef CONFIG_SYS_DEV1_PAR + GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR); #endif -#ifdef CFG_DEV2_PAR - GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR); +#ifdef CONFIG_SYS_DEV2_PAR + GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR); #endif #ifdef CONFIG_EVB64260 -#ifdef CFG_32BIT_BOOT_PAR +#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* detect if we are booting from the 32 bit flash */ if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) { /* 32 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); } else { /* 8 bit boot flash */ - GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); } #else /* 8 bit boot flash only */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR); #endif #else /* CONFIG_EVB64260 not defined */ /* We are booting from 16-bit flash. */ - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR); #endif gt_cpu_config(); /* MPP setup */ - GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); - GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX); + GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); + GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX); return 0; } @@ -309,7 +309,7 @@ int board_early_init_f (void) int misc_init_r (void) { icache_enable(); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable(); #endif @@ -330,9 +330,9 @@ after_reloc(ulong dest_addr) * back to the way they should be. (we're running from main * memory at this point now */ - if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) { - memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE); - memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M); + if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) { + memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE); + memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M); } /* now, jump to the main U-Boot board init code */ @@ -350,7 +350,7 @@ after_reloc(ulong dest_addr) int checkboard (void) { - puts ("Board: " CFG_BOARD_NAME "\n"); + puts ("Board: " CONFIG_SYS_BOARD_NAME "\n"); return (0); } @@ -365,29 +365,29 @@ debug_led(int led, int mode) if (mode == 1) { switch (led) { case 0: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000); + addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000); break; case 1: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000); + addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000); break; case 2: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000); + addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000); break; } } else if (mode == 0) { switch (led) { case 0: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000); + addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000); break; case 1: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000); + addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000); break; case 2: - addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000); + addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000); break; } } @@ -443,3 +443,9 @@ display_mem_map(void) printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n", base, size>>20, width); } + +int board_eth_init(bd_t *bis) +{ + gt6426x_eth_initialize(bis); + return 0; +} diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c index 6ab23dce2..115e8cd4d 100644 --- a/board/evb64260/flash.c +++ b/board/evb64260/flash.c @@ -46,7 +46,7 @@ int flash_erase_intel(flash_info_t *info, int s_first, int s_last); int write_word_intel(bank_addr_t addr, bank_word_t value); -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -67,16 +67,16 @@ flash_init (void) unsigned long base, flash_size; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* the boot flash */ - base = CFG_FLASH_BASE; -#ifndef CFG_BOOT_FLASH_WIDTH -#define CFG_BOOT_FLASH_WIDTH 1 + base = CONFIG_SYS_FLASH_BASE; +#ifndef CONFIG_SYS_BOOT_FLASH_WIDTH +#define CONFIG_SYS_BOOT_FLASH_WIDTH 1 #endif - size_b0 = flash_get_size(CFG_BOOT_FLASH_WIDTH, (vu_long *)base, + size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base, &flash_info[0]); #ifndef CONFIG_P3G4 @@ -90,9 +90,9 @@ flash_init (void) base, size_b0, size_b0<<20); } - base = memoryGetDeviceBaseAddress(CFG_EXTRA_FLASH_DEVICE); - for(i=1;i<CFG_MAX_FLASH_BANKS;i++) { - unsigned long size = flash_get_size(CFG_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]); + base = memoryGetDeviceBaseAddress(CONFIG_SYS_EXTRA_FLASH_DEVICE); + for(i=1;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) { + unsigned long size = flash_get_size(CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]); #ifndef CONFIG_P3G4 printf("["); @@ -111,20 +111,20 @@ flash_init (void) base+=size; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, + flash_get_info(CONFIG_ENV_ADDR)); #endif flash_size = size_b0 + size_b1; @@ -183,13 +183,13 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->start[0] <= base && base <= info->start[0] + info->size - 1) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -682,7 +682,7 @@ flash_erase (flash_info_t *info, int s_first, int s_last) addr = (volatile unsigned char *)(info->start[l_sect]); /* broken for 2x16: TODO */ while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -846,7 +846,7 @@ write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c index ed6a2a029..994264a7a 100644 --- a/board/evb64260/intel_flash.c +++ b/board/evb64260/intel_flash.c @@ -157,7 +157,7 @@ write_word_intel(bank_addr_t addr, bank_word_t value) /* data polling for D7 */ start = get_timer (0); do { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { retval = 1; goto done; } @@ -234,7 +234,7 @@ flash_erase_intel(flash_info_t *info, int s_first, int s_last) do { now = get_timer(start); - if (now - estart > CFG_FLASH_ERASE_TOUT) { + if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (sect %d)\n", sect); haderr = 1; break; diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h index dc2aa0008..cc3a33965 100644 --- a/board/evb64260/intel_flash.h +++ b/board/evb64260/intel_flash.h @@ -42,7 +42,7 @@ /* ID and Lock Configuration */ #define CHIP_RD_ID_LOCK 0x01 /* Bit 0 of each byte */ #define CHIP_RD_ID_MAN 0x89 /* Manufacturer code = 0x89 */ -#define CHIP_RD_ID_DEV CFG_FLASH_ID +#define CHIP_RD_ID_DEV CONFIG_SYS_FLASH_ID /* dimensions */ #define CHIP_WIDTH 2 /* chips are in 16 bit mode */ diff --git a/board/evb64260/local.h b/board/evb64260/local.h index 3d9b443e7..8a3f4b294 100644 --- a/board/evb64260/local.h +++ b/board/evb64260/local.h @@ -26,7 +26,7 @@ /* #define CONFIG_BOOTCOMMAND */ /* #define CONFIG_RAMBOOTCOMMAND */ /* #define CONFIG_NFSBOOTCOMMAND */ -/* #define CFG_AUTOLOAD */ +/* #define CONFIG_SYS_AUTOLOAD */ /* #define CONFIG_PREBOOT */ /* These don't */ diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S index 438dea612..f09528d42 100644 --- a/board/evb64260/misc.S +++ b/board/evb64260/misc.S @@ -16,7 +16,7 @@ board_relocate_rom: mflr r7 /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h + lis r11, CONFIG_SYS_GT_REGS@h /* if we're using ECC, we must use the DMA engine to copy ourselves */ bl start_idma_transfer_0 bl wait_for_idma_0 @@ -29,12 +29,12 @@ board_relocate_rom: board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ /* now that we're running from ram, init the rest of main memory * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l + lis r8, CONFIG_SYS_MONITOR_LEN@h + ori r8, r8, CONFIG_SYS_MONITOR_LEN@l divw r3, r10, r8 @@ -120,15 +120,15 @@ stop_idma_engine_0: blr #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* NOTE: trashes r3-r7 */ .globl board_asm_init board_asm_init: /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r3, CONFIG_SYS_DFL_GT_REGS@h + ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTERNAL_SPACE_DECODE /* test to see if we've already moved */ diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c index 3b338c72e..8c4a4c899 100644 --- a/board/evb64260/mpsc.c +++ b/board/evb64260/mpsc.c @@ -390,7 +390,7 @@ galbrg_set_baudrate(int channel, int rate) #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4) /* from tclk */ - clock = (CFG_BUS_HZ/(16*rate)) - 1; + clock = (CONFIG_SYS_BUS_HZ/(16*rate)) - 1; #else clock = (3686400/(16*rate)) - 1; #endif diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c index 59b9acb2f..582f24c67 100644 --- a/board/evb64260/pci.c +++ b/board/evb64260/pci.c @@ -675,14 +675,14 @@ void pci_init_board (void) local_buses[0] = pci0_hose.first_busno; /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -720,14 +720,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c index 9ae446544..e2f07699c 100644 --- a/board/evb64260/sdram_init.c +++ b/board/evb64260/sdram_init.c @@ -300,7 +300,7 @@ static int check_dimm (uchar slot, sdram_info_t * info) DP (printf ("tpar set to: %d\n", info->tpar)); -#ifdef CFG_BROKEN_CL2 +#ifdef CONFIG_SYS_BROKEN_CL2 if (info->tpar == 2) { info->tpar = 3; DP (printf ("tpar fixed-up to: %d\n", info->tpar)); @@ -598,7 +598,7 @@ phys_size_t initdram (int board_type) * limitation: we only support 256M per bank due to * us only having 1 BAT for all DRAM */ - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { /* skip over banks that are not populated */ if (!checkbank[bank_no]) continue; @@ -617,7 +617,7 @@ phys_size_t initdram (int board_type) * space. */ dimm_info[0].banks = dimm_info[1].banks = 0; - for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) { + for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { if (!checkbank[bank_no]) continue; diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c index f1bcab3f0..9d711151f 100644 --- a/board/evb64260/serial.c +++ b/board/evb64260/serial.c @@ -31,7 +31,7 @@ #include <command.h> #include <galileo/memory.h> -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) #include <ns16550.h> #endif @@ -41,26 +41,26 @@ DECLARE_GLOBAL_DATA_PTR; -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) -const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, - (NS16550_t) CFG_NS16550_COM2 }; +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) +const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1, + (NS16550_t) CONFIG_SYS_NS16550_COM2 }; #endif #ifdef CONFIG_MPSC int serial_init (void) { -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; #endif mpsc_init(gd->baudrate); /* init the DUART chans so that KGDB in the kernel can use them */ -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit(COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit(COM_PORTS[1], clock_divisor); #endif return (0); @@ -97,12 +97,12 @@ serial_setbrg (void) int serial_init (void) { - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 (void)NS16550_init(COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 (void)NS16550_init(COM_PORTS[1], clock_divisor); #endif @@ -113,32 +113,32 @@ void serial_putc(const char c) { if (c == '\n') - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } int serial_getc(void) { - return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); } int serial_tstc(void) { - return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); } void serial_setbrg (void) { - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit(COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit(COM_PORTS[1], clock_divisor); #endif } diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index 1a95755ab..ff2d8b7fe 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c index 296e4619c..1d0357093 100644 --- a/board/evb64260/zuma_pbb.c +++ b/board/evb64260/zuma_pbb.c @@ -149,8 +149,10 @@ void zuma_init_pbb (void) pci_read_config_dword (dev, PCI_BASE_ADDRESS_0, &iobase); - zuma_pbb_reg = - (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + + zuma_pbb_reg = (PBB_DMA_REG_MAP *)iobase; + if (!zuma_pbb_reg) { printf ("zuma pbb bar none! (hah hah, get it?)\n"); diff --git a/board/evb64260/zuma_pbb_mbox.c b/board/evb64260/zuma_pbb_mbox.c index 6f5df6e80..8e381024b 100644 --- a/board/evb64260/zuma_pbb_mbox.c +++ b/board/evb64260/zuma_pbb_mbox.c @@ -165,7 +165,9 @@ int zuma_mbox_init(void) pci_read_config_dword(zuma_mbox_dev.dev, PCI_BASE_ADDRESS_0, &iobase); - zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *) (iobase & PCI_BASE_ADDRESS_MEM_MASK); + iobase &= PCI_BASE_ADDRESS_MEM_MASK; + + zuma_mbox_dev.sip = (PBB_DMA_REG_MAP *)iobase; zuma_mbox_dev.sip->int_mask.word=0; diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c index 4dd538287..cd45cb697 100644 --- a/board/exbitgen/flash.c +++ b/board/exbitgen/flash.c @@ -33,7 +33,7 @@ #include <asm/processor.h> #include <ppc4xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -68,7 +68,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].size = 0; } @@ -76,7 +76,7 @@ unsigned long flash_init (void) tot_size = 0; /* Detect Boot Flash */ - bank_addr = CFG_FLASH0_BASE; + bank_addr = CONFIG_SYS_FLASH0_BASE; bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]); if (bank_size > 0) { (void)flash_protect(FLAG_PROTECT_CLEAR, @@ -91,8 +91,8 @@ unsigned long flash_init (void) tot_size += bank_size; /* Detect Application Flash */ - bank_addr = CFG_FLASH1_BASE; - for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) { + bank_addr = CONFIG_SYS_FLASH1_BASE; + for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]); if (flash_info[i].flash_id == FLASH_UNKNOWN) { break; @@ -112,13 +112,13 @@ unsigned long flash_init (void) } /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#if 0xfffffffc >= CFG_FLASH0_BASE -#if 0xfffffffc <= CFG_FLASH0_BASE + CFG_FLASH0_SIZE - 1 +#if 0xfffffffc >= CONFIG_SYS_FLASH0_BASE +#if 0xfffffffc <= CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_FLASH0_SIZE - 1 flash_protect(FLAG_PROTECT_SET, 0xfffffffc, 0xffffffff, &flash_info[0]); @@ -126,10 +126,10 @@ unsigned long flash_init (void) #endif #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -450,7 +450,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr2[0] & 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { if ((now=get_timer(start)) > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); addr[0] = (FLASH_WORD_SIZE)0x00F000F0; return 1; @@ -581,7 +581,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { addr2[0] = (FLASH_WORD_SIZE)0x00F000F0; return (1); } diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index 71aefb97c..760835aab 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -265,7 +265,7 @@ setup_continue: .globl sdram_init sdram_init: -#if CFG_MONITOR_BASE < CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE blr #else mflr r31 @@ -402,7 +402,7 @@ sdram_init: addi r9, 0, 13 /* bit offset of addressing mode in configuration register */ slw r29, r29, r9 /* */ or r3, r29, r3 /* merge size code and addressing mode */ - ori r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */ + ori r6, r3, CONFIG_SYS_SDRAM_BASE + 1 /* insert base address and enable bank */ /* Calculate banksize r15 = (density << 22) / 2 */ /*--------------------------------------------- */ diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds index e4faa446e..d76b97ea7 100644 --- a/board/exbitgen/u-boot.lds +++ b/board/exbitgen/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -145,6 +145,7 @@ SECTIONS . = ALIGN(4); *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/fads/fads.c b/board/fads/fads.c index 9e601df1b..9f7faaf47 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -190,7 +190,7 @@ static const uint edo_70ns[] = /* ------------------------------------------------------------------------- */ static int _draminit (uint base, uint noMbytes, uint edo, uint delay) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* init upm */ @@ -283,7 +283,7 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay) static void _dramdisable(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_br2 = 0x00000000; @@ -423,7 +423,7 @@ static const uint sdram_table[] = static int _initsdram(uint base, uint noMbytes) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); @@ -449,19 +449,19 @@ static int _initsdram(uint base, uint noMbytes) /* Now run the precharge/nop/mrs commands. */ - memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50Mhz) */ - /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100Mhz) */ + memctl->memc_mcr = 0x80808111; /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */ + /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */ udelay(200); /* Run 8 refresh cycles */ - memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 Mhz)*/ + memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/ /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */ udelay(200); - memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 Mhz) or TLF 8 (50MHz) */ - memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 Mhz) */ + memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */ + memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */ /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */ udelay(200); @@ -501,7 +501,7 @@ static int _initsdram(uint base, uint noMbytes) static int _initsdram(uint base, uint noMbytes) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint)); @@ -564,7 +564,7 @@ static int _initsdram(uint base, uint noMbytes) static void _sdramdisable(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_br4 = 0x00000000; @@ -576,7 +576,7 @@ static void _sdramdisable(void) static int initsdram(uint base, uint *noMbytes) { - uint m = CFG_SDRAM_SIZE>>20; + uint m = CONFIG_SYS_SDRAM_SIZE>>20; /* _initsdram needs access to sdram */ *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */ @@ -688,7 +688,7 @@ int testdram (void) * Check Board Identity: */ -#if defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) +#if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) static void checkdboard(void) { /* get db type from BCSR 3 */ @@ -722,7 +722,7 @@ static void checkdboard(void) default : printf("0x%x", k); } } -#endif /* defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) */ +#endif /* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */ int checkboard (void) { @@ -780,8 +780,8 @@ int checkboard (void) #if defined(CONFIG_CMD_PCMCIA) -#ifdef CFG_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; +#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR +volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR; #endif int pcmcia_init(void) @@ -792,10 +792,10 @@ int pcmcia_init(void) /* ** Enable the PCMCIA for a Flash card. */ - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); #if 0 - pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR; + pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; pcmp->pcmc_por0 = 0xc00ff05d; #endif @@ -925,25 +925,25 @@ int pcmcia_init(void) /* ========================================================================= */ -#ifdef CFG_PC_IDE_RESET +#ifdef CONFIG_SYS_PC_IDE_RESET void ide_set_reset(int on) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* * Configure PC for IDE Reset Pin */ if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; } /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); + immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); + immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; } -#endif /* CFG_PC_IDE_RESET */ +#endif /* CONFIG_SYS_PC_IDE_RESET */ diff --git a/board/fads/fads.h b/board/fads/fads.h index 0a8b98352..24e43eab3 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -95,7 +95,7 @@ #endif #ifdef CONFIG_FEC_ENET -#define CFG_DISCOVER_PHY +#define CONFIG_SYS_DISCOVER_PHY #define CONFIG_MII_INIT 1 #endif @@ -130,24 +130,24 @@ /* * Miscellaneous configurable options */ -#define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_LONGHELP /* #undef to save memory */ +#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP /* #undef to save memory */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_LOAD_ADDR 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* * Low Level Configuration Settings @@ -158,25 +158,25 @@ /*----------------------------------------------------------------------- * Internal Memory Mapped Register */ -#define CFG_IMMR 0xFF000000 +#define CONFIG_SYS_IMMR 0xFF000000 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ -#define CFG_INIT_RAM_ADDR CFG_IMMR -#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR +#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ -#define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ +#define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ /* * 2048 SDRAM rows * 1000 factor s -> ms @@ -184,55 +184,55 @@ * 4 Number of refresh cycles per period * 64 Refresh cycle in ms per number of rows */ -#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) +#define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64)) #elif defined(CONFIG_FADS) /* Old/new FADS */ -#define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ +#define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ #else /* Old ADS */ -#define CFG_SDRAM_SIZE 0x00000000 /* No SDRAM */ +#define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */ #endif -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#if (CFG_SDRAM_SIZE) -#define CFG_MEMTEST_END CFG_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ +#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ +#if (CONFIG_SYS_SDRAM_SIZE) +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */ #else -#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#endif /* CFG_SDRAM_SIZE */ +#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ +#endif /* CONFIG_SYS_SDRAM_SIZE */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ #ifdef CONFIG_BZIP2 -#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ #else -#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ #endif /* CONFIG_BZIP2 */ /*----------------------------------------------------------------------- * Flash organization */ -#define CFG_FLASH_BASE CFG_MONITOR_BASE -#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */ -#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ -#define CFG_ENV_OFFSET CFG_ENV_SECT_SIZE -#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment */ -#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */ +#define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ +#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ -#define CFG_DIRECT_FLASH_TFTP +#define CONFIG_SYS_DIRECT_FLASH_TFTP #if defined(CONFIG_CMD_JFFS2) @@ -254,22 +254,22 @@ #define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)" */ -#define CFG_JFFS2_SORT_FRAGMENTS +#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS #endif /*----------------------------------------------------------------------- * Cache Configuration */ -#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ /*----------------------------------------------------------------------- * I2C configuration */ #if defined(CONFIG_CMD_I2C) #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */ +#define CONFIG_SYS_I2C_SLAVE 0x7F #endif /*----------------------------------------------------------------------- @@ -279,10 +279,10 @@ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ #if defined(CONFIG_WATCHDOG) -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) #else -#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) #endif /*----------------------------------------------------------------------- @@ -290,21 +290,21 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */ -#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) +#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) /*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */ -#define CFG_PISCR (PISCR_PS | PISCR_PITF) +#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) /*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register 15-27 @@ -313,14 +313,14 @@ * power management and some other internal clocks */ #define SCCR_MASK SCCR_EBDF11 -#define CFG_SCCR SCCR_TBS +#define CONFIG_SYS_SCCR SCCR_TBS /*----------------------------------------------------------------------- * DER - Debug Enable Register *----------------------------------------------------------------------- * Set to zero to prevent the processor from entering debug mode */ -#define CFG_DER 0 +#define CONFIG_SYS_DER 0 /* Because of the way the 860 starts up and assigns CS0 the entire * address space, we have to set the memory controller differently. @@ -339,17 +339,17 @@ #define BCSR_ADDR ((uint) 0xFF080000) -#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ +#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */ -#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX) -#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 8 Mbyte until detected */ -#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_V ) +#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */ +#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V ) /* BCSRx - Board Control and Status Registers */ -#define CFG_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ -#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V) /* * Internal Definitions @@ -442,9 +442,9 @@ /* BSCR5 exists on MPC86xADS and MPC885ADS only */ -#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) +#define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000) -#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) +#define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300) #define BCSR5_MII2_EN 0x40 #define BCSR5_MII2_RST 0x20 @@ -462,14 +462,14 @@ * PCMCIA stuff *----------------------------------------------------------------------- */ -#define CFG_PCMCIA_MEM_ADDR (0xE0000000) -#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_DMA_ADDR (0xE4000000) -#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) -#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CFG_PCMCIA_IO_ADDR (0xEC000000) -#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) +#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) +#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) +#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) /*----------------------------------------------------------------------- * IDE/ATA stuff @@ -487,18 +487,18 @@ #undef CONFIG_IDE_LED /* LED for ide not supported */ #undef CONFIG_IDE_RESET /* reset for ide not supported */ -#define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */ +#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) +#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) /* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) +#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) /* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET 0x0000 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 #define CONFIG_DISK_SPINUP_TIME 1000000 /* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */ diff --git a/board/fads/flash.c b/board/fads/flash.c index 7cda3a412..b9afb7517 100644 --- a/board/fads/flash.c +++ b/board/fads/flash.c @@ -24,17 +24,17 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -54,14 +54,14 @@ static int write_word (flash_info_t * info, ulong dest, ulong data); */ unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; vu_long *bcsr = (vu_long *)BCSR_ADDR; unsigned long pd_size, total_size, bsize, or_am; int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].size = 0; flash_info[i].sector_count = 0; @@ -94,8 +94,8 @@ unsigned long flash_init (void) } total_size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) { - bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size), + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && total_size < pd_size; ++i) { + bsize = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + total_size), &flash_info[i]); if (flash_info[i].flash_id == FLASH_UNKNOWN) { @@ -112,24 +112,24 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH; + memctl->memc_or0 = or_am | CONFIG_SYS_OR_TIMING_FLASH; - for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) { +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ - if (CFG_MONITOR_BASE >= flash_info[i].start[0]) + if (CONFIG_SYS_MONITOR_BASE >= flash_info[i].start[0]) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[i]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ - if (CFG_ENV_ADDR >= flash_info[i].start[0]) + if (CONFIG_ENV_ADDR >= flash_info[i].start[0]) flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[i]); #endif } @@ -428,7 +428,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr = (vu_long *) (info->start[l_sect]); while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return ERR_TIMOUT; } @@ -552,7 +552,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) start = get_timer (0); while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return ERR_TIMOUT; } } diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index c7571e499..194ca6987 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS cpu/mpc8xx/start.o (.text) /*. = DEFINED(env_offset) ? env_offset : .;*/ - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -124,6 +124,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug index fd2245f57..67d37ae33 100644 --- a/board/fads/u-boot.lds.debug +++ b/board/fads/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c index 7caedc99a..dc9e2dcc1 100644 --- a/board/flagadm/flagadm.c +++ b/board/flagadm/flagadm.c @@ -98,18 +98,18 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0; - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + memctl->memc_or2 = CONFIG_SYS_OR2; + memctl->memc_br2 = CONFIG_SYS_BR2; udelay(100); upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); memctl->memc_mptpr = MPTPR_PTP_DIV16; - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X; + memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X; /*Do the initialization of the SDRAM*/ /*Start with the precharge cycle*/ @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) MCR_MLCF(1) | MCR_MAD(0x5)); /*Then we need two refresh cycles*/ - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X; + memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X; memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ MCR_MLCF(2) | MCR_MAD(0x30)); @@ -127,7 +127,7 @@ phys_size_t initdram (int board_type) MCR_MLCF(1) | MCR_MAD(0x1C)); /* That should do it, just enable the periodic refresh in burst of 4*/ - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X; + memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X; memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS); size_b0 = 16*1024*1024; @@ -143,8 +143,8 @@ phys_size_t initdram (int board_type) memctl->memc_mbmr = MBMR_GPL_B4DIS; - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; return (size_b0); } diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c index fd0082c13..bbefbacea 100644 --- a/board/flagadm/flash.c +++ b/board/flagadm/flash.c @@ -25,7 +25,7 @@ #include <mpc8xx.h> #include <flash.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -39,53 +39,53 @@ int _flash_real_protect(flash_info_t *info, long idx, int on); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; int i; int rec; - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - *((vu_short*)CFG_FLASH_BASE) = 0xffff; + *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff; - flash_get_geometry ((vu_long*)CFG_FLASH_BASE, &flash_info[0]); + flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); - rec = flash_recognize((vu_long*)CFG_FLASH_BASE); + rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE); if (rec == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", flash_info[0].size, flash_info[0].size<<20); } -#if CFG_FLASH_PROTECTION +#if CONFIG_SYS_FLASH_PROTECTION /*Unprotect all the flash memory*/ flash_unprotect(&flash_info[0]); #endif - *((vu_short*)CFG_FLASH_BASE) = 0xffff; + *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff; return (flash_info[0].size); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_OFFSET, - CFG_ENV_OFFSET+CFG_ENV_SIZE-1, + CONFIG_ENV_OFFSET, + CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif return (flash_info[0].size); @@ -400,7 +400,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = 0x70; /*Read status register command*/ tmp = (short)*addr & 0x00FF; /* Read the status */ while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x0050; /* Reset the status register */ *addr = 0xffff; printf ("Timeout\n"); @@ -440,7 +440,7 @@ void flash_unprotect (flash_info_t *info) for(i = 0; i < info->sector_count; i++) info->protect[i] = 0; -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION _flash_real_protect(info, 0, 0); #endif } @@ -555,7 +555,7 @@ int write_word (flash_info_t *info, ulong dest, ulong da) flag = 0; *addr = 0x0070; /*Read statusregister command */ while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flag = 1; break; } @@ -642,7 +642,7 @@ int _flash_real_protect(flash_info_t *info, long idx, int prot) while(!(tmp & INTEL_FLASH_STATUS_WSMS)) { /*Write State Machine Busy*/ /*Wait untill done or timeout.*/ - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0x0050; /* Reset the status register */ *addr = 0xffff; /* Reset the chip */ printf ("TTimeout\n"); @@ -670,7 +670,7 @@ int _flash_real_protect(flash_info_t *info, long idx, int prot) tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */ while (!(tmp & INTEL_FLASH_STATUS_WSMS)) { /* Write State Machine Busy */ - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0x0050; /* Reset the status register */ *addr = 0xffff; printf ("Timeout\n"); diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index f0984126b..f36259acb 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index 85072feda..dbec9860a 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 508e3b569..02a824d9f 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -30,12 +30,12 @@ endif LIB = $(obj)lib$(VENDOR).a COBJS-${CONFIG_FSL_CADMUS} += cadmus.o -COBJS-${CONFIG_FSL_CDS_EEPROM} += cds_eeprom.o COBJS-${CONFIG_FSL_VIA} += cds_via.o COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o COBJS-${CONFIG_FSL_PIXIS} += pixis.o COBJS-${CONFIG_PQ_MDS_PIB} += pq-mds-pib.o COBJS-${CONFIG_ID_EEPROM} += sys_eeprom.o +COBJS-${CONFIG_FSL_SGMII_RISER} += sgmii_riser.o COBJS-${CONFIG_MPC8541CDS} += cds_pci_ft.o COBJS-${CONFIG_MPC8548CDS} += cds_pci_ft.o diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c index 5f86de5af..db54bc4d5 100644 --- a/board/freescale/common/cadmus.c +++ b/board/freescale/common/cadmus.c @@ -27,8 +27,8 @@ /* * CADMUS Board System Registers */ -#ifndef CFG_CADMUS_BASE_REG -#define CFG_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) +#ifndef CONFIG_SYS_CADMUS_BASE_REG +#define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) #endif typedef struct cadmus_reg { @@ -47,7 +47,7 @@ typedef struct cadmus_reg { unsigned int get_board_version(void) { - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; return cadmus->cm_ver; } @@ -56,7 +56,7 @@ get_board_version(void) unsigned long get_clock_freq(void) { - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ @@ -74,7 +74,7 @@ get_clock_freq(void) unsigned int get_pci_slot(void) { - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; /* * PCI slot in USER bits CSR[6:7] by convention. @@ -86,7 +86,7 @@ get_pci_slot(void) unsigned int get_pci_dual(void) { - volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG; + volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; /* * PCI DUAL in CM_PCI[3] diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 75f782e9d..2fc878be8 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -205,7 +205,7 @@ int fsl_diu_init(int xres, unsigned int i, j; debug("Enter fsl_diu_init\n"); - dr.diu_reg = (struct diu *) (CFG_DIU_ADDR); + dr.diu_reg = (struct diu *) (CONFIG_SYS_DIU_ADDR); hw = (struct diu *) dr.diu_reg; disable_lcdc(); @@ -242,10 +242,10 @@ int fsl_diu_init(int xres, printf("Unable to allocate fb memory 1\n"); return -1; } - } else { - memset(info->screen_base, 0, info->smem_len); } + memset(info->screen_base, 0, info->smem_len); + dr.diu_reg->desc[0] = (unsigned int) &dummy_ad; dr.diu_reg->desc[1] = (unsigned int) &dummy_ad; dr.diu_reg->desc[2] = (unsigned int) &dummy_ad; @@ -403,7 +403,7 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align) mask = bytes_align - 1; offset = (unsigned long)info->screen_base & mask; if (offset) { - info->screen_base += offset; + info->screen_base += (bytes_align - offset); info->smem_len = info->smem_len - (bytes_align - offset); } else info->smem_len = info->smem_len - bytes_align; diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 64e2e08c5..96820ac60 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -26,6 +26,7 @@ #include <command.h> #include <watchdog.h> #include <asm/cache.h> +#include <asm/io.h> #include "pixis.h" @@ -206,8 +207,8 @@ void read_from_px_regs_altbank(int set) out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp); } -#ifndef CFG_PIXIS_VBOOT_MASK -#define CFG_PIXIS_VBOOT_MASK (0x40) +#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK +#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40) #endif void clear_altbank(void) @@ -215,7 +216,7 @@ void clear_altbank(void) u8 tmp; tmp = in8(PIXIS_BASE + PIXIS_VBOOT); - tmp &= ~CFG_PIXIS_VBOOT_MASK; + tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK; out8(PIXIS_BASE + PIXIS_VBOOT, tmp); } @@ -226,7 +227,7 @@ void set_altbank(void) u8 tmp; tmp = in8(PIXIS_BASE + PIXIS_VBOOT); - tmp |= CFG_PIXIS_VBOOT_MASK; + tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK; out8(PIXIS_BASE + PIXIS_VBOOT, tmp); } @@ -282,6 +283,76 @@ U_BOOT_CMD( "diswd - Disable watchdog timer \n", NULL); +#ifdef CONFIG_PIXIS_SGMII_CMD +int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int which_tsec = -1; + uchar mask; + uchar switch_mask; + + if (argc > 2) + if (strcmp(argv[1], "all") != 0) + which_tsec = simple_strtoul(argv[1], NULL, 0); + + switch (which_tsec) { +#ifdef CONFIG_TSEC1 + case 1: + mask = PIXIS_VSPEED2_TSEC1SER; + switch_mask = PIXIS_VCFGEN1_TSEC1SER; + break; +#endif +#ifdef CONFIG_TSEC2 + case 2: + mask = PIXIS_VSPEED2_TSEC2SER; + switch_mask = PIXIS_VCFGEN1_TSEC2SER; + break; +#endif +#ifdef CONFIG_TSEC3 + case 3: + mask = PIXIS_VSPEED2_TSEC3SER; + switch_mask = PIXIS_VCFGEN1_TSEC3SER; + break; +#endif +#ifdef CONFIG_TSEC4 + case 4: + mask = PIXIS_VSPEED2_TSEC4SER; + switch_mask = PIXIS_VCFGEN1_TSEC4SER; + break; +#endif + default: + mask = PIXIS_VSPEED2_MASK; + switch_mask = PIXIS_VCFGEN1_MASK; + break; + } + + /* Toggle whether the switches or FPGA control the settings */ + if (!strcmp(argv[argc - 1], "switch")) + clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1, + switch_mask); + else + setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1, + switch_mask); + + /* If it's not the switches, enable or disable SGMII, as specified */ + if (!strcmp(argv[argc - 1], "on")) + clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask); + else if (!strcmp(argv[argc - 1], "off")) + setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask); + + return 0; +} + +U_BOOT_CMD( + pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii, + "pixis_set_sgmii" + " - Enable or disable SGMII mode for a given TSEC \n", + "\npixis_set_sgmii [TSEC num] <on|off|switch>\n" + " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n" + " on - enables SGMII\n" + " off - disables SGMII\n" + " switch - use switch settings\n"); +#endif + /* * This function takes the non-integral cpu:mpx pll ratio * and converts it to an integer that can be used to assign @@ -398,7 +469,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll)) || unknown_param) { +#ifdef CONFIG_SYS_LONGHELP puts(cmdtp->help); +#endif return 1; } @@ -428,7 +501,9 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (!(set_px_sysclk(sysclk) && set_px_corepll(corepll) && set_px_mpxpll(mpxpll))) { +#ifdef CONFIG_SYS_LONGHELP puts(cmdtp->help); +#endif return 1; } read_from_px_regs(1); @@ -463,7 +538,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( - pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd, + pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, "pixis_reset - Reset the board using the FPGA sequencer\n", " pixis_reset\n" " pixis_reset [altbank]\n" diff --git a/board/freescale/common/sgmii_riser.c b/board/freescale/common/sgmii_riser.c new file mode 100644 index 000000000..5ccd6bcad --- /dev/null +++ b/board/freescale/common/sgmii_riser.c @@ -0,0 +1,26 @@ +/* + * Freescale SGMII Riser Card + * + * This driver supports the SGMII Riser card found on the + * "DS" style of development board from Freescale. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + */ + +#include <config.h> +#include <common.h> +#include <tsec.h> + +void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num) +{ + int i; + + for (i = 0; i < num; i++) + if (tsec_info[i].flags & TSEC_SGMII) + tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET; +} diff --git a/board/freescale/common/sgmii_riser.h b/board/freescale/common/sgmii_riser.h new file mode 100644 index 000000000..8d56a1f59 --- /dev/null +++ b/board/freescale/common/sgmii_riser.h @@ -0,0 +1,15 @@ +/* + * Freescale SGMII Riser Card + * + * This driver supports the SGMII Riser card found on the + * "DS" style of development board from Freescale. + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * Copyright 2008 Freescale Semiconductor, Inc. + * + */ + +void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num); diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index e53ead04f..eb58c7fd5 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -30,8 +30,8 @@ #include "../common/eeprom.h" -#if !defined(CFG_I2C_EEPROM_CCID) && !defined(CFG_I2C_EEPROM_NXID) -#error "Please define either CFG_I2C_EEPROM_CCID or CFG_I2C_EEPROM_NXID" +#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID) +#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID" #endif /** @@ -40,7 +40,7 @@ * See application note AN3638 for details. */ static struct __attribute__ ((__packed__)) eeprom { -#ifdef CFG_I2C_EEPROM_CCID +#ifdef CONFIG_SYS_I2C_EEPROM_CCID u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'CCID' */ u8 major; /* 0x04 Board revision, major */ u8 minor; /* 0x05 Board revision, minor */ @@ -53,7 +53,7 @@ static struct __attribute__ ((__packed__)) eeprom { u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */ u32 crc; /* 0x72 CRC32 checksum */ #endif -#ifdef CFG_I2C_EEPROM_NXID +#ifdef CONFIG_SYS_I2C_EEPROM_NXID u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */ u8 sn[12]; /* 0x04 - 0x0F Serial Number */ u8 errata[5]; /* 0x10 - 0x14 Errata Level */ @@ -74,12 +74,12 @@ static struct __attribute__ ((__packed__)) eeprom { /* Set to 1 if we've read EEPROM into memory */ static int has_been_read = 0; -#ifdef CFG_I2C_EEPROM_NXID +#ifdef CONFIG_SYS_I2C_EEPROM_NXID /* Is this a valid NXID EEPROM? */ #define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D')) #endif -#ifdef CFG_I2C_EEPROM_CCID +#ifdef CONFIG_SYS_I2C_EEPROM_CCID /* Is this a valid CCID EEPROM? */ #define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) #endif @@ -93,7 +93,7 @@ static void show_eeprom(void) unsigned int crc; /* EEPROM tag ID, either CCID or NXID */ -#ifdef CFG_I2C_EEPROM_NXID +#ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3], be32_to_cpu(e.version)); #else @@ -104,7 +104,7 @@ static void show_eeprom(void) printf("SN: %s\n", e.sn); /* Errata level. */ -#ifdef CFG_I2C_EEPROM_NXID +#ifdef CONFIG_SYS_I2C_EEPROM_NXID printf("Errata: %s\n", e.errata); #else printf("Errata: %c%c\n", @@ -152,22 +152,22 @@ static void show_eeprom(void) static int read_eeprom(void) { int ret; -#ifdef CFG_EEPROM_BUS_NUM +#ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus; #endif if (has_been_read) return 0; -#ifdef CFG_EEPROM_BUS_NUM +#ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); - i2c_set_bus_num(CFG_EEPROM_BUS_NUM); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif - ret = i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN, + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e, sizeof(e)); -#ifdef CFG_EEPROM_BUS_NUM +#ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); #endif @@ -188,12 +188,12 @@ static int prog_eeprom(void) int ret, i, length; unsigned int crc; void *p; -#ifdef CFG_EEPROM_BUS_NUM +#ifdef CONFIG_SYS_EEPROM_BUS_NUM unsigned int bus; #endif /* Set the reserved values to 0xFF */ -#ifdef CFG_I2C_EEPROM_NXID +#ifdef CONFIG_SYS_I2C_EEPROM_NXID e.res_0 = 0xFF; memset(e.res_1, 0xFF, sizeof(e.res_1)); #else @@ -204,20 +204,20 @@ static int prog_eeprom(void) crc = crc32(0, (void *)&e, length - 4); e.crc = cpu_to_be32(crc); -#ifdef CFG_EEPROM_BUS_NUM +#ifdef CONFIG_SYS_EEPROM_BUS_NUM bus = i2c_get_bus_num(); - i2c_set_bus_num(CFG_EEPROM_BUS_NUM); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); #endif for (i = 0, p = &e; i < length; i += 8, p += 8) { - ret = i2c_write(CFG_I2C_EEPROM_ADDR, i, CFG_I2C_EEPROM_ADDR_LEN, + ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, p, min((length - i), 8)); if (ret) break; udelay(5000); /* 5ms write cycle timing */ } -#ifdef CFG_EEPROM_BUS_NUM +#ifdef CONFIG_SYS_EEPROM_BUS_NUM i2c_set_bus_num(bus); #endif @@ -343,7 +343,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1); break; case 'e': /* errata */ -#ifdef CFG_I2C_EEPROM_NXID +#ifdef CONFIG_SYS_I2C_EEPROM_NXID memset(e.errata, 0, 5); strncpy((char *)e.errata, argv[2], 4); #else @@ -429,7 +429,7 @@ int mac_read_from_eeprom(void) return 0; } -#ifdef CFG_I2C_EEPROM_CCID +#ifdef CONFIG_SYS_I2C_EEPROM_CCID /** * get_cpu_board_revision - get the CPU board revision on 85xx boards @@ -439,11 +439,11 @@ int mac_read_from_eeprom(void) * This function is called before relocation, so we need to read a private * copy of the EEPROM into a local variable on the stack. * - * Also, we assume that CFG_EEPROM_BUS_NUM == CFG_SPD_BUS_NUM. The global - * variable i2c_bus_num must be compile-time initialized to CFG_SPD_BUS_NUM, + * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM. The global + * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM, * so that the SPD code will work. This means that all pre-relocation I2C - * operations can only occur on the CFG_SPD_BUS_NUM bus. So if - * CFG_EEPROM_BUS_NUM != CFG_SPD_BUS_NUM, then we can't read the EEPROM when + * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus. So if + * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when * this function is called. Oh well. */ unsigned int get_cpu_board_revision(void) @@ -454,7 +454,7 @@ unsigned int get_cpu_board_revision(void) u8 minor; /* 0x05 Board revision, minor */ } be; - i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN, + i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&be, sizeof(be)); if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D')) @@ -463,6 +463,6 @@ unsigned int get_cpu_board_revision(void) if ((be.major == 0xff) && (be.minor == 0xff)) return MPC85XX_CPU_BOARD_REV(0, 0); - return MPC85XX_CPU_BOARD_REV(e.major, e.minor); + return MPC85XX_CPU_BOARD_REV(be.major, be.minor); } #endif diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk index ce014edca..b42fcc94c 100644 --- a/board/freescale/m52277evb/config.mk +++ b/board/freescale/m52277evb/config.mk @@ -22,4 +22,6 @@ # MA 02111-1307 USA # -TEXT_BASE = 0 +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c index e5f47d2d9..9109edb37 100644 --- a/board/freescale/m52277evb/m52277evb.c +++ b/board/freescale/m52277evb/m52277evb.c @@ -38,10 +38,20 @@ int checkboard(void) phys_size_t initdram(int board_type) { + u32 dramsize; + +#ifdef CONFIG_CF_SBF + /* + * Serial Boot: The dram is already initialized in start.S + * only require to return DRAM size + */ + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; +#else volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); - u32 dramsize, i; + volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); + u32 i; - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -49,31 +59,39 @@ phys_size_t initdram(int board_type) } i--; - sdram->sdcs0 = (CFG_SDRAM_BASE | i); + gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; - sdram->sdcfg1 = CFG_SDRAM_CFG1; - sdram->sdcfg2 = CFG_SDRAM_CFG2; + sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); + + sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; /* Issue PALL */ - sdram->sdcr = CFG_SDRAM_CTRL | 2; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + __asm__("nop"); /* Issue LEMR */ - /*sdram->sdmr = CFG_SDRAM_EMOD; */ - sdram->sdmr = CFG_SDRAM_MODE; + sdram->sdmr = CONFIG_SYS_SDRAM_MODE; + __asm__("nop"); + sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; + __asm__("nop"); udelay(1000); /* Issue PALL */ - sdram->sdcr = CFG_SDRAM_CTRL | 2; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; + __asm__("nop"); /* Perform two refresh cycles */ - sdram->sdcr = CFG_SDRAM_CTRL | 4; - sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + __asm__("nop"); + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + __asm__("nop"); - sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00; udelay(100); - +#endif return (dramsize); }; diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.spa index 098e9d346..7ae70d455 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.spa @@ -63,7 +63,7 @@ SECTIONS common/main.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m52277evb/u-boot.stm b/board/freescale/m52277evb/u-boot.stm new file mode 100644 index 000000000..03ff53296 --- /dev/null +++ b/board/freescale/m52277evb/u-boot.stm @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(m68k) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mcf5227x/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + + .reloc : + { + __got_start = .; + *(.got) + __got_end = .; + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + _sbss = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/freescale/m5235evb/Makefile b/board/freescale/m5235evb/Makefile index 74c252869..981763d20 100644 --- a/board/freescale/m5235evb/Makefile +++ b/board/freescale/m5235evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index bd8a4e5e6..b9e61269c 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -57,7 +57,7 @@ phys_size_t initdram(int board_type) GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -65,7 +65,7 @@ phys_size_t initdram(int board_type) i--; if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { - dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); /* Initialize DRAM Control Register: DCR */ sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | @@ -73,7 +73,7 @@ phys_size_t initdram(int board_type) /* Initialize DACR0 */ sdram->dacr0 = - SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | + SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; asm("nop"); @@ -90,7 +90,7 @@ phys_size_t initdram(int board_type) } /* Write to this block to initiate precharge */ - *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696; + *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; /* Set RE (bit 15) in DACR */ sdram->dacr0 |= SDRAMC_DARCn_RE; @@ -105,7 +105,7 @@ phys_size_t initdram(int board_type) asm("nop"); /* Write to the SDRAM Mode Register */ - *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } return dramsize; diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c deleted file mode 100644 index 1fd4d99c1..000000000 --- a/board/freescale/m5235evb/mii.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO); - } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK); - } - - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ -#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" -#define STR_ID_KS8721BL "KS8721BL" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - strcpy(info->phy_name, - STR_ID_KS8721BL); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - printf(STR_ID_KS8721BL); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5235evb/u-boot.16 b/board/freescale/m5235evb/u-boot.16 index 4ca026fc5..c13488437 100644 --- a/board/freescale/m5235evb/u-boot.16 +++ b/board/freescale/m5235evb/u-boot.16 @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5235evb/u-boot.32 b/board/freescale/m5235evb/u-boot.32 index eeffdfb4e..53c337df8 100644 --- a/board/freescale/m5235evb/u-boot.32 +++ b/board/freescale/m5235evb/u-boot.32 @@ -71,7 +71,7 @@ SECTIONS lib_generic/libgeneric.a (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c index c9ed341bb..b1ccbebde 100644 --- a/board/freescale/m5249evb/m5249evb.c +++ b/board/freescale/m5249evb/m5249evb.c @@ -42,7 +42,7 @@ int checkboard (void) { /* * Set LED on */ - val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED; + val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED; mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */ return 0; @@ -57,13 +57,13 @@ phys_size_t initdram (int board_type) { * RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1 */ -#ifdef CFG_FAST_CLK +#ifdef CONFIG_SYS_FAST_CLK /* * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39 */ mbar_writeShort(MCFSIM_DCR, 0x8239); -#elif CFG_PLL_BYPASS +#elif CONFIG_SYS_PLL_BYPASS /* * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K) * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02 @@ -101,7 +101,7 @@ phys_size_t initdram (int board_type) { mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */ - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index afdb7202c..aec7e9bf4 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c index 1bf1e9759..08f767d10 100644 --- a/board/freescale/m5253demo/flash.c +++ b/board/freescale/m5253demo/flash.c @@ -28,7 +28,7 @@ #include <asm/immap.h> -#ifndef CFG_FLASH_CFI +#ifndef CONFIG_SYS_FLASH_CFI typedef unsigned short FLASH_PORT_WIDTH; typedef volatile unsigned short FLASH_PORT_WIDTHV; @@ -49,14 +49,14 @@ int flash_get_offsets(ulong base, flash_info_t * info); int write_word(flash_info_t * info, FPWV * dest, u16 data); void inline spin_wheel(void); -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; ulong flash_init(void) { ulong size = 0; ulong fbase = 0; - fbase = (ulong) CFG_FLASH_BASE; + fbase = (ulong) CONFIG_SYS_FLASH_BASE; flash_get_size((FPWV *) fbase, &flash_info[0]); flash_get_offsets((ulong) fbase, &flash_info[0]); fbase += flash_info[0].size; @@ -64,8 +64,8 @@ ulong flash_init(void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); return size; } @@ -77,8 +77,8 @@ int flash_get_offsets(ulong base, flash_info_t * info) if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { info->start[0] = base; - for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) { - info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ; + for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) { + info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ; info->protect[k] = 0; } } @@ -174,16 +174,16 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info) info->sector_count = 0; info->size = 0; - info->sector_count = CFG_SST_SECT; - info->size = CFG_SST_SECT * CFG_SST_SECTSZ; + info->sector_count = CONFIG_SYS_SST_SECT; + info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ; /* reset ID mode */ *addr = (FPWV) 0x00F000F0; - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } return (info->size); @@ -235,7 +235,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) start = get_timer(0); last = start; - if ((s_last - s_first) == (CFG_SST_SECT - 1)) { + if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) { if (prot == 0) { addr = (FPWV *) info->start[0]; @@ -255,7 +255,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) count = 0; } - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); *addr = 0x00F0; /* reset to read mode */ @@ -271,7 +271,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) enable_interrupts(); return 0; - } else if (prot == CFG_SST_SECT) { + } else if (prot == CONFIG_SYS_SST_SECT) { return 1; } } @@ -294,7 +294,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) flag = disable_interrupts(); - base = (FPWV *) (CFG_FLASH_BASE); /* First sector */ + base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* First sector */ base[FLASH_CYCLE1] = 0x00AA; /* unlock */ base[FLASH_CYCLE2] = 0x0055; /* unlock */ @@ -308,7 +308,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) while ((*addr & 0x0080) != 0x0080) { if (get_timer(start) > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); *addr = 0x00F0; /* reset to read mode */ @@ -424,7 +424,7 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data) return (2); } - base = (FPWV *) (CFG_FLASH_BASE); + base = (FPWV *) (CONFIG_SYS_FLASH_BASE); /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); @@ -444,7 +444,7 @@ int write_word(flash_info_t * info, FPWV * dest, u16 data) /* data polling for D7 */ while (res == 0 && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (u8) 0x00F000F0; /* reset bank */ res = 1; } diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 2eb6a0444..b39cd4d7a 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -45,7 +45,7 @@ phys_size_t initdram(int board_type) if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, temp; - RC = (CFG_CLK / 1000000) >> 1; + RC = (CONFIG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* Initialize DRAM Control Register: DCR */ @@ -56,7 +56,7 @@ phys_size_t initdram(int board_type) __asm__("nop"); /* Initialize DMR0 */ - dramsize = (CFG_SDRAM_SIZE << 20); + dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); temp = (dramsize - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, temp | 1); __asm__("nop"); @@ -65,7 +65,7 @@ phys_size_t initdram(int board_type) __asm__("nop"); /* Write to this block to initiate precharge */ - *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; + *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; __asm__("nop"); /* Set RE bit in DACR */ @@ -81,7 +81,7 @@ phys_size_t initdram(int board_type) mbar_readLong(MCFSIM_DACR0) | 0x0040); __asm__("nop"); - *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; } return dramsize; @@ -104,7 +104,7 @@ int ide_preinit(void) void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; + volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ @@ -121,7 +121,7 @@ void ide_set_reset(int idereset) mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); #define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CFG_CLK / 2); /* period in ns */ + period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ ata->t1 = CALC_TIMING(piotms[2][0]); diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index 4bdea5ed5..a29576457 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index f3b1efdb2..ae69f67b4 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -43,7 +43,7 @@ phys_size_t initdram(int board_type) if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, dramsize; - RC = (CFG_CLK / 1000000) >> 1; + RC = (CONFIG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* Initialize DRAM Control Register: DCR */ @@ -54,7 +54,7 @@ phys_size_t initdram(int board_type) asm("nop"); /* Initialize DMR0 */ - dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; + dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, dramsize | 1); asm("nop"); @@ -62,7 +62,7 @@ phys_size_t initdram(int board_type) asm("nop"); /* Write to this block to initiate precharge */ - *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; + *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; asm("nop"); /* Set RE bit in DACR */ @@ -78,10 +78,10 @@ phys_size_t initdram(int board_type) mbar_readLong(MCFSIM_DACR0) | 0x0040); asm("nop"); - *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; } - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } int testdram(void) @@ -101,7 +101,7 @@ int ide_preinit(void) void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; + volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ @@ -118,7 +118,7 @@ void ide_set_reset(int idereset) mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); #define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CFG_CLK / 2); /* period in ns */ + period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ ata->t1 = CALC_TIMING(piotms[2][0]); diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index 6d225f528..239cf95e5 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5271evb/Makefile b/board/freescale/m5271evb/Makefile index 2ec71ee1d..424ab1cf9 100644 --- a/board/freescale/m5271evb/Makefile +++ b/board/freescale/m5271evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c index e089d5f02..5505cc42c 100644 --- a/board/freescale/m5271evb/m5271evb.c +++ b/board/freescale/m5271evb/m5271evb.c @@ -66,7 +66,7 @@ phys_size_t initdram (int board_type) { * PS: 32bit port size */ mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) + MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | MCF_SDRAMC_DACRn_CASL(1) | MCF_SDRAMC_DACRn_CBM(3) | MCF_SDRAMC_DACRn_PS(0)); @@ -85,7 +85,7 @@ phys_size_t initdram (int board_type) { asm(" nop"); /* Write to this block to initiate precharge */ - *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5; + *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; /* Set RE bit in DACR */ mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0) @@ -108,10 +108,10 @@ phys_size_t initdram (int board_type) { * Burst Type = Sequential * Burst Length = 1 */ - *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5; + *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5; } - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; int testdram (void) { diff --git a/board/freescale/m5271evb/mii.c b/board/freescale/m5271evb/mii.c deleted file mode 100644 index 78a7028bc..000000000 --- a/board/freescale/m5271evb/mii.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); - } else { - } - - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ -#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" -#define STR_ID_KS8721BL "KS8721BL" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - strcpy(info->phy_name, - STR_ID_KS8721BL); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - printf(STR_ID_KS8721BL); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index c07d02383..0bc7fa1ab 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) diff --git a/board/freescale/m5272c3/Makefile b/board/freescale/m5272c3/Makefile index be704b76f..424ab1cf9 100644 --- a/board/freescale/m5272c3/Makefile +++ b/board/freescale/m5272c3/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5272c3/flash.c b/board/freescale/m5272c3/flash.c deleted file mode 100644 index ea0b1fd7e..000000000 --- a/board/freescale/m5272c3/flash.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#define PHYS_FLASH_1 CFG_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_PL160CB & FLASH_TYPEMASK): - printf ("AM29PL160CB (16Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done: - return; -} - - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_PL160CB & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured to many flash banks!\n"); - - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 224 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 10)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x40000 + 0x40000 * (j - - 4); - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x3ffff, &flash_info[0]); - - return size; -} - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - printf ("\n"); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = - (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - set_timer (0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - } - -#if 0 - if (cnt & 1) { - printf ("odd transfer sizes not supported\n"); - return ERR_ALIGN; - } -#endif - - wp = addr; - - if (addr & 1) { - data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *) - src); - if ((rc = write_word (info, wp - 1, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src) << 8) | - *((volatile u8 *) (wp + 1)); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c index d17cb2ef9..902ca3aac 100644 --- a/board/freescale/m5272c3/m5272c3.c +++ b/board/freescale/m5272c3/m5272c3.c @@ -40,7 +40,7 @@ phys_size_t initdram (int board_type) { /* Dummy write to start SDRAM */ *((volatile unsigned long *)0) = 0; - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; int testdram (void) { diff --git a/board/freescale/m5272c3/mii.c b/board/freescale/m5272c3/mii.c deleted file mode 100644 index b30ba803f..000000000 --- a/board/freescale/m5272c3/mii.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER | GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 | GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 | GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3; - } else { - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_AMD79C874VC "AMD79C874VC" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - strcpy(info->phy_name, - STR_ID_AMD79C874VC); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - printf(STR_ID_AMD79C874VC); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index 8420c91a7..e5c7b67c6 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5275evb/Makefile b/board/freescale/m5275evb/Makefile index 74c252869..981763d20 100644 --- a/board/freescale/m5275evb/Makefile +++ b/board/freescale/m5275evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c index be19e0275..35c9b2018 100644 --- a/board/freescale/m5275evb/m5275evb.c +++ b/board/freescale/m5275evb/m5275evb.c @@ -44,7 +44,7 @@ phys_size_t initdram(int board_type) gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */ /* Set up chip select */ - sdp->sdbar0 = CFG_SDRAM_BASE; + sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE; sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V; /* Set up timing */ @@ -58,34 +58,34 @@ phys_size_t initdram(int board_type) sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; /* Dummy write to start SDRAM */ - *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LEMR */ sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) | MCF_SDRAMC_SDMR_CMD; - *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Send LMR */ sdp->sdmr = 0x058d0000; - *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); /* Set precharge */ sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL; - *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop manual precharge, send 2 IREF */ sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL); sdp->sdcr |= MCF_SDRAMC_SDCR_IREF; - *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; - *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Write mode register, clear reset DLL */ sdp->sdmr = 0x018d0000; - *((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696; + *((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696; /* Stop sending commands */ sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD); @@ -100,7 +100,7 @@ phys_size_t initdram(int board_type) | MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1) | MCF_SDRAMC_SDCR_DQS_OE(0x3); - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; int testdram(void) diff --git a/board/freescale/m5275evb/mii.c b/board/freescale/m5275evb/mii.c deleted file mode 100644 index 6c7ace956..000000000 --- a/board/freescale/m5275evb/mii.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - struct fec_info_s *info = (struct fec_info_s *) dev->priv; - volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; - - if (setclear) { - /* Enable Ethernet pins */ - if (info->iobase == CFG_FEC0_IOBASE) { - gpio->par_feci2c |= 0x0F00; - gpio->par_fec0hl |= 0xC0; - } else { - gpio->par_feci2c |= 0x00A0; - gpio->par_fec1hl |= 0xC0; - } - } else { - if (info->iobase == CFG_FEC0_IOBASE) { - gpio->par_feci2c &= ~0x0F00; - gpio->par_fec0hl &= ~0xC0; - } else { - gpio->par_feci2c &= ~0x00A0; - gpio->par_fec1hl &= ~0xC0; - } - } - - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ -#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" -#define STR_ID_KS8721BL "KS8721BL" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - strcpy(info->phy_name, - STR_ID_KS8721BL); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - printf(STR_ID_KS8721BL); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index d810ebc14..a3e03d556 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/freescale/m5282evb/Makefile b/board/freescale/m5282evb/Makefile index 2ec71ee1d..424ab1cf9 100644 --- a/board/freescale/m5282evb/Makefile +++ b/board/freescale/m5282evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c index 31d69231a..b0c9fc83f 100644 --- a/board/freescale/m5282evb/m5282evb.c +++ b/board/freescale/m5282evb/m5282evb.c @@ -36,7 +36,7 @@ phys_size_t initdram (int board_type) { u32 dramsize, i, dramclk; - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -45,7 +45,7 @@ phys_size_t initdram (int board_type) if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) { - dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); /* Initialize DRAM Control Register: DCR */ MCFSDRAMC_DCR = (0 @@ -55,7 +55,7 @@ phys_size_t initdram (int board_type) /* Initialize DACR0 */ MCFSDRAMC_DACR0 = (0 - | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) + | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE) | MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | MCFSDRAMC_DACR_PS_32); @@ -77,7 +77,7 @@ phys_size_t initdram (int board_type) } /* Write to this block to initiate precharge */ - *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; + *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; asm("nop"); /* Set RE (bit 15) in DACR */ @@ -94,7 +94,7 @@ phys_size_t initdram (int board_type) asm("nop"); /* Write to the SDRAM Mode Register */ - *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } return dramsize; } diff --git a/board/freescale/m5282evb/mii.c b/board/freescale/m5282evb/mii.c deleted file mode 100644 index 8ae2ec69c..000000000 --- a/board/freescale/m5282evb/mii.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - MCFGPIO_PASPAR |= 0x0F00; - MCFGPIO_PEHLPAR = CFG_PEHLPAR; - } else { - MCFGPIO_PASPAR &= 0xF0FF; - MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR; - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_AMD79C874VC 0x0022561B /* AMD 79C874 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_AMD79C874VC "AMD79C874VC" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - strcpy(info->phy_name, - STR_ID_AMD79C874VC); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_AMD79C874VC: - printf(STR_ID_AMD79C874VC); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index 96fde6538..707b228af 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/mgsuvd/Makefile b/board/freescale/m53017evb/Makefile index af0d400c8..981763d20 100644 --- a/board/mgsuvd/Makefile +++ b/board/freescale/m53017evb/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2007 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/freescale/m53017evb/config.mk b/board/freescale/m53017evb/config.mk new file mode 100644 index 000000000..ce014edca --- /dev/null +++ b/board/freescale/m53017evb/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0 diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c new file mode 100644 index 000000000..f331786bf --- /dev/null +++ b/board/freescale/m53017evb/m53017evb.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + puts("Board: "); + puts("Freescale M53017EVB\n"); + return 0; +}; + +phys_size_t initdram(int board_type) +{ + volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + u32 dramsize, i; + + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; + + for (i = 0x13; i < 0x20; i++) { + if (dramsize == (1 << i)) + break; + } + i--; + + sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); +#ifdef CONFIG_SYS_SDRAM_BASE1 + sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i); +#endif + sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + + udelay(500); + + /* Issue PALL */ + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + /* Perform two refresh cycles */ + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + asm("nop"); + + /* Issue LEMR */ + sdram->mode = CONFIG_SYS_SDRAM_MODE; + asm("nop"); + sdram->mode = CONFIG_SYS_SDRAM_EMOD; + asm("nop"); + + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + asm("nop"); + + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + asm("nop"); + + udelay(100); + + return dramsize; +}; + +int testdram(void) +{ + /* TODO: XXX XXX XXX */ + printf("DRAM test not implemented!\n"); + + return (0); +} diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index 1aa53c23f..dc531418c 100644 --- a/board/freescale/m54455evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -55,14 +55,14 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf5445x/start.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) + cpu/mcf532x/start.o (.text) + cpu/mcf532x/libmcf532x.a (.text) + lib_m68k/libm68k.a (.text) common/dlmalloc.o (.text) lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5329evb/Makefile b/board/freescale/m5329evb/Makefile index ab0f11e9d..07b693c13 100644 --- a/board/freescale/m5329evb/Makefile +++ b/board/freescale/m5329evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o nand.o +COBJS = $(BOARD).o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c index f9fa9fb9c..b4df22f1f 100644 --- a/board/freescale/m5329evb/m5329evb.c +++ b/board/freescale/m5329evb/m5329evb.c @@ -42,7 +42,7 @@ phys_size_t initdram(int board_type) volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -50,29 +50,29 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CFG_SDRAM_BASE | i); - sdram->cfg1 = CFG_SDRAM_CFG1; - sdram->cfg2 = CFG_SDRAM_CFG2; + sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); + sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; /* Issue PALL */ - sdram->ctrl = CFG_SDRAM_CTRL | 2; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; /* Issue LEMR */ - sdram->mode = CFG_SDRAM_EMOD; - sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + sdram->mode = CONFIG_SYS_SDRAM_EMOD; + sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CFG_SDRAM_CTRL | 2); + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CFG_SDRAM_CTRL | 4; - sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->mode = CFG_SDRAM_MODE; + sdram->mode = CONFIG_SYS_SDRAM_MODE; - sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; udelay(100); diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c deleted file mode 100644 index 8f6abf3ee..000000000 --- a/board/freescale/m5329evb/mii.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; - } else { - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - strcpy(info->phy_name, - STR_ID_DP83848VV); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - printf(STR_ID_DP83848VV); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index f84912e37..cf27dda2f 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -36,56 +36,42 @@ DECLARE_GLOBAL_DATA_PTR; #include <linux/mtd/mtd.h> #define SET_CLE 0x10 -#define CLR_CLE ~SET_CLE #define SET_ALE 0x08 -#define CLR_ALE ~SET_ALE -static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtdinfo->priv; -/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */ - u32 nand_baseaddr = (u32) this->IO_ADDR_W; + volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - nand_baseaddr |= SET_CLE; - else - nand_baseaddr &= CLR_CLE; - if ( ctrl & NAND_ALE ) - nand_baseaddr |= SET_ALE; - else - nand_baseaddr &= CLR_ALE; - } - this->IO_ADDR_W = (void __iomem *)(nand_baseaddr); + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} + IO_ADDR_W &= ~(SET_ALE | SET_CLE); + *nCE &= 0xFFFB; -static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - *((volatile u8 *)(this->IO_ADDR_W)) = byte; -} + if (ctrl & NAND_NCE) + *nCE |= 0x0004; + if (ctrl & NAND_CLE) + IO_ADDR_W |= SET_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= SET_ALE; -static u8 nand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - return (u8) (*((volatile u8 *)this->IO_ADDR_R)); -} + this->IO_ADDR_W = (void *)IO_ADDR_W; + } -static int nand_dev_ready(struct mtd_info *mtdinfo) -{ - return 1; + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } int board_nand_init(struct nand_chip *nand) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; - - /* set up pin configuration */ + /* + * set up pin configuration - enabled 2nd output buffer's signals + * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) + * to use nCE signal + */ gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; gpio->pddr_timer |= 0x08; gpio->ppd_timer |= 0x08; @@ -95,9 +81,6 @@ int board_nand_init(struct nand_chip *nand) nand->chip_delay = 50; nand->ecc.mode = NAND_ECC_SOFT; nand->cmd_ctrl = nand_hwcontrol; - nand->read_byte = nand_read_byte; - nand->write_byte = nand_write_byte; - nand->dev_ready = nand_dev_ready; return 0; } diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index 1ddfbc470..c9da922ae 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m5373evb/Makefile b/board/freescale/m5373evb/Makefile index ab0f11e9d..07b693c13 100644 --- a/board/freescale/m5373evb/Makefile +++ b/board/freescale/m5373evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o nand.o +COBJS = $(BOARD).o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c index a269ee6d4..376de4b95 100644 --- a/board/freescale/m5373evb/m5373evb.c +++ b/board/freescale/m5373evb/m5373evb.c @@ -42,7 +42,7 @@ phys_size_t initdram(int board_type) volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -50,29 +50,29 @@ phys_size_t initdram(int board_type) } i--; - sdram->cs0 = (CFG_SDRAM_BASE | i); - sdram->cfg1 = CFG_SDRAM_CFG1; - sdram->cfg2 = CFG_SDRAM_CFG2; + sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i); + sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; /* Issue PALL */ - sdram->ctrl = CFG_SDRAM_CTRL | 2; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; /* Issue LEMR */ - sdram->mode = CFG_SDRAM_EMOD; - sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + sdram->mode = CONFIG_SYS_SDRAM_EMOD; + sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CFG_SDRAM_CTRL | 2); + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CFG_SDRAM_CTRL | 4; - sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->mode = CFG_SDRAM_MODE; + sdram->mode = CONFIG_SYS_SDRAM_MODE; - sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; udelay(100); diff --git a/board/freescale/m5373evb/mii.c b/board/freescale/m5373evb/mii.c deleted file mode 100644 index 8f6abf3ee..000000000 --- a/board/freescale/m5373evb/mii.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - if (setclear) { - gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC; - gpio->par_feci2c |= - GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO; - } else { - gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC); - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO); - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - strcpy(info->phy_name, - STR_ID_DP83848VV); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - printf(STR_ID_DP83848VV); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index 404a9c386..3ebef059e 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -41,19 +41,21 @@ DECLARE_GLOBAL_DATA_PTR; static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { struct nand_chip *this = mtdinfo->priv; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - u32 nand_baseaddr = (u32) this->IO_ADDR_W; + volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(SET_ALE | SE_CLE); + IO_ADDR_W &= ~(SET_ALE | SET_CLE); + *nCE &= 0xFFFB; + + if (ctrl & NAND_NCE) + *nCE |= 0x0004; if (ctrl & NAND_CLE) IO_ADDR_W |= SET_CLE; if (ctrl & NAND_ALE) IO_ADDR_W |= SET_ALE; - at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE)); this->IO_ADDR_W = (void *)IO_ADDR_W; } @@ -67,10 +69,13 @@ int board_nand_init(struct nand_chip *nand) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - *((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004; fbcs->csmr2 &= ~FBCS_CSMR_WP; - /* set up pin configuration */ + /* + * set up pin configuration - enabled 2nd output buffer's signals + * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc) + * to use nCE signal + */ gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3; gpio->pddr_timer |= 0x08; gpio->ppd_timer |= 0x08; diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index d30a401be..fcf1ff1d8 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m54451evb/Makefile b/board/freescale/m54451evb/Makefile index 74c252869..981763d20 100644 --- a/board/freescale/m54451evb/Makefile +++ b/board/freescale/m54451evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c index 768f40bb0..088c8c4d1 100644 --- a/board/freescale/m54451evb/m54451evb.c +++ b/board/freescale/m54451evb/m54451evb.c @@ -49,16 +49,16 @@ phys_size_t initdram(int board_type) * Serial Boot: The dram is already initialized in start.S * only require to return DRAM size */ - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; #else volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); u32 i; - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; - if ((sdram->sdcfg1 == CFG_SDRAM_CFG1) && - (sdram->sdcfg2 == CFG_SDRAM_CFG2)) + if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) && + (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2)) return dramsize; for (i = 0x13; i < 0x20; i++) { @@ -67,32 +67,32 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH; + gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; - sdram->sdcs0 = (CFG_SDRAM_BASE | i); + sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); - sdram->sdcfg1 = CFG_SDRAM_CFG1; - sdram->sdcfg2 = CFG_SDRAM_CFG2; + sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; udelay(200); /* Issue PALL */ - sdram->sdcr = CFG_SDRAM_CTRL | 2; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; __asm__("nop"); /* Perform two refresh cycles */ - sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; __asm__("nop"); - sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; __asm__("nop"); /* Issue LEMR */ - sdram->sdmr = CFG_SDRAM_MODE; + sdram->sdmr = CONFIG_SYS_SDRAM_MODE; __asm__("nop"); - sdram->sdmr = CFG_SDRAM_EMOD; + sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; __asm__("nop"); - sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000000; + sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000; udelay(100); #endif diff --git a/board/freescale/m54451evb/mii.c b/board/freescale/m54451evb/mii.c deleted file mode 100644 index 5a4330c74..000000000 --- a/board/freescale/m54451evb/mii.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_s *info = (struct fec_info_s *)dev->priv; - - if (setclear) { - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; - else - gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; - } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; - else - gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_KSZ8041NL 0x00221512 -#define STR_ID_KSZ8041NL "KSZ8041NL" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - struct eth_device *dev; - int i, miispd; - u16 rst = 0; - - dev = eth_get_dev(); - - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); - for (i = 0; i < FEC_RESET_DELAY; ++i) { - udelay(500); - miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); - if ((rst & PHY_BMCR_RESET) == 0) - break; - } - if (i == FEC_RESET_DELAY) - printf("Mii reset timeout %d\n", i); -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_KSZ8041NL: - strcpy(info->phy_name, - STR_ID_KSZ8041NL); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_KSZ8041NL: - printf(STR_ID_KSZ8041NL); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__ ((weak, alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m54451evb/u-boot.spa b/board/freescale/m54451evb/u-boot.spa index 22c604865..08e184c1e 100644 --- a/board/freescale/m54451evb/u-boot.spa +++ b/board/freescale/m54451evb/u-boot.spa @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m54451evb/u-boot.stm b/board/freescale/m54451evb/u-boot.stm index 0752e2715..e9eac67b9 100644 --- a/board/freescale/m54451evb/u-boot.stm +++ b/board/freescale/m54451evb/u-boot.stm @@ -68,7 +68,7 @@ SECTIONS board/freescale/m54455evb/m54455evb.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) */ *(.text) *(.fixup) diff --git a/board/freescale/m54455evb/Makefile b/board/freescale/m54455evb/Makefile index 74c252869..981763d20 100644 --- a/board/freescale/m54455evb/Makefile +++ b/board/freescale/m54455evb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c index 100682a26..293b5b0e4 100644 --- a/board/freescale/m54455evb/m54455evb.c +++ b/board/freescale/m54455evb/m54455evb.c @@ -45,13 +45,13 @@ phys_size_t initdram(int board_type) * Serial Boot: The dram is already initialized in start.S * only require to return DRAM size */ - dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; #else volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); u32 i; - dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) @@ -59,33 +59,33 @@ phys_size_t initdram(int board_type) } i--; - gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH; + gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH; - sdram->sdcs0 = (CFG_SDRAM_BASE | i); - sdram->sdcs1 = (CFG_SDRAM_BASE1 | i); + sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i); + sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i); - sdram->sdcfg1 = CFG_SDRAM_CFG1; - sdram->sdcfg2 = CFG_SDRAM_CFG2; + sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2; /* Issue PALL */ - sdram->sdcr = CFG_SDRAM_CTRL | 2; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; /* Issue LEMR */ - sdram->sdmr = CFG_SDRAM_EMOD | 0x408; - sdram->sdmr = CFG_SDRAM_MODE | 0x300; + sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408; + sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300; udelay(500); /* Issue PALL */ - sdram->sdcr = CFG_SDRAM_CTRL | 2; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2; /* Perform two refresh cycles */ - sdram->sdcr = CFG_SDRAM_CTRL | 4; - sdram->sdcr = CFG_SDRAM_CTRL | 4; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->sdmr = CFG_SDRAM_MODE | 0x200; + sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200; - sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00; + sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00; udelay(100); #endif @@ -175,11 +175,11 @@ void pci_init_board(void) #include <flash.h> ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) { - int sect[] = CFG_ATMEL_SECT; - int sectsz[] = CFG_ATMEL_SECTSZ; + int sect[] = CONFIG_SYS_ATMEL_SECT; + int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ; int i, j, k; - if (base != CFG_ATMEL_BASE) + if (base != CONFIG_SYS_ATMEL_BASE) return 0; info->flash_id = 0x01000000; @@ -205,9 +205,9 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) info->name = "CFI conformant"; info->size = 0; - info->sector_count = CFG_ATMEL_TOTALSECT; + info->sector_count = CONFIG_SYS_ATMEL_TOTALSECT; info->start[0] = base; - for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) { + for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) { info->size += sect[i] * sectsz[i]; for (j = 0; j < sect[i]; j++, k++) { @@ -218,4 +218,4 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) return 1; } -#endif /* CFG_FLASH_CFI */ +#endif /* CONFIG_SYS_FLASH_CFI */ diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c deleted file mode 100644 index 0be5439ef..000000000 --- a/board/freescale/m54455evb/mii.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_s *info = (struct fec_info_s *)dev->priv; - - if (setclear) { - gpio->par_feci2c |= - (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; - else - gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; - } else { - gpio->par_feci2c &= - ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); - - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; - else - gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - struct eth_device *dev; - int i, miispd; - u16 rst = 0; - - dev = eth_get_dev(); - - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); - for (i = 0; i < FEC_RESET_DELAY; ++i) { - udelay(500); - miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); - if ((rst & PHY_BMCR_RESET) == 0) - break; - } - if (i == FEC_RESET_DELAY) - printf("Mii reset timeout %d\n", i); -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - strcpy(info->phy_name, - STR_ID_DP83848VV); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_DP83848VV: - printf(STR_ID_DP83848VV); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m54455evb/u-boot.atm b/board/freescale/m54455evb/u-boot.atm index 22c604865..08e184c1e 100644 --- a/board/freescale/m54455evb/u-boot.atm +++ b/board/freescale/m54455evb/u-boot.atm @@ -62,7 +62,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m547xevb/Makefile b/board/freescale/m547xevb/Makefile index 74c252869..981763d20 100644 --- a/board/freescale/m547xevb/Makefile +++ b/board/freescale/m547xevb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c index 6d7d27090..9f1ec3854 100644 --- a/board/freescale/m547xevb/m547xevb.c +++ b/board/freescale/m547xevb/m547xevb.c @@ -43,53 +43,53 @@ phys_size_t initdram(int board_type) volatile siu_t *siu = (siu_t *) (MMAP_SIU); volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); u32 dramsize, i; -#ifdef CFG_DRAMSZ1 +#ifdef CONFIG_SYS_DRAMSZ1 u32 temp; #endif - siu->drv = CFG_SDRAM_DRVSTRENGTH; + siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; - dramsize = CFG_DRAMSZ * 0x100000; + dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; } i--; - siu->cs0cfg = (CFG_SDRAM_BASE | i); + siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); -#ifdef CFG_DRAMSZ1 - temp = CFG_DRAMSZ1 * 0x100000; +#ifdef CONFIG_SYS_DRAMSZ1 + temp = CONFIG_SYS_DRAMSZ1 * 0x100000; for (i = 0x13; i < 0x20; i++) { if (temp == (1 << i)) break; } i--; dramsize += temp; - siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i); + siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); #endif - sdram->cfg1 = CFG_SDRAM_CFG1; - sdram->cfg2 = CFG_SDRAM_CFG2; + sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; /* Issue PALL */ - sdram->ctrl = CFG_SDRAM_CTRL | 2; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; /* Issue LEMR */ - sdram->mode = CFG_SDRAM_EMOD; - sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + sdram->mode = CONFIG_SYS_SDRAM_EMOD; + sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CFG_SDRAM_CTRL | 2); + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CFG_SDRAM_CTRL | 4; - sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->mode = CFG_SDRAM_MODE; + sdram->mode = CONFIG_SYS_SDRAM_MODE; - sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; udelay(100); diff --git a/board/freescale/m547xevb/mii.c b/board/freescale/m547xevb/mii.c deleted file mode 100644 index 5b2683b6c..000000000 --- a/board/freescale/m547xevb/mii.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <net.h> - -#include <asm/immap.h> -#include <asm/fec.h> -#include <asm/fsl_mcdmafec.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; - - if (setclear) { - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_feci2cirq |= 0xF000; - else - gpio->par_feci2cirq |= 0x0FC0; - } else { - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_feci2cirq &= 0x0FFF; - else - gpio->par_feci2cirq &= 0xF03F; - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ -#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" -#define STR_ID_BCM5222 "BCM5222" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_dma *info) -{ - volatile fecdma_t *fecp = (fecdma_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_dma *info; - struct eth_device *dev; - volatile fecdma_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fecdma_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_dma *info = dev->priv; - int phyaddr, pass, temp; - uint phyno, phytype; - - if (info->phyname_init) { - return info->phy_addr; - } - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - temp = 0; - if (info->index > 0) { - /* Some phy have multiple address, to solve the issue - where phyno keeps starting from 0, check the - previous phy address if both miibase are the same. */ - if (info->miibase == (info->next)->miibase) { - temp = (info->next)->phy_addr + 1; - } - } - - for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_BCM5222: - strcpy(info->phy_name, STR_ID_BCM5222); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_BCM5222: - printf(STR_ID_BCM5222); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__ ((weak, alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fecdma_t *fecp; - struct fec_info_dma *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fecdma_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index cc7f3eba8..c25c8dcdc 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS common/dlmalloc.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/m548xevb/Makefile b/board/freescale/m548xevb/Makefile index 74c252869..981763d20 100644 --- a/board/freescale/m548xevb/Makefile +++ b/board/freescale/m548xevb/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o mii.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c index e6510c955..4a2a5c78f 100644 --- a/board/freescale/m548xevb/m548xevb.c +++ b/board/freescale/m548xevb/m548xevb.c @@ -44,49 +44,49 @@ phys_size_t initdram(int board_type) volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); u32 dramsize, i; - siu->drv = CFG_SDRAM_DRVSTRENGTH; + siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; - dramsize = CFG_DRAMSZ * 0x100000; + dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; } i--; - siu->cs0cfg = (CFG_SDRAM_BASE | i); + siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); -#ifdef CFG_DRAMSZ1 - temp = CFG_DRAMSZ1 * 0x100000; +#ifdef CONFIG_SYS_DRAMSZ1 + temp = CONFIG_SYS_DRAMSZ1 * 0x100000; for (i = 0x13; i < 0x20; i++) { if (temp == (1 << i)) break; } i--; dramsize += temp; - siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i); + siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); #endif - sdram->cfg1 = CFG_SDRAM_CFG1; - sdram->cfg2 = CFG_SDRAM_CFG2; + sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; + sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; /* Issue PALL */ - sdram->ctrl = CFG_SDRAM_CTRL | 2; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; /* Issue LEMR */ - sdram->mode = CFG_SDRAM_EMOD; - sdram->mode = (CFG_SDRAM_MODE | 0x04000000); + sdram->mode = CONFIG_SYS_SDRAM_EMOD; + sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); udelay(500); /* Issue PALL */ - sdram->ctrl = (CFG_SDRAM_CTRL | 2); + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); /* Perform two refresh cycles */ - sdram->ctrl = CFG_SDRAM_CTRL | 4; - sdram->ctrl = CFG_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->mode = CFG_SDRAM_MODE; + sdram->mode = CONFIG_SYS_SDRAM_MODE; - sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; udelay(100); diff --git a/board/freescale/m548xevb/mii.c b/board/freescale/m548xevb/mii.c deleted file mode 100644 index 5b2683b6c..000000000 --- a/board/freescale/m548xevb/mii.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <config.h> -#include <net.h> - -#include <asm/immap.h> -#include <asm/fec.h> -#include <asm/fsl_mcdmafec.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; - - if (setclear) { - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_feci2cirq |= 0xF000; - else - gpio->par_feci2cirq |= 0x0FC0; - } else { - if (info->iobase == CFG_FEC0_IOBASE) - gpio->par_feci2cirq &= 0x0FFF; - else - gpio->par_feci2cirq &= 0xF03F; - } - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ -#define PHY_ID_BCM5222 0x00406322 /* Broadcom 5222 */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" -#define STR_ID_BCM5222 "BCM5222" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_dma *info) -{ - volatile fecdma_t *fecp = (fecdma_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_dma *info; - struct eth_device *dev; - volatile fecdma_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fecdma_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_dma *info = dev->priv; - int phyaddr, pass, temp; - uint phyno, phytype; - - if (info->phyname_init) { - return info->phy_addr; - } - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - temp = 0; - if (info->index > 0) { - /* Some phy have multiple address, to solve the issue - where phyno keeps starting from 0, check the - previous phy address if both miibase are the same. */ - if (info->miibase == (info->next)->miibase) { - temp = (info->next)->phy_addr + 1; - } - } - - for (phyno = temp; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_BCM5222: - strcpy(info->phy_name, STR_ID_BCM5222); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_BCM5222: - printf(STR_ID_BCM5222); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__ ((weak, alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fecdma_t *fecp; - struct fec_info_dma *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fecdma_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index cc7f3eba8..c25c8dcdc 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS common/dlmalloc.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S index 521301fce..b9495fd34 100644 --- a/board/freescale/mpc7448hpc2/asm_init.S +++ b/board/freescale/mpc7448hpc2/asm_init.S @@ -123,7 +123,7 @@ board_asm_init: /* Initialize pointer to Tsi108 register space */ - LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ + LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */ ori r4,r29,TSI108_PB_REG_OFFSET /* Check Processor Version Number */ @@ -214,12 +214,12 @@ do_tsi108_init: ori r4,r29,TSI108_PB_REG_OFFSET -#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE) +#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE) /* Relocate (if required) Tsi108 registers. Set new value for * PB_REG_BAR: * Note we are in the 32-bit address mode. */ - LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ + LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */ stw r5,PB_REG_BAR(r4) andis. r29,r5,0xFFFF sync diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c index 6f74c314e..117b951c5 100644 --- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c +++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c @@ -32,6 +32,7 @@ #include <common.h> #include <74xx_7xx.h> #include <fdt_support.h> +#include <netdev.h> #undef DEBUG @@ -59,7 +60,7 @@ int checkboard (void) { int l_type = 0; - printf ("BOARD: %s\n", CFG_BOARD_NAME); + printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME); return (l_type); } @@ -92,3 +93,12 @@ ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#if defined(CONFIG_TSI108_ETH) + rc = tsi108_eth_initialize(bis); +#endif + return rc; +} diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c index 9c40b72a1..74bb564ed 100644 --- a/board/freescale/mpc7448hpc2/tsi108_init.c +++ b/board/freescale/mpc7448hpc2/tsi108_init.c @@ -88,7 +88,7 @@ PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = { {0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/ }; -#ifdef CFG_CLK_SPREAD +#ifdef CONFIG_SYS_CLK_SPREAD typedef struct { ulong ctrl0; ulong ctrl1; @@ -111,7 +111,7 @@ static PLL_CTRL_SET pll0_config[8] = { {0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */ {0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */ }; -#endif /* CFG_CLK_SPREAD */ +#endif /* CONFIG_SYS_CLK_SPREAD */ /* * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT @@ -129,7 +129,7 @@ unsigned long get_board_bus_clk (void) ulong i; /* Detect PB clock freq. */ - i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ return pb_clk_sel[i] * 1000000; @@ -146,7 +146,7 @@ int board_early_init_f (void) ulong i; gd->mem_clk = 0; - i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + + i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); i = (i >> 20) & 0x07; /* Get GD PLL multiplier */ switch (i) { @@ -182,7 +182,7 @@ int board_early_init_r (void) volatile ulong *reg_ptr; reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); + (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900); for (i = 0; i < 32; i++) { *reg_ptr++ = 0x00000201; /* SWAP ENABLED */ @@ -194,7 +194,7 @@ int board_early_init_r (void) /* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2, 0x80000001); __asm__ __volatile__ ("sync"); @@ -202,7 +202,7 @@ int board_early_init_r (void) * read from SDRAM) */ - temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); + temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2); __asm__ __volatile__ ("sync"); /* @@ -221,7 +221,7 @@ int board_early_init_r (void) * initialize pointer to LUT associated with PB_OCN_BAR1 */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); + (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800); for (i = 0; i < 32; i++) { *reg_ptr++ = pb2ocn_lut1[i].lower; @@ -232,73 +232,73 @@ int board_early_init_r (void) /* Base addresses for CS0, CS1, CS2, CS3 */ - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR, 0x00000000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR, 0x00100000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR, 0x00200000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR, 0x00300000); __asm__ __volatile__ ("sync"); /* Masks for HLP banks */ - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK, 0xFFF00000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK, 0xFFF00000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK, 0xFFF00000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK, 0xFFF00000); __asm__ __volatile__ ("sync"); /* Set CTRL0 values for banks */ - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0, 0x7FFC44C2); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0, 0x7FFC44C0); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0, 0x7FFC44C0); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0, 0x7FFC44C2); __asm__ __volatile__ ("sync"); /* Set banks to latched mode, enabled, and other default settings */ - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1, 0x7C0F2000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1, 0x7C0F2000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1, 0x7C0F2000); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1, 0x7C0F2000); __asm__ __volatile__ ("sync"); @@ -306,7 +306,7 @@ int board_early_init_r (void) * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode. * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable) */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1, 0xE0000011); __asm__ __volatile__ ("sync"); @@ -314,7 +314,7 @@ int board_early_init_r (void) * immediate read from SDRAM) */ - temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); + temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1); __asm__ __volatile__ ("sync"); /* @@ -341,7 +341,7 @@ int board_early_init_r (void) temp = get_cpu_type (); if ((CPU_750FX == temp) || (CPU_750GX == temp)) - out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD, 0x00009955); #endif /* DISABLE_PBM */ @@ -351,27 +351,27 @@ int board_early_init_r (void) */ /* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER, 0); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0, 0xFB000001); __asm__ __volatile__ ("sync"); /* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */ - temp = in32(CFG_TSI108_CSR_BASE + + temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT); temp &= ~0xFF00; /* Clear the BUS_NUM field */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT, temp); /* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER, 0); __asm__ __volatile__ ("sync"); @@ -379,7 +379,7 @@ int board_early_init_r (void) * and maps it as a IO address. */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO, 0x00000001); __asm__ __volatile__ ("sync"); @@ -405,7 +405,7 @@ int board_early_init_r (void) */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); + (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500); #ifdef DISABLE_PBM @@ -442,7 +442,7 @@ int board_early_init_r (void) __asm__ __volatile__ ("eieio"); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, reg_val); __asm__ __volatile__ ("sync"); @@ -450,9 +450,9 @@ int board_early_init_r (void) * ( 0 is the best choice for easy mapping) */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2, 0x00000000); - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER, 0x00000000); __asm__ __volatile__ ("sync"); @@ -470,7 +470,7 @@ int board_early_init_r (void) * set pointer to LUT associated with PCI P2O_BAR3 */ reg_ptr = - (ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); + (ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600); reg_val = 0x00000004; /* Destination port = SDC */ @@ -490,19 +490,19 @@ int board_early_init_r (void) /* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */ reg_val = - in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + + in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES); reg_val &= ~0x00FF; reg_val |= 0x0071; - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES, reg_val); __asm__ __volatile__ ("sync"); /* Set 64-bit base PCI bus address for window (0x20000000) */ - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER, 0x00000000); - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3, 0x20000000); __asm__ __volatile__ ("sync"); @@ -511,17 +511,17 @@ int board_early_init_r (void) #ifdef ENABLE_PCI_CSR_BAR /* open if required access to Tsi108 CSRs from the PCI/X bus */ /* enable BAR0 on the PCI/X bus */ - reg_val = in32(CFG_TSI108_CSR_BASE + + reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR); reg_val |= 0x02; - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR, reg_val); __asm__ __volatile__ ("sync"); - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER, 0x00000000); - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, - CFG_TSI108_CSR_BASE); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0, + CONFIG_SYS_TSI108_CSR_BASE); __asm__ __volatile__ ("sync"); #endif @@ -530,9 +530,9 @@ int board_early_init_r (void) * Finally enable PCI/X Bus Master and Memory Space access */ - reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); + reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR); reg_val |= 0x06; - out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val); __asm__ __volatile__ ("sync"); #endif /* CONFIG_PCI */ @@ -546,10 +546,10 @@ int board_early_init_r (void) * PB_INT[3] -> MCP (CPU1) * Set interrupt controller outputs as Level_Sensitive/Active_Low */ - out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); - out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); - out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); - out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02); __asm__ __volatile__ ("sync"); /* @@ -584,42 +584,42 @@ unsigned long get_l2cr (void) int misc_init_r (void) { -#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ +#ifdef CONFIG_SYS_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */ ulong i; /* Ensure that Spread-Spectrum is disabled */ - out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); - out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0); + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0); /* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5% */ - out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */ - out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */ /* Initialize PLL0: CG_PB_CLKO */ /* Detect PB clock freq. */ - i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); + i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS); i = (i >> 16) & 0x07; /* Get PB PLL multiplier */ - out32 (CFG_TSI108_CSR_BASE + + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0); - out32 (CFG_TSI108_CSR_BASE + + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1); /* Wait and set SSEN for both PLL0 and 1 */ udelay (1000); - out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */ - out32 (CFG_TSI108_CSR_BASE + + out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0x80000000 | pll0_config[i].ctrl0); -#endif /* CFG_CLK_SPREAD */ +#endif /* CONFIG_SYS_CLK_SPREAD */ -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif printf ("BUS: %lu MHz\n", gd->bus_clk / 1000000); diff --git a/board/freescale/mpc7448hpc2/u-boot.lds b/board/freescale/mpc7448hpc2/u-boot.lds index 6b228f7a9..f3f6c544d 100644 --- a/board/freescale/mpc7448hpc2/u-boot.lds +++ b/board/freescale/mpc7448hpc2/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/freescale/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c index 59997aac4..e03852f68 100644 --- a/board/freescale/mpc8260ads/flash.c +++ b/board/freescale/mpc8260ads/flash.c @@ -52,7 +52,7 @@ #define INTEL_FINISHED 0x80808080 #define INTEL_OK 0x80808080 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.) @@ -66,8 +66,8 @@ unsigned long flash_init (void) ulong size = 0, sect_start, sect_size = 0, bank_size; ushort sect_count = 0; int i, j, nbanks; - vu_long *addr = (vu_long *)CFG_FLASH_BASE; - vu_long *bcsr = (vu_long *)CFG_BCSR; + vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE; + vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; switch (bcsr[2] & 0xF) { case 0: @@ -80,11 +80,11 @@ unsigned long flash_init (void) nbanks = 1; break; default: /* Unsupported configurations */ - nbanks = CFG_MAX_FLASH_BANKS; + nbanks = CONFIG_SYS_MAX_FLASH_BANKS; } - if (nbanks > CFG_MAX_FLASH_BANKS) - nbanks = CFG_MAX_FLASH_BANKS; + if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS) + nbanks = CONFIG_SYS_MAX_FLASH_BANKS; for (i = 0; i < nbanks; i++) { *addr = INTEL_READID; /* Read Intelligent Identifier */ @@ -98,9 +98,9 @@ unsigned long flash_init (void) break; default: flash_info[i].flash_id = FLASH_UNKNOWN; - sect_count = CFG_MAX_FLASH_SECT; + sect_count = CONFIG_SYS_MAX_FLASH_SECT; sect_size = - CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT; + CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT; } } else @@ -127,10 +127,10 @@ unsigned long flash_init (void) } if (size == 0) { /* Unknown flash, fill with hard-coded values */ - sect_start = CFG_FLASH_BASE; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + sect_start = CONFIG_SYS_FLASH_BASE; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS; + flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS; flash_info[i].sector_count = sect_count; for (j = 0; j < sect_count; j++) { flash_info[i].start[j] = sect_start; @@ -138,28 +138,28 @@ unsigned long flash_init (void) sect_start += sect_size; } } - size = CFG_FLASH_SIZE; + size = CONFIG_SYS_FLASH_SIZE; } else - for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].size = 0; flash_info[i].sector_count = 0; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif return (size); @@ -274,7 +274,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) enable_interrupts(); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = INTEL_RESET; /* reset bank */ return 1; @@ -338,7 +338,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf("Write timed out\n"); rc = 1; break; @@ -454,7 +454,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) start = get_timer(0); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; break; @@ -480,7 +480,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) addr = (vu_long *)(info->start[i]); *addr = INTEL_LOCKBIT; /* Sector lock bit */ *addr = INTEL_PROTECT; /* set */ - udelay(CFG_FLASH_LOCK_TOUT * 1000); + udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000); } if (flag) diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c index 8ab7d356c..49a88bbdd 100644 --- a/board/freescale/mpc8260ads/mpc8260ads.c +++ b/board/freescale/mpc8260ads/mpc8260ads.c @@ -58,32 +58,32 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) +#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3) const iop_conf_t iop_conf_tab[4][32] = { /* Port A configuration */ { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ @@ -102,34 +102,34 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B configuration */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ @@ -147,32 +147,32 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ - /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ + /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */ + /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ -#if CONFIG_ADSTYPE == CFG_8272ADS +#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ - /* PC16 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ + /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */ + /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */ #else - /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ - /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ + /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */ + /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ -#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ +#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ -#if CONFIG_ADSTYPE == CFG_8272ADS +#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */ #else /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */ -#endif /* CONFIG_ADSTYPE == CFG_8272ADS */ +#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ @@ -223,10 +223,10 @@ const iop_conf_t iop_conf_tab[4][32] = { void reset_phy (void) { - vu_long *bcsr = (vu_long *)CFG_BCSR; + vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; /* Reset the PHY */ -#if CFG_PHY_ADDR == 0 +#if CONFIG_SYS_PHY_ADDR == 0 bcsr[1] &= ~(FETHIEN1 | FETH1_RST); udelay(2); bcsr[1] |= FETH1_RST; @@ -234,16 +234,16 @@ void reset_phy (void) bcsr[3] &= ~(FETHIEN2 | FETH2_RST); udelay(2); bcsr[3] |= FETH2_RST; -#endif /* CFG_PHY_ADDR == 0 */ +#endif /* CONFIG_SYS_PHY_ADDR == 0 */ udelay(1000); #ifdef CONFIG_MII -#if CONFIG_ADSTYPE >= CFG_PQ2FADS +#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS /* * Do not bypass Rx/Tx (de)scrambler (fix configuration error) * Enable autonegotiation. */ - bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610); - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); #else /* @@ -254,14 +254,14 @@ void reset_phy (void) */ /* Advertise all capabilities */ - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_ANAR, 0x01E1); /* Do not bypass Rx/Tx (de)scrambler */ - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR, 0x0000); + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_DCR, 0x0000); - bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, + bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ +#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ #endif /* CONFIG_MII */ } @@ -274,10 +274,10 @@ typedef struct pci_ic_s { int board_early_init_f (void) { - vu_long *bcsr = (vu_long *)CFG_BCSR; + vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR; #ifdef CONFIG_PCI - volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT; + volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT; /* mask alll the PCI interrupts */ pci_ic->pci_int_mask |= 0xfff00000; @@ -289,19 +289,19 @@ int board_early_init_f (void) bcsr[1] &= ~RS232EN_2; #endif -#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */ -#if CONFIG_ADSTYPE == CFG_PQ2FADS +#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */ +#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */ -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ +#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; } -#endif /* CONFIG_ADSTYPE != CFG_8260ADS */ +#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */ return 0; } @@ -310,16 +310,16 @@ int board_early_init_f (void) phys_size_t initdram (int board_type) { -#if CONFIG_ADSTYPE == CFG_PQ2FADS +#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS long int msize = 32; -#elif CONFIG_ADSTYPE == CFG_8272ADS +#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS long int msize = 64; #else long int msize = 16; #endif -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *) CFG_IMMR; +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *ramaddr, c = 0xff; uint or; @@ -332,33 +332,33 @@ phys_size_t initdram (int board_type) immap->im_siu_conf.sc_ppc_alrh = 0x01267893; immap->im_siu_conf.sc_tescr1 = 0x00004000; - memctl->memc_mptpr = CFG_MPTPR; -#ifdef CFG_LSDRAM_BASE + memctl->memc_mptpr = CONFIG_SYS_MPTPR; +#ifdef CONFIG_SYS_LSDRAM_BASE /* Initialise local bus SDRAM only if the pins are configured as local bus pins and not as PCI. The configuration is determined by the HRCW. */ if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CFG_LSRT; -#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */ + memctl->memc_lsrt = CONFIG_SYS_LSRT; +#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */ memctl->memc_or3 = 0xFF803280; - memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861; + memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861; #else /* CS4 */ memctl->memc_or4 = 0xFFC01480; - memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861; -#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */ - memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; - ramaddr = (uchar *) CFG_LSDRAM_BASE; + memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861; +#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */ + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000; + ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE; *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000; for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000; *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000; } -#endif /* CFG_LSDRAM_BASE */ +#endif /* CONFIG_SYS_LSDRAM_BASE */ /* Init 60x bus SDRAM */ #ifdef CONFIG_SPD_EEPROM @@ -498,14 +498,14 @@ phys_size_t initdram (int board_type) #endif /* SPD_DEBUG */ } #else /* !CONFIG_SPD_EEPROM */ - or = CFG_OR2; - psdmr = CFG_PSDMR; - psrt = CFG_PSRT; + or = CONFIG_SYS_OR2; + psdmr = CONFIG_SYS_PSDMR; + psrt = CONFIG_SYS_PSRT; #endif /* CONFIG_SPD_EEPROM */ memctl->memc_psrt = psrt; memctl->memc_or2 = or; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041; - ramaddr = (uchar *) CFG_SDRAM_BASE; + memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041; + ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE; memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */ *ramaddr = c; memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */ @@ -516,7 +516,7 @@ phys_size_t initdram (int board_type) *ramaddr = c; memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */ *ramaddr = c; -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* return total 60x bus SDRAM size */ return (msize * 1024 * 1024); @@ -524,13 +524,13 @@ phys_size_t initdram (int board_type) int checkboard (void) { -#if CONFIG_ADSTYPE == CFG_8260ADS +#if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS puts ("Board: Motorola MPC8260ADS\n"); -#elif CONFIG_ADSTYPE == CFG_8266ADS +#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS puts ("Board: Motorola MPC8266ADS\n"); -#elif CONFIG_ADSTYPE == CFG_PQ2FADS +#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS puts ("Board: Motorola PQ2FADS-ZU\n"); -#elif CONFIG_ADSTYPE == CFG_8272ADS +#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS puts ("Board: Motorola MPC8272ADS\n"); #else puts ("Board: unknown\n"); diff --git a/board/freescale/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c index 9512c72a0..06dde36e6 100644 --- a/board/freescale/mpc8266ads/flash.c +++ b/board/freescale/mpc8266ads/flash.c @@ -29,17 +29,17 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -56,7 +56,7 @@ static int clear_block_lock_bit(vu_long * addr); unsigned long flash_init (void) { #ifndef CONFIG_MPC8266ADS - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; #endif @@ -71,7 +71,7 @@ unsigned long flash_init (void) #endif - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; /* set the default sector offset */ @@ -88,28 +88,28 @@ unsigned long flash_init (void) #ifndef CONFIG_MPC8266ADS /* Remap FLASH according to real size */ - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br1 & ~(BR_BA_MSK)); #endif /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif return (size); @@ -336,7 +336,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = 0xFFFFFFFF; /* reset bank */ return 1; } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xFFFFFFFF; /* reset bank */ return 1; @@ -461,7 +461,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); flag = 0; while (((csr = *addr) & 0x80808080) != 0x80808080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flag = 1; break; } @@ -499,7 +499,7 @@ static int clear_block_lock_bit(vu_long * addr) start = get_timer (0); while(*addr != 0x80808080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout on clearing Block Lock Bit\n"); *addr = 0xFFFFFFFF; /* reset bank */ return 1; diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c index 090a53413..66acc41e9 100644 --- a/board/freescale/mpc8266ads/mpc8266ads.c +++ b/board/freescale/mpc8266ads/mpc8266ads.c @@ -224,7 +224,7 @@ typedef struct pci_ic_s { void reset_phy(void) { - volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; + volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; /* reset the FEC port */ bcsr->bcsr1 &= ~FETH_RST; @@ -234,8 +234,8 @@ void reset_phy(void) int board_early_init_f (void) { - volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR; - volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT; + volatile bcsr_t *bcsr = (bcsr_t *)CONFIG_SYS_BCSR; + volatile pci_ic_t *pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT; bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2; @@ -254,17 +254,17 @@ int checkboard(void) phys_size_t initdram(int board_type) { /* Autoinit part stolen from board/sacsng/sacsng.c */ - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar c = 0xff; - volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); - uint psdmr = CFG_PSDMR; + volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); + uint psdmr = CONFIG_SYS_PSDMR; int i; uint psrt = 0x21; /* for no SPD */ uint chipselects = 1; /* for no SPD */ - uint sdram_size = CFG_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CFG_OR2_PRELIM; /* for no SPD */ + uint sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ uint data_width; uint rows; uint banks; @@ -286,7 +286,7 @@ phys_size_t initdram(int board_type) /* * Read the SDRAM SPD EEPROM via I2C. */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1); spd_size = data; @@ -506,13 +506,13 @@ phys_size_t initdram(int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_psrt = psrt; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; memctl->memc_or2 = or; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; @@ -536,7 +536,7 @@ phys_size_t initdram(int board_type) { ramaddr += sdram_size; - memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; memctl->memc_or3 = or; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index ebb703d3e..9ffd4bff8 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -36,8 +36,8 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { -#ifndef CFG_8313ERDB_BROKEN_PMC - volatile immap_t *im = (immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) gd->flags |= GD_FLG_SILENT; @@ -55,28 +55,28 @@ int checkboard(void) #ifndef CONFIG_NAND_SPL static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI1_MEM_BASE, - phys_start: CFG_PCI1_MEM_PHYS, - size: CFG_PCI1_MEM_SIZE, + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI1_MMIO_BASE, - phys_start: CFG_PCI1_MMIO_PHYS, - size: CFG_PCI1_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI1_IO_BASE, - phys_start: CFG_PCI1_IO_PHYS, - size: CFG_PCI1_IO_SIZE, + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, flags: PCI_REGION_IO } }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; @@ -88,14 +88,14 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; #endif @@ -135,13 +135,13 @@ void ft_board_setup(void *blob, bd_t *bd) void board_init_f(ulong bootflag) { board_early_init_f(); - NS16550_init((NS16550_t)(CFG_IMMR + 0x4500), - CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE); + NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); puts("NAND boot... "); init_timebase(); initdram(0); - relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, - CFG_NAND_U_BOOT_RELOC); + relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CONFIG_SYS_NAND_U_BOOT_RELOC); } void board_init_r(gd_t *gd, ulong dest_addr) @@ -155,8 +155,8 @@ void putc(char c) return; if (c == '\n') - NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r'); + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); - NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c); + NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c); } #endif diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c index 3a6347fe1..cb138296b 100644 --- a/board/freescale/mpc8313erdb/sdram.c +++ b/board/freescale/mpc8313erdb/sdram.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC static void resume_from_sleep(void) { u32 magic = *(u32 *)0; @@ -58,15 +58,15 @@ static void resume_from_sleep(void) */ static long fixed_sdram(void) { - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; -#ifndef CFG_RAMBOOT - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; /* * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], @@ -75,29 +75,29 @@ static long fixed_sdram(void) udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; /* Currently we use only one CS, so disable the other bank. */ im->ddr.cs_config[1] = 0; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI; + im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI; else #endif - im->ddr.sdram_cfg = CFG_SDRAM_CFG; + im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE_2; + im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; sync(); /* enable DDR controller */ @@ -109,8 +109,8 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile lbus83xx_t *lbc = &im->lbus; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc = &im->lbus; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) @@ -120,11 +120,11 @@ phys_size_t initdram(int board_type) msize = fixed_sdram(); /* Local Bus setup lbcr and mrtpr */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; sync(); -#ifndef CFG_8313ERDB_BROKEN_PMC +#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) resume_from_sleep(); #endif diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index 3eecee251..ea4b04fd3 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -29,12 +29,13 @@ #include <fdt_support.h> #include <pci.h> #include <mpc83xx.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) gd->flags |= GD_FLG_SILENT; @@ -47,7 +48,7 @@ static u8 read_board_info(void) u8 val8; i2c_set_bus_num(0); - if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) + if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) return val8; else return 0; @@ -75,28 +76,28 @@ int checkboard(void) static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI_MEM_BASE, - phys_start: CFG_PCI_MEM_PHYS, - size: CFG_PCI_MEM_SIZE, + bus_start: CONFIG_SYS_PCI_MEM_BASE, + phys_start: CONFIG_SYS_PCI_MEM_PHYS, + size: CONFIG_SYS_PCI_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI_MMIO_BASE, - phys_start: CFG_PCI_MMIO_PHYS, - size: CFG_PCI_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI_MMIO_BASE, + phys_start: CONFIG_SYS_PCI_MMIO_PHYS, + size: CONFIG_SYS_PCI_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI_IO_BASE, - phys_start: CFG_PCI_IO_PHYS, - size: CFG_PCI_IO_SIZE, + bus_start: CONFIG_SYS_PCI_IO_BASE, + phys_start: CONFIG_SYS_PCI_IO_PHYS, + size: CONFIG_SYS_PCI_IO_SIZE, flags: PCI_REGION_IO } }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; @@ -108,10 +109,10 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; @@ -165,3 +166,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_tsec1_fixup(blob, bd); } #endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Initialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index 07e6486ee..ead7b1e0d 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -56,13 +56,13 @@ static void resume_from_sleep(void) */ static long fixed_sdram(void) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; /* * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], @@ -71,27 +71,27 @@ static long fixed_sdram(void) udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; /* Currently we use only one CS, so disable the other bank. */ im->ddr.cs_config[1] = 0; - im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; else - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; sync(); /* enable DDR controller */ @@ -103,7 +103,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index f5220abdb..8680a19a6 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -75,14 +75,14 @@ int fixed_sdram(void); phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; msize = fixed_sdram(); @@ -95,12 +95,12 @@ phys_size_t initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { if (ddr_size & 1) { @@ -109,18 +109,18 @@ int fixed_sdram(void) } im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; __asm__ __volatile__ ("sync"); udelay(200); @@ -137,28 +137,28 @@ int checkboard(void) static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI1_MEM_BASE, - phys_start: CFG_PCI1_MEM_PHYS, - size: CFG_PCI1_MEM_SIZE, + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI1_MMIO_BASE, - phys_start: CFG_PCI1_MMIO_PHYS, - size: CFG_PCI1_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI1_IO_BASE, - phys_start: CFG_PCI1_IO_PHYS, - size: CFG_PCI1_IO_SIZE, + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, flags: PCI_REGION_IO } }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; @@ -167,10 +167,10 @@ void pci_init_board(void) clk->occr |= 0xe0000000; /* Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; mpc83xx_pci_init(1, reg, 0); @@ -186,7 +186,7 @@ void ft_board_setup(void *blob, bd_t *bd) } #endif -#if defined(CFG_I2C_MAC_OFFSET) +#if defined(CONFIG_SYS_I2C_MAC_OFFSET) int mac_read_from_eeprom(void) { uchar buf[28]; @@ -196,9 +196,9 @@ int mac_read_from_eeprom(void) unsigned char enetvar[32]; /* Read MAC addresses from EEPROM */ - if (eeprom_read(CFG_I2C_EEPROM_ADDR, CFG_I2C_MAC_OFFSET, buf, 28)) { + if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) { printf("\nEEPROM @ 0x%02x read FAILED!!!\n", - CFG_I2C_EEPROM_ADDR); + CONFIG_SYS_I2C_EEPROM_ADDR); } else { if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) { printf("Reading MAC from EEPROM\n"); diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 4ad6e9d45..d4d447931 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -76,7 +76,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { int board_early_init_f(void) { - volatile u8 *bcsr = (volatile u8 *)CFG_BCSR; + volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ bcsr[9] &= ~0x08; @@ -96,14 +96,14 @@ int fixed_sdram(void); phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; msize = fixed_sdram(); @@ -116,12 +116,12 @@ phys_size_t initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { if (ddr_size & 1) { @@ -130,21 +130,21 @@ int fixed_sdram(void) } im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 128) +#if (CONFIG_SYS_DDR_SIZE != 128) #warning Currenly any ddr size other than 128 is not supported #endif - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; __asm__ __volatile__ ("sync"); udelay(200); diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index b0304229d..2a48dd24e 100644 --- a/board/freescale/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -67,7 +67,7 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; @@ -93,7 +93,7 @@ void pci_init_board(void) hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); reg16 = 0xff; pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), @@ -134,7 +134,7 @@ void pci_init_board(void) u32 val32; u32 dev; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -161,10 +161,10 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; /* @@ -172,26 +172,26 @@ void pci_init_board(void) */ /* PCI mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI IO space */ - pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ - pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; + pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; + pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | @@ -209,31 +209,31 @@ void pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose[0].regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + CONFIG_SYS_PCI_MEM_BASE, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose[0].regions + 1, - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI_MMIO_BASE, + CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose[0].regions + 2, - CFG_PCI_IO_BASE, - CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI_IO_BASE, + CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose[0].regions + 3, - CFG_PCI_SLV_MEM_LOCAL, - CFG_PCI_SLV_MEM_BUS, - CFG_PCI_SLV_MEM_SIZE, + CONFIG_SYS_PCI_SLV_MEM_LOCAL, + CONFIG_SYS_PCI_SLV_MEM_BUS, + CONFIG_SYS_PCI_SLV_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); hose[0].region_count = 4; pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); pci_register_hose(hose); diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 4c04f2c4d..06064d970 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -44,12 +44,12 @@ void ddr_enable_ecc(unsigned int dram_size); int board_early_init_f (void) { - volatile u8* bcsr = (volatile u8*)CFG_BCSR; + volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR; /* Enable flash write */ bcsr[1] &= ~0x01; -#ifdef CFG_USE_MPC834XSYS_USB_PHY +#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY /* Use USB PHY on SYS board */ bcsr[5] |= 0x02; #endif @@ -61,14 +61,14 @@ int board_early_init_f (void) phys_size_t initdram (int board_type) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else @@ -96,12 +96,12 @@ phys_size_t initdram (int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size>>1, ddr_size_log2++) { @@ -109,36 +109,36 @@ int fixed_sdram(void) return -1; } } - im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) +#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif #ifdef CONFIG_DDR_II - im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS; - im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS; + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CFG_DDR_CONFIG; + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; im->ddr.cs_config[1] = 0; im->ddr.cs_config[3] = 0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; im->ddr.sdram_cfg = SDRAM_CFG_SREN @@ -150,9 +150,9 @@ int fixed_sdram(void) /* for 32-bit mode burst length is 8 */ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); #endif - im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; #endif udelay(200); @@ -160,7 +160,7 @@ int fixed_sdram(void) im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; return msize; } -#endif/*!CFG_SPD_EEPROM*/ +#endif/*!CONFIG_SYS_SPD_EEPROM*/ int checkboard (void) @@ -181,41 +181,41 @@ int checkboard (void) /* * if MPC8349EMDS is soldered with SDRAM */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#if defined(CONFIG_SYS_BR2_PRELIM) \ + && defined(CONFIG_SYS_OR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWAR2_PRELIM) /* * Initialize SDRAM memory on the Local Bus. */ void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile lbus83xx_t *lbc= &immap->lbus; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc = &immap->lbus; + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ - lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -243,12 +243,12 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ asm("sync"); *sdram_addr = 0xff; udelay(100); @@ -273,14 +273,14 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { - volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; iopd->dat &= ~SPI_CS_MASK; } void spi_cs_deactivate(struct spi_slave *slave) { - volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; iopd->dat |= SPI_CS_MASK; } diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index 9c19e303f..ad7bf5d50 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -33,21 +33,21 @@ DECLARE_GLOBAL_DATA_PTR; static struct pci_region pci1_regions[] = { { - bus_start: CFG_PCI1_MEM_BASE, - phys_start: CFG_PCI1_MEM_PHYS, - size: CFG_PCI1_MEM_SIZE, + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI1_IO_BASE, - phys_start: CFG_PCI1_IO_PHYS, - size: CFG_PCI1_IO_SIZE, + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, flags: PCI_REGION_IO }, { - bus_start: CFG_PCI1_MMIO_BASE, - phys_start: CFG_PCI1_MMIO_PHYS, - size: CFG_PCI1_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, flags: PCI_REGION_MEM }, }; @@ -55,21 +55,21 @@ static struct pci_region pci1_regions[] = { #ifdef CONFIG_MPC83XX_PCI2 static struct pci_region pci2_regions[] = { { - bus_start: CFG_PCI2_MEM_BASE, - phys_start: CFG_PCI2_MEM_PHYS, - size: CFG_PCI2_MEM_SIZE, + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI2_IO_BASE, - phys_start: CFG_PCI2_IO_PHYS, - size: CFG_PCI2_IO_SIZE, + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, flags: PCI_REGION_IO }, { - bus_start: CFG_PCI2_MMIO_BASE, - phys_start: CFG_PCI2_MMIO_PHYS, - size: CFG_PCI2_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, flags: PCI_REGION_MEM }, }; @@ -135,7 +135,7 @@ void pib_init(void) void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; #ifndef CONFIG_MPC83XX_PCI2 @@ -152,10 +152,10 @@ void pci_init_board(void) udelay(2000); /* Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; udelay(2000); @@ -170,7 +170,7 @@ void pci_init_board(void) #else void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; @@ -181,10 +181,10 @@ void pci_init_board(void) udelay(2000); /* Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; udelay(2000); diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index d3fc560df..35285b4c9 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -42,11 +42,11 @@ ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 ddr_size; /* The size of RAM, in bytes */ u32 ddr_size_log2 = 0; - for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { + for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) { if (ddr_size & 1) { return -1; } @@ -55,11 +55,11 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->sysconf.ddrlaw[0].bar = (CFG_DDR_SDRAM_BASE >> 12) & 0xfffff; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; /* Only one CS0 for DDR */ im->ddr.csbnds[0].csbnds = 0x0000000f; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds); debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]); @@ -67,15 +67,15 @@ int fixed_sdram(void) debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar); debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar); - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1; im->ddr.sdram_mode = (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT); im->ddr.sdram_interval = (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT); - im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; udelay(200); @@ -87,7 +87,7 @@ int fixed_sdram(void) debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval); debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg); - return CFG_DDR_SIZE; + return CONFIG_SYS_DDR_SIZE; } #endif @@ -130,7 +130,7 @@ volatile static struct pci_controller hose[] = { phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; #ifdef CONFIG_DDR_ECC volatile ddr83xx_t *ddr = &im->ddr; @@ -140,7 +140,7 @@ phys_size_t initdram(int board_type) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #ifdef CONFIG_SPD_EEPROM msize = spd_sdram(); #else @@ -196,7 +196,7 @@ int misc_init_f(void) don't enable compact flash for U-Boot. */ - vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); + vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0); *vsc7385_cpuctrl |= 0x0c; #endif @@ -220,11 +220,11 @@ int misc_init_f(void) 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 }; - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbus = &immap->lbus; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbus = &immap->lbus; - lbus->bank[3].br = CFG_BR3_PRELIM; - lbus->bank[3].or = CFG_OR3_PRELIM; + lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM; + lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM; /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000, GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000 @@ -265,26 +265,26 @@ int misc_init_r(void) unsigned int orig_bus = i2c_get_bus_num(); u8 i2c_data; -#ifdef CFG_I2C_RTC_ADDR +#ifdef CONFIG_SYS_I2C_RTC_ADDR u8 ds1339_data[17]; #endif -#ifdef CFG_I2C_EEPROM_ADDR +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR static u8 eeprom_data[] = /* HRCW data */ { 0xAA, 0x55, 0xAA, /* Preamble */ 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ - (CFG_HRCW_LOW >> 24) & 0xFF, - (CFG_HRCW_LOW >> 16) & 0xFF, - (CFG_HRCW_LOW >> 8) & 0xFF, - CFG_HRCW_LOW & 0xFF, + (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF, + (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF, + (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF, + CONFIG_SYS_HRCW_LOW & 0xFF, 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ - (CFG_HRCW_HIGH >> 24) & 0xFF, - (CFG_HRCW_HIGH >> 16) & 0xFF, - (CFG_HRCW_HIGH >> 8) & 0xFF, - CFG_HRCW_HIGH & 0xFF + (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF, + (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF, + (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF, + CONFIG_SYS_HRCW_HIGH & 0xFF }; u8 data[sizeof(eeprom_data)]; @@ -292,22 +292,22 @@ int misc_init_r(void) printf("Board revision: "); i2c_set_bus_num(1); - if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); - else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) + else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0) printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01); else { printf("Unknown\n"); rc = 1; } -#ifdef CFG_I2C_EEPROM_ADDR +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR i2c_set_bus_num(0); - if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) { if (memcmp(data, eeprom_data, sizeof(data)) != 0) { if (i2c_write - (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data, + (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data, sizeof(eeprom_data)) != 0) { puts("Failure writing the HRCW to EEPROM via I2C.\n"); rc = 1; @@ -319,10 +319,10 @@ int misc_init_r(void) } #endif -#ifdef CFG_I2C_RTC_ADDR +#ifdef CONFIG_SYS_I2C_RTC_ADDR i2c_set_bus_num(1); - if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) + if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data)) == 0) { /* Work-around for MPC8349E-mITX bug #13601. @@ -366,7 +366,7 @@ int misc_init_r(void) */ if (i2c_write - (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, + (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))) { puts("Failure writing to the RTC via I2C.\n"); rc = 1; diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index d33edf367..fd2c172de 100644 --- a/board/freescale/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -37,8 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; /* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc8349itx_config_table[] = { @@ -92,7 +92,7 @@ void pci_init_board(void) u32 dev; struct pci_controller *hose; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -111,8 +111,8 @@ void pci_init_board(void) #ifdef CONFIG_HARD_I2C i2c_set_bus_num(1); /* Read the PCI_M66EN jumper setting */ - if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || - (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { + if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) || + (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) { if (reg8 & I2C_8574_PCI66) clk->occr = 0xff000000; /* 66 MHz PCI */ else @@ -150,10 +150,10 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; /* @@ -161,18 +161,18 @@ void pci_init_board(void) */ /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; /* @@ -192,19 +192,19 @@ void pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI1_MMIO_BASE, - CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_MMIO_BASE, + CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 3, @@ -215,7 +215,7 @@ void pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); pci_register_hose(hose); @@ -251,18 +251,18 @@ void pci_init_board(void) */ /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; /* PCI2 IO space */ - pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; /* @@ -283,19 +283,19 @@ void pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI2_MMIO_BASE, - CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI2_MMIO_BASE, + CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 3, @@ -306,7 +306,7 @@ void pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384)); + (CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384)); pci_register_hose(hose); diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 5c3b5dbc9..85c0120f2 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -92,8 +92,8 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { int board_early_init_f(void) { - u8 *bcsr = (u8 *)CFG_BCSR; - const immap_t *immr = (immap_t *)CFG_IMMR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* Enable flash write */ bcsr[0xa] &= ~0x04; @@ -120,18 +120,18 @@ int board_early_init_r(void) extern void ddr_enable_ecc(unsigned int dram_size); #endif int fixed_sdram(void); -void sdram_init(void); +static int sdram_init(unsigned int base); phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else @@ -147,7 +147,7 @@ phys_size_t initdram(int board_type) /* * Initialize SDRAM if it is on local bus. */ - sdram_init(); + msize += sdram_init(msize * 1024 * 1024); /* return total bus SDRAM size(bytes) -- DDR */ return (msize * 1024 * 1024); @@ -159,12 +159,12 @@ phys_size_t initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { if (ddr_size & 1) { @@ -173,42 +173,42 @@ int fixed_sdram(void) } im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) +#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif #ifdef CONFIG_DDR_II - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else im->ddr.csbnds[0].csbnds = 0x00000007; im->ddr.csbnds[1].csbnds = 0x0008000f; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - im->ddr.cs_config[1] = CFG_DDR_CONFIG; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; + im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.sdram_cfg = CFG_DDR_CONTROL; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; #endif udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; return msize; } -#endif /*!CFG_SPD_EEPROM */ +#endif /*!CONFIG_SYS_SPD_EEPROM */ int checkboard(void) { @@ -219,34 +219,43 @@ int checkboard(void) /* * if MPC8360EMDS is soldered with SDRAM */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#ifdef CONFIG_SYS_LB_SDRAM /* * Initialize SDRAM memory on the Local Bus. */ -void sdram_init(void) +static int sdram_init(unsigned int base) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile lbus83xx_t *lbc = &immap->lbus; - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc = &immap->lbus; + const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024; + int rem = base % sdram_size; + uint *sdram_addr; + /* window base address should be aligned to the window size */ + if (rem) + base = base - rem + sdram_size; + + sdram_addr = (uint *)base; /* - * Setup SDRAM Base and Option Registers, already done in cpu_init.c + * Setup SDRAM Base and Option Registers */ + immap->lbus.bank[2].br = base | CONFIG_SYS_BR2; + immap->lbus.bank[2].or = CONFIG_SYS_OR2; + immap->sysconf.lblaw[2].bar = base; + immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2; + /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ - lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */ asm("sync"); *sdram_addr = 0xff; udelay(100); @@ -254,7 +263,7 @@ void sdram_init(void) /* * We need do 8 times auto refresh operation. */ - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); *sdram_addr = 0xff; /* 1 times */ udelay(100); @@ -274,27 +283,33 @@ void sdram_init(void) udelay(100); /* Mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *(sdram_addr + 0xcc) = 0xff; udelay(100); /* Normal operation */ - lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000; asm("sync"); *sdram_addr = 0xff; udelay(100); + + /* + * In non-aligned case we don't [normally] use that memory because + * there is a hole. + */ + if (rem) + return 0; + return CONFIG_SYS_LBC_SDRAM_SIZE; } #else -void sdram_init(void) -{ -} +static int sdram_init(unsigned int base) { return 0; } #endif #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - const immap_t *immr = (immap_t *)CFG_IMMR; + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 4a0d460fa..935aca26d 100644 --- a/board/freescale/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -67,7 +67,7 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; @@ -93,7 +93,7 @@ void pci_init_board(void) hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); reg16 = 0xff; pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), @@ -134,7 +134,7 @@ void pci_init_board(void) u32 val32; u32 dev; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -161,10 +161,10 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; /* @@ -172,26 +172,26 @@ void pci_init_board(void) */ /* PCI mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI IO space */ - pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ - pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; + pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; + pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | @@ -209,31 +209,31 @@ void pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose[0].regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + CONFIG_SYS_PCI_MEM_BASE, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose[0].regions + 1, - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI_MMIO_BASE, + CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose[0].regions + 2, - CFG_PCI_IO_BASE, - CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI_IO_BASE, + CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose[0].regions + 3, - CFG_PCI_SLV_MEM_LOCAL, - CFG_PCI_SLV_MEM_BUS, - CFG_PCI_SLV_MEM_SIZE, + CONFIG_SYS_PCI_SLV_MEM_LOCAL, + CONFIG_SYS_PCI_SLV_MEM_BUS, + CONFIG_SYS_PCI_SLV_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); hose[0].region_count = 4; pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); pci_register_hose(hose); diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 61d700014..af3b8ceae 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -214,7 +214,7 @@ int board_early_init_f(void) int board_early_init_r(void) { - void *reg = (void *)(CFG_IMMR + 0x14a8); + void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); u32 val; /* @@ -233,12 +233,12 @@ int board_early_init_r(void) int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { if (ddr_size & 1) @@ -248,18 +248,18 @@ int fixed_sdram(void) im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; @@ -271,14 +271,14 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) extern void ddr_enable_ecc(unsigned int dram_size); #endif - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; msize = fixed_sdram(); #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC) @@ -300,28 +300,28 @@ int checkboard(void) static struct pci_region pci_regions[] = { { - .bus_start = CFG_PCI1_MEM_BASE, - .phys_start = CFG_PCI1_MEM_PHYS, - .size = CFG_PCI1_MEM_SIZE, + .bus_start = CONFIG_SYS_PCI1_MEM_BASE, + .phys_start = CONFIG_SYS_PCI1_MEM_PHYS, + .size = CONFIG_SYS_PCI1_MEM_SIZE, .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH, }, { - .bus_start = CFG_PCI1_MMIO_BASE, - .phys_start = CFG_PCI1_MMIO_PHYS, - .size = CFG_PCI1_MMIO_SIZE, + .bus_start = CONFIG_SYS_PCI1_MMIO_BASE, + .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS, + .size = CONFIG_SYS_PCI1_MMIO_SIZE, .flags = PCI_REGION_MEM, }, { - .bus_start = CFG_PCI1_IO_BASE, - .phys_start = CFG_PCI1_IO_PHYS, - .size = CFG_PCI1_IO_SIZE, + .bus_start = CONFIG_SYS_PCI1_IO_BASE, + .phys_start = CONFIG_SYS_PCI1_IO_PHYS, + .size = CONFIG_SYS_PCI1_IO_SIZE, .flags = PCI_REGION_IO, }, }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions, }; @@ -338,10 +338,10 @@ void pci_init_board(void) udelay(2000); /* Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; mpc83xx_pci_init(1, reg, 0); diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c index 8b44a0f38..8e22e138a 100644 --- a/board/freescale/mpc8360erdk/nand.c +++ b/board/freescale/mpc8360erdk/nand.c @@ -18,7 +18,7 @@ #include <linux/mtd/fsl_upm.h> #include <nand.h> -static struct immap *im = (struct immap *)CFG_IMMR; +static struct immap *im = (struct immap *)CONFIG_SYS_IMMR; static const u32 upm_array[] = { 0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */ @@ -70,7 +70,7 @@ static int dev_ready(void) static struct fsl_upm_nand fun = { .upm = { - .io_addr = (void *)CFG_NAND_BASE, + .io_addr = (void *)CONFIG_SYS_NAND_BASE, }, .width = 8, .upm_cmd_offset = 8, diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 40f1e6328..acf8ada7b 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -15,16 +15,14 @@ #include <asm/io.h> #include <asm/fsl_serdes.h> #include <spd_sdram.h> -#if defined(CONFIG_OF_LIBFDT) +#include <tsec.h> #include <libfdt.h> -#endif -#if defined(CONFIG_PQ_MDS_PIB) +#include <fdt_support.h> #include "../common/pq-mds-pib.h" -#endif int board_early_init_f(void) { - u8 *bcsr = (u8 *)CFG_BCSR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ bcsr[0x9] &= ~0x04; @@ -32,7 +30,7 @@ int board_early_init_f(void) bcsr[0xe] = 0xff; #ifdef CONFIG_FSL_SERDES - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ @@ -44,7 +42,9 @@ int board_early_init_f(void) FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, + FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: @@ -62,6 +62,125 @@ int board_early_init_f(void) return 0; } +#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) +int board_eth_init(bd_t *bd) +{ + struct tsec_info_struct tsec_info[2]; + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + u32 rcwh = in_be32(&im->reset.rcwh); + u32 tsec_mode; + int num = 0; + + /* New line after Net: */ + printf("\n"); + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + + printf(CONFIG_TSEC1_NAME ": "); + + tsec_mode = rcwh & HRCWH_TSEC1M_MASK; + if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) { + printf("RGMII\n"); + /* this is default, no need to fixup */ + } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) { + printf("SGMII\n"); + tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII; + tsec_info[num].flags = TSEC_GIGABIT; + } else { + printf("unsupported PHY type\n"); + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + + printf(CONFIG_TSEC2_NAME ": "); + + tsec_mode = rcwh & HRCWH_TSEC2M_MASK; + if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) { + printf("RGMII\n"); + /* this is default, no need to fixup */ + } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) { + printf("SGMII\n"); + tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; + tsec_info[num].flags = TSEC_GIGABIT; + } else { + printf("unsupported PHY type\n"); + } + num++; +#endif + return tsec_eth_init(bd, tsec_info, num); +} + +static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias, + int phy_addr) +{ + const char *phy_type = "sgmii"; + const u32 *ph; + int off; + int err; + + off = fdt_path_offset(blob, alias); + if (off < 0) { + printf("WARNING: could not find %s alias: %s.\n", alias, + fdt_strerror(off)); + return; + } + + err = fdt_setprop(blob, off, "phy-connection-type", phy_type, + strlen(phy_type) + 1); + if (err) { + printf("WARNING: could not set phy-connection-type for %s: " + "%s.\n", alias, fdt_strerror(err)); + return; + } + + ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0); + if (!ph) { + printf("WARNING: could not get phy-handle for %s.\n", + alias); + return; + } + + off = fdt_node_offset_by_phandle(blob, *ph); + if (off < 0) { + printf("WARNING: could not get phy node for %s: %s\n", alias, + fdt_strerror(off)); + return; + } + + phy_addr = cpu_to_fdt32(phy_addr); + err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr)); + if (err < 0) { + printf("WARNING: could not set phy node's reg for %s: " + "%s.\n", alias, fdt_strerror(err)); + return; + } +} + +static void ft_tsec_fixup(void *blob, bd_t *bd) +{ + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + u32 rcwh = in_be32(&im->reset.rcwh); + u32 tsec_mode; + +#ifdef CONFIG_TSEC1 + tsec_mode = rcwh & HRCWH_TSEC1M_MASK; + if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) + __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII); +#endif + +#ifdef CONFIG_TSEC2 + tsec_mode = rcwh & HRCWH_TSEC2M_MASK; + if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) + __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII); +#endif +} +#else +static inline void ft_tsec_fixup(void *blob, bd_t *bd) {} +#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */ + int board_early_init_r(void) { #ifdef CONFIG_PQ_MDS_PIB @@ -77,7 +196,7 @@ int fixed_sdram(void); phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) @@ -104,43 +223,43 @@ phys_size_t initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); -#if (CFG_DDR_SIZE != 512) +#if (CONFIG_SYS_DDR_SIZE != 512) #warning Currenly any ddr size other than 512 is not supported #endif - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; udelay(50000); - im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; udelay(1000); - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; udelay(1000); - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; __asm__ __volatile__("sync"); udelay(1000); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; udelay(2000); - return CFG_DDR_SIZE; + return CONFIG_SYS_DDR_SIZE; } -#endif /*!CFG_SPD_EEPROM */ +#endif /*!CONFIG_SYS_SPD_EEPROM */ int checkboard(void) { @@ -148,12 +267,55 @@ int checkboard(void) return 0; } +#ifdef CONFIG_PCI +int board_pci_host_broken(void) +{ + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST; + const char *pci_ea = getenv("pci_external_arbiter"); + + /* It's always OK in case of external arbiter. */ + if (pci_ea && !strcmp(pci_ea, "yes")) + return 0; + + if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask) + return 1; + + return 0; +} + +static void ft_pci_fixup(void *blob, bd_t *bd) +{ + const char *status = "broken (no arbiter)"; + int off; + int err; + + off = fdt_path_offset(blob, "pci0"); + if (off < 0) { + printf("WARNING: could not find pci0 alias: %s.\n", + fdt_strerror(off)); + return; + } + + err = fdt_setprop(blob, off, "status", status, strlen(status) + 1); + if (err) { + printf("WARNING: could not set status for pci0: %s.\n", + fdt_strerror(err)); + return; + } +} +#endif + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + ft_tsec_fixup(blob, bd); + fdt_fixup_dr_usb(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); + if (board_pci_host_broken()) + ft_pci_fixup(blob, bd); #endif } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c index ab909790e..df4e748e9 100644 --- a/board/freescale/mpc837xemds/pci.c +++ b/board/freescale/mpc837xemds/pci.c @@ -21,41 +21,44 @@ #if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI_MEM_BASE, - phys_start: CFG_PCI_MEM_PHYS, - size: CFG_PCI_MEM_SIZE, + bus_start: CONFIG_SYS_PCI_MEM_BASE, + phys_start: CONFIG_SYS_PCI_MEM_PHYS, + size: CONFIG_SYS_PCI_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI_MMIO_BASE, - phys_start: CFG_PCI_MMIO_PHYS, - size: CFG_PCI_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI_MMIO_BASE, + phys_start: CONFIG_SYS_PCI_MMIO_PHYS, + size: CONFIG_SYS_PCI_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI_IO_BASE, - phys_start: CFG_PCI_IO_PHYS, - size: CFG_PCI_IO_SIZE, + bus_start: CONFIG_SYS_PCI_IO_BASE, + phys_start: CONFIG_SYS_PCI_IO_PHYS, + size: CONFIG_SYS_PCI_IO_SIZE, flags: PCI_REGION_IO } }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; + if (board_pci_host_broken()) + return; + /* Enable all 5 PCI_CLK_OUTPUTS */ clk->occr |= 0xf8000000; udelay(2000); /* Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; udelay(2000); diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index aaefc1899..318a3dce7 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -20,17 +20,17 @@ #include <spd_sdram.h> #include <vsc7385.h> -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); + CONFIG_SYS_MEMTEST_START, + CONFIG_SYS_MEMTEST_END); printf("DRAM test phase 1:\n"); for (p = pstart; p < pend; p++) @@ -66,7 +66,7 @@ int fixed_sdram(void); phys_size_t initdram(int board_type) { - immap_t *im = (immap_t *) CFG_IMMR; + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) @@ -92,40 +92,40 @@ phys_size_t initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; udelay(50000); - im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; udelay(1000); - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; udelay(1000); - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; sync(); udelay(1000); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; udelay(2000); - return CFG_DDR_SIZE; + return CONFIG_SYS_DDR_SIZE; } -#endif /*!CFG_SPD_EEPROM */ +#endif /*!CONFIG_SYS_SPD_EEPROM */ int checkboard(void) { @@ -136,7 +136,7 @@ int checkboard(void) int board_early_init_f(void) { #ifdef CONFIG_FSL_SERDES - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ @@ -148,7 +148,7 @@ int board_early_init_f(void) FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c index 26e732028..8bb31fc74 100644 --- a/board/freescale/mpc837xerdb/pci.c +++ b/board/freescale/mpc837xerdb/pci.c @@ -17,28 +17,28 @@ #if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI_MEM_BASE, - phys_start: CFG_PCI_MEM_PHYS, - size: CFG_PCI_MEM_SIZE, + bus_start: CONFIG_SYS_PCI_MEM_BASE, + phys_start: CONFIG_SYS_PCI_MEM_PHYS, + size: CONFIG_SYS_PCI_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI_MMIO_BASE, - phys_start: CFG_PCI_MMIO_PHYS, - size: CFG_PCI_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI_MMIO_BASE, + phys_start: CONFIG_SYS_PCI_MMIO_PHYS, + size: CONFIG_SYS_PCI_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI_IO_BASE, - phys_start: CFG_PCI_IO_PHYS, - size: CFG_PCI_IO_SIZE, + bus_start: CONFIG_SYS_PCI_IO_BASE, + phys_start: CONFIG_SYS_PCI_IO_PHYS, + size: CONFIG_SYS_PCI_IO_SIZE, flags: PCI_REGION_IO } }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; @@ -48,10 +48,10 @@ void pci_init_board(void) udelay(2000); /* Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; mpc83xx_pci_init(1, reg, 0); diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index 2e88c7933..3135d6dfe 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { @@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index cdf5215fc..0861fa708 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -28,16 +28,17 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 8216c70ca..2b17612b3 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -25,6 +25,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/immap_fsl_pci.h> #include <asm/fsl_ddr_sdram.h> @@ -34,12 +35,11 @@ #include <libfdt.h> #include <spd_sdram.h> #include <fdt_support.h> +#include <tsec.h> +#include <netdev.h> #include "../common/pixis.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif +#include "../common/sgmii_riser.h" phys_size_t fixed_sdram(void); @@ -61,20 +61,12 @@ initdram(int board_type) #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; #else dram_size = fixed_sdram(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } @@ -86,34 +78,34 @@ initdram(int board_type) phys_size_t fixed_sdram (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_ddr_t *ddr= &immap->im_ddr; uint d_init; - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_3 = CFG_DDR_TIMING_3; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE_1; - ddr->sdram_mode_2 = CFG_DDR_MODE_2; - ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; #if defined (CONFIG_DDR_ECC) - ddr->err_int_en = CFG_DDR_ERR_INT_EN; - ddr->err_disable = CFG_DDR_ERR_DIS; - ddr->err_sbe = CFG_DDR_SBE; + ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; + ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; + ddr->err_sbe = CONFIG_SYS_DDR_SBE; #endif asm("sync;isync"); udelay(500); - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) d_init = 1; @@ -151,12 +143,15 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + int first_free_busno=0; void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint sdrs2_io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; @@ -176,11 +171,11 @@ pci_init_board(void) #ifdef CONFIG_PCIE3 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 1); int pcie_configured = (io_sel == 7); + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE3 connected to Slot3 as %s (base address %x)", @@ -193,27 +188,23 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE3_MEM_BASE, - CFG_PCIE3_MEM_PHYS, - CFG_PCIE3_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE3_IO_BASE, - CFG_PCIE3_IO_PHYS, - CFG_PCIE3_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -234,12 +225,12 @@ pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); int pcie_configured = (io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 7); + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE1 connected to Slot1 as %s (base address %x)", @@ -252,36 +243,31 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCIE1_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCIE1_MEM_BASE2, - CFG_PCIE1_MEM_PHYS2, - CFG_PCIE1_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE2, + CONFIG_SYS_PCIE1_MEM_PHYS2, + CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -303,11 +289,11 @@ pci_init_board(void) #ifdef CONFIG_PCIE2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 3); int pcie_configured = (io_sel == 5 || io_sel == 7); + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)", @@ -320,36 +306,31 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE2_MEM_BASE, - CFG_PCIE2_MEM_PHYS, - CFG_PCIE2_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE2_IO_BASE, - CFG_PCIE2_IO_PHYS, - CFG_PCIE2_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCIE2_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE2_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCIE2_MEM_BASE2, - CFG_PCIE2_MEM_PHYS2, - CFG_PCIE2_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE2, + CONFIG_SYS_PCIE2_MEM_PHYS2, + CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -370,9 +351,9 @@ pci_init_board(void) #ifdef CONFIG_PCI1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; uint pci_agent = (host_agent == 6); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ @@ -393,35 +374,31 @@ pci_init_board(void) ); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCI1_MEM_BASE2 + +#ifdef CONFIG_SYS_PCI1_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCI1_MEM_BASE2, - CFG_PCI1_MEM_PHYS2, - CFG_PCI1_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE2, + CONFIG_SYS_PCI1_MEM_PHYS2, + CONFIG_SYS_PCI1_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -441,8 +418,7 @@ pci_init_board(void) int board_early_init_r(void) { - unsigned int i; - const unsigned int flashbase = CFG_FLASH_BASE; + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = 1; /* @@ -450,11 +426,9 @@ int board_early_init_r(void) * so that flash can be erased properly. */ - /* Invalidate any remaining lines of the flash from caches. */ - for (i = 0; i < 256*1024*1024; i+=32) { - asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); - asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); - } + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); @@ -608,46 +582,75 @@ get_board_ddr_clk(ulong dummy) } #endif -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) +int is_sata_supported(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint sdrs2_io_sel = + (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; + if (sdrs2_io_sel & 0x04) + return 0; + + return 1; +} + +int board_eth_init(bd_t *bis) { - int node, tmp[2]; - const char *path; +#ifdef CONFIG_TSEC_ENET + struct tsec_info_struct tsec_info[2]; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + uint sdrs2_io_sel = + (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { + tsec_info[num].phyaddr = 0; + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (sdrs2_io_sel == 4) { + tsec_info[num].phyaddr = 1; + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) + fsl_sgmii_riser_init(tsec_info, num); + + tsec_eth_init(bis, tsec_info, num); +#endif + return pci_eth_init(bis); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + +void ft_board_setup(void *blob, bd_t *bd) +{ ft_cpu_setup(blob, bd); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); #endif -#ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci2", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } +#ifdef CONFIG_PCIE2 + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif -#ifdef CONFIG_PCIE3 - path = fdt_getprop(blob, node, "pci3", NULL); - if (path) { - tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } +#ifdef CONFIG_PCIE1 + ft_fsl_pci_setup(blob, "pci3", &pcie3_hose); #endif - } } #endif diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index 28a9fa87f..c81a95922 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -47,25 +47,30 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1M, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 45372f427..7850794d6 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index 3b8bd05ad..7dd8f2958 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 005e4d97e..a0b6fbd12 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -71,7 +71,7 @@ initdram(int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* @@ -116,8 +116,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -127,8 +127,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ @@ -137,10 +137,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ } else { /* @@ -155,7 +155,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ udelay(200); /* @@ -176,52 +176,52 @@ local_bus_init(void) void sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); /* * Configure the SDRAM controller. */ - lbc->lsdmr = CFG_LBC_LSDMR_1; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_3; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_5; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -234,15 +234,15 @@ sdram_init(void) ************************************************************************/ long int fixed_sdram (void) { - #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; + #ifndef CONFIG_SYS_RAMBOOT + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000000D; ddr->err_sbe = 0x00ff0000; @@ -251,14 +251,14 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 4fe2862f7..2ec3ccce9 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -95,7 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -103,7 +103,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 7: 16K Non-cacheable, guarded * 0xf8000000 16K BCSR registers */ - SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), @@ -117,11 +117,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Likely it needs to be increased by two for these entries. */ #error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_64M, 1), #endif diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index 11ce57d36..c84a6cbe1 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c index fbf2bdc07..8e3de22a4 100644 --- a/board/freescale/mpc8541cds/law.c +++ b/board/freescale/mpc8541cds/law.c @@ -47,12 +47,12 @@ */ struct law_entry law_table[] = { - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index de3a79151..7e40c5c80 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -200,7 +200,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -258,7 +258,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -290,8 +290,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -302,8 +302,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ @@ -337,56 +337,56 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; asm("msync"); - lbc->br2 = CFG_BR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; asm("msync"); - lbc->lbcr = CFG_LBC_LBCR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * Determine which address lines to use baed on CPU board rev. */ cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; } else { /* * Assume something unable to identify itself is * really old, and likely has lines 16/17 mapped. */ - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; } /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -396,7 +396,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -406,7 +406,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -415,7 +415,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c index c5434a069..bf957c08c 100644 --- a/board/freescale/mpc8541cds/tlb.c +++ b/board/freescale/mpc8541cds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index bbb5ee2c4..34f84a265 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c index 54cf36bd4..317ba2696 100644 --- a/board/freescale/mpc8544ds/law.c +++ b/board/freescale/mpc8544ds/law.c @@ -28,15 +28,15 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), /* contains both PCIE3 MEM & IO space */ - SET_LAW(CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 4e976b78f..14581abdd 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -32,18 +32,17 @@ #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> +#include <tsec.h> +#include <netdev.h> #include "../common/pixis.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif +#include "../common/sgmii_riser.h" int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %lx\n",(ulong)&gur->porpllsr); @@ -74,12 +73,6 @@ initdram(int board_type) dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } @@ -100,12 +93,15 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + int first_free_busno=0; void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; @@ -122,11 +118,11 @@ pci_init_board(void) #ifdef CONFIG_PCIE3 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 1); int pcie_configured = io_sel >= 1; + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE3 connected to ULI as %s (base address %x)", @@ -139,36 +135,31 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE3_MEM_BASE, - CFG_PCIE3_MEM_PHYS, - CFG_PCIE3_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE3_IO_BASE, - CFG_PCIE3_IO_PHYS, - CFG_PCIE3_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCIE3_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE3_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCIE3_MEM_BASE2, - CFG_PCIE3_MEM_PHYS2, - CFG_PCIE3_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE2, + CONFIG_SYS_PCIE3_MEM_PHYS2, + CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -182,7 +173,7 @@ pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((u32 *)CFG_PCIE3_MEM_BASE); + in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE); } else { printf (" PCIE3: disabled\n"); } @@ -194,11 +185,11 @@ pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); int pcie_configured = io_sel & 6; + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", @@ -211,36 +202,31 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCIE1_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE1_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCIE1_MEM_BASE2, - CFG_PCIE1_MEM_PHYS2, - CFG_PCIE1_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE2, + CONFIG_SYS_PCIE1_MEM_PHYS2, + CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -262,11 +248,11 @@ pci_init_board(void) #ifdef CONFIG_PCIE2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 3); int pcie_configured = io_sel & 4; + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", @@ -279,36 +265,31 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE2_MEM_BASE, - CFG_PCIE2_MEM_PHYS, - CFG_PCIE2_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE2_IO_BASE, - CFG_PCIE2_IO_PHYS, - CFG_PCIE2_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCIE2_MEM_BASE2 +#ifdef CONFIG_SYS_PCIE2_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCIE2_MEM_BASE2, - CFG_PCIE2_MEM_PHYS2, - CFG_PCIE2_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE2, + CONFIG_SYS_PCIE2_MEM_PHYS2, + CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -329,9 +310,9 @@ pci_init_board(void) #ifdef CONFIG_PCI1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; uint pci_agent = (host_agent == 6); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ @@ -352,35 +333,31 @@ pci_init_board(void) ); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; -#ifdef CFG_PCIE3_MEM_BASE2 + +#ifdef CONFIG_SYS_PCIE3_MEM_BASE2 /* outbound memory */ - pci_set_region(hose->regions + 3, - CFG_PCIE3_MEM_BASE2, - CFG_PCIE3_MEM_PHYS2, - CFG_PCIE3_MEM_SIZE2, + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE2, + CONFIG_SYS_PCIE3_MEM_PHYS2, + CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); - hose->region_count++; #endif + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -463,47 +440,62 @@ get_board_sys_clk(ulong dummy) return val; } +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_TSEC_ENET + struct tsec_info_struct tsec_info[2]; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + if (io_sel & 1) + fsl_sgmii_riser_init(tsec_info, num); + + + tsec_eth_init(bis, tsec_info, num); +#endif + return pci_eth_init(bis); +} + #if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); -void -ft_board_setup(void *blob, bd_t *bd) +void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - ft_cpu_setup(blob, bd); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { + #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif #ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci2", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci2", &pcie3_hose); #endif #ifdef CONFIG_PCIE3 - path = fdt_getprop(blob, node, "pci3", NULL); - if (path) { - tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci3", &pcie2_hose); #endif - } } #endif diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index 40e049951..c7442b26f 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* @@ -45,28 +45,28 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000 * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, + SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), /* * TLB 1: 1G Non-cacheable, guarded * 0x80000000 1G PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1), /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe100_0000 255M PCI IO range */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), @@ -83,7 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 64M Non-cacheable, guarded * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF */ - SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), }; diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index f07d746c2..ab64fa88f 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c index 34b9d1c4d..98748aa47 100644 --- a/board/freescale/mpc8548cds/law.c +++ b/board/freescale/mpc8548cds/law.c @@ -51,22 +51,22 @@ */ struct law_entry law_table[] = { -#ifdef CFG_PCI1_MEM_PHYS - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), +#ifdef CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), #endif -#ifdef CFG_PCI2_MEM_PHYS - SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), +#ifdef CONFIG_SYS_PCI2_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), #endif -#ifdef CFG_PCIE1_MEM_PHYS - SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), #endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -#ifdef CFG_RIO_MEM_PHYS - SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_RIO_MEM_PHYS + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif }; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 84d3850cc..c562fc9d9 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -38,10 +38,6 @@ #include "../common/eeprom.h" #include "../common/via.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); @@ -49,14 +45,13 @@ void sdram_init(void); int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); uint cpu_board_rev = get_cpu_board_revision (); - uint svr; printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); @@ -69,17 +64,6 @@ int checkboard (void) */ local_bus_init (); - svr = get_svr(); - - /* - * Fix CPU2 errata: A core hang possible while executing a - * msync instruction and a snoopable transaction from an I/O - * master tagged to make quick forward progress is present. - * Fixed in Silicon Rev.2.1 - */ - if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1)) - ecm->eebpcr |= (1 << 16); - /* * Hack TSEC 3 and 4 IO voltages. */ @@ -106,7 +90,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -118,13 +102,6 @@ initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* * SDRAM Initialization */ @@ -140,8 +117,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -174,46 +151,46 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; asm("msync"); - lbc->br2 = CFG_BR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; asm("msync"); - lbc->lbcr = CFG_LBC_LBCR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8548 uses "new" 15-16 style addressing. */ cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CFG_LBC_LSDMR_COMMON; - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -223,7 +200,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -233,7 +210,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -242,7 +219,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -285,22 +262,25 @@ static struct pci_controller pci2_hose; static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + int first_free_busno=0; void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; #ifdef CONFIG_PCI1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_config_table *table; + struct pci_region *r = hose->regions; uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ @@ -322,27 +302,22 @@ pci_init_board(void) /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; /* relocate config table pointers */ hose->config_table = \ @@ -357,7 +332,7 @@ pci_init_board(void) first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); @@ -392,10 +367,10 @@ pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; @@ -411,27 +386,23 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -484,29 +455,16 @@ int last_stage_init(void) #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { +void ft_pci_setup(void *blob, bd_t *bd) +{ #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif - } } #endif diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index ab99af7e1..eab212a4c 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK, + SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,22 +54,22 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 1G Non-cacheable, guarded * 0x80000000 1G PCI1/PCIE 8,9,a,b */ - SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1G, 1), -#ifdef CFG_RIO_MEM_PHYS +#ifdef CONFIG_SYS_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), #endif @@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 7: 64M Non-cacheable, guarded * 0xf8000000 64M CADMUS registers, relocated L2SRAM */ - SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1), }; diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index 11ce57d36..c84a6cbe1 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c index fbf2bdc07..8e3de22a4 100644 --- a/board/freescale/mpc8555cds/law.c +++ b/board/freescale/mpc8555cds/law.c @@ -47,12 +47,12 @@ */ struct law_entry law_table[] = { - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index 826056a84..33685c19f 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -198,7 +198,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -256,7 +256,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -290,8 +290,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -302,8 +302,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ @@ -337,55 +337,55 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint cpu_board_rev; uint lsdmr_common; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; asm("msync"); - lbc->br2 = CFG_BR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; asm("msync"); - lbc->lbcr = CFG_LBC_LBCR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * Determine which address lines to use baed on CPU board rev. */ cpu_board_rev = get_cpu_board_revision(); - lsdmr_common = CFG_LBC_LSDMR_COMMON; + lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; } else { /* * Assume something unable to identify itself is * really old, and likely has lines 16/17 mapped. */ - lsdmr_common |= CFG_LBC_LSDMR_BSMA1617; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; } /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -395,7 +395,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -405,7 +405,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -414,7 +414,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c index c5434a069..bf957c08c 100644 --- a/board/freescale/mpc8555cds/tlb.c +++ b/board/freescale/mpc8555cds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -96,7 +96,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 45372f427..7850794d6 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index 3b8bd05ad..7dd8f2958 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 851fc5706..37308189d 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -217,7 +217,7 @@ typedef struct bcsr_ { void reset_phy (void) { #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR; + volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR; #endif /* reset Giga bit Ethernet port if needed here */ @@ -275,7 +275,7 @@ initdram(int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* @@ -320,8 +320,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -331,8 +331,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ @@ -341,10 +341,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ } else { /* @@ -359,7 +359,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ udelay(200); /* @@ -380,52 +380,52 @@ local_bus_init(void) void sdram_init(void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); /* * Configure the SDRAM controller. */ - lbc->lsdmr = CFG_LBC_LSDMR_1; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_3; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_5; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -438,15 +438,15 @@ sdram_init(void) ************************************************************************/ long int fixed_sdram (void) { - #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; + #ifndef CONFIG_SYS_RAMBOOT + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000000D; ddr->err_sbe = 0x00ff0000; @@ -455,14 +455,14 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 4fe2862f7..2ec3ccce9 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -95,7 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -103,7 +103,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 7: 16K Non-cacheable, guarded * 0xf8000000 16K BCSR registers */ - SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), @@ -117,11 +117,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Likely it needs to be increased by two for these entries. */ #error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_64M, 1), #endif diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c index 791a50fc9..30676e1e1 100644 --- a/board/freescale/mpc8568mds/bcsr.c +++ b/board/freescale/mpc8568mds/bcsr.c @@ -27,9 +27,9 @@ void enable_8568mds_duart() { - volatile uint* duart_mux = (uint *)(CFG_CCSRBAR + 0xe0060); - volatile uint* devices = (uint *)(CFG_CCSRBAR + 0xe0070); - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060); + volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */ *devices = 0; /* Enable all peripheral devices */ @@ -38,21 +38,21 @@ void enable_8568mds_duart() void enable_8568mds_flash_write() { - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[9] |= 0x01; } void disable_8568mds_flash_write() { - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[9] &= ~(0x01); } void enable_8568mds_qe_mdio() { - u8 *bcsr = (u8 *)(CFG_BCSR); + u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); bcsr[7] |= 0x01; } @@ -60,7 +60,7 @@ void enable_8568mds_qe_mdio() #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2) void reset_8568mds_uccs(void) { - volatile u8 *bcsr = (u8 *)(CFG_BCSR); + volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR); /* Turn off UCC1 & UCC2 */ out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN); diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index 1b8ecec5a..482fd919f 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -38,7 +39,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c index 3bc24c5c9..da7b6dcb7 100644 --- a/board/freescale/mpc8568mds/law.c +++ b/board/freescale/mpc8568mds/law.c @@ -50,13 +50,13 @@ */ struct law_entry law_table[] = { - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), /* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index f9e35cc7e..bc93be80f 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -99,11 +99,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - void local_bus_init(void); void sdram_init(void); @@ -123,10 +118,10 @@ int board_early_init_f (void) enable_8568mds_qe_mdio(); #endif -#ifdef CFG_I2C2_OFFSET +#ifdef CONFIG_SYS_I2C2_OFFSET /* Enable I2C2_SCL and I2C2_SDA */ volatile struct par_io *port_c; - port_c = (struct par_io*)(CFG_IMMR + 0xe0140); + port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140); port_c->cpdir2 |= 0x0f000000; port_c->cppar2 &= ~0x0f000000; port_c->cppar2 |= 0x0a000000; @@ -158,7 +153,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -170,13 +165,6 @@ initdram(int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* * SDRAM Initialization */ @@ -192,8 +180,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -223,44 +211,44 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) +#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or2 = CFG_OR2_PRELIM; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; asm("msync"); - lbc->br2 = CFG_BR2_PRELIM; + lbc->br2 = CONFIG_SYS_BR2_PRELIM; asm("msync"); - lbc->lbcr = CFG_LBC_LBCR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8568 uses "new" 15-16 style addressing. */ - lsdmr_common = CFG_LBC_LSDMR_COMMON; - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -270,7 +258,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -280,7 +268,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -289,7 +277,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -323,6 +311,9 @@ static struct pci_controller pci1_hose = { static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + int first_free_busno = 0; /* @@ -371,7 +362,7 @@ pib_init(void) void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; @@ -379,9 +370,9 @@ pci_init_board(void) { pib_init(); - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; uint pci_32 = 1; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ @@ -402,27 +393,23 @@ pci_init_board(void) ); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -440,10 +427,10 @@ pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; @@ -459,27 +446,23 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -500,31 +483,18 @@ pci_init_board(void) #endif /* CONFIG_PCI */ #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; - const char *path; +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); +void ft_board_setup(void *blob, bd_t *bd) +{ ft_cpu_setup(blob, bd); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif - } } #endif diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index 75651765f..107755273 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH (upper half) * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -55,7 +55,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLBe 1: 16M Non-cacheable, guarded * 0xfe000000 16M FLASH (lower half) */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_16M, 1), @@ -64,7 +64,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0x80000000 512M PCI1 MEM * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1), @@ -74,7 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_64M, 1), @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLBe 4: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_64M, 1), @@ -92,7 +92,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf8008000 32K PIB (CS4) * 0xf8010000 32K PIB (CS5) */ - SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256K, 1), }; diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index 5f8c55504..d66ede2d5 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { @@ -38,40 +39,108 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ + + +/* XXX: these values need to be checked for all interleaving modes. */ +/* XXX: No reliable dual-rank 800 MHz setting has been found. It may + * seem reliable, but errors will appear when memory intensive + * program is run. */ +/* XXX: Single rank at 800 MHz is OK. */ +const board_specific_parameters_t board_specific_parameters[][20] = { + { + /* memory controller 0 */ + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 2, 6, 7, 3, 0}, + {334, 400, 2, 6, 9, 3, 0}, + {401, 549, 2, 6, 11, 3, 0}, + {550, 680, 2, 1, 10, 5, 0}, + {681, 850, 2, 1, 12, 5, 1}, + { 0, 333, 1, 6, 7, 3, 0}, + {334, 400, 1, 6, 9, 3, 0}, + {401, 549, 1, 6, 11, 3, 0}, + {550, 680, 1, 1, 10, 5, 0}, + {681, 850, 1, 1, 12, 5, 0} + }, + + { + /* memory controller 1 */ + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 2, 6, 7, 3, 0}, + {334, 400, 2, 6, 9, 3, 0}, + {401, 549, 2, 6, 11, 3, 0}, + {550, 680, 2, 1, 11, 6, 0}, + {681, 850, 2, 1, 13, 6, 1}, + { 0, 333, 1, 6, 7, 3, 0}, + {334, 400, 1, 6, 9, 3, 0}, + {401, 549, 1, 6, 11, 3, 0}, + {550, 680, 1, 1, 11, 6, 0}, + {681, 850, 1, 1, 13, 6, 0} + } +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; + const board_specific_parameters_t *pbsp = + &(board_specific_parameters[ctrl_num][0]); + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / + sizeof(board_specific_parameters[0][0]); + u32 i; + ulong ddr_freq; - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 + /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ - popts->cpo_override = 10; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i&1) { /* odd CS */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 0; + } else { /* even CS */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 4; + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + popts->cs_local_opts[i].odt_rd_cfg = 3; + popts->cs_local_opts[i].odt_wr_cfg = 3; + } + } + } - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. */ - popts->write_data_delay = 5; + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm->n_ranks == pbsp->n_ranks) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->twoT_en = pbsp->force_2T; + } + pbsp++; + } /* * Factors to consider for half-strength driver enable: diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index d69b59345..83eb6811c 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -28,14 +28,15 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 70b548bc3..a14db5ad2 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -25,6 +25,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/mmu.h> +#include <asm/cache.h> #include <asm/immap_85xx.h> #include <asm/immap_fsl_pci.h> #include <asm/fsl_ddr_sdram.h> @@ -32,12 +33,10 @@ #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> +#include <tsec.h> #include "../common/pixis.h" - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif +#include "../common/sgmii_riser.h" long int fixed_sdram(void); @@ -58,20 +57,12 @@ phys_size_t initdram(int board_type) #ifdef CONFIG_SPD_EEPROM dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; #else dram_size = fixed_sdram(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif puts(" DDR: "); return dram_size; } @@ -83,34 +74,34 @@ phys_size_t initdram(int board_type) phys_size_t fixed_sdram (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_ddr_t *ddr= &immap->im_ddr; uint d_init; - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - ddr->timing_cfg_3 = CFG_DDR_TIMING_3; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE_1; - ddr->sdram_mode_2 = CFG_DDR_MODE_2; - ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; #if defined (CONFIG_DDR_ECC) - ddr->err_int_en = CFG_DDR_ERR_INT_EN; - ddr->err_disable = CFG_DDR_ERR_DIS; - ddr->err_sbe = CFG_DDR_SBE; + ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; + ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; + ddr->err_sbe = CONFIG_SYS_DDR_SBE; #endif asm("sync;isync"); udelay(500); - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) d_init = 1; @@ -144,11 +135,14 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + int first_free_busno=0; #ifdef CONFIG_PCI void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; @@ -168,12 +162,12 @@ void pci_init_board(void) #ifdef CONFIG_PCIE3 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 0) || (host_agent == 3) || (host_agent == 5) || (host_agent == 6); int pcie_configured = io_sel >= 1; + struct pci_region *r = hose->regions; u32 temp32; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -187,27 +181,23 @@ void pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE3_MEM_BASE, - CFG_PCIE3_MEM_PHYS, - CFG_PCIE3_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE3_MEM_BASE, + CONFIG_SYS_PCIE3_MEM_PHYS, + CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE3_IO_BASE, - CFG_PCIE3_IO_PHYS, - CFG_PCIE3_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE3_IO_BASE, + CONFIG_SYS_PCIE3_IO_PHYS, + CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -225,7 +215,7 @@ void pci_init_board(void) pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), PCI_BASE_ADDRESS_1, &temp32); - if (temp32 >= CFG_PCIE3_MEM_PHYS) { + if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) { debug(" uli1572 read to %x\n", temp32); in_be32((unsigned *)temp32); } @@ -240,12 +230,12 @@ void pci_init_board(void) #ifdef CONFIG_PCIE2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6); + (host_agent == 6) || (host_agent == 0); int pcie_configured = io_sel & 4; + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", @@ -258,27 +248,23 @@ void pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE2_MEM_BASE, - CFG_PCIE2_MEM_PHYS, - CFG_PCIE2_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE2_IO_BASE, - CFG_PCIE2_IO_PHYS, - CFG_PCIE2_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -297,12 +283,12 @@ void pci_init_board(void) #endif #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 1) || (host_agent == 4) || + int pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); int pcie_configured = io_sel & 6; + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", @@ -315,27 +301,23 @@ void pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -359,8 +341,7 @@ void pci_init_board(void) int board_early_init_r(void) { - unsigned int i; - const unsigned int flashbase = CFG_FLASH_BASE; + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = 2; /* @@ -368,11 +349,9 @@ int board_early_init_r(void) * so that flash can be erased properly. */ - /* Invalidate any remaining lines of the flash from caches. */ - for (i = 0; i < 256*1024*1024; i+=32) { - asm volatile ("dcbi %0,%1": : "b" (flashbase), "r" (i)); - asm volatile ("icbi %0,%1": : "b" (flashbase), "r" (i)); - } + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); /* invalidate existing TLB entry for flash + promjet */ disable_tlb(flash_esel); @@ -521,11 +500,58 @@ unsigned long get_board_ddr_clk(ulong dummy) } #endif +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct tsec_info_struct tsec_info[4]; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif +#ifdef CONFIG_TSEC4 + SET_STD_TSEC_INFO(tsec_info[num], 4); + if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + tsec_info[num].flags |= TSEC_SGMII; + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + + return 0; + } + + fsl_sgmii_riser_init(tsec_info, num); + + tsec_eth_init(bis, tsec_info, num); + + return 0; +} +#endif + #if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; ulong base, size; ft_cpu_setup(blob, bd); @@ -535,31 +561,15 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #ifdef CONFIG_PCIE3 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pcie3_hose); #endif #ifdef CONFIG_PCIE2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pcie2_hose); #endif #ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci2", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci2", &pcie1_hose); #endif - } } #endif diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index 965356a84..8d1f646fa 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -52,34 +52,40 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS, CFG_PCIE3_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x40000000, CFG_PCIE3_MEM_PHYS + 0x40000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x50000000, CFG_PCIE3_MEM_PHYS + 0x50000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_1M, 1), + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 2d22da177..414ac243a 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -36,7 +37,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index 91b922b86..2aad28aee 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -29,16 +29,16 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW(CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index af79fc2c6..2792778e3 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -32,22 +32,19 @@ #include <libfdt.h> #include <fdt_support.h> #include <spd_sdram.h> +#include <netdev.h> #include "../common/pixis.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - void sdram_init(void); -long int fixed_sdram(void); +phys_size_t fixed_sdram(void); void mpc8610hpcd_diu_init(void); /* called before any console output */ int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ @@ -97,7 +94,7 @@ int misc_init_r(void) int checkboard(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; printf ("Board: MPC8610HPCD, System ID: 0x%02x, " @@ -120,7 +117,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - long dram_size = 0; + phys_size_t dram_size = 0; #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); @@ -128,18 +125,11 @@ initdram(int board_type) dram_size = fixed_sdram(); #endif -#if defined(CFG_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) puts(" DDR: "); return dram_size; #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - puts(" DDR: "); return dram_size; } @@ -150,10 +140,10 @@ initdram(int board_type) * Fixed sdram init -- doesn't use serial presence detect. */ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void) { -#if !defined(CFG_RAMBOOT) - volatile immap_t *immap = (immap_t *)CFG_IMMR; +#if !defined(CONFIG_SYS_RAMBOOT) + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_ddr_t *ddr = &immap->im_ddr1; uint d_init; @@ -200,7 +190,7 @@ long int fixed_sdram(void) return 512 * 1024 * 1024; #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif @@ -239,9 +229,12 @@ static struct pci_controller pcie2_hose; int first_free_busno = 0; +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + void pci_init_board(void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) @@ -254,12 +247,12 @@ void pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_configured = (io_sel == 1) || (io_sel == 4); int pcie_ep = (host_agent == 0) || (host_agent == 2) || (host_agent == 5); + struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { printf(" PCIe 1 connected to Uli as %s (base address %x)\n", @@ -269,27 +262,23 @@ void pci_init_board(void) pci->pme_msg_det = 0xffffffff; /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int)&pci->cfg_addr, @@ -311,9 +300,9 @@ void pci_init_board(void) #ifdef CONFIG_PCIE2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; + struct pci_region *r = hose->regions; int pcie_configured = (io_sel == 0) || (io_sel == 4); int pcie_ep = (host_agent == 0) || (host_agent == 1) || @@ -328,27 +317,23 @@ void pci_init_board(void) pci->pme_msg_det = 0xffffffff; /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE2_MEM_BASE, - CFG_PCIE2_MEM_PHYS, - CFG_PCIE2_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_MEM_BASE, + CONFIG_SYS_PCIE2_MEM_PHYS, + CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE2_IO_BASE, - CFG_PCIE2_IO_PHYS, - CFG_PCIE2_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE2_IO_BASE, + CONFIG_SYS_PCIE2_IO_PHYS, + CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int)&pci->cfg_addr, @@ -369,10 +354,10 @@ void pci_init_board(void) #ifdef CONFIG_PCI1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; int pci_agent = (host_agent >= 4) && (host_agent <= 6); + struct pci_region *r = hose->regions; if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { printf(" PCI connected to PCI slots as %s" \ @@ -381,27 +366,23 @@ void pci_init_board(void) (uint)pci); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, @@ -421,12 +402,12 @@ void pci_init_board(void) } #if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 4, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, @@ -441,36 +422,15 @@ ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); - - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { - #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } - + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif #ifdef CONFIG_PCIE2 - path = fdt_getprop(blob, node, "pci2", NULL); - if (path) { - tmp[1] = pcie2_hose.last_busno - - pcie2_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci2", &pcie2_hose); #endif - } } #endif @@ -520,12 +480,7 @@ get_board_sys_clk(ulong dummy) return val; } -extern int uli526x_initialize(bd_t *); - int board_eth_init(bd_t *bis) { -#if defined(CONFIG_ULI526) - uli526x_initialize(bis); -#endif - return 0; + return pci_eth_init(bis); } diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 4db941ced..cd25d4aa8 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -43,7 +43,7 @@ static int xres, yres; void diu_set_pixel_clock(unsigned int pixclock) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; unsigned long speed_ccb, temp, pixval; @@ -137,7 +137,7 @@ int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp, } U_BOOT_CMD( - diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp, + diufb, CONFIG_SYS_MAXARGS, 1, mpc8610diu_init_show_bmp, "diufb init | addr - Init or Display BMP file\n", "init\n - initialize DIU\n" "addr\n - display bmp at address 'addr'\n" diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds index b88138e19..41274923d 100644 --- a/board/freescale/mpc8610hpcd/u-boot.lds +++ b/board/freescale/mpc8610hpcd/u-boot.lds @@ -128,6 +128,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/freescale/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk index f778dcbe0..487a76699 100644 --- a/board/freescale/mpc8641hpcn/config.mk +++ b/board/freescale/mpc8641hpcn/config.mk @@ -25,7 +25,7 @@ # default CCSRBAR is at 0xff700000 # assume U-Boot is less than 0.5MB # -TEXT_BASE = 0xfff00000 +TEXT_BASE = 0xeff00000 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 5163abf05..3789b5442 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -45,44 +46,120 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 cpo; + u32 write_data_delay; +} board_specific_parameters_t; + +/* XXX: these values need to be checked for all interleaving modes. */ +const board_specific_parameters_t board_specific_parameters[2][16] = { + { + /* memory controller 0 */ + /* lo| hi| num| clk| cpo|wrdata */ + /* mhz| mhz|ranks|adjst| | delay */ + { 0, 333, 4, 7, 7, 3}, + {334, 400, 4, 7, 9, 3}, + {401, 549, 4, 7, 9, 3}, + {550, 650, 4, 7, 10, 4}, + + { 0, 333, 3, 7, 7, 3}, + {334, 400, 3, 7, 9, 3}, + {401, 549, 3, 7, 9, 3}, + {550, 650, 3, 7, 10, 4}, + + { 0, 333, 2, 7, 7, 3}, + {334, 400, 2, 7, 9, 3}, + {401, 549, 2, 7, 9, 3}, + {550, 650, 2, 7, 10, 4}, + + { 0, 333, 1, 7, 7, 3}, + {334, 400, 1, 7, 9, 3}, + {401, 549, 1, 7, 9, 3}, + {550, 650, 1, 7, 10, 4} + }, + + { + /* memory controller 1 */ + /* lo| hi| num| clk| cpo|wrdata */ + /* mhz| mhz|ranks|adjst| | delay */ + { 0, 333, 4, 7, 7, 3}, + {334, 400, 4, 7, 9, 3}, + {401, 549, 4, 7, 9, 3}, + {550, 650, 4, 7, 10, 4}, + + { 0, 333, 3, 7, 7, 3}, + {334, 400, 3, 7, 9, 3}, + {401, 549, 3, 7, 9, 3}, + {550, 650, 3, 7, 10, 4}, + + { 0, 333, 2, 7, 7, 3}, + {334, 400, 2, 7, 9, 3}, + {401, 549, 2, 7, 9, 3}, + {550, 650, 2, 7, 10, 4}, + + { 0, 333, 1, 7, 7, 3}, + {334, 400, 1, 7, 9, 3}, + {401, 549, 1, 7, 9, 3}, + {550, 650, 1, 7, 10, 4} + } +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; + const board_specific_parameters_t *pbsp = + &(board_specific_parameters[ctrl_num][0]); + u32 num_params = sizeof(board_specific_parameters[ctrl_num]) / + sizeof(board_specific_parameters[0][0]); + u32 i; + u32 j; + ulong ddr_freq; - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 + /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i&1) { /* odd CS */ + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 0; + } else { /* even CS */ + if ((CONFIG_DIMM_SLOTS_PER_CTLR == 2) && + (pdimm[i/2].n_ranks != 0)) { + popts->cs_local_opts[i].odt_rd_cfg = 3; + popts->cs_local_opts[i].odt_wr_cfg = 3; + } else { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 4; + } + } + } - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed + /* Get clk_adjust, cpo, write_data_delay, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. */ - popts->half_strength_driver_enable = 0; + ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + if (pdimm[j].n_ranks > 0) { + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm[j].n_ranks == pbsp->n_ranks) { + popts->clk_adjust = pbsp->clk_adjust; + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + break; + } + pbsp++; + } + } + } + } diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 2d6c3c175..bd357b866 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -31,34 +31,38 @@ * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G + * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf800_0000 0xf80f_ffff CCSRBAR 1M - * 0xf810_0000 0xf81f_ffff PIXIS 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT) + * 0x8000_0000 0x9fff_ffff RapidIO 512M + * endif + * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT) + * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K + * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K + * 0xffe0_0000 0xffef_ffff CCSRBAR 1M + * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K + * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M * * Notes: - * CCSRBAR don't need a configured Local Access Window. + * CCSRBAR doesn't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif - SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - SET_LAW((CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), -#if !defined(CONFIG_SPD_EEPROM) - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), +#ifdef CONFIG_PCI + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), +#elif defined(CONFIG_RIO) + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif - SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 1bb563e41..b83ed6c45 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -29,14 +29,11 @@ #include <asm/io.h> #include <libfdt.h> #include <fdt_support.h> +#include <netdev.h> #include "../common/pixis.h" -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -long int fixed_sdram(void); +phys_size_t fixed_sdram(void); int board_early_init_f(void) { @@ -56,7 +53,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - long dram_size = 0; + phys_size_t dram_size = 0; #if defined(CONFIG_SPD_EEPROM) dram_size = fsl_ddr_sdram(); @@ -64,18 +61,11 @@ initdram(int board_type) dram_size = fixed_sdram(); #endif -#if defined(CFG_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) puts(" DDR: "); return dram_size; #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - puts(" DDR: "); return dram_size; } @@ -85,26 +75,26 @@ initdram(int board_type) /* * Fixed sdram init -- doesn't use serial presence detect. */ -long int +phys_size_t fixed_sdram(void) { -#if !defined(CFG_RAMBOOT) - volatile immap_t *immap = (immap_t *) CFG_IMMR; +#if !defined(CONFIG_SYS_RAMBOOT) + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_ddr_t *ddr = &immap->im_ddr1; - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_3 = CFG_DDR_TIMING_3; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode_1 = CFG_DDR_MODE_1; - ddr->sdram_mode_2 = CFG_DDR_MODE_2; - ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; - ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL; - ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; + ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL; + ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000008D; @@ -116,42 +106,22 @@ fixed_sdram(void) #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg_1 = CFG_DDR_CONTROL; - ddr->sdram_cfg_2 = CFG_DDR_CONTROL2; + ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; #endif asm("sync; isync"); udelay(500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ #if defined(CONFIG_PCI) -/* - * Initialize PCI Devices, report devices found. - */ - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_fsl86xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, - {} -}; -#endif - - -static struct pci_controller pci1_hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table -#endif -}; +static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */ #ifdef CONFIG_PCI2 @@ -160,20 +130,22 @@ static struct pci_controller pci2_hose; int first_free_busno = 0; +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); void pci_init_board(void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; + struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); - struct pci_controller *hose = &pci1_hose; #ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) >> MPC8641_PORBMSR_HA_SHIFT; @@ -192,27 +164,23 @@ void pci_init_board(void) debug("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -227,8 +195,8 @@ void pci_init_board(void) * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ - in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE - + CFG_PCI1_MEM_SIZE - 0x1000000))); + in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE + + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); } else { puts("PCI-EXPRESS 1: Disabled\n"); @@ -240,33 +208,28 @@ void pci_init_board(void) #ifdef CONFIG_PCI2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; struct pci_controller *hose = &pci2_hose; - + struct pci_region *r = hose->regions; /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -285,32 +248,46 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); void ft_board_setup(void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; + int off; + u64 *tmp; + u32 *addrcells; ft_cpu_setup(blob, bd); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCI2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pci2_hose); #endif + + /* + * Warn if it looks like the device tree doesn't match u-boot. + * This is just an estimation, based on the location of CCSR, + * which is defined by the "reg" property in the soc node. + */ + off = fdt_path_offset(blob, "/soc8641"); + addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL); + tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL); + + if (tmp) { + u64 addr; + if (addrcells && (*addrcells == 1)) + addr = *(u32 *)tmp; + else + addr = *tmp; + + if (addr != CONFIG_SYS_CCSRBAR_PHYS) + printf("WARNING: The CCSRBAR address in your .dts " + "does not match the address of the CCSR " + "in u-boot. This means your .dts might " + "be old.\n"); } } #endif @@ -379,3 +356,10 @@ get_board_sys_clk(ulong dummy) return val; } + +int board_eth_init(bd_t *bis) +{ + /* Initialize TSECs */ + cpu_eth_init(bis); + return pci_eth_init(bis); +} diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds index 4f884f987..6c9da1f32 100644 --- a/board/freescale/mpc8641hpcn/u-boot.lds +++ b/board/freescale/mpc8641hpcn/u-boot.lds @@ -129,6 +129,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index c379460c9..e682f307f 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -44,7 +44,7 @@ SECTIONS drivers/mtd/libmtd.a (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) } @@ -65,6 +65,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss : { *(.bss) } + .bss : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c index 7dd0d3f23..fd3b16ea5 100644 --- a/board/funkwerk/vovpn-gw/flash.c +++ b/board/funkwerk/vovpn-gw/flash.c @@ -27,7 +27,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define FLASH_CMD_READ_ID 0x90 #define FLASH_CMD_READ_STATUS 0x70 @@ -46,7 +46,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define FLASH_WRITE_BUFFER_SIZE 32 -#ifdef CFG_FLASH_16BIT +#ifdef CONFIG_SYS_FLASH_16BIT #define FLASH_WORD_SIZE unsigned short #define FLASH_ID_MASK 0xffff #define FLASH_CMD_ADDR_SHIFT 0 @@ -130,10 +130,10 @@ flash_init(void) unsigned long size; int i; - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size = flash_get((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get((volatile FLASH_WORD_SIZE *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH Size=0x%08lx\n", size); return (0); @@ -145,16 +145,16 @@ flash_init(void) flash_info[0].start[1] - 1, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_FLASH, - CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1, + CONFIG_SYS_MONITOR_FLASH, + CONFIG_SYS_MONITOR_FLASH+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif return (size); @@ -265,7 +265,7 @@ flash_erase(flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Flash erase timeout at address %lx\n", info->start[sect]); *addr = FLASH_CMD_SUSPEND_ERASE; *addr = FLASH_CMD_RESET; @@ -307,7 +307,7 @@ write_buff2( volatile FLASH_WORD_SIZE *dst, enable_interrupts(); } - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (-1); } } @@ -337,7 +337,7 @@ poll_status( volatile FLASH_WORD_SIZE *addr ) break; } } - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = FLASH_CMD_RESET; return (-1); } @@ -367,7 +367,7 @@ write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt) addr = (volatile FLASH_WORD_SIZE *)(info->start[0]); dst = (volatile FLASH_WORD_SIZE *) udst; -#ifdef CFG_FLASH_16BIT +#ifdef CONFIG_SYS_FLASH_16BIT #error NYI #else while (cnt > 0) { @@ -435,7 +435,7 @@ flash_real_protect(flash_info_t *info, long sector, int prot) /* wait for error or finish */ start = get_timer (0); while(!(addr[0] & FLASH_STATUS_DONE)){ - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Flash protect timeout at address %lx\n", info->start[sector]); addr[0] = FLASH_CMD_RESET; return (1); diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c index 1c3f627a4..8c4abdd37 100644 --- a/board/funkwerk/vovpn-gw/vovpn-gw.c +++ b/board/funkwerk/vovpn-gw/vovpn-gw.c @@ -189,7 +189,7 @@ void reset_phy (void) unsigned short val; #endif - iop = ioport_addr((immap_t *)CFG_IMMR, 0); + iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0); /* Reset the PHY */ iop->pdat &= 0xfff7ffff; /* PA12 = |SWITCH_RESET */ @@ -198,12 +198,12 @@ void reset_phy (void) iop->pdat |= 0x00080000; for (i=0; i<100; i++) { udelay(20000); - if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) { + if (bb_miiphy_read("FCC1 ETHERNET", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) { break; } } /* initialize switch */ - m88e6060_initialize( CFG_PHY_ADDR ); + m88e6060_initialize( CONFIG_SYS_PHY_ADDR ); #endif } @@ -233,7 +233,7 @@ int board_early_init_f (void) volatile unsigned char *dummy; int i; - immap = (immap_t *) CFG_IMMR; + immap = (immap_t *) CONFIG_SYS_IMMR; memctl = &immap->im_memctl; #if 0 @@ -272,7 +272,7 @@ int misc_init_r (void) unsigned char c; int i; - immap = (immap_t *) CFG_IMMR; + immap = (immap_t *) CONFIG_SYS_IMMR; memctl = &immap->im_memctl; @@ -289,7 +289,7 @@ int misc_init_r (void) memctl->memc_mamr = 0x00044440; #endif /* enable buffers (DSP, DPRAM) */ - iop = ioport_addr((immap_t *)CFG_IMMR, 0); + iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0); iop->pdat &= 0xfffbffff; /* PA13 = |EN_M_BCTL1 */ /* destroy DPRAM magic */ @@ -310,7 +310,7 @@ do_reset (void *cmdtp, int flag, int argc, char *argv[]) { volatile ioport_t *iop; - iop = ioport_addr((immap_t *)CFG_IMMR, 2); + iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2); iop->pdat |= 0x00002000; /* PC18 = HW_RESET */ return 1; } @@ -320,16 +320,16 @@ do_reset (void *cmdtp, int flag, int argc, char *argv[]) phys_size_t initdram (int board_type) { -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT volatile immap_t *immap; volatile memctl8260_t *memctl; volatile uchar *ramaddr; int i; uchar c; - immap = (immap_t *) CFG_IMMR; + immap = (immap_t *) CONFIG_SYS_IMMR; memctl = &immap->im_memctl; - ramaddr = (uchar *) CFG_SDRAM_BASE; + ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE; c = 0xff; immap->im_siu_conf.sc_ppc_acr = 0x02; @@ -338,30 +338,30 @@ phys_size_t initdram (int board_type) immap->im_siu_conf.sc_tescr1 = 0x00000000; immap->im_siu_conf.sc_tescr2 = 0x00000000; - memctl->memc_mptpr = CFG_MPTPR; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM; /* Precharge all banks */ - memctl->memc_psdmr = CFG_PSDMR | 0x28000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000; *ramaddr = c; /* CBR refresh */ - memctl->memc_psdmr = CFG_PSDMR | 0x08000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000; for (i = 0; i < 8; i++) *ramaddr = c; /* Mode Register write */ - memctl->memc_psdmr = CFG_PSDMR | 0x18000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000; *ramaddr = c; /* Refresh enable */ - memctl->memc_psdmr = CFG_PSDMR | 0x40000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000; *ramaddr = c; -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ - return (CFG_SDRAM_SIZE); + return (CONFIG_SYS_SDRAM_SIZE); } int checkboard (void) diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 647f4b705..48fc643dc 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -33,7 +33,7 @@ #define MEM_SDTR1_INIT_VAL 0x00854005 #define SDRAM0_CFG_ENABLE 0x80000000 -#define CFG_SDRAM_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ int board_early_init_f (void) { @@ -77,8 +77,8 @@ int misc_init_r (void) /* * Set NAND-FLASH GPIO signals to default */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); + out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE)); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE); #endif return (0); @@ -127,7 +127,7 @@ long int init_sdram_static_settings(void) udelay(500); mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE ); - return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */ + return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */ } @@ -151,11 +151,11 @@ phys_size_t initdram (int board_type) #if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; void nand_init(void) { - nand_probe(CFG_NAND_BASE); + nand_probe(CONFIG_SYS_NAND_BASE); if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { print_size(nand_dev_desc[0].totlen, "\n"); } diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c index 8446e0210..effe65a36 100644 --- a/board/g2000/strataflash.c +++ b/board/g2000/strataflash.c @@ -101,7 +101,7 @@ typedef union { #define NUM_ERASE_REGIONS 4 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -116,7 +116,7 @@ static int flash_detect_cfi(flash_info_t * info); static ulong flash_get_size (ulong base, int banknum); static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); #endif /*----------------------------------------------------------------------- @@ -176,14 +176,14 @@ unsigned long flash_init (void) * */ - address = CFG_FLASH_BASE; + address = CONFIG_SYS_FLASH_BASE; size = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; + address += CONFIG_SYS_FLASH_INCREMENT; if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, flash_info[0].size, flash_info[i].size<<20); @@ -192,14 +192,14 @@ unsigned long flash_init (void) #if 0 /* test-only */ /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++) (void)flash_real_protect(&flash_info[0], i, 1); #endif #else /* monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - - CFG_MONITOR_LEN, + - CONFIG_SYS_MONITOR_LEN, - 1, &flash_info[1]); #endif @@ -273,7 +273,7 @@ void flash_print_info (flash_info_t *info) printf (" Sector Start Addresses:"); for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO int k; int size; int erased; @@ -353,7 +353,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp = cp; } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE while(cnt >= info->portwidth) { i = info->buffer_size > cnt? cnt: info->buffer_size; if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) @@ -374,7 +374,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp += info->portwidth; cnt -= info->portwidth; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); } @@ -716,7 +716,7 @@ static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) return flash_full_status_check(info, 0, info->write_tout, "write"); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* loop through the sectors from the highest address * when the passed address is greater or equal to the sector address @@ -790,4 +790,4 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, in flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds index d70d37934..d8fbea396 100644 --- a/board/g2000/u-boot.lds +++ b/board/g2000/u-boot.lds @@ -66,14 +66,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -144,6 +144,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index 3958670bb..a0876310c 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS *(.start) cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */ +/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, * no global data accesses please. diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index 100350d7a..e461a36fa 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS *(.start) cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */ +/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, * no global data accesses please. diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 3848c684a..ddd27d455 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS *(.start) cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */ +/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, * no global data accesses please. diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index 1e8bb6957..a9cc7ca4b 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS *(.start) cpu/leon3/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */ +/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, * no global data accesses please. diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index 2a22082a8..b3462d463 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS *(.start) cpu/leon2/start.o (.text) -/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */ +/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */ . = ALIGN(8192); /* PROM CODE, Will be relocated to the end of memory, * no global data accesses please. diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c index 36d7363a8..8511582ba 100644 --- a/board/gcplus/flash.c +++ b/board/gcplus/flash.c @@ -29,7 +29,7 @@ #include <common.h> #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -67,7 +67,7 @@ flash_init(void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -83,12 +83,12 @@ flash_init(void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -207,10 +207,10 @@ flash_get_size(FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -282,7 +282,7 @@ flash_erase(flash_info_t * info, int s_first, int s_last) while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -418,7 +418,7 @@ write_data(flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/gcplus/u-boot.lds b/board/gcplus/u-boot.lds index 5ab680181..ab7f76bcb 100644 --- a/board/gcplus/u-boot.lds +++ b/board/gcplus/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/xilinx/xupv2p/Makefile b/board/gdsys/neo/Makefile index 10b47b2ae..1270feafc 100644 --- a/board/xilinx/xupv2p/Makefile +++ b/board/gdsys/neo/Makefile @@ -1,6 +1,6 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -26,13 +26,14 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o +SOBJS = SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) diff --git a/board/gdsys/neo/config.mk b/board/gdsys/neo/config.mk new file mode 100644 index 000000000..1bdf5e4fc --- /dev/null +++ b/board/gdsys/neo/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFC0000 diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c new file mode 100644 index 000000000..817ce17ff --- /dev/null +++ b/board/gdsys/neo/neo.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2007-2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> + +#define HWTYPE_CCX16 1 +#define HWREV_300 3 + +int board_early_init_f(void) +{ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ + mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + /* + * EBC Configuration Register: set ready timeout to 512 ebc-clks + * -> ca. 15 us + */ + mtebc(epcr, 0xa8400000); /* ebc always driven */ + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2); + u8 unit_type; + u8 hardware_cpu_ports; + u8 hardware_con_ports; + u8 hardware_version; + + printf("Board: CATCenter Neo"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + puts("\n "); + + unit_type = (val & 0xf000) >> 12; + hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8; + hardware_con_ports = ((val & 0x00f0) >> 4) * 2; + hardware_version = val & 0x000f; + + switch (unit_type) { + case HWTYPE_CCX16: + printf("CCX16-FPGA (80 UARTs)"); + break; + + default: + printf("UnitType %d, unsupported", unit_type); + break; + } + + printf(", %d cpu ports, %d console ports,", + hardware_cpu_ports, hardware_con_ports); + + switch (hardware_version) { + case HWREV_300: + printf(" HW-Ver 3.00\n"); + break; + + default: + printf(" HW-Ver %d, unsupported\n", + hardware_version); + break; + } + + return 0; +} diff --git a/board/gdsys/neo/u-boot.lds b/board/gdsys/neo/u-boot.lds new file mode 100644 index 000000000..d803625b5 --- /dev/null +++ b/board/gdsys/neo/u-boot.lds @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c index b4c2c8988..c6be83f65 100644 --- a/board/gen860t/beeper.c +++ b/board/gen860t/beeper.c @@ -36,14 +36,14 @@ /* * Initialize beeper-related hardware. Initialize timer 1 for use with - * the beeper. Use 66 Mhz internal clock with prescale of 33 to get + * the beeper. Use 66 MHz internal clock with prescale of 33 to get * 1 uS period per count. * FIXME: we should really compute the prescale based on the reported * core clock frequency. */ void init_beeper (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1; immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK) @@ -62,7 +62,7 @@ void set_beeper_frequency (uint frequency) { #define FREQ_LIMIT 2500 - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* * Compute timer ticks given desired frequency. The timer is set up @@ -79,7 +79,7 @@ void set_beeper_frequency (uint frequency) */ void beeper_on (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1; } @@ -89,7 +89,7 @@ void beeper_on (void) */ void beeper_off (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1; } @@ -104,7 +104,7 @@ void beeper_off (void) */ void set_beeper_volume (int steps) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; int i; if (steps >= 0) { diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c index 13faaf39f..827d9e0c6 100644 --- a/board/gen860t/flash.c +++ b/board/gen860t/flash.c @@ -25,15 +25,15 @@ #include <common.h> #include <mpc8xx.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -41,15 +41,15 @@ * Use buffered writes to flash by default - they are about 32x faster than * single byte writes. */ -#ifndef CFG_GEN860T_FLASH_USE_WRITE_BUFFER -#define CFG_GEN860T_FLASH_USE_WRITE_BUFFER +#ifndef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER +#define CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER #endif /* * Max time to wait (in mS) for flash device to allocate a write buffer. */ -#ifndef CFG_FLASH_ALLOC_BUFFER_TOUT -#define CFG_FLASH_ALLOC_BUFFER_TOUT 100 +#ifndef CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT +#define CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT 100 #endif /* @@ -94,7 +94,7 @@ #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions @@ -109,12 +109,12 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; - for (i= 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i= 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -139,7 +139,7 @@ flash_init (void) * Remap FLASH according to real size */ memctl->memc_or0 |= (-size_b0 & 0xFFFF8000); - memctl->memc_br0 |= (CFG_FLASH_BASE & BR_BA_MSK); + memctl->memc_br0 |= (CONFIG_SYS_FLASH_BASE & BR_BA_MSK); PRINTF("## After remap:\n" " BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); @@ -147,27 +147,27 @@ flash_init (void) /* * Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((vu_char *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size ((vu_char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b0; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* * Monitor protection is ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* * Environment protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif @@ -307,10 +307,10 @@ ulong flash_get_size (vu_char *addr, flash_info_t *info) return (NO_FLASH); } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } return (info->size); } @@ -385,7 +385,7 @@ flash_erase(flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = SCS_BLOCK_ERASE_SUSPEND_CMD; *addr = SCS_READ_CMD; @@ -408,7 +408,7 @@ flash_erase(flash_info_t *info, int s_first, int s_last) } -#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER +#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER /* * Allocate a flash buffer, fill it with data and write it to the flash. * 0 - OK @@ -451,10 +451,10 @@ write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, */ *block_addr_p = SCS_WRITE_BUF_CMD; while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) { - if (get_timer(time) > CFG_FLASH_ALLOC_BUFFER_TOUT) { + if (get_timer(time) > CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT) { PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n", __FUNCTION__, __LINE__, block_addr_p, - CFG_FLASH_ALLOC_BUFFER_TOUT); + CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT); return 1; } *block_addr_p = SCS_WRITE_BUF_CMD; @@ -478,9 +478,9 @@ write_flash_buffer8(flash_info_t *info_p, vu_char *src_p, vu_char *dest_p, #if 1 time = get_timer(0); while ((*block_addr_p & SCS_SR7) != SCS_SR7) { - if (get_timer(time) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(time) > CONFIG_SYS_FLASH_WRITE_TOUT) { PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n", - __FUNCTION__, __LINE__, block_addr_p, CFG_FLASH_WRITE_TOUT); + __FUNCTION__, __LINE__, block_addr_p, CONFIG_SYS_FLASH_WRITE_TOUT); return 1; } } @@ -502,7 +502,7 @@ int write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count) { int rc = 0; -#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER +#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER #define FLASH_WRITE_BUF_SIZE 0x00000020 /* 32 bytes */ int i; uint bufs; @@ -520,7 +520,7 @@ write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count) return 4; } -#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER +#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER sp = src_p; dp = (uchar *)addr; @@ -632,7 +632,7 @@ write_data8 (flash_info_t *info, ulong dest, uchar data) start = get_timer (0); while (((status = *addr) & SCS_SR7) != SCS_SR7) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = SCS_READ_CMD; return (1); } diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 1e6bdf1cc..29cad2ee8 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -161,7 +161,7 @@ int test_fpga_ibtr (void) */ void fpga_reset (int assert) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); if (assert) { @@ -210,7 +210,7 @@ int gen860t_init_fpga (void) */ int fpga_pgm_fn (int assert, int flush, int cookie) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); @@ -233,7 +233,7 @@ int fpga_pgm_fn (int assert, int flush, int cookie) */ int fpga_init_fn (int cookie) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { @@ -251,7 +251,7 @@ int fpga_init_fn (int cookie) */ int fpga_done_fn (int cookie) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index e3d0e435d..008f765af 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -160,7 +160,7 @@ int checkboard (void) */ phys_size_t initdram (int board_type) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; upmconfig (UPMA, @@ -171,14 +171,14 @@ phys_size_t initdram (int board_type) /* * Setup MAMR register */ - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ /* * Map CS1* to SDRAM bank */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; + memctl->memc_or1 = CONFIG_SYS_OR1; + memctl->memc_br1 = CONFIG_SYS_BR1; /* * Perform SDRAM initialization sequence: @@ -223,8 +223,6 @@ phys_size_t initdram (int board_type) * The DOC lives in the CS2* space */ #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); - void doc_init (void) { printf ("Probing at 0x%.8x: ", DOC_BASE); @@ -237,7 +235,7 @@ void doc_init (void) */ int misc_init_r (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; /* diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index bb03d3aac..6c8346ab5 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -125,6 +125,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; @@ -133,6 +134,6 @@ SECTIONS .ppcenv: { . = env_offset; - common/environment.o + common/env_embedded.o } } diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index d33aa2ea1..cab7a1024 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -126,6 +126,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/genietv/flash.c b/board/genietv/flash.c index 7292c9c12..5313ad8b0 100644 --- a/board/genietv/flash.c +++ b/board/genietv/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -42,20 +42,20 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; /* Detect size */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* Setup offsets */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif @@ -322,7 +322,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr[0] & 0xFF) != 0xFF) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -454,7 +454,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c index fc2116967..0a015ea2d 100644 --- a/board/genietv/genietv.c +++ b/board/genietv/genietv.c @@ -29,7 +29,7 @@ #include <common.h> #include <mpc8xx.h> -#define CFG_PA7 0x0100 +#define CONFIG_SYS_PA7 0x0100 /* ------------------------------------------------------------------------- */ @@ -104,7 +104,7 @@ int checkboard (void) #if 0 static void PrintState (void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &im->im_memctl; printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, @@ -120,18 +120,18 @@ static void PrintState (void) phys_size_t initdram (int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &im->im_memctl; long int size_b0, size_b1, size8; /* Enable SDRAM */ /* Configuring PA7 for general purpouse output pin */ - im->im_ioport.iop_papar &= ~CFG_PA7; /* 0 = general purpouse */ - im->im_ioport.iop_padir |= CFG_PA7; /* 1 = output */ + im->im_ioport.iop_papar &= ~CONFIG_SYS_PA7; /* 0 = general purpouse */ + im->im_ioport.iop_padir |= CONFIG_SYS_PA7; /* 1 = output */ /* Enable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat |= CFG_PA7; /* value of PA7 */ + im->im_ioport.iop_padat |= CONFIG_SYS_PA7; /* value of PA7 */ /* * Preliminary prescaler for refresh (depends on number of @@ -139,9 +139,9 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; - memctl->memc_mbmr = CFG_MBMR_8COL; + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; upmconfig (UPMB, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); @@ -152,11 +152,11 @@ phys_size_t initdram (int board_type) * SDRAM size has been determined. */ - memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM; + memctl->memc_or1 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); - memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM; + memctl->memc_or2 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V); @@ -168,14 +168,14 @@ phys_size_t initdram (int board_type) memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */ /* Execute refresh 8 times */ - memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; + memctl->memc_mbmr = (CONFIG_SYS_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X; memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */ memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */ /* Execute refresh 4 times */ - memctl->memc_mbmr = CFG_MBMR_8COL; + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* * Check Bank 0 Memory Size for re-configuration @@ -187,7 +187,7 @@ phys_size_t initdram (int board_type) PrintState (); #endif /* printf ("\nChecking bank1..."); */ - size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, + size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); size_b0 = size8; @@ -201,17 +201,17 @@ phys_size_t initdram (int board_type) * Final mapping: map bigger bank first */ - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; if (size_b1 > 0) { /* * Position Bank 1 immediately above Bank 0 */ memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) + (size_b0 & BR_BA_MSK); } else { /* @@ -221,14 +221,14 @@ phys_size_t initdram (int board_type) */ memctl->memc_br2 = 0; /* adjust refresh rate depending on SDRAM type, one bank */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; } /* If no memory detected, disable SDRAM */ if ((size_b0 + size_b1) == 0) { printf ("disabling SDRAM!\n"); /* Disable SDRAM - PA7 = 1 */ - im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */ + im->im_ioport.iop_padat &= ~CONFIG_SYS_PA7; /* value of PA7 */ } /* else */ /* printf("done! (%08lx)\n", size_b0 + size_b1); */ @@ -269,8 +269,8 @@ static long int dram_size (long int mbmr_value, long int *base, #if defined(CONFIG_CMD_PCMCIA) -#ifdef CFG_PCMCIA_MEM_ADDR -volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR; +#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR +volatile unsigned char *pcmcia_mem = (unsigned char *) CONFIG_SYS_PCMCIA_MEM_ADDR; #endif int pcmcia_init (void) @@ -281,10 +281,10 @@ int pcmcia_init (void) /* ** Enable the PCMCIA for a Flash card. */ - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); #if 0 - pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR; + pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR; pcmp->pcmc_por0 = 0xc00ff05d; #endif diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 3573608d2..3c19d19ab 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -137,8 +137,9 @@ SECTIONS . = ALIGN(256 * 1024); .ppcenv : { - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) } + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index 8dedba814..61fdfe53e 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -135,7 +135,7 @@ SECTIONS . = ALIGN(256 * 1024); .ppcenv : { - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) } _end = . ; PROVIDE (end = .); diff --git a/board/gth/ee_access.c b/board/gth/ee_access.c index 716c90ed6..2a33a0edd 100644 --- a/board/gth/ee_access.c +++ b/board/gth/ee_access.c @@ -152,7 +152,7 @@ read_byte(void){ int i; int Value; u8 Result=0; -#ifndef CFG_IMMR +#ifndef CONFIG_SYS_IMMR u32 Flags; #endif @@ -162,7 +162,7 @@ read_byte(void){ /* Small delay between pulses */ udelay(1); -#ifndef CFG_IMMR +#ifndef CONFIG_SYS_IMMR /* Disable irq */ save_flags(Flags); cli(); @@ -182,7 +182,7 @@ read_byte(void){ if(Value) Value=1; -#ifndef CFG_IMMR +#ifndef CONFIG_SYS_IMMR /* Enable irq */ restore_flags(Flags); #endif @@ -205,7 +205,7 @@ write_byte(u8 Byte){ Write LSb first */ int i; int Value; -#ifndef CFG_IMMR +#ifndef CONFIG_SYS_IMMR u32 Flags; #endif @@ -216,7 +216,7 @@ write_byte(u8 Byte){ udelay(1); Value = Byte&1; -#ifndef CFG_IMMR +#ifndef CONFIG_SYS_IMMR /* Disable irq */ save_flags(Flags); cli(); @@ -237,7 +237,7 @@ write_byte(u8 Byte){ WRITE_PORT(1); -#ifndef CFG_IMMR +#ifndef CONFIG_SYS_IMMR /* Enable irq */ restore_flags(Flags); #endif @@ -289,7 +289,7 @@ int ee_init_data(void){ int i; u8 Tx[10]; int tmp; - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; while(0){ tmp = 1-tmp; diff --git a/board/gth/ee_dev.h b/board/gth/ee_dev.h index 417c7b675..3004b4661 100644 --- a/board/gth/ee_dev.h +++ b/board/gth/ee_dev.h @@ -9,10 +9,10 @@ #define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args) -#define PORT_B_PAR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbpar -#define PORT_B_ODR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbodr -#define PORT_B_DIR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdir -#define PORT_B_DAT ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat +#define PORT_B_PAR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar +#define PORT_B_ODR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr +#define PORT_B_DIR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir +#define PORT_B_DAT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat #define SET_PORT_B_INPUT(Mask) PORT_B_DIR &= ~(Mask) #define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask diff --git a/board/gth/flash.c b/board/gth/flash.c index 11e105e58..169270be1 100644 --- a/board/gth/flash.c +++ b/board/gth/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -44,7 +44,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; @@ -54,7 +54,7 @@ unsigned long flash_init (void) return(0x1fffff); /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -90,45 +90,45 @@ unsigned long flash_init (void) size_b1 = 0; /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR0_PRELIM; - memctl->memc_br0 = CFG_BR0_PRELIM; + memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM; + memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif if (size_b1) { - /* memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; */ + /* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif } else { -/* memctl->memc_or1 = CFG_OR1_PRELIM; - FIXME memctl->memc_br1 = CFG_BR1_PRELIM; */ +/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + FIXME memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ flash_info[1].flash_id = FLASH_UNKNOWN; flash_info[1].sector_count = -1; @@ -501,7 +501,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) #endif { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -638,7 +638,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) #endif { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/gth/gth.c b/board/gth/gth.c index 788a6a094..4399db2d5 100644 --- a/board/gth/gth.c +++ b/board/gth/gth.c @@ -38,7 +38,7 @@ int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; int Id = 0; int Rev = 0; u32 Pbdat; @@ -162,7 +162,7 @@ const uint fpga_table[] = { int _initsdram (uint base, uint * noMbytes) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *mc = &immap->im_memctl; volatile u32 *memptr; @@ -235,7 +235,7 @@ int _initsdram (uint base, uint * noMbytes) void _sdramdisable (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_br1 = 0x00000000; @@ -345,7 +345,7 @@ do \ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) { u16 data; - volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); + volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE); if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) { printf ("Invalid system data %u, setting failsafe\n", System); @@ -376,12 +376,12 @@ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) static void maybe_update_restart_reason (volatile u32 * addr32) { /* Update addr if sw wd restart */ - volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); + volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE); volatile u16 *addr_16 = (u16 *) addr32; u32 rsr; /* Dont reset register now */ - rsr = ((volatile immap_t *) CFG_IMMR)->im_clkrst.car_rsr; + rsr = ((volatile immap_t *) CONFIG_SYS_IMMR)->im_clkrst.car_rsr; rsr >>= 24; @@ -419,7 +419,7 @@ static void check_restart_reason (void) int i; volatile u32 *raddr; - raddr = (u32 *) (CFG_FLASH_BASE + POWER_OFFSET); + raddr = (u32 *) (CONFIG_SYS_FLASH_BASE + POWER_OFFSET); if (*raddr == 0xFFFFFFFF) { /* Nothing written */ @@ -456,7 +456,7 @@ static void check_boot_tries (void) u8 system; u8 count; - addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET); + addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET); if (*addr == 0xFFFF) { printf ("*** No bootdata exists. ***\n"); @@ -528,7 +528,7 @@ int misc_init_r (void) u8 Tx[5]; int page; int read = 0; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* Kill fpga */ immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE); diff --git a/board/gth/pcmcia.c b/board/gth/pcmcia.c index cffcbde89..a4db16d0c 100644 --- a/board/gth/pcmcia.c +++ b/board/gth/pcmcia.c @@ -31,10 +31,10 @@ int pcmcia_hardware_enable (int slot) debug ("hardware_enable: GTH Slot %c\n", 'A' + slot); - immap = (immap_t *) CFG_IMMR; - sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); + immap = (immap_t *) CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm)); /* clear interrupt state, and disable interrupts */ pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds index 95f94454d..d5df1f4f4 100644 --- a/board/gth/u-boot.lds +++ b/board/gth/u-boot.lds @@ -54,7 +54,7 @@ SECTIONS { cpu/mpc8xx/start.o(.text) *(.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.fixup) *(.got1) } @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/gth2/flash.c b/board/gth2/flash.c index f96edffa2..1b3c43c43 100644 --- a/board/gth2/flash.c +++ b/board/gth2/flash.c @@ -23,7 +23,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * flash_init() diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index cea65c677..59873d5ef 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -154,19 +154,19 @@ int checkboard (void) We need to map it into a 32 bit addresses */ write_one_tlb(20, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_IO_BASE, /* Hi */ + CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ 0x3C000017, /* Lo0 */ 0x3C200017); /* Lo1 */ write_one_tlb(21, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_ATTR_BASE, /* Hi */ + CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ 0x3D000017, /* Lo0 */ 0x3D200017); /* Lo1 */ write_one_tlb(22, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_MEM_ADDR, /* Hi */ + CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ 0x3E000017, /* Lo0 */ 0x3E200017); /* Lo1 */ @@ -209,7 +209,7 @@ do \ static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) { u16 data; - volatile u16 *flash = (u16 *) (CFG_FLASH_BASE); + volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE); switch(System){ case FAILSAFE_BOOT: @@ -302,7 +302,7 @@ static void check_boot_tries (void) u8 system = FAILSAFE_BOOT; u8 count; - addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET); + addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET); if (*addr == 0xFFFF) { printf ("*** No bootdata exists. ***\n"); diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S index 4c4f0ebd2..bc31c0053 100644 --- a/board/gth2/lowlevel_init.S +++ b/board/gth2/lowlevel_init.S @@ -6,7 +6,7 @@ #include <asm/mipsregs.h> #define CP0_Config0 $16 -#define MEM_1MS ((CFG_MHZ) * 1000) +#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000) #define GPIO_RJ1LY (1<<22) #define GPIO_CFRESET (1<<10) diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index 8265130ff..05946434a 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -65,6 +65,6 @@ SECTIONS . = ALIGN(4); .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } uboot_end = .; } diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c index 5620a1d8b..6035f6976 100644 --- a/board/gw8260/flash.c +++ b/board/gw8260/flash.c @@ -54,7 +54,7 @@ #include <common.h> #include <mpc8260.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static ulong flash_get_size (vu_long *addr, flash_info_t *info); static int write_word (flash_info_t *info, ulong dest, ulong data); @@ -82,35 +82,35 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); /* * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif - return (CFG_FLASH0_SIZE * 1024 * 1024); /*size*/ + return (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); /*size*/ } /*********************************************************************/ @@ -357,7 +357,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -512,7 +512,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c index 42c9e0d10..28f5ca99e 100644 --- a/board/gw8260/gw8260.c +++ b/board/gw8260/gw8260.c @@ -226,7 +226,7 @@ int checkboard (void) } -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ /* */ @@ -256,7 +256,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaULL, @@ -319,7 +319,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_SDRAM_BASE; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -346,9 +346,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -373,8 +373,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_SDRAM_BASE; - const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4; + (volatile unsigned int *) CONFIG_SYS_SDRAM_BASE; + const unsigned int size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 4; unsigned int i; /* write address to each location */ @@ -391,9 +391,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -451,7 +451,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -483,8 +483,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_SDRAM_BASE; - const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8; + (volatile unsigned long long *) CONFIG_SYS_SDRAM_BASE; + const unsigned long size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 8; unsigned int i; @@ -557,21 +557,21 @@ int testdram (void) if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) { printf ("Testing RAM ... "); } -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { if (mem_test_data () == 1) { return 1; } } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { if (mem_test_address () == 1) { return 1; } } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { if (mem_test_walk () == 1) { return 1; @@ -584,7 +584,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /*********************************************************************/ /* NAME: initdram() - initializes SDRAM controller */ @@ -593,11 +593,11 @@ int testdram (void) /* Initializes the MPC8260's SDRAM controller. */ /* */ /* INPUTS: */ -/* CFG_IMMR - MPC8260 Internal memory map */ -/* CFG_SDRAM_BASE - Physical start address of SDRAM */ -/* CFG_PSDMR - SDRAM mode register */ -/* CFG_MPTPR - Memory refresh timer prescaler register */ -/* CFG_SDRAM0_SIZE - SDRAM size */ +/* CONFIG_SYS_IMMR - MPC8260 Internal memory map */ +/* CONFIG_SYS_SDRAM_BASE - Physical start address of SDRAM */ +/* CONFIG_SYS_PSDMR - SDRAM mode register */ +/* CONFIG_SYS_MPTPR - Memory refresh timer prescaler register */ +/* CONFIG_SYS_SDRAM0_SIZE - SDRAM size */ /* */ /* RETURNS: */ /* SDRAM size in bytes */ @@ -608,10 +608,10 @@ int testdram (void) /*********************************************************************/ phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); - ulong psdmr = CFG_PSDMR; + volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); + ulong psdmr = CONFIG_SYS_PSDMR; int i; /* @@ -631,11 +631,11 @@ phys_size_t initdram (int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; @@ -651,7 +651,7 @@ phys_size_t initdram (int board_type) *ramaddr = c; /* return total ram size */ - return (CFG_SDRAM0_SIZE * 1024 * 1024); + return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024); } /*********************************************************************/ diff --git a/board/hermes/flash.c b/board/hermes/flash.c index 799fe83f3..888231c5f 100644 --- a/board/hermes/flash.c +++ b/board/hermes/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -58,20 +58,20 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif @@ -376,7 +376,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_char*)(info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -449,7 +449,7 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c index f9b57204f..9a3e5f669 100644 --- a/board/hermes/hermes.c +++ b/board/hermes/hermes.c @@ -136,7 +136,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size, size8, size9; @@ -153,8 +153,8 @@ phys_size_t initdram (int board_type) /* * Map controller banks 1 to the SDRAM banks at preliminary address */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; /* HERMES-PRO boards have only one bank SDRAM */ @@ -179,7 +179,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -187,7 +187,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -195,7 +195,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -203,7 +203,7 @@ phys_size_t initdram (int board_type) udelay (1000); memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; udelay (10000); @@ -223,7 +223,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -264,7 +264,7 @@ static long int dram_size (long int mamr_value, long int *base, static ulong board_init (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ulong reg, revision, speed = 100; int ethspeed; char *s; @@ -403,7 +403,7 @@ static ulong board_init (void) */ void hermes_start_lxt980 (int speed) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm); volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]); volatile cbd_t *bd; @@ -595,7 +595,7 @@ static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd, void show_boot_progress (int status) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; if (status < -32) status = -1; /* let things compatible */ status ^= 0x0F; diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index 5f5fb0d58..540e614fc 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_ppc/cache.o (.text) lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 41d603f7e..78456e6d8 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_ppc/time.o (.text) lib_ppc/ticks.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S index 07dafb716..531dcdf4a 100644 --- a/board/hidden_dragon/early_init.S +++ b/board/hidden_dragon/early_init.S @@ -32,68 +32,68 @@ #if defined(USE_DINK32) /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) + #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) #else - #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) + #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) #endif .text /* Values to program into memory controller registers */ tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT + .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT .long MCCR3 - .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ - (CFG_RDLAT << MCCR3_RDLAT_SHIFT) + .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ + (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \ + (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT) .long MCCR4 - .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CFG_REGISTERD_TYPE_BUFFER << 20) | \ - (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ - (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) + .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ + (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \ + (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ + ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \ + (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ + (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ + ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) .long MSAR1 - .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMSAR1 - .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MSAR2 - .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMSAR2 - .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MEAR1 - .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMEAR1 - .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MEAR2 - .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMEAR2 - .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long 0 @@ -123,7 +123,7 @@ loop: lwz r1, 4(r5) /* set bank enable bits */ lis r0, MBER@h ori r0, 0, MBER@l - li r1, CFG_BANK_ENABLE + li r1, CONFIG_SYS_BANK_ENABLE stwbrx r0, 0, r3 eieio stb r1, 0(r4) @@ -145,8 +145,8 @@ delay: bdnz delay eieio /* set up stack pointer */ - lis r1, CFG_INIT_SP_OFFSET@h - ori r1, r1, CFG_INIT_SP_OFFSET@l + lis r1, CONFIG_SYS_INIT_SP_OFFSET@h + ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l mtlr r10 blr diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c index 21c5a01c1..2ce1dc4fb 100644 --- a/board/hidden_dragon/flash.c +++ b/board/hidden_dragon/flash.c @@ -33,17 +33,17 @@ #define ROM_CS0_START 0xFF800000 #define ROM_CS1_START 0xFF000000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -120,10 +120,10 @@ unsigned long flash_init (void) { unsigned long i; unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; + static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info_t *const pflinfo = &flash_info[i]; pflinfo->flash_id = FLASH_UNKNOWN; @@ -135,10 +135,10 @@ unsigned long flash_init (void) { register unsigned char temp; - CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, + CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, + CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); } @@ -205,17 +205,17 @@ unsigned long flash_init (void) } /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -426,7 +426,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) start[0]) << sh8b)); while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -565,7 +565,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c index 5713a3384..027aa457f 100644 --- a/board/hidden_dragon/hidden_dragon.c +++ b/board/hidden_dragon/hidden_dragon.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc824x.h> #include <pci.h> +#include <netdev.h> int checkboard (void) { @@ -51,7 +52,7 @@ phys_size_t initdram (int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -93,3 +94,8 @@ void pci_init_board(void) { pci_mpc824x_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c index 8cfd75bd8..9cbed4b8c 100644 --- a/board/hmi1001/hmi1001.c +++ b/board/hmi1001/hmi1001.c @@ -33,7 +33,7 @@ #include <asm/processor.h> #include <malloc.h> -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -76,14 +76,14 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; uint svr, pvr; @@ -105,9 +105,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -129,7 +129,7 @@ phys_size_t initdram (int board_type) } *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -147,7 +147,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -193,8 +193,8 @@ struct kbd_data_t { struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) { - kbd_data->s1 = *((volatile uchar*)(CFG_STATUS1_BASE)); - kbd_data->s2 = *((volatile uchar*)(CFG_STATUS2_BASE)); + kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE)); + kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE)); return kbd_data; } @@ -300,9 +300,9 @@ int board_early_init_r (void) { *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); + *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); return 0; } #ifdef CONFIG_PCI diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c index 12f140201..1848bb3fc 100644 --- a/board/hymod/bsp.c +++ b/board/hymod/bsp.c @@ -304,7 +304,7 @@ int do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { uchar data[HYMOD_EEPROM_SIZE]; - uint addr = CFG_I2C_EEPROM_ADDR; + uint addr = CONFIG_SYS_I2C_EEPROM_ADDR; switch (argc) { diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c index c9b9b1811..4d48d7dbb 100644 --- a/board/hymod/eeprom.c +++ b/board/hymod/eeprom.c @@ -36,7 +36,7 @@ static char *def_bddb_cfgdir = "/hymod/bddb"; static int hymod_eeprom_load (int which, hymod_eeprom_t *ep) { - unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ + unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); unsigned offset = 0; uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp; @@ -466,7 +466,7 @@ eerec_callback (uchar *name, uchar *val) static int hymod_eeprom_fetch(int which, char *filename, ulong addr) { - unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ + unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0]; ulong crc; @@ -635,7 +635,7 @@ int hymod_eeprom_read (int which, hymod_eeprom_t *ep) { char *label = which ? "mezzanine" : "main"; - unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \ + unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \ (which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN); char filename[50], prompt[50], *dir; int serno, count = 0, rc; @@ -682,7 +682,7 @@ hymod_eeprom_read (int which, hymod_eeprom_t *ep) printf ("*** fetching %s board EEPROM contents from server\n", label); - rc = hymod_eeprom_fetch (which, filename, CFG_LOAD_ADDR); + rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR); if (rc == 0) { puts ("*** fetch failed - ignoring eeprom contents\n"); diff --git a/board/hymod/env.c b/board/hymod/env.c index 062553bfa..c0e2cd5d6 100644 --- a/board/hymod/env.c +++ b/board/hymod/env.c @@ -35,7 +35,7 @@ static int env_callback (uchar *name, uchar *value) { hymod_conf_t *cp = &gd->bd->bi_hymod_conf; - char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver; + char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver; int override = 1, append = 0, remove = 0, nnl, ovl, nvl; nn = (char *)name; @@ -205,7 +205,7 @@ hymod_check_env (void) if ((path = getenv ("global_env_path")) == NULL || *path == '\0') path = def_global_env_path; - if (fetch_and_parse (path, CFG_LOAD_ADDR, env_callback) == 0) { + if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) { puts ("*** Fetch of global environment failed!\n"); return; } diff --git a/board/hymod/flash.c b/board/hymod/flash.c index ad0a229d9..e2cf38c8e 100644 --- a/board/hymod/flash.c +++ b/board/hymod/flash.c @@ -27,7 +27,7 @@ #include <mpc8260.h> #include <board/hymod/flash.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Protection Flags: @@ -95,7 +95,7 @@ bank_probe (flash_info_t *fip, volatile bank_addr_t base) (unsigned long)word, (unsigned long)base); } - if (fip->sector_count >= CFG_MAX_FLASH_SECT) + if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT) panic ("\ntoo many sectors (%d) in flash at address 0x%08lx", fip->sector_count, (unsigned long)base); @@ -198,7 +198,7 @@ bank_write_word (volatile bank_addr_t addr, bank_word_t value) /* data polling for D7 */ start = get_timer (0); do { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { retval = 1; goto done; } @@ -228,30 +228,30 @@ flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - bank_probe (&flash_info[0], (bank_addr_t)CFG_FLASH_BASE); + bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE); /* * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE == CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE (void)flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#if defined(CFG_FLASH_ENV_ADDR) +#if defined(CONFIG_SYS_FLASH_ENV_ADDR) (void)flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_ENV_ADDR, -#if defined(CFG_FLASH_ENV_BUF) - CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_BUF - 1, + CONFIG_SYS_FLASH_ENV_ADDR, +#if defined(CONFIG_SYS_FLASH_ENV_BUF) + CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1, #else - CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_SIZE - 1, + CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1, #endif &flash_info[0]); #endif @@ -368,7 +368,7 @@ flash_erase (flash_info_t *info, int s_first, int s_last) do { now = get_timer (start); - if (now - estart > CFG_FLASH_ERASE_TOUT) { + if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (sect %d)\n", sect); haderr = 1; rcode = 1; diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c index 91aaab1b0..2af304989 100644 --- a/board/hymod/hymod.c +++ b/board/hymod/hymod.c @@ -255,7 +255,7 @@ uchar fs6377_regs[16] = { int board_postclk_init (void) { - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* * Initialise the FS6377 clock chip @@ -347,16 +347,16 @@ uint upmc_table[] = { int misc_init_f (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; printf ("UPMs: "); upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]); - memctl->memc_mbmr = CFG_MBMR; + memctl->memc_mbmr = CONFIG_SYS_MBMR; upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]); - memctl->memc_mcmr = CFG_MCMR; + memctl->memc_mcmr = CONFIG_SYS_MCMR; printf ("configured\n"); return (0); @@ -367,10 +367,10 @@ misc_init_f (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); - ulong psdmr = CFG_PSDMR; + volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); + ulong psdmr = CONFIG_SYS_PSDMR; int i; /* @@ -390,11 +390,11 @@ initdram (int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; @@ -409,7 +409,7 @@ initdram (int board_type) memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN; *ramaddr = c; - return (CFG_SDRAM_SIZE << 20); + return (CONFIG_SYS_SDRAM_SIZE << 20); } /* ------------------------------------------------------------------------- */ @@ -517,18 +517,18 @@ last_stage_init (void) #ifdef CONFIG_SHOW_ACTIVITY void board_show_activity (ulong timebase) { -#ifdef CFG_HYMOD_DBLEDS - volatile immap_t *immr = (immap_t *) CFG_IMMR; +#ifdef CONFIG_SYS_HYMOD_DBLEDS + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile iop8260_t *iop = &immr->im_ioport; static int shift = 0; - if ((timestamp % CFG_HZ) == 0) { + if ((timestamp % CONFIG_SYS_HZ) == 0) { if (++shift > 3) shift = 0; iop->iop_pdatd = (iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift)); } -#endif /* CFG_HYMOD_DBLEDS */ +#endif /* CONFIG_SYS_HYMOD_DBLEDS */ } void show_activity(int arg) diff --git a/board/hymod/input.c b/board/hymod/input.c index 63aa13c4a..998132d65 100644 --- a/board/hymod/input.c +++ b/board/hymod/input.c @@ -24,7 +24,7 @@ #include <common.h> /* imports from common/main.c */ -extern char console_buffer[CFG_CBSIZE]; +extern char console_buffer[CONFIG_SYS_CBSIZE]; int hymod_get_serno (const char *prompt) diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index cb7b4ea06..fdd584dd8 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -140,8 +140,9 @@ SECTIONS . = ALIGN(256 * 1024); .ppcenv : { - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) } + . = ALIGN(4); _end = . ; PROVIDE (end = .); } diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index c33581d25..ea8538900 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/icecube/flash.c b/board/icecube/flash.c index 2d4026a9d..7a433b3a3 100644 --- a/board/icecube/flash.c +++ b/board/icecube/flash.c @@ -24,7 +24,7 @@ #include <common.h> #ifndef CONFIG_FLASH_CFI_DRIVER -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -66,12 +66,12 @@ unsigned long flash_init (void) int i; extern void flash_preinit(void); extern void flash_afterinit(ulong); - ulong flashbase = CFG_FLASH_BASE; + ulong flashbase = CONFIG_SYS_FLASH_BASE; flash_preinit(); /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { memset(&flash_info[i], 0, sizeof(flash_info_t)); flash_info[i].size = @@ -80,20 +80,20 @@ unsigned long flash_init (void) size += flash_info[i].size; flashbase += 0x800000; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif @@ -122,14 +122,14 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->size && info->start[0] <= base && base <= info->start[0] + info->size - 1) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -360,7 +360,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -374,14 +374,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ putc ('.'); last = get_timer(0); } } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = get_timer(0); } @@ -482,7 +482,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00F000F0; /* reset bank */ res = 1; } diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 760db7368..75244610c 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -29,6 +29,7 @@ #include <pci.h> #include <asm/processor.h> #include <libfdt.h> +#include <netdev.h> #if defined(CONFIG_LITE5200B) #include "mt46v32m16.h" @@ -86,7 +87,7 @@ void lite5200b_wakeup(void) #define lite5200b_wakeup() #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -129,7 +130,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -140,7 +141,7 @@ phys_size_t initdram (int board_type) ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -161,9 +162,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -189,10 +190,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -214,7 +215,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -232,7 +233,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -262,7 +263,7 @@ phys_size_t initdram (int board_type) phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup and enable SDRAM chip selects */ @@ -281,9 +282,9 @@ phys_size_t initdram (int board_type) /* find RAM size */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -294,12 +295,12 @@ phys_size_t initdram (int board_type) /* set SDRAM end address according to size */ *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* Retrieve amount of SDRAM available */ dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize; } @@ -339,9 +340,9 @@ void flash_afterinit(ulong size) { if (size == 0x800000) { /* adjust mapping */ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } @@ -390,3 +391,9 @@ ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); } #endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +} diff --git a/board/icu862/flash.c b/board/icu862/flash.c index ca5bcf31a..2afeff4b5 100644 --- a/board/icu862/flash.c +++ b/board/icu862/flash.c @@ -24,17 +24,17 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -50,13 +50,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -92,27 +92,27 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif @@ -468,7 +468,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) #endif { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { puts ("Timeout\n"); return 1; } @@ -606,7 +606,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) #endif { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c index 18aa8bf6d..b99d256c8 100644 --- a/board/icu862/icu862.c +++ b/board/icu862/icu862.c @@ -96,7 +96,7 @@ static long int dram_size (long int, long int *, long int); phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size_b0 = 0; @@ -111,7 +111,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -120,10 +120,10 @@ phys_size_t initdram (int board_type) * preliminary address - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -143,7 +143,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -151,7 +151,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -159,7 +159,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -172,7 +172,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -180,12 +180,12 @@ phys_size_t initdram (int board_type) * Final mapping */ - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; udelay (10000); @@ -206,7 +206,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c index 20922d8a4..a4c0b54bc 100644 --- a/board/icu862/pcmcia.c +++ b/board/icu862/pcmcia.c @@ -22,8 +22,8 @@ static void cfg_port_B (void) volatile cpm8xx_t *cp; uint reg; - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure Port B for TPS2205 PC-Card Power-Interface Switch @@ -58,10 +58,10 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Port B for TPS2205 PC-Card Power-Interface Switch */ cfg_port_B (); @@ -165,9 +165,9 @@ int pcmcia_hardware_disable(int slot) debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* Shut down */ cp->cp_pbdat &= ~(TPS2205_SHDN); @@ -198,9 +198,9 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) * and assert RESET signal diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index be4bf7278..645baa0ed 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) */ *(.text) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 7a7a40c23..dbd1f9d10 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/idmr/Makefile b/board/idmr/Makefile index be704b76f..cf07cf40f 100644 --- a/board/idmr/Makefile +++ b/board/idmr/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o mii.o +COBJS = $(BOARD).o flash.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/idmr/flash.c b/board/idmr/flash.c index 33512b894..57c994863 100644 --- a/board/idmr/flash.c +++ b/board/idmr/flash.c @@ -23,11 +23,11 @@ #include <common.h> -#define PHYS_FLASH_1 CFG_FLASH_BASE +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE #define FLASH_BANK_SIZE 0x800000 #define EN29LV640 0x227e227e -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; void flash_print_info (flash_info_t * info) { @@ -75,15 +75,15 @@ unsigned long flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | (EN29LV640 & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -96,8 +96,8 @@ unsigned long flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x2ffff, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]); return size; } @@ -111,8 +111,8 @@ unsigned long flash_init (void) #define CMD_PROGRAM 0x00A0 #define CMD_UNLOCK_BYPASS 0x0020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1))) #define BIT_ERASE_DONE 0x0080 #define BIT_RDY_MASK 0x0080 @@ -191,7 +191,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -280,7 +280,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) { + if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) { chip1 = ERR | TMO; break; } diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c index 4f073fc31..682991379 100644 --- a/board/idmr/idmr.c +++ b/board/idmr/idmr.c @@ -35,7 +35,7 @@ phys_size_t initdram (int board_type) { /* * After reset, CS0 is configured to cover entire address space. We * need to configure it to its proper values, so that writes to - * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do + * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual). */ @@ -78,7 +78,7 @@ phys_size_t initdram (int board_type) { MCF_GPIO_SDRAM_SDCS_01); /* - * Wait 100us. We run the bus at 50Mhz, one cycle is 20ns. So 5 + * Wait 100us. We run the bus at 50MHz, one cycle is 20ns. So 5 * iterations will do, but we do 10 just to be safe. */ for (i = 0; i < 10; ++i) @@ -99,7 +99,7 @@ phys_size_t initdram (int board_type) { * PS: 16 bit */ mbar_writeLong(MCF_SDRAMC_DACR0, - MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) | + MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) | MCF_SDRAMC_DACRn_BA(0x00) | MCF_SDRAMC_DACRn_CASL(0x03) | MCF_SDRAMC_DACRn_CBM(0x03) | @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) { MCF_SDRAMC_DACRn_IP); /* Write to this block to initiate precharge */ - *(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5; + *(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5; /* * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We @@ -153,9 +153,9 @@ phys_size_t initdram (int board_type) { * Burst Type = Sequential * Burst Length = 1 */ - *(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; + *(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5; - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }; diff --git a/board/idmr/mii.c b/board/idmr/mii.c deleted file mode 100644 index 78a7028bc..000000000 --- a/board/idmr/mii.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fec.h> -#include <asm/immap.h> - -#include <config.h> -#include <net.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -#undef MII_DEBUG -#undef ET_DEBUG - -int fecpin_setclear(struct eth_device *dev, int setclear) -{ - if (setclear) { - /* Enable Ethernet pins */ - mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C); - } else { - } - - return 0; -} - -#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) -#include <miiphy.h> - -/* Make MII read/write commands for the FEC. */ -#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) - -#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) - -/* PHY identification */ -#define PHY_ID_LXT970 0x78100000 /* LXT970 */ -#define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */ -#define PHY_ID_82555 0x02a80150 /* Intel 82555 */ -#define PHY_ID_QS6612 0x01814400 /* QS6612 */ -#define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */ -#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */ -#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */ -#define PHY_ID_DP83848VV 0x20005C90 /* National 83848 */ -#define PHY_ID_DP83849 0x20005CA2 /* National 82849 */ -#define PHY_ID_KS8721BL 0x00221619 /* Micrel KS8721BL/SL */ - -#define STR_ID_LXT970 "LXT970" -#define STR_ID_LXT971 "LXT971" -#define STR_ID_82555 "Intel82555" -#define STR_ID_QS6612 "QS6612" -#define STR_ID_AMD79C784 "AMD79C784" -#define STR_ID_LSI80225 "LSI80225" -#define STR_ID_LSI80225B "LSI80225/B" -#define STR_ID_DP83848VV "N83848" -#define STR_ID_DP83849 "N83849" -#define STR_ID_KS8721BL "KS8721BL" - -/**************************************************************************** - * mii_init -- Initialize the MII for MII command without ethernet - * This function is a subset of eth_init - **************************************************************************** - */ -void mii_reset(struct fec_info_s *info) -{ - volatile fec_t *fecp = (fec_t *) (info->miibase); - int i; - - fecp->ecr = FEC_ECR_RESET; - for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { - udelay(1); - } - if (i == FEC_RESET_DELAY) { - printf("FEC_RESET_DELAY timeout\n"); - } -} - -/* send command to phy using mii, wait for result */ -uint mii_send(uint mii_cmd) -{ - struct fec_info_s *info; - struct eth_device *dev; - volatile fec_t *ep; - uint mii_reply; - int j = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - ep = (fec_t *) info->miibase; - - ep->mmfr = mii_cmd; /* command to phy */ - - /* wait for mii complete */ - while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { - udelay(1); - j++; - } - if (j >= MCFFEC_TOUT_LOOP) { - printf("MII not complete\n"); - return -1; - } - - mii_reply = ep->mmfr; /* result from phy */ - ep->eir = FEC_EIR_MII; /* clear MII complete */ -#ifdef ET_DEBUG - printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", - __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); -#endif - - return (mii_reply & 0xffff); /* data read from phy */ -} -#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */ - -#if defined(CFG_DISCOVER_PHY) -int mii_discover_phy(struct eth_device *dev) -{ -#define MAX_PHY_PASSES 11 - struct fec_info_s *info = dev->priv; - int phyaddr, pass; - uint phyno, phytype; - - if (info->phyname_init) - return info->phy_addr; - - phyaddr = -1; /* didn't find a PHY yet */ - for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { - if (pass > 1) { - /* PHY may need more time to recover from reset. - * The LXT970 needs 50ms typical, no maximum is - * specified, so wait 10ms before try again. - * With 11 passes this gives it 100ms to wake up. - */ - udelay(10000); /* wait 10ms */ - } - - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { - - phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); -#ifdef ET_DEBUG - printf("PHY type 0x%x pass %d type\n", phytype, pass); -#endif - if (phytype != 0xffff) { - phyaddr = phyno; - phytype <<= 16; - phytype |= - mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); - - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - strcpy(info->phy_name, - STR_ID_KS8721BL); - info->phyname_init = 1; - break; - default: - strcpy(info->phy_name, "unknown"); - info->phyname_init = 1; - break; - } - -#ifdef ET_DEBUG - printf("PHY @ 0x%x pass %d type ", phyno, pass); - switch (phytype & 0xffffffff) { - case PHY_ID_KS8721BL: - printf(STR_ID_KS8721BL); - break; - default: - printf("0x%08x\n", phytype); - break; - } -#endif - } - } - } - if (phyaddr < 0) - printf("No PHY device found.\n"); - - return phyaddr; -} -#endif /* CFG_DISCOVER_PHY */ - -void mii_init(void) __attribute__((weak,alias("__mii_init"))); - -void __mii_init(void) -{ - volatile fec_t *fecp; - struct fec_info_s *info; - struct eth_device *dev; - int miispd = 0, i = 0; - u16 autoneg = 0; - - /* retrieve from register structure */ - dev = eth_get_dev(); - info = dev->priv; - - fecp = (fec_t *) info->miibase; - - fecpin_setclear(dev, 1); - - mii_reset(info); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set MII speed */ - miispd = (gd->bus_clk / 1000000) / 5; - fecp->mscr = miispd << 1; - - info->phy_addr = mii_discover_phy(dev); - -#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) - while (i < MCFFEC_TOUT_LOOP) { - autoneg = 0; - miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); - i++; - - if ((autoneg & AUTONEGLINK) == AUTONEGLINK) - break; - - udelay(500); - } - if (i >= MCFFEC_TOUT_LOOP) { - printf("Auto Negotiation not complete\n"); - } - - /* adapt to the half/full speed settings */ - info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; - info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); -} - -/***************************************************************************** - * Read and write a MII PHY register, routines used by MII Utilities - * - * FIXME: These routines are expected to return 0 on success, but mii_send - * does _not_ return an error code. Maybe 0xFFFF means error, i.e. - * no PHY connected... - * For now always return 0. - * FIXME: These routines only work after calling eth_init() at least once! - * Otherwise they hang in mii_send() !!! Sorry! - *****************************************************************************/ - -int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); -#endif - rdreg = mii_send(mk_mii_read(addr, reg)); - - *value = rdreg; - -#ifdef MII_DEBUG - printf("0x%04x\n", *value); -#endif - - return 0; -} - -int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, - unsigned short value) -{ - short rdreg; /* register working value */ - -#ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); -#endif - - rdreg = mii_send(mk_mii_write(addr, reg, value)); - -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - - return 0; -} - -#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index c07d02383..0bc7fa1ab 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) diff --git a/board/ids8247/config.mk b/board/ids8247/config.mk index 136cdb864..2a7f3dd12 100644 --- a/board/ids8247/config.mk +++ b/board/ids8247/config.mk @@ -25,7 +25,7 @@ # IDS 8247 Board # -# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_IDS8247.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/ids8247/flash.c b/board/ids8247/flash.c index 4eba4b968..5107553c9 100644 --- a/board/ids8247/flash.c +++ b/board/ids8247/flash.c @@ -31,17 +31,17 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -84,16 +84,16 @@ unsigned long flash_init (void) { unsigned long size_b0; int i; - volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", @@ -105,19 +105,19 @@ unsigned long flash_init (void) flash_get_offsets (0xff800000, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -258,10 +258,10 @@ static ulong flash_get_size (FPWV * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -332,7 +332,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) udelay (1000); while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -472,7 +472,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) start = get_timer (0); while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c index 065014a11..68b70703f 100644 --- a/board/ids8247/ids8247.c +++ b/board/ids8247/ids8247.c @@ -254,7 +254,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -265,7 +265,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -278,7 +278,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; long psize, lsize; @@ -286,15 +286,15 @@ phys_size_t initdram (int board_type) psize = 16 * 1024 * 1024; lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - psize = try_init (memctl, CFG_PSDMR, CFG_OR2, - (uchar *) CFG_SDRAM_BASE); -#endif /* CFG_RAMBOOT */ + psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2, + (uchar *) CONFIG_SYS_SDRAM_BASE); +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -315,8 +315,8 @@ nand_init (void) { ulong totlen = 0; - debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE); - totlen += nand_probe (CFG_NAND0_BASE); + debug ("Probing at 0x%.8x\n", CONFIG_SYS_NAND0_BASE); + totlen += nand_probe (CONFIG_SYS_NAND0_BASE); printf ("%4lu MB\n", totlen >>20); } diff --git a/board/impa7/flash.c b/board/impa7/flash.c index ca76fe832..d0c5880b3 100644 --- a/board/impa7/flash.c +++ b/board/impa7/flash.c @@ -28,7 +28,7 @@ #define MAIN_SECT_SIZE 0x20000 #define PARAM_SECT_SIZE 0x4000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- @@ -39,15 +39,15 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F320B3T & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else if (i == 1) @@ -69,13 +69,13 @@ ulong flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -175,7 +175,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((*addr & 0x00800080) != 0x00800080) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B000B0; /* suspend erase */ *addr = 0x00FF00FF; /* reset to read mode */ rc = ERR_TIMOUT; @@ -243,7 +243,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) /* wait while polling the status register */ while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; /* suspend program command */ *addr = 0x00B000B0; diff --git a/board/impa7/u-boot.lds b/board/impa7/u-boot.lds index 4a89cebaa..a79bb8cb8 100644 --- a/board/impa7/u-boot.lds +++ b/board/impa7/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/imx31_litekit/u-boot.lds b/board/imx31_litekit/u-boot.lds index 1460adcdd..9285bd574 100644 --- a/board/imx31_litekit/u-boot.lds +++ b/board/imx31_litekit/u-boot.lds @@ -54,6 +54,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss : { *(.bss) } + .bss : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/imx31_phycore/u-boot.lds b/board/imx31_phycore/u-boot.lds index 1460adcdd..9285bd574 100644 --- a/board/imx31_phycore/u-boot.lds +++ b/board/imx31_phycore/u-boot.lds @@ -54,6 +54,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss : { *(.bss) } + .bss : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/incaip/flash.c b/board/incaip/flash.c index 520514dea..cc11e24fe 100644 --- a/board/incaip/flash.c +++ b/board/incaip/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/inca-ip.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -73,7 +73,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; ulong * buscon = (ulong *) ((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2); @@ -96,20 +96,20 @@ unsigned long flash_init (void) size += flash_info[i].size; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif @@ -173,13 +173,13 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->start[0] <= base && base < info->start[0] + info->size) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -484,7 +484,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -498,14 +498,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ putc ('.'); last = get_timer(0); } } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = get_timer(0); } @@ -609,7 +609,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00F000F0; /* reset bank */ res = 1; } @@ -655,7 +655,7 @@ static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) start = get_timer (0); while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00B000B0; /* Suspend program */ res = 1; } diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index ac7ad8f29..3b30970b9 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> +#include <netdev.h> #include <asm/addrspace.h> #include <asm/inca-ip.h> #include <asm/io.h> @@ -39,16 +40,16 @@ static ulong max_sdram_size(void) { /* The only supported SDRAM data width is 16bit. */ -#define CFG_DW 2 +#define CONFIG_SYS_DW 2 /* The only supported number of SDRAM banks is 4. */ -#define CFG_NB 4 +#define CONFIG_SYS_NB 4 ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; int cols = cfgpb0 & 0xF; int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; + ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB; return size; } @@ -74,7 +75,7 @@ phys_size_t initdram(int board_type) { *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) | (rows << 4) | cols; - size = get_ram_size((long *)CFG_SDRAM_BASE, + size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, max_sdram_size()); if (size > max_size) @@ -116,3 +117,10 @@ int checkboard (void) return 0; } + +#if defined(CONFIG_INCA_IP_SWITCH) +int board_eth_init(bd_t *bis) +{ + return inca_switch_initialize(bis); +} +#endif diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 1e1c5590d..da20de1ad 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -65,6 +65,6 @@ SECTIONS . = ALIGN(4); .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } uboot_end = .; } diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index a2e35ff0f..507196bb2 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -45,7 +45,7 @@ #error "INKA4x0 SDRAM: invalid chip type specified!" #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -88,14 +88,14 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long test1, test2; /* setup SDRAM chip selects */ @@ -116,9 +116,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -140,7 +140,7 @@ phys_size_t initdram (int board_type) } *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -149,7 +149,7 @@ phys_size_t initdram (int board_type) } else { dramsize = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize; } @@ -179,7 +179,7 @@ int misc_init_f (void) i = getenv_r("brightness", tmp, sizeof(tmp)); br = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) - : CFG_BRIGHTNESS; + : CONFIG_SYS_BRIGHTNESS; if (br > 255) br = 255; diff --git a/board/innokom/flash.c b/board/innokom/flash.c index 8fc6e5bd9..8c95341b6 100644 --- a/board/innokom/flash.c +++ b/board/innokom/flash.c @@ -72,7 +72,7 @@ #define MAIN_SECT_SIZE 0x00020000 /* 128k per sector */ #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /** * flash_init: - initialize data structures for flash chips @@ -85,14 +85,14 @@ ulong flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F128J3 & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: @@ -110,14 +110,14 @@ ulong flash_init(void) /* Protect u-boot sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + (256*1024) - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + (256*1024) - 1, &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -135,7 +135,7 @@ void flash_print_info (flash_info_t *info) { int i, j; - for (j=0; j<CFG_MAX_FLASH_BANKS; j++) { + for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) { switch (info->flash_id & FLASH_VENDMASK) { @@ -235,7 +235,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) while ((*addr & 0x0080) != 0x0080) { PRINTK("."); - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = 0x00B0; /* suspend erase*/ *addr = 0x00FF; /* read mode */ rc = ERR_TIMOUT; @@ -306,7 +306,7 @@ static int write_word (flash_info_t *info, ulong dest, ushort data) /* wait while polling the status register */ while(((val = *addr) & 0x80) != 0x80) { - if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) { rc = ERR_TIMOUT; *addr = 0xB0; /* suspend program command */ goto outahere; diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S index 4c9f10ffb..9892430a1 100644 --- a/board/innokom/lowlevel_init.S +++ b/board/innokom/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -54,71 +54,71 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ -/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ +/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */ /* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ /* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ /* */ @@ -168,17 +168,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -187,37 +187,37 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] @@ -239,7 +239,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 @@ -269,7 +269,7 @@ mem_init: /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] @@ -292,7 +292,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ @@ -325,7 +325,7 @@ mem_init: /* Jan 2003, Errata #116, page 30. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -345,7 +345,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] diff --git a/board/innokom/u-boot.lds b/board/innokom/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/innokom/u-boot.lds +++ b/board/innokom/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/integratorap/flash.c b/board/integratorap/flash.c index b120d63eb..0492be762 100644 --- a/board/integratorap/flash.c +++ b/board/integratorap/flash.c @@ -32,7 +32,7 @@ #include <linux/byteorder/swab.h> #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #undef FLASH_PORT_WIDTH32 @@ -88,7 +88,7 @@ unsigned long flash_init (void) { int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -104,8 +104,8 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); return size; } @@ -223,10 +223,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -318,7 +318,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ *addr = (FPW) 0x00B000B0; @@ -454,7 +454,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c index e65990756..ddacabb2e 100644 --- a/board/integratorap/integratorap.c +++ b/board/integratorap/integratorap.c @@ -39,6 +39,8 @@ #include <pci.h> #endif +#include <netdev.h> + DECLARE_GLOBAL_DATA_PTR; void flash__init (void); @@ -517,7 +519,7 @@ extern void dram_query(void); * can be divided by 16 or 256 * and is a 16-bit counter */ -/* U-Boot expects a 32 bit timer running at CFG_HZ*/ +/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/ static ulong timestamp; /* U-Boot ticks since startup */ static ulong total_count = 0; /* Total timer count */ static ulong lastdec; /* Timer reading at last call */ @@ -525,12 +527,12 @@ static ulong div_clock = 256; /* Divisor applied to the timer clock */ static ulong div_timer = 1; /* Divisor to convert timer reading * change to U-Boot ticks */ -/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */ +/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */ #define TIMER_LOAD_VAL 0x0000FFFFL -#define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL) +#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL) -/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec +/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec * - unless otherwise stated */ @@ -541,7 +543,7 @@ static ulong div_timer = 1; /* Divisor to convert timer reading int interrupt_init (void) { /* Load timer with initial value */ - *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; /* Set timer to be * enabled 1 * free-running 0 @@ -549,12 +551,12 @@ int interrupt_init (void) * divider 256 10 * XX 00 */ - *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088; total_count = 0; /* init the timestamp and lastdec value */ reset_timer_masked(); - div_timer = CFG_HZ_CLOCK / CFG_HZ; + div_timer = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ; div_timer /= div_clock; return (0); @@ -586,7 +588,7 @@ void udelay (unsigned long usec) ulong tmo, tmp; /* Convert to U-Boot ticks */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000000L); tmp = get_timer_masked(); /* get current timestamp */ @@ -645,5 +647,10 @@ unsigned long long get_ticks(void) */ ulong get_tbclk (void) { - return CFG_HZ_CLOCK/div_clock; + return CONFIG_SYS_HZ_CLOCK/div_clock; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); } diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c index 59961cdab..5059daeec 100644 --- a/board/integratorcp/flash.c +++ b/board/integratorcp/flash.c @@ -37,7 +37,7 @@ #define DEBUG #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -106,30 +106,30 @@ unsigned long flash_init (void) else nbanks = 1; - if (nbanks > CFG_MAX_FLASH_BANKS) - nbanks = CFG_MAX_FLASH_BANKS; + if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS) + nbanks = CONFIG_SYS_MAX_FLASH_BANKS; /* Enable flash write */ cpcr[1] |= 3; for (i = 0; i < nbanks; i++) { - flash_get_size ((FPW *)(CFG_FLASH_BASE + size), &flash_info[i]); - flash_get_offsets (CFG_FLASH_BASE + size, &flash_info[i]); + flash_get_size ((FPW *)(CONFIG_SYS_FLASH_BASE + size), &flash_info[i]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size, &flash_info[i]); size += flash_info[i].size; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif @@ -228,8 +228,8 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) else nsects = 64; - if (nsects > CFG_MAX_FLASH_SECT) - nsects = CFG_MAX_FLASH_SECT; + if (nsects > CONFIG_SYS_MAX_FLASH_SECT) + nsects = CONFIG_SYS_MAX_FLASH_SECT; /* Write auto select command: read Manufacturer ID */ addr[0x5555] = (FPW) 0x00AA00AA; @@ -280,10 +280,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -308,7 +308,7 @@ void flash_unprotect_sectors (FPWV * addr) reset_timer_masked(); while (((status = *addr) & (FPW)0x00800080) != 0x00800080) { - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout"); break; } @@ -384,7 +384,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) enable_interrupts(); while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = (FPW)0x00700070; status = *addr; if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) { @@ -538,7 +538,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { #ifdef DEBUG *addr = (FPW) 0x00700070; status = *addr; diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c index d6d6e13d5..72629ce2b 100644 --- a/board/integratorcp/integratorcp.c +++ b/board/integratorcp/integratorcp.c @@ -34,6 +34,7 @@ */ #include <common.h> +#include <div64.h> DECLARE_GLOBAL_DATA_PTR; @@ -142,7 +143,7 @@ extern void dram_query(void); * can be divided by 16 or 256 * and can be set up as a 32-bit timer */ -/* U-Boot expects a 32 bit timer, running at CFG_HZ */ +/* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */ /* Keep total timer count to avoid losing decrements < div_timer */ static unsigned long long total_count = 0; static unsigned long long lastdec; /* Timer reading at last call */ @@ -150,13 +151,13 @@ static unsigned long long div_clock = 1; /* Divisor applied to timer clock */ static unsigned long long div_timer = 1; /* Divisor to convert timer reading * change to U-Boot ticks */ -/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */ +/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */ static ulong timestamp; /* U-Boot ticks since startup */ #define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF) -#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4)) +#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) -/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec +/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec * - unless otherwise stated */ @@ -165,7 +166,7 @@ static ulong timestamp; /* U-Boot ticks since startup */ int interrupt_init (void) { /* Load timer with initial value */ - *(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL; /* Set timer to be * enabled 1 * periodic 1 @@ -175,12 +176,12 @@ int interrupt_init (void) * 32 bit 1 * wrapping 0 */ - *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2; + *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2; /* init the timestamp */ total_count = 0ULL; reset_timer_masked(); - div_timer = (unsigned long long)(CFG_HZ_CLOCK / CFG_HZ); + div_timer = (unsigned long long)(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ); div_timer /= div_clock; return (0); @@ -211,7 +212,7 @@ void udelay (unsigned long usec) ulong tmo, tmp; /* Convert to U-Boot ticks */ - tmo = usec * CFG_HZ; + tmo = usec * CONFIG_SYS_HZ; tmo /= (1000000L); tmp = get_timer_masked(); /* get current timestamp */ @@ -244,7 +245,11 @@ ulong get_timer_masked (void) total_count += lastdec - now; } lastdec = now; - timestamp = (ulong)(total_count/div_timer); + + /* Reuse "now" */ + now = total_count; + do_div(now, div_timer); + timestamp = now; return timestamp; } @@ -270,5 +275,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk (void) { - return (ulong)(((unsigned long long)CFG_HZ_CLOCK)/div_clock); + return (ulong)(((unsigned long long)CONFIG_SYS_HZ_CLOCK)/div_clock); } diff --git a/board/ip860/flash.c b/board/ip860/flash.c index 2cf23b3e8..6491af2ff 100644 --- a/board/ip860/flash.c +++ b/board/ip860/flash.c @@ -24,17 +24,17 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -50,7 +50,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE; unsigned long size; @@ -61,7 +61,7 @@ unsigned long flash_init (void) */ bcsr->bd_ctrl |= BD_CTRL_FLWE; - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -75,30 +75,30 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br1 & ~(BR_BA_MSK)); /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif return (size); @@ -309,7 +309,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xFFFFFFFF; /* reset bank */ return 1; @@ -434,7 +434,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); flag = 0; while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flag = 1; break; } diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c index 375cd4d26..e2a185146 100644 --- a/board/ip860/ip860.c +++ b/board/ip860/ip860.c @@ -87,12 +87,12 @@ const uint sdram_table[] = { /* ------------------------------------------------------------------------- */ int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; return 0; } @@ -139,7 +139,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; ulong refresh_val; @@ -167,8 +167,8 @@ phys_size_t initdram (int board_type) /* * Map controller banks 2 to the SDRAM address */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + memctl->memc_or2 = CONFIG_SYS_OR2; + memctl->memc_br2 = CONFIG_SYS_BR2; /* IP860 boards have only one bank SDRAM */ @@ -197,7 +197,7 @@ phys_size_t initdram (int board_type) udelay (1000); memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; udelay (10000); @@ -205,34 +205,34 @@ phys_size_t initdram (int board_type) * Also, map other memory to correct position */ -#if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM)) - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; +#if (defined(CONFIG_SYS_OR1) && defined(CONFIG_SYS_BR1_PRELIM)) + memctl->memc_or1 = CONFIG_SYS_OR1; + memctl->memc_br1 = CONFIG_SYS_BR1; #endif -#if defined(CFG_OR3) && defined(CFG_BR3) - memctl->memc_or3 = CFG_OR3; - memctl->memc_br3 = CFG_BR3; +#if defined(CONFIG_SYS_OR3) && defined(CONFIG_SYS_BR3) + memctl->memc_or3 = CONFIG_SYS_OR3; + memctl->memc_br3 = CONFIG_SYS_BR3; #endif -#if defined(CFG_OR4) && defined(CFG_BR4) - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; +#if defined(CONFIG_SYS_OR4) && defined(CONFIG_SYS_BR4) + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; #endif -#if defined(CFG_OR5) && defined(CFG_BR5) - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; +#if defined(CONFIG_SYS_OR5) && defined(CONFIG_SYS_BR5) + memctl->memc_or5 = CONFIG_SYS_OR5; + memctl->memc_br5 = CONFIG_SYS_BR5; #endif -#if defined(CFG_OR6) && defined(CFG_BR6) - memctl->memc_or6 = CFG_OR6; - memctl->memc_br6 = CFG_BR6; +#if defined(CONFIG_SYS_OR6) && defined(CONFIG_SYS_BR6) + memctl->memc_or6 = CONFIG_SYS_OR6; + memctl->memc_br6 = CONFIG_SYS_BR6; #endif -#if defined(CFG_OR7) && defined(CFG_BR7) - memctl->memc_or7 = CFG_OR7; - memctl->memc_br7 = CFG_BR7; +#if defined(CONFIG_SYS_OR7) && defined(CONFIG_SYS_BR7) + memctl->memc_or7 = CONFIG_SYS_OR7; + memctl->memc_br7 = CONFIG_SYS_BR7; #endif return (size); @@ -251,7 +251,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -263,7 +263,7 @@ static long int dram_size (long int mamr_value, long int *base, void reset_phy (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ulong mask = PB_ENET_RESET | PB_ENET_JABD; ulong reg; diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index ef8829793..d1cb7e262 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_ppc/ticks.o (.text) /** . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) **/ *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index ad685e6f8..e8a47f7a0 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/ticks.o (.text) /** . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) **/ *(.text) *(.fixup) diff --git a/board/iphase4539/flash.c b/board/iphase4539/flash.c index 4eca46720..3dfee1fde 100644 --- a/board/iphase4539/flash.c +++ b/board/iphase4539/flash.c @@ -31,7 +31,7 @@ #include <flash.h> #include <asm/io.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern int hwc_flash_size(void); static ulong flash_get_size (u32 addr, flash_info_t *info); @@ -52,41 +52,41 @@ unsigned long flash_init (void) unsigned int bank = 0; /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; flash_info[i].size = 0; } /* Initialise the BOOT Flash */ - if (bank == CFG_MAX_FLASH_BANKS) { + if (bank == CONFIG_SYS_MAX_FLASH_BANKS) { puts ("Warning: not all Flashes are initialised !"); return flash_size; } - bank_size = flash_get_size (CFG_FLASH_BASE, flash_info + bank); + bank_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info + bank); if (bank_size) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \ - CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_MAX_FLASH_SIZE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \ + CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MAX_FLASH_SIZE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, flash_info + bank); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, flash_info + bank); #endif /* HWC protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + 0x10000 - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + 0x10000 - 1, flash_info + bank); flash_size += bank_size; @@ -144,10 +144,10 @@ static ulong flash_get_size (u32 addr, flash_info_t *info) case AMD_ID_LV033C: info->flash_id += FLASH_AM033C; info->size = hwc_flash_size(); - if (info->size > CFG_MAX_FLASH_SIZE) { + if (info->size > CONFIG_SYS_MAX_FLASH_SIZE) { printf("U-Boot supports only %d MB\n", - CFG_MAX_FLASH_SIZE); - info->size = CFG_MAX_FLASH_SIZE; + CONFIG_SYS_MAX_FLASH_SIZE); + info->size = CONFIG_SYS_MAX_FLASH_SIZE; } info->sector_count = info->size / 0x10000; break; /* => 4 MB */ @@ -281,7 +281,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = info->start[l_sect]; while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -421,7 +421,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((in32(dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } iobarrier_rw(); diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c index e5d0254a1..7fec2cc79 100644 --- a/board/iphase4539/iphase4539.c +++ b/board/iphase4539/iphase4539.c @@ -195,16 +195,16 @@ const iop_conf_t iop_conf_tab[4][32] = { phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *base; ulong maxsize; int i; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT immap->im_siu_conf.sc_ppc_acr = 0x00000026; immap->im_siu_conf.sc_ppc_alrh = 0x01276345; immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF; @@ -217,7 +217,7 @@ phys_size_t initdram (int board_type) /* Init Main SDRAM */ #define OP_VALUE 0x404A241A #define OP_VALUE_M (OP_VALUE & 0x87FFFFFF); - base = (uchar *) CFG_SDRAM_BASE; + base = (uchar *) CONFIG_SYS_SDRAM_BASE; memctl->memc_psdmr = 0x28000000 | OP_VALUE_M; *base = 0xFF; memctl->memc_psdmr = 0x08000000 | OP_VALUE_M; diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c index 12fb91fb8..9254e0a64 100644 --- a/board/ispan/ispan.c +++ b/board/ispan/ispan.c @@ -39,31 +39,31 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) -#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3) +#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3) const iop_conf_t iop_conf_tab[4][32] = { /* Port A */ { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ @@ -82,34 +82,34 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ - /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ - /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ - /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ - /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ - /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ - /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ - /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ - /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ - /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ - /* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ - /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ - /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ - /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ + /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */ + /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */ + /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */ + /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */ + /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */ + /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */ + /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */ + /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */ + /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */ + /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */ + /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */ + /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */ + /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */ + /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ @@ -131,9 +131,9 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */ + /* PC18 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */ /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */ + /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ @@ -179,8 +179,8 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */ /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */ /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { CFG_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */ - /* PD5 */ { CFG_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */ + /* PD6 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */ + /* PD5 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */ /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ @@ -360,8 +360,8 @@ phys_size_t initdram (int board_type) { long maxsize = hwc_main_sdram_size(); -#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE) - volatile immap_t *immap = (immap_t *) CFG_IMMR; +#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE) + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar *base; int i; @@ -375,37 +375,37 @@ phys_size_t initdram (int board_type) immap->im_siu_conf.sc_tescr1 = 0x00004000; immap->im_siu_conf.sc_ltescr1 = 0x00004000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* Initialise 60x bus SDRAM */ - base = (uchar *)(CFG_SDRAM_BASE | 0x110); - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_60x_OR; - memctl->memc_br1 = CFG_SDRAM_BASE | CFG_60x_BR; + base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110); + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_or1 = CONFIG_SYS_60x_OR; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR; - memctl->memc_psdmr = CFG_PSDMR | 0x28000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000; *base = 0xFF; - memctl->memc_psdmr = CFG_PSDMR | 0x08000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000; for (i = 0; i < 8; i++) *base = 0xFF; - memctl->memc_psdmr = CFG_PSDMR | 0x18000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000; *base = 0xFF; - memctl->memc_psdmr = CFG_PSDMR | 0x40000000; + memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000; /* Initialise local bus SDRAM */ - base = (uchar *)CFG_LSDRAM_BASE; - memctl->memc_lsrt = CFG_LSRT; - memctl->memc_or2 = CFG_LOC_OR; - memctl->memc_br2 = CFG_LSDRAM_BASE | CFG_LOC_BR; + base = (uchar *)CONFIG_SYS_LSDRAM_BASE; + memctl->memc_lsrt = CONFIG_SYS_LSRT; + memctl->memc_or2 = CONFIG_SYS_LOC_OR; + memctl->memc_br2 = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR; - memctl->memc_lsdmr = CFG_LSDMR | 0x28000000; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000; *base = 0xFF; - memctl->memc_lsdmr = CFG_LSDMR | 0x08000000; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000; for (i = 0; i < 8; i++) *base = 0xFF; - memctl->memc_lsdmr = CFG_LSDMR | 0x18000000; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000; *base = 0xFF; - memctl->memc_lsdmr = CFG_LSDMR | 0x40000000; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000; /* We must be able to test a location outsize the maximum legal size * to find out THAT we are outside; but this address still has to be @@ -420,7 +420,7 @@ phys_size_t initdram (int board_type) if (maxsize != hwc_main_sdram_size()) puts("Oops: memory test has not found all memory!\n"); -#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */ +#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */ /* Return total RAM size (size of 60x SDRAM) */ return maxsize; diff --git a/board/ivm/flash.c b/board/ivm/flash.c index 140ba2d53..cf309d77a 100644 --- a/board/ivm/flash.c +++ b/board/ivm/flash.c @@ -24,17 +24,17 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -50,13 +50,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -72,30 +72,30 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \ + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \ BR_MS_GPCM | BR_PS_16 | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b0; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif @@ -383,10 +383,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } saddr[0] = 0x00FF; /* restore read mode */ @@ -454,7 +454,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = *addr) & 0x0080) != 0x0080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0x00FF; /* reset to read mode */ return 1; @@ -583,7 +583,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while (((status = *addr) & 0x0080) != 0x0080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0x00FF; /* restore read mode */ return (1); } diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c index 4882f0450..9bec198c2 100644 --- a/board/ivm/ivm.c +++ b/board/ivm/ivm.c @@ -161,28 +161,28 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; long int size_b0; /* enable SDRAM clock ("switch on" SDRAM) */ - immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */ - immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */ - immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */ + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* active output */ + immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE; /* output */ + immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE; /* assert SDRAM CLKE */ udelay (1); /* * Map controller bank 1 for ELIC SACCO */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; + memctl->memc_or1 = CONFIG_SYS_OR1; + memctl->memc_br1 = CONFIG_SYS_BR1; /* * Map controller bank 2 for ELIC EPIC */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + memctl->memc_or2 = CONFIG_SYS_OR2; + memctl->memc_br2 = CONFIG_SYS_BR2; /* * Configure UPMA for SHARC @@ -194,15 +194,15 @@ phys_size_t initdram (int board_type) /* * Map controller bank 4 for HDLC Address space */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; #endif /* * Map controller bank 5 for SHARC */ - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; + memctl->memc_or5 = CONFIG_SYS_OR5; + memctl->memc_br5 = CONFIG_SYS_BR5; memctl->memc_mamr = 0x00001000; @@ -212,17 +212,17 @@ phys_size_t initdram (int board_type) upmconfig (UPMB, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ udelay (200); memctl->memc_mcr = 0x80806105; /* precharge */ @@ -251,10 +251,10 @@ phys_size_t initdram (int board_type) * Check Bank 0 Memory Size for re-configuration */ size_b0 = - dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM, + dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; return (size_b0); } @@ -272,7 +272,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; memctl->memc_mbmr = mamr_value; @@ -284,13 +284,13 @@ static long int dram_size (long int mamr_value, long int *base, void reset_phy (void) { - immap_t *immr = (immap_t *) CFG_IMMR; + immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */ - immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN; /* output */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* active output */ + immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN; /* output */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ udelay (1000); /* @@ -302,13 +302,13 @@ void reset_phy (void) * Note: The RESET pin is high active, but there is an * inverter on the SPD823TS board... */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET; + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET); + immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET; /* assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET); + immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET); udelay (10); /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET; + immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET; udelay (10); } @@ -332,21 +332,21 @@ void show_boot_progress (int status) void ide_set_reset (int on) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* * Configure PC for IDE Reset Pin */ if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; } /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); + immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); + immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; } /* ------------------------------------------------------------------------- */ diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index d7f360f3b..2583a5996 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index 995fc8327..4d49f1bbe 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c index 704dea863..f1d9190ea 100644 --- a/board/ixdp425/flash.c +++ b/board/ixdp425/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #undef FLASH_PORT_WIDTH32 @@ -65,7 +65,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -81,13 +81,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -198,10 +198,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -270,7 +270,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -406,7 +406,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c index e0d763780..43ac8f6a4 100644 --- a/board/ixdp425/ixdp425.c +++ b/board/ixdp425/ixdp425.c @@ -31,6 +31,7 @@ #include <common.h> #include <command.h> #include <malloc.h> +#include <netdev.h> #include <asm/arch/ixp425.h> DECLARE_GLOBAL_DATA_PTR; @@ -53,25 +54,25 @@ int board_init (void) /* * Get realtek RTL8305 switch and SLIC out of reset */ - GPIO_OUTPUT_SET(CFG_GPIO_SWITCH_RESET_N); - GPIO_OUTPUT_ENABLE(CFG_GPIO_SWITCH_RESET_N); - GPIO_OUTPUT_SET(CFG_GPIO_SLIC_RESET_N); - GPIO_OUTPUT_ENABLE(CFG_GPIO_SLIC_RESET_N); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SWITCH_RESET_N); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SWITCH_RESET_N); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N); /* * Setup GPIO's for PCI INTA & INTB */ - GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA_N); - GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA_N); - GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB_N); - GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB_N); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N); /* * Setup GPIO's for 33MHz clock output */ *IXP425_GPIO_GPCLKR = 0x01FF01FF; - GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK); - GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); #endif return 0; @@ -118,3 +119,8 @@ void pci_init_board(void) pci_ixp_init(&hose); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/ixdp425/u-boot.lds b/board/ixdp425/u-boot.lds index 58393d0af..f46a7c7e5 100644 --- a/board/ixdp425/u-boot.lds +++ b/board/ixdp425/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/jse/flash.c b/board/jse/flash.c index c462fe031..92acdb102 100644 --- a/board/jse/flash.c +++ b/board/jse/flash.c @@ -32,10 +32,10 @@ #include <ppc4xx.h> #include <asm/processor.h> -#if CFG_MAX_FLASH_BANKS != 1 -#error "CFG_MAX_FLASH_BANKS must be 1" +#if CONFIG_SYS_MAX_FLASH_BANKS != 1 +#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1" #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -281,7 +281,7 @@ int wait_for_DQ7 (flash_info_t * info, int sect) last = start; while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return -1; } @@ -510,7 +510,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/jse/jse.c b/board/jse/jse.c index 929081468..6a6b9dd74 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -67,7 +67,7 @@ int board_early_init_f (void) /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, CFG_SYSTEMACE_BASE | 0x00018000); + mtdcr (ebccfgd, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ /* CPC0_CR1 |= PCIPW */ @@ -95,11 +95,11 @@ int checkboard (void) /* check that the SystemACE chip is alive. */ printf ("ACE: "); - vers = readw (CFG_SYSTEMACE_BASE + 0x16); + vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16); printf ("SystemACE %u.%u (build %u)", (vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff); - status = readl (CFG_SYSTEMACE_BASE + 0x04); + status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); #ifdef DEBUG printf (" STATUS=0x%08x", status); #endif @@ -110,23 +110,23 @@ int checkboard (void) if (status & 0x04) { /* CONTROLREG = CFGPROG */ - writew (0x1000, CFG_SYSTEMACE_BASE + 0x18); + writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); udelay (500); /* CONTROLREG = CFGRESET */ - writew (0x0080, CFG_SYSTEMACE_BASE + 0x18); + writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18); udelay (500); - writew (0x0000, CFG_SYSTEMACE_BASE + 0x18); + writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18); /* CONTROLREG = CFGSTART */ - writew (0x0020, CFG_SYSTEMACE_BASE + 0x18); + writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18); - status = readl (CFG_SYSTEMACE_BASE + 0x04); + status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); } } /* Wait for the SystemACE to program its chain of devices. */ while ((status & 0x84) == 0x00) { udelay (500); - status = readl (CFG_SYSTEMACE_BASE + 0x04); + status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04); } if (status & 0x04) diff --git a/board/jse/sdram.c b/board/jse/sdram.c index 8ba6c454f..a1f526de6 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -151,7 +151,7 @@ int testdram (void) /* Start memory test. */ printf ("test: %u MB - ", SDRAM_LEN / 1048576); - sdram = (unsigned long *) CFG_SDRAM_BASE; + sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE; printf ("write - "); for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) { diff --git a/board/jse/u-boot.lds b/board/jse/u-boot.lds index 7e060cbfd..7141c5a39 100644 --- a/board/jse/u-boot.lds +++ b/board/jse/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -136,6 +136,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c index 7913c7537..6e752c655 100644 --- a/board/jupiter/jupiter.c +++ b/board/jupiter/jupiter.c @@ -45,7 +45,7 @@ #define SDRAM_CONFIG2 0x88b70004 #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -88,7 +88,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -98,7 +98,7 @@ phys_size_t initdram (int board_type) ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -119,9 +119,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -147,10 +147,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -172,7 +172,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -190,7 +190,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -244,9 +244,9 @@ void flash_afterinit(ulong size) { if (size == 0x1000000) { /* adjust mapping */ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } #if defined(CONFIG_MPC5200) *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ diff --git a/board/kb9202/u-boot.lds b/board/kb9202/u-boot.lds index 3b7977672..d0666ac73 100644 --- a/board/kb9202/u-boot.lds +++ b/board/kb9202/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c new file mode 100644 index 000000000..a4cf24cf7 --- /dev/null +++ b/board/keymile/common/common.c @@ -0,0 +1,523 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8260.h> +#include <ioports.h> +#include <malloc.h> +#include <hush.h> + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +#include <i2c.h> +#endif +#include <asm/io.h> + +extern int i2c_soft_read_pin (void); + +int ivm_calc_crc (unsigned char *buf, int len) +{ + const unsigned short crc_tab[16] = { + 0x0000, 0xCC01, 0xD801, 0x1400, + 0xF001, 0x3C00, 0x2800, 0xE401, + 0xA001, 0x6C00, 0x7800, 0xB401, + 0x5000, 0x9C01, 0x8801, 0x4400}; + + unsigned short crc = 0; /* final result */ + unsigned short r1 = 0; /* temp */ + unsigned char byte = 0; /* input buffer */ + int i; + + /* calculate CRC from array data */ + for (i = 0; i < len; i++) { + byte = buf[i]; + + /* lower 4 bits */ + r1 = crc_tab[crc & 0xF]; + crc = ((crc) >> 4) & 0x0FFF; + crc = crc ^ r1 ^ crc_tab[byte & 0xF]; + + /* upper 4 bits */ + r1 = crc_tab[crc & 0xF]; + crc = (crc >> 4) & 0x0FFF; + crc = crc ^ r1 ^ crc_tab[(byte >> 4) & 0xF]; + } + return crc; +} + +static int ivm_set_value (char *name, char *value) +{ + char tempbuf[256]; + + if (value != NULL) { + sprintf (tempbuf, "%s=%s", name, value); + return set_local_var (tempbuf, 0); + } else { + unset_local_var (name); + } + return 0; +} + +static int ivm_get_value (unsigned char *buf, int len, char *name, int off, + int check) +{ + unsigned short val; + unsigned char valbuf[30]; + + if ((buf[off + 0] != buf[off + 2]) && + (buf[off + 2] != buf[off + 4])) { + printf ("%s Error corrupted %s\n", __FUNCTION__, name); + val = -1; + } else { + val = buf[off + 0] + (buf[off + 1] << 8); + if ((val == 0) && (check == 1)) + val = -1; + } + sprintf ((char *)valbuf, "%x", val); + ivm_set_value (name, (char *)valbuf); + return val; +} + +#define INVENTORYBLOCKSIZE 0x100 +#define INVENTORYDATAADDRESS 0x21 +#define INVENTORYDATASIZE (INVENTORYBLOCKSIZE - INVENTORYDATAADDRESS - 3) + +#define IVM_POS_SHORT_TEXT 0 +#define IVM_POS_MANU_ID 1 +#define IVM_POS_MANU_SERIAL 2 +#define IVM_POS_PART_NUMBER 3 +#define IVM_POS_BUILD_STATE 4 +#define IVM_POS_SUPPLIER_PART_NUMBER 5 +#define IVM_POS_DELIVERY_DATE 6 +#define IVM_POS_SUPPLIER_BUILD_STATE 7 +#define IVM_POS_CUSTOMER_ID 8 +#define IVM_POS_CUSTOMER_PROD_ID 9 +#define IVM_POS_HISTORY 10 +#define IVM_POS_SYMBOL_ONLY 11 + +static char convert_char (char c) +{ + return (c < ' ' || c > '~') ? '.' : c; +} + +static int ivm_findinventorystring (int type, + unsigned char* const string, + unsigned long maxlen, + unsigned char *buf) +{ + int xcode = 0; + unsigned long cr = 0; + unsigned long addr = INVENTORYDATAADDRESS; + unsigned long size = 0; + unsigned long nr = type; + int stop = 0; /* stop on semicolon */ + + memset(string, '\0', maxlen); + switch (type) { + case IVM_POS_SYMBOL_ONLY: + nr = 0; + stop= 1; + break; + default: + nr = type; + stop = 0; + } + + /* Look for the requested number of CR. */ + while ((cr != nr) && (addr < INVENTORYDATASIZE)) { + if ((buf[addr] == '\r')) { + cr++; + } + addr++; + } + + /* the expected number of CR was found until the end of the IVM + * content --> fill string */ + if (addr < INVENTORYDATASIZE) { + /* Copy the IVM string in the corresponding string */ + for (; (buf[addr] != '\r') && + ((buf[addr] != ';') || (!stop)) && + (size < (maxlen - 1) && + (addr < INVENTORYDATASIZE)); addr++) + { + size += sprintf((char *)string + size, "%c", + convert_char (buf[addr])); + } + + /* copy phase is done: check if everything is ok. If not, + * the inventory data is most probably corrupted: tell + * the world there is a problem! */ + if (addr == INVENTORYDATASIZE) { + xcode = -1; + printf ("Error end of string not found\n"); + } else if ((size >= (maxlen - 1)) && + (buf[addr] != '\r')) { + xcode = -1; + printf ("string too long till next CR\n"); + } + } else { + /* some CR are missing... + * the inventory data is most probably corrupted */ + xcode = -1; + printf ("not enough cr found\n"); + } + return xcode; +} + +#define GET_STRING(name, which, len) \ + if (ivm_findinventorystring (which, valbuf, len, buf) == 0) { \ + ivm_set_value (name, (char *)valbuf); \ + } + +static int ivm_check_crc (unsigned char *buf, int block) +{ + unsigned long crc; + unsigned long crceeprom; + + crc = ivm_calc_crc (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2); + crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \ + buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256); + if (crc != crceeprom) { + printf ("Error CRC Block: %d EEprom: calculated: %lx EEprom: %lx\n", + block, crc, crceeprom); + return -1; + } + return 0; +} + +static int ivm_analyze_block2 (unsigned char *buf, int len) +{ + unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; + unsigned long count; + + /* IVM_MacAddress */ + sprintf ((char *)valbuf, "%02X:%02X:%02X:%02X:%02X:%02X", + buf[1], + buf[2], + buf[3], + buf[4], + buf[5], + buf[6]); + ivm_set_value ("IVM_MacAddress", (char *)valbuf); + if (getenv ("ethaddr") == NULL) + setenv ((char *)"ethaddr", (char *)valbuf); + /* IVM_MacCount */ + count = (buf[10] << 24) + + (buf[11] << 16) + + (buf[12] << 8) + + buf[13]; + if (count == 0xffffffff) + count = 1; + sprintf ((char *)valbuf, "%lx", count); + ivm_set_value ("IVM_MacCount", (char *)valbuf); + return 0; +} + +int ivm_analyze_eeprom (unsigned char *buf, int len) +{ + unsigned short val; + unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; + unsigned char *tmp; + + if (ivm_check_crc (buf, 0) != 0) + return -1; + + ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_BoardId", 0, 1); + val = ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_HWKey", 6, 1); + if (val != 0xffff) { + sprintf ((char *)valbuf, "%x", ((val /100) % 10)); + ivm_set_value ("IVM_HWVariant", (char *)valbuf); + sprintf ((char *)valbuf, "%x", (val % 100)); + ivm_set_value ("IVM_HWVersion", (char *)valbuf); + } + ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_Functions", 12, 0); + + GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8) + GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64) + tmp = (unsigned char *) getenv("IVM_DeviceName"); + if (tmp) { + int len = strlen ((char *)tmp); + int i = 0; + + while (i < len) { + if (tmp[i] == ';') { + ivm_set_value ("IVM_ShortText", (char *)&tmp[i + 1]); + break; + } + i++; + } + if (i >= len) + ivm_set_value ("IVM_ShortText", NULL); + } else { + ivm_set_value ("IVM_ShortText", NULL); + } + GET_STRING("IVM_ManufacturerID", IVM_POS_MANU_ID, 32) + GET_STRING("IVM_ManufacturerSerialNumber", IVM_POS_MANU_SERIAL, 20) + GET_STRING("IVM_ManufacturerPartNumber", IVM_POS_PART_NUMBER, 32) + GET_STRING("IVM_ManufacturerBuildState", IVM_POS_BUILD_STATE, 32) + GET_STRING("IVM_SupplierPartNumber", IVM_POS_SUPPLIER_PART_NUMBER, 32) + GET_STRING("IVM_DelieveryDate", IVM_POS_DELIVERY_DATE, 32) + GET_STRING("IVM_SupplierBuildState", IVM_POS_SUPPLIER_BUILD_STATE, 32) + GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32) + GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32) + + if (ivm_check_crc (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0) + return -2; + ivm_analyze_block2 (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], CONFIG_SYS_IVM_EEPROM_PAGE_LEN); + + return 0; +} + +int ivm_read_eeprom (void) +{ + I2C_MUX_DEVICE *dev = NULL; + uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + uchar *buf; + unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR; + + /* First init the Bus, select the Bus */ +#if defined(CONFIG_SYS_I2C_IVM_BUS) + dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS); +#else + buf = (unsigned char *) getenv ("EEprom_ivm"); + if (buf != NULL) + dev = i2c_mux_ident_muxstring (buf); +#endif + if (dev == NULL) { + printf ("Error couldnt add Bus for IVM\n"); + return -1; + } + i2c_set_bus_num (dev->busid); + + buf = (unsigned char *) getenv ("EEprom_ivm_addr"); + if (buf != NULL) + dev_addr = simple_strtoul ((char *)buf, NULL, 16); + + if (eeprom_read (dev_addr, 0, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) { + printf ("Error reading EEprom\n"); + return -2; + } + + return ivm_analyze_eeprom (i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN); +} + +#if defined(CONFIG_SYS_I2C_INIT_BOARD) +#define DELAY_ABORT_SEQ 62 +#define DELAY_HALF_PERIOD (500 / (CONFIG_SYS_I2C_SPEED / 1000)) + +#if defined(CONFIG_MGCOGE) +#define SDA_MASK 0x00010000 +#define SCL_MASK 0x00020000 +static void set_pin (int state, unsigned long mask) +{ + volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3); + + if (state) + iop->pdat |= (mask); + else + iop->pdat &= ~(mask); + + iop->pdir |= (mask); +} + +static int get_pin (unsigned long mask) +{ + volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3); + + iop->pdir &= ~(mask); + return (0 != (iop->pdat & (mask))); +} + +static void set_sda (int state) +{ + set_pin (state, SDA_MASK); +} + +static void set_scl (int state) +{ + set_pin (state, SCL_MASK); +} + +static int get_sda (void) +{ + return get_pin (SDA_MASK); +} + +static int get_scl (void) +{ + return get_pin (SCL_MASK); +} + +#if defined(CONFIG_HARD_I2C) +static void setports (int gpio) +{ + volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3); + + if (gpio) { + iop->ppar &= ~(SDA_MASK | SCL_MASK); + iop->podr &= ~(SDA_MASK | SCL_MASK); + } else { + iop->ppar |= (SDA_MASK | SCL_MASK); + iop->pdir &= ~(SDA_MASK | SCL_MASK); + iop->podr |= (SDA_MASK | SCL_MASK); + } +} +#endif +#endif + +#if defined(CONFIG_MGSUVD) +static void set_sda (int state) +{ + I2C_SDA(state); +} + +static void set_scl (int state) +{ + I2C_SCL(state); +} + +static int get_sda (void) +{ + return I2C_READ; +} + +static int get_scl (void) +{ + int val; + + *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; + udelay (1); + val = *(unsigned char *)(I2C_BASE_PORT); + + return ((val & SCL_BIT) == SCL_BIT); +} + +#endif + +static void writeStartSeq (void) +{ + set_sda (1); + udelay (DELAY_HALF_PERIOD); + set_scl (1); + udelay (DELAY_HALF_PERIOD); + set_sda (0); + udelay (DELAY_HALF_PERIOD); + set_scl (0); + udelay (DELAY_HALF_PERIOD); +} + +/* I2C is a synchronous protocol and resets of the processor in the middle + of an access can block the I2C Bus until a powerdown of the full unit is + done. This function toggles the SCL until the SCL and SCA line are + released, but max. 16 times, after this a I2C start-sequence is sent. + This I2C Deblocking mechanism was developed by Keymile in association + with Anatech and Atmel in 1998. + */ +static int i2c_make_abort (void) +{ + int scl_state = 0; + int sda_state = 0; + int i = 0; + int ret = 0; + + if (!get_sda ()) { + ret = -1; + while (i < 16) { + i++; + set_scl (0); + udelay (DELAY_ABORT_SEQ); + set_scl (1); + udelay (DELAY_ABORT_SEQ); + scl_state = get_scl (); + sda_state = get_sda (); + if (scl_state && sda_state) { + ret = 0; + break; + } + } + } + if (ret == 0) { + for (i =0; i < 5; i++) { + writeStartSeq (); + } + } + get_sda (); + return ret; +} + +/** + * i2c_init_board - reset i2c bus. When the board is powercycled during a + * bus transfer it might hang; for details see doc/I2C_Edge_Conditions. + */ +void i2c_init_board(void) +{ +#if defined(CONFIG_HARD_I2C) + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; + + /* disable I2C controller first, otherwhise it thinks we want to */ + /* talk to the slave port... */ + i2c->i2c_i2mod &= ~0x01; + + /* Set the PortPins to GPIO */ + setports (1); +#endif + + /* Now run the AbortSequence() */ + i2c_make_abort (); + +#if defined(CONFIG_HARD_I2C) + /* Set the PortPins back to use for I2C */ + setports (0); +#endif +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +int fdt_set_node_and_value (void *blob, + char *nodename, + char *regname, + void *var, + int size) +{ + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_setprop (blob, nodeoffset, regname, var, + size); + if (ret < 0) + printf("ft_blob_update(): cannot set %s/%s " + "property err:%s\n", nodename, regname, + fdt_strerror (ret)); + } else { + printf("ft_blob_update(): cannot find %s node " + "err:%s\n", nodename, fdt_strerror (nodeoffset)); + } + return ret; +} +#endif diff --git a/board/keymile/common/keymile_hdlc_enet.c b/board/keymile/common/keymile_hdlc_enet.c new file mode 100644 index 000000000..141371b8f --- /dev/null +++ b/board/keymile/common/keymile_hdlc_enet.c @@ -0,0 +1,620 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * Based in part on cpu/mpc8260/ether_scc.c. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <net.h> + +#ifdef CONFIG_KEYMILE_HDLC_ENET +#ifdef TEST_IT +#include <command.h> +#endif + +#include "keymile_hdlc_enet.h" + +extern char keymile_slot; /* our slot number in the backplane */ + +/* Allow up to about 50 ms for sending */ +#define TOUT_LOOP 50000 + +/* + * Since, except during initialization, ethact is always HDLC ETHERNET + * while we're in the driver, just use serial_printf() everywhere for + * output. This avoids possible conflicts when netconsole is being + * used. + */ +#define dprintf(fmt, args...) serial_printf(fmt, ##args) + +/* Cannot use the storage from net.c because we allocate larger buffers */ +static volatile uchar MyPktBuf[HDLC_PKTBUFSRX * PKT_MAXBLR_SIZE + PKTALIGN]; +static volatile uchar *MyRxPackets[HDLC_PKTBUFSRX]; /* Receive packet */ + +static unsigned int keymile_rxIdx; /* index of the current RX buffer */ + +static IPaddr_t cachedNumbers[CACHEDNUMBERS]; /* 4 bytes per entry */ +void initCachedNumbers(int); + +/* + * SCC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ +typedef volatile struct CommonBufferDescriptor { + cbd_t txbd; /* Tx BD */ + cbd_t rxbd[HDLC_PKTBUFSRX]; /* Rx BD */ +} RTXBD; + +/* + * This must be extern because it is allocated in DPRAM using CPM-sepcific + * code. + */ +static RTXBD *rtx; + +static int keymile_hdlc_enet_send(struct eth_device *, volatile void *, int); +static int keymile_hdlc_enet_recv(struct eth_device *); +void keymile_hdlc_enet_init_bds(RTXBD *); +extern int keymile_hdlc_enet_init(struct eth_device *, bd_t *); +extern void keymile_hdlc_enet_halt(struct eth_device *); + +/* flags in the buffer descriptor not defined anywhere else */ +#define BD_SC_CT BD_SC_CD +#define BD_SC_CR 0x04 +#define BD_SC_DE 0x80 +#ifndef BD_SC_TC +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#endif +#define BD_SC_FIRST BD_SC_TC +#define BD_SC_STATS (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_CR | BD_SC_CD \ + | BD_SC_OV | BD_SC_DE) + +#if defined(TEST_RX) || defined(TEST_TX) || defined(TEST_IT) +static void hexdump(unsigned char *buf, int len) +{ + int i; + const int bytesPerLine = 32; + + if (len > 4 * bytesPerLine) + len = 4 * bytesPerLine; + dprintf("\t address: %08x\n", (unsigned int)buf); + for (i = 0; i < len; i++) { + if (i % bytesPerLine == 0) + dprintf("%04x: ", (unsigned short)i); + dprintf("%02x ", buf[i]); + if ((i + 1) % bytesPerLine == 0) { + dprintf("\n"); + continue; + } + if ((i + 1) % 8 == 0) + printf(" "); + } + if (len % bytesPerLine) + dprintf("\n"); +} +#endif + +int keymile_hdlc_enet_initialize(bd_t *bis) +{ + struct eth_device *dev; + + dev = (struct eth_device *) malloc(sizeof *dev); + memset(dev, 0, sizeof *dev); +#ifdef TEST_IT + seth = dev; +#endif + + sprintf(dev->name, "HDLC ETHERNET"); + dev->init = keymile_hdlc_enet_init; + dev->halt = keymile_hdlc_enet_halt; + dev->send = keymile_hdlc_enet_send; + dev->recv = keymile_hdlc_enet_recv; + + eth_register(dev); + + return 1; +} + +/* + * This is called from the board-specific driver after rtx is allocated. + */ +void keymile_hdlc_enet_init_bds(RTXBD *board_rtx) +{ + volatile cbd_t *bdp; + int i; + + rtx = board_rtx; + keymile_rxIdx = 0; + /* + * Initialize the buffer descriptors. + */ + bdp = &rtx->txbd; + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; + bdp->cbd_sc = BD_SC_WRAP; + + /* + * Setup RX packet buffers, aligned correctly. + * Borrowed from net/net.c. + */ + MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1); + MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN; + for (i = 1; i < HDLC_PKTBUFSRX; i++) + MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE; + + bdp = &rtx->rxbd[0]; + for (i = 0; i < HDLC_PKTBUFSRX; i++) { + bdp->cbd_sc = BD_SC_EMPTY; + /* Leave space at the start for INET header. */ + bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] + + INET_HDR_ALIGN); + bdp++; + } + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; +} + +/* + * This returns the current port number for NETCONSOLE. If nc_port + * in netconsole.c weren't declared static we wouldn't need this. + */ +static short get_netcons_port(void) +{ + char *p; + short nc_port; + + nc_port = 6666; /* default */ + + p = getenv("ncip"); + if (p != NULL) { + p = strchr(p, ':'); + if (p != NULL) + nc_port = simple_strtoul(p + 1, NULL, 10); + } + + return htons(nc_port); +} + +/* + * Read the port numbers from the variables + */ +void initCachedNumbers(int verbose) +{ + char *str; + ushort port; + + /* already in network order */ + cachedNumbers[IP_ADDR] = getenv_IPaddr("ipaddr"); + /* already in network order */ + cachedNumbers[IP_SERVER] = getenv_IPaddr("serverip"); + str = getenv("tftpsrcp"); + if (str != NULL) { + /* avoid doing htons() again and again */ + port = htons((ushort)simple_strtol(str, NULL, 10)); + cachedNumbers[TFTP_SRC_PORT] = port; + } else + /* this can never be a valid port number */ + cachedNumbers[TFTP_SRC_PORT] = (ulong)-1; + str = getenv("tftpdstp"); + if (str != NULL) { + /* avoid doing htons() again and again */ + port = htons((ushort)simple_strtol(str, NULL, 10)); + cachedNumbers[TFTP_DST_PORT] = port; + } else + /* this is the default value */ + cachedNumbers[TFTP_DST_PORT] = htons(WELL_KNOWN_PORT); + /* already in network order */ + cachedNumbers[NETCONS_PORT] = get_netcons_port(); + if (verbose) { + dprintf("\nIP Number Initialization:\n"); + dprintf(" ip address %08lx\n", cachedNumbers[IP_ADDR]); + dprintf(" server ip address %08lx\n", + cachedNumbers[IP_SERVER]); + dprintf(" tftp client port %ld\n", + cachedNumbers[TFTP_SRC_PORT]); + dprintf(" tftp server port %ld\n", + cachedNumbers[TFTP_DST_PORT]); + dprintf(" netcons port %ld\n", + cachedNumbers[NETCONS_PORT]); + dprintf(" slot number (hex) %02x\n", keymile_slot); + } +} + +static void keymile_hdlc_enet_doarp(volatile void *packet, int len) +{ + ARP_t *arp; + IPaddr_t src_ip; /* U-Boot's IP */ + IPaddr_t dest_ip; /* the mgcoge's IP */ + unsigned char *packet_copy = malloc(len); + + /* + * Handling an ARP request means that a new transfer has started. + * Update our cached parameters now. + */ + initCachedNumbers(0); /* may reinit port numbers */ + + /* special handling required for ARP */ + arp = (ARP_t *)(packet + ETHER_HDR_SIZE); + /* + * XXXX + * This is pretty dirty! NetReceive only uses + * a few fields when handling an ARP reply, so + * we only modify those here. This could + * result in catastrophic failure at a later + * time if the handler is modified! + */ + arp->ar_op = htons(ARPOP_REPLY); + /* save his/our IP */ + src_ip = NetReadIP(&arp->ar_data[6]); + dest_ip = NetReadIP(&arp->ar_data[16]); + /* copy target IP to source IP */ + NetCopyIP(&arp->ar_data[6], &dest_ip); + /* copy our IP to the right place */ + NetCopyIP(&arp->ar_data[16], &src_ip); + /* always use 0x7f as the MAC for the coge */ + arp->ar_data[0] = HDLC_UACUA; + /* + * copy the packet + * if NetReceive wants to write to stdout, it may overwrite packet + * especially if stdout is set to nc! + * + * However, if the malloc() above fails then we can still try the + * original packet, rather than causing the transfer to fail. + */ + if (packet_copy != NULL) { + memcpy(packet_copy, (char *)packet, len); + NetReceive(packet_copy, len); + free(packet_copy); + } else + NetReceive(packet, len); +} + +/* + * NOTE all callers ignore the returned value! + * At the moment this only handles ARP Requests, TFTP and NETCONSOLE. + */ +static int keymile_hdlc_enet_send(struct eth_device *dev, volatile void *packet, + int len) +{ + int j; + uint data_addr; + int data_len; + struct icn_hdr header; + struct icn_frame *frame; + Ethernet_t *et; + ARP_t *arp; + IP_t *ip; + + if (len > (MAX_FRAME_LENGTH - sizeof(header))) + return -1; + + frame = NULL; + et = NULL; + arp = NULL; + ip = NULL; + + j = 0; + while ((rtx->txbd.cbd_sc & BD_SC_READY) && (j < TOUT_LOOP)) { + /* will also trigger Wd if needed, but maybe too often */ + udelay(1); + j++; + } + if (j >= TOUT_LOOP) { + dprintf("TX not ready sc %x\n", rtx->txbd.cbd_sc); + return -1; + } + + /* + * First check for an ARP Request since this requires special handling. + */ + if (len >= (ARP_HDR_SIZE + ETHER_HDR_SIZE)) { + et = (Ethernet_t *)packet; + arp = (ARP_t *)(((char *)et) + ETHER_HDR_SIZE); + /* ARP and REQUEST? */ + if (et->et_protlen == PROT_ARP && + arp->ar_op == htons(ARPOP_REQUEST)) { + /* just short-circuit the request on the U-Boot side */ + keymile_hdlc_enet_doarp(packet, len); + return 0; + } + } + + /* + * GJ - I suppose the assumption here that len will always be + * > INET_HDR_SIZE is alright as long as the network stack + * isn't changed. + * Do not send INET header. + */ + data_len = len + sizeof(header) - INET_HDR_SIZE; + frame = (struct icn_frame *) (((char *)packet) + INET_HDR_SIZE - + sizeof(header)); + +#ifdef TEST_TX + printf("frame: %08x, ", frame); + hexdump((unsigned char *)packet, data_len + INET_HDR_SIZE); +#endif + + data_addr = (uint)frame; + if (len >= (IP_HDR_SIZE + ETHER_HDR_SIZE)) + ip = (IP_t *)(packet + ETHER_HDR_SIZE); + /* Is it TFTP? TFTP always uses UDP and the cached dport */ + if (ip != NULL && ip->ip_p == IPPROTO_UDP && ip->udp_dst == + (ushort)cachedNumbers[TFTP_DST_PORT]) { + /* just in case the port wasn't set in the environment */ + if (cachedNumbers[TFTP_SRC_PORT] == (ulong)-1) + cachedNumbers[TFTP_SRC_PORT] = ip->udp_src; + frame->hdr.application = MGS_TFTP; + } + /* + * Is it NETCONSOLE? NETCONSOLE always uses UDP. + */ + else if (ip != NULL && ip->ip_p == IPPROTO_UDP + && ip->udp_dst == (ushort)cachedNumbers[NETCONS_PORT]) { + frame->hdr.application = MGS_NETCONS; + } else { + /* reject unknown packets */ + /* may do some check on frame->hdr.application */ + dprintf("Unknown packet type in %s, rejected\n", + __func__); + return -1; + } + /* + * Could extract the target's slot ID from its MAC here, + * but u-boot only wants to talk to the active server. + * + * avoid setting new source address when moving to another slot + */ + frame->hdr.src_addr = keymile_slot; + frame->hdr.dest_addr = HDLC_UACUA; +#ifdef TEST_TX + { + dprintf("TX: "); + hexdump((unsigned char *)data_addr, data_len); + } +#endif + + flush_cache(data_addr, data_len); + rtx->txbd.cbd_bufaddr = data_addr; + rtx->txbd.cbd_datlen = data_len; + rtx->txbd.cbd_sc |= (BD_SC_READY | BD_SC_TC | BD_SC_LAST | BD_SC_WRAP); + + while ((rtx->txbd.cbd_sc & BD_SC_READY) && (j < TOUT_LOOP)) { + /* will also trigger Wd if needed, but maybe too often */ + udelay(1); + j++; + } + if (j >= TOUT_LOOP) + dprintf("TX timeout\n"); +#ifdef ET_DEBUG + dprintf("cycles: %d status: %x\n", j, rtx->txbd.cbd_sc); +#endif + j = (rtx->txbd.cbd_sc & BD_SC_STATS); /* return only status bits */ + return j; +} + +/* + * During a receive, the RxIdx points to the current incoming buffer. + * When we update through the ring, if the next incoming buffer has + * not been given to the system, we just set the empty indicator, + * effectively tossing the packet. + */ +static int keymile_hdlc_enet_recv(struct eth_device *dev) +{ + int length; + unsigned char app; + struct icn_frame *fp; + Ethernet_t *ep; + IP_t *ip; + + for (;;) { + if (rtx->rxbd[keymile_rxIdx].cbd_sc & BD_SC_EMPTY) { + length = -1; + break; /* nothing received - leave for() loop */ + } + + length = rtx->rxbd[keymile_rxIdx].cbd_datlen; +#ifdef TEST_RX + dprintf("packet %d bytes long\n", length); +#endif + + /* + * BD_SC_BR -> LG bit + * BD_SC_FR -> NO bit + * BD_SC_PR -> AB bit + * BD_SC_NAK -> CR bit + * 0x80 -> DE bit + */ + if (rtx->rxbd[keymile_rxIdx].cbd_sc & BD_SC_STATS) { +#ifdef ET_DEBUG + dprintf("err: %x\n", rtx->rxbd[keymile_rxIdx].cbd_sc); +#endif + } else if (length > MAX_FRAME_LENGTH) { /* can't happen */ +#ifdef ET_DEBUG + dprintf("err: packet too big\n"); +#endif + } else { + fp = (struct icn_frame *)(MyRxPackets[keymile_rxIdx] + + INET_HDR_ALIGN - INET_HDR_SIZE); +#ifdef TEST_RX + dprintf("RX %d: ", keymile_rxIdx); + hexdump((unsigned char *)MyRxPackets[keymile_rxIdx], + INET_HDR_ALIGN + INET_HDR_SIZE + 4); +#endif + /* copy icn header to the beginning */ + memcpy(fp, ((char *)fp + INET_HDR_SIZE), + sizeof(struct icn_hdr)); + app = fp->hdr.application; + if (app == MGS_NETCONS || app == MGS_TFTP) { + struct icn_hdr *ih = &fp->hdr; + unsigned char icn_src_addr = ih->src_addr; + unsigned char icn_dest_addr = ih->dest_addr; + + /* + * expand header by INET_HDR_SIZE + */ + length += INET_HDR_SIZE; + /* initalize header */ + memset((char *)fp->data, 0x00, INET_HDR_SIZE); + ep = (Ethernet_t *)fp->data; + /* set MACs */ + ep->et_dest[0] = icn_dest_addr; + ep->et_src[0] = icn_src_addr; + ep->et_protlen = htons(PROT_IP); + /* set ip stuff */ + ip = (IP_t *)(fp->data + ETHER_HDR_SIZE); + /* set ip addresses */ + ip->ip_src = cachedNumbers[IP_SERVER]; + ip->ip_dst = cachedNumbers[IP_ADDR]; + /* ip length */ + ip->ip_len = htons(length - ETHER_HDR_SIZE - + REMOVE); + /* ip proto */ + ip->ip_p = IPPROTO_UDP; + switch (app) { + case MGS_TFTP: + /* swap src/dst port numbers */ + ip->udp_src = (ushort) + cachedNumbers[TFTP_DST_PORT]; + ip->udp_dst = (ushort) + cachedNumbers[TFTP_SRC_PORT]; + ip->udp_len = ip->ip_len - + IP_HDR_SIZE_NO_UDP; + ip->udp_xsum = 0; + break; + case MGS_NETCONS: + ip->udp_src = (ushort) + cachedNumbers[NETCONS_PORT]; + /* + * in drivers/net/netconsole.c src port + * equals dest port + */ + ip->udp_dst = ip->udp_src; + ip->udp_len = ip->ip_len - + IP_HDR_SIZE_NO_UDP; + ip->udp_xsum = 0; + break; + } + /* ip version */ + ip->ip_hl_v = (0x40) | (0x0f & + (IP_HDR_SIZE_NO_UDP / 4)); + ip->ip_tos = 0; + ip->ip_id = 0; + /* flags, fragment offset */ + ip->ip_off = htons(0x4000); + ip->ip_ttl = 255; /* time to live */ + /* have to fixup the checksum */ + ip->ip_sum = ~NetCksum((uchar *)ip, + IP_HDR_SIZE_NO_UDP / 2); + /* + * Pass the packet up to the protocol layers + * but remove dest_addr, src_addr, application + * and the CRC. + */ +#ifdef TEST_RX + hexdump((unsigned char *)fp->data, + INET_HDR_SIZE + 4); +#endif + NetReceive(fp->data, length - REMOVE); + } else { + /* + * the other application types are not yet + * supported by u-boot. + */ + /* normally drop it */ +#ifdef TEST_NO + /* send it anyway */ + fp = (struct icn_frame *) + (MyRxPackets[keymile_rxIdx] + + INET_HDR_ALIGN); + NetReceive(fp->data, length - REMOVE); +#endif + } + } + + /* Give the buffer back to the SCC. */ + rtx->rxbd[keymile_rxIdx].cbd_datlen = 0; + + /* wrap around buffer index when necessary */ + if ((keymile_rxIdx + 1) >= HDLC_PKTBUFSRX) { + rtx->rxbd[HDLC_PKTBUFSRX - 1].cbd_sc = + (BD_SC_WRAP | BD_SC_EMPTY); + keymile_rxIdx = 0; + } else { + rtx->rxbd[keymile_rxIdx].cbd_sc = BD_SC_EMPTY; + keymile_rxIdx++; + } + } + return length; +} + +#ifdef TEST_IT +/* simple send test routine */ +int hdlc_enet_stest(struct cmd_tbl_s *a, int b, int c, char **d) +{ + unsigned char pkt[2]; + int ret; + + dprintf("enter stest\n"); + /* may have to initialize things */ + if (seth->state != ETH_STATE_ACTIVE) { + /* the bd_t* is not used */ + if (seth->init(seth, NULL) >= 0) + seth->state = ETH_STATE_ACTIVE; + } + pkt[0] = 0xea; + pkt[1] = 0xae; + ret = keymile_hdlc_enet_send(seth, pkt, 2); + dprintf("return from send %x\n", ret); + dprintf("exit stest\n"); + return ret; +} +U_BOOT_CMD( + stest, 1, 1, hdlc_enet_stest, + "stest - simple send test for hdlc_enet\n", + "no arguments\n" +); +/* simple receive test routine */ +int hdlc_enet_rtest(struct cmd_tbl_s *a, int b, int c, char **d) +{ + int ret; + + dprintf("enter rtest\n"); + /* may have to initialize things */ + if (seth->state != ETH_STATE_ACTIVE) { + /* the bd_t* is not used */ + if (seth->init(seth, NULL) >= 0) + seth->state = ETH_STATE_ACTIVE; + } + ret = keymile_hdlc_enet_recv(seth); + dprintf("return from recv %x\n", ret); + dprintf("exit rtest\n"); + return ret; +} +U_BOOT_CMD( + rtest, 1, 1, hdlc_enet_rtest, + "rtest - simple receive test for hdlc_enet\n", + "no arguments\n" +); +#endif + +#endif /* CONFIG_KEYMILE_HDLC_ENET */ diff --git a/board/keymile/common/keymile_hdlc_enet.h b/board/keymile/common/keymile_hdlc_enet.h new file mode 100644 index 000000000..965bd5a4b --- /dev/null +++ b/board/keymile/common/keymile_hdlc_enet.h @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _KEYMILE_HDLC_ENET_H_ +#define _KEYMILE_HDLC_ENET_H_ + +/* Unfortuantely, we have do this to get the flag defines in the cbd_t */ +#ifdef CONFIG_MGSUVD +#include <commproc.h> +#endif +#ifdef CONFIG_MGCOGE +#include <mpc8260.h> +#include <asm/cpm_8260.h> +#endif + +/* + * Defines for the ICN protocol used for communication over HDLC + * on the backplane between MGSUVDs and MGCOGEs. + */ + +/* + * MAC which is reserved for communication (0x00 - 0xff in the last byte, + * which is the slot number) + */ + +/* + * A DLL frame looks like this: + * 8 bit | 8 bit | 8 bit | 8 bit | n * 8 bit| 16 bit| 8 bit + * opening| destination| source | application| data | FCS | closing + * flag | address | address| | | | flag + * (HW) (APP) (APP) (APP) (APP) (HW) (HW) + */ + +/* + * The opening flag, the FCS and the closing flag are set by the hardware so + * they are not reflected in this struct. + */ +struct icn_hdr { + unsigned char dest_addr; + unsigned char src_addr; + unsigned char application; +} __attribute__((packed)); + +#define ICNHDR_LEN (sizeof(struct icn_hdr)) +#define CRC_LEN (sizeof(short)) +/* bytes to remove from packet before sending it upstream */ +#define REMOVE (ICNHDR_LEN + CRC_LEN) + +struct icn_frame { + struct icn_hdr hdr; + unsigned char data[0]; /* a place holder */ +} __attribute__((packed)); + +/* Address field */ +#define HDLC_UUA 0x00 /* Unicast Unit Address */ +#define HDLC_UUA_MASK 0x3f /* the last 6 bits contain the slot number */ +#define SET_HDLC_UUA(x) ((HDLC_UUA | ((x) & HDLC_UUA_MASK))) +#define HDLC_UACUA 0x7f /* Unicast Active Control Unit Address */ +#define HDLC_BCAST 0xff /* broadcast */ + +/* Application field */ +#define MGS_UUSP 0x00 +#define MGS_UREP 0x01 +#define MGS_IUP 0x02 +#define MGS_UTA 0x03 +#define MGS_MDS 0x04 +#define MGS_ITIME 0x05 +/* added by DENX */ +#define MGS_NETCONS 0x06 /* netconsole */ +#define MGS_TFTP 0x07 + +/* Useful defines for buffer sizes, etc. */ +#define HDLC_PKTBUFSRX 32 +#define MAX_FRAME_LENGTH 1500 /* ethernet frame size */ + /* 14 + 28 */ +#define INET_HDR_SIZE (ETHER_HDR_SIZE + IP_HDR_SIZE) +#define INET_HDR_ALIGN (((INET_HDR_SIZE + PKTALIGN - 1) / PKTALIGN) * PKTALIGN) +/* INET_HDR_SIZE is stripped off */ +#define PKT_MAXBLR_SIZE (MAX_FRAME_LENGTH + INET_HDR_ALIGN) + +/* + * It is too slow to read always the port numbers and IP addresses from the + * string variables. + * cachedNumbers is meant to cache it. + * THIS IS ONLY A SPEED IMPROVEMENT! + */ +enum { + IP_ADDR = 0, /* getenv_IPaddr("serverip"); */ + IP_SERVER, /* getenv_IPaddr("ipaddr"); */ + TFTP_SRC_PORT, /* simple_strtol(getenv("tftpsrcp"), NULL, 10); */ + TFTP_DST_PORT, /* simple_strtol(getenv("tftpdstp"), NULL, 10); */ + NETCONS_PORT, /* simple_strtol(getenv("ncip"), NULL, 10); */ + CACHEDNUMBERS +}; + +#define WELL_KNOWN_PORT 69 /* Well known TFTP port # */ + +/* define this to create a test commend (htest) */ +#undef TEST_IT +#ifdef TEST_IT +/* have to save a copy of the eth_device for the test command's use */ +struct eth_device *seth; +#endif +/* define this for outputting of received packets */ +#undef TEST_RX +/* define this for outputting of packets being sent */ +#undef TEST_TX + +#endif /* _KEYMILE_HDLC_ENET_H_ */ diff --git a/board/mgcoge/Makefile b/board/keymile/mgcoge/Makefile index d4087ccbb..2774a702b 100644 --- a/board/mgcoge/Makefile +++ b/board/keymile/mgcoge/Makefile @@ -22,10 +22,14 @@ # include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS := $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \ + mgcoge_hdlc_enet.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/mgcoge/config.mk b/board/keymile/mgcoge/config.mk index 143bc9f76..143bc9f76 100644 --- a/board/mgcoge/config.mk +++ b/board/keymile/mgcoge/config.mk diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c new file mode 100644 index 000000000..3683417f5 --- /dev/null +++ b/board/keymile/mgcoge/mgcoge.c @@ -0,0 +1,349 @@ +/* + * (C) Copyright 2007 - 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8260.h> +#include <ioports.h> +#include <malloc.h> +#include <asm/io.h> + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +#include <i2c.h> +#endif + +extern int ivm_read_eeprom (void); +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */ + /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */ + /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */ + /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */ + /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */ + /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */ + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */ + /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */ + /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */ + /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */ + /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */ + /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */ + /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */ + /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ + /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */ + /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */ + /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */ + /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */ + /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */ + /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */ + /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */ + /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */ + /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */ + /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */ + /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */ + /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */ + /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */ + /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */ + /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ + /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ + /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ + /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */ + /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ + /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */ + /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */ + /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else + /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */ +#endif + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff))/* / 2*/; + + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size ((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +phys_size_t initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + + long psize; + + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; + +#ifndef CONFIG_SYS_RAMBOOT + /* 60x SDRAM setup: + */ + psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1, + (uchar *) CONFIG_SYS_SDRAM_BASE); +#endif /* CONFIG_SYS_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +int checkboard(void) +{ + puts ("Board: mgcoge\n"); + + return 0; +} + +/* + * Early board initalization. + */ +int board_early_init_r (void) +{ + /* setup the UPIOx */ + out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0); + out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x15); + return 0; +} + +int hush_init_var (void) +{ + ivm_read_eeprom (); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +extern int fdt_set_node_and_value (void *blob, + char *nodename, + char *regname, + void *var, + int size); + +/* + * update "memory" property in the blob + */ +void ft_blob_update (void *blob, bd_t *bd) +{ + ulong memory_data[2] = {0}; + ulong flash_data[8] = {0}; + + memory_data[0] = cpu_to_be32 (bd->bi_memstart); + memory_data[1] = cpu_to_be32 (bd->bi_memsize); + fdt_set_node_and_value (blob, "/memory", "reg", memory_data, + sizeof (memory_data)); + + /* update Flash addr, size */ + flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE); + flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE); + flash_data[4] = cpu_to_be32 (5); + flash_data[5] = cpu_to_be32 (0); + flash_data[6] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1); + flash_data[7] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE_1); + fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data, + sizeof (flash_data)); + /* MAC addr */ + fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address", + bd->bi_enetaddr, sizeof (u8) * 6); +} + +void ft_board_setup (void *blob, bd_t *bd) +{ + ft_cpu_setup (blob, bd); + ft_blob_update (blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/keymile/mgcoge/mgcoge_hdlc_enet.c b/board/keymile/mgcoge/mgcoge_hdlc_enet.c new file mode 100644 index 000000000..34f04f562 --- /dev/null +++ b/board/keymile/mgcoge/mgcoge_hdlc_enet.c @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * Based in part on cpu/mpc8260/ether_scc.c. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <net.h> + +#ifdef CONFIG_KEYMILE_HDLC_ENET + +#include "../common/keymile_hdlc_enet.h" + +char keymile_slot; /* our slot number in the backplane */ + +/* + * Since, except during initialization, ethact is always HDLC ETHERNET + * while we're in the driver, just use serial_printf() everywhere for + * output. This avoids possible conflicts when netconsole is being + * used. + */ +#define dprintf(fmt, args...) serial_printf(fmt, ##args) + +static int already_inited; + +/* + * SCC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ +typedef volatile struct CommonBufferDescriptor { + cbd_t txbd; /* Tx BD */ + cbd_t rxbd[HDLC_PKTBUFSRX]; /* Rx BD */ +} RTXBD; + +static RTXBD *rtx; + +int keymile_hdlc_enet_init(struct eth_device *, bd_t *); +void keymile_hdlc_enet_halt(struct eth_device *); +extern void keymile_hdlc_enet_init_bds(RTXBD *); +extern void initCachedNumbers(int); + +/* Use SCC1 */ +#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE +#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK +#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\ + CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK) +#define CMXSCR_VALUE (CMXSCR_RS1CS_CLK11|CMXSCR_TS1CS_CLK11) +#define MGC_PROFF_HDLC PROFF_SCC1 +#define MGC_SCC_HDLC 0 /* Index, not number! */ + +int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis) +{ + /* int i; */ + uint dpr; + /* volatile cbd_t *bdp; */ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + volatile cpm8260_t *cp = &(im->im_cpm); + volatile scc_t *sccp; + volatile scc_hdlc_t *hpr; + volatile iop8260_t *iop; + + if (already_inited) + return 0; + + hpr = (scc_hdlc_t *)(&im->im_dprambase[MGC_PROFF_HDLC]); + sccp = (scc_t *)(&im->im_scc[MGC_SCC_HDLC]); + iop = &im->im_ioport; + + /* + * Disable receive and transmit just in case. + */ + sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + /* + * Avoid exhausting DPRAM, which would cause a panic. + */ + if (rtx == NULL) { + /* dpr is an offset into dpram */ + dpr = m8260_cpm_dpalloc(sizeof(RTXBD), 8); + rtx = (RTXBD *)&im->im_dprambase[dpr]; + } + + /* We need the slot number for addressing. */ + keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE + + CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK; + /* + * Be consistent with the Linux driver and set + * only enetaddr[0]. + * + * Always add 1 to the slot number so that + * there are no problems with an ethaddr which + * is all 0s. This should be acceptable because + * a board should never have a slot number of 255, + * which is the broadcast address. The HDLC addressing + * uses only the slot number. + */ + dev->enetaddr[0] = keymile_slot + 1; +#ifdef TEST_IT + dprintf("slot %d\n", keymile_slot); +#endif + + /* use pd30, pd31 pins for TXD1, RXD1 respectively */ + iop->iop_ppard |= (0x80000000 >> 30) | (0x80000000 >> 31); + iop->iop_pdird |= (0x80000000 >> 30); + iop->iop_psord |= (0x80000000 >> 30); + + /* use pc21 as CLK11 */ + iop->iop_pparc |= (0x80000000 >> 21); + iop->iop_pdirc &= ~(0x80000000 >> 21); + iop->iop_psorc &= ~(0x80000000 >> 21); + + /* use pc15 as CTS1 */ + iop->iop_pparc |= (0x80000000 >> 15); + iop->iop_pdirc &= ~(0x80000000 >> 15); + iop->iop_psorc &= ~(0x80000000 >> 15); + + /* + * SI clock routing + * use CLK11 + * this also connects SCC1 to NMSI + */ + im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr & ~CMXSCR_MASK) | + CMXSCR_VALUE; + + /* keymile_rxIdx = 0; */ + + /* + * Initialize function code registers for big-endian. + */ + hpr->sh_genscc.scc_rfcr = CPMFCR_EB; + hpr->sh_genscc.scc_tfcr = CPMFCR_EB; + + /* + * Set maximum bytes per receive buffer. + */ + hpr->sh_genscc.scc_mrblr = MAX_FRAME_LENGTH; + + /* Setup CRC generator values for HDLC */ + hpr->sh_cmask = 0x0000F0B8; + hpr->sh_cpres = 0x0000FFFF; + + /* Initialize all error counters to 0 */ + hpr->sh_disfc = 0; + hpr->sh_crcec = 0; + hpr->sh_abtsc = 0; + hpr->sh_nmarc = 0; + hpr->sh_retrc = 0; + + /* Set maximum frame length size */ + hpr->sh_mflr = MAX_FRAME_LENGTH; + + /* set to 1 for per frame processing change later if needed */ + hpr->sh_rfthr = 1; + + hpr->sh_hmask = 0xff; + + hpr->sh_haddr2 = SET_HDLC_UUA(keymile_slot); + hpr->sh_haddr3 = hpr->sh_haddr2; + hpr->sh_haddr4 = hpr->sh_haddr2; + /* broadcast */ + hpr->sh_haddr1 = HDLC_BCAST; + + hpr->sh_genscc.scc_rbase = (unsigned int) &rtx->rxbd[0]; + hpr->sh_genscc.scc_tbase = (unsigned int) &rtx->txbd; + +#if 0 + /* + * Initialize the buffer descriptors. + */ + bdp = &rtx->txbd; + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; + bdp->cbd_sc = BD_SC_WRAP; + + /* + * Setup RX packet buffers, aligned correctly. + * Borrowed from net/net.c. + */ + MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1); + MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN; + for (i = 1; i < HDLC_PKTBUFSRX; i++) + MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE; + + bdp = &rtx->rxbd[0]; + for (i = 0; i < HDLC_PKTBUFSRX; i++) { + bdp->cbd_sc = BD_SC_EMPTY; + /* Leave space at the start for INET header. */ + bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] + + INET_HDR_ALIGN); + bdp++; + } + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; +#else + keymile_hdlc_enet_init_bds(rtx); +#endif + + /* Let's re-initialize the channel now. We have to do it later + * than the manual describes because we have just now finished + * the BD initialization. + */ + cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK, + 0, CPM_CR_INIT_TRX) | CPM_CR_FLG; + while (cp->cp_cpcr & CPM_CR_FLG); + + sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC; + /* CTSS=1 */ + sccp->scc_gsmrh = SCC_GSMRH_CTSS; + /* NOF=0, RTE=1, DRT=0, BUS=1 */ + sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10)); + +/* loopback for local testing */ +#ifdef GJTEST + dprintf("LOOPBACK!\n"); + sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP; +#endif + + /* + * Disable all interrupts and clear all pending + * events. + */ + sccp->scc_sccm = 0; + sccp->scc_scce = 0xffff; + + /* + * And last, enable the transmit and receive processing. + */ + sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name, + MGC_SCC_HDLC + 1); + + /* + * We may not get an ARP packet because ARP was already done on + * a different interface, so initialize the cached values now. + */ + initCachedNumbers(1); + + already_inited = 1; + + return 0; +} + +void keymile_hdlc_enet_halt(struct eth_device *dev) +{ +#if 0 /* just return, but keep this for reference */ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + /* maybe should do a graceful stop here? */ + immr->im_scc[MGC_SCC_HDLC].scc_gsmrl &= + ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); +#endif +} + +#endif /* CONFIG_MGCOGE_HDLC_ENET */ diff --git a/board/keymile/mgsuvd/Makefile b/board/keymile/mgsuvd/Makefile new file mode 100644 index 000000000..2c5732d16 --- /dev/null +++ b/board/keymile/mgsuvd/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2007 +# Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \ + mgsuvd_hdlc_enet.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mgsuvd/config.mk b/board/keymile/mgsuvd/config.mk index 8625cea56..8625cea56 100644 --- a/board/mgsuvd/config.mk +++ b/board/keymile/mgsuvd/config.mk diff --git a/board/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c index c51ea7e76..3726acf4a 100644 --- a/board/mgsuvd/mgsuvd.c +++ b/board/keymile/mgsuvd/mgsuvd.c @@ -20,18 +20,16 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ - -#if 0 -#define DEBUG -#endif - #include <common.h> #include <mpc8xx.h> +#include <asm/io.h> #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif +extern int ivm_read_eeprom (void); + DECLARE_GLOBAL_DATA_PTR; const uint sdram_table[] = @@ -68,7 +66,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -81,7 +79,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* * The following value is used as an address (i.e. opcode) for @@ -96,17 +94,17 @@ phys_size_t initdram (int board_type) * | +----------- Operating Mode = Standard * +-------------- Write Burst Mode = Programmed Burst Length */ - memctl->memc_mar = CFG_MAR; + memctl->memc_mar = CONFIG_SYS_MAR; /* * Map controller banks 1 to the SDRAM banks 1 at * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mbmr = CFG_MBMR & (~(MBMR_PTBE)); /* no refresh yet */ + memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE)); /* no refresh yet */ udelay (200); @@ -140,88 +138,67 @@ phys_size_t initdram (int board_type) int board_early_init_r(void) { /* setup the UPIOx */ - *(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0; - *(char *)(CFG_PIGGY_BASE + 0x03) = 0x35; + out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x02), 0xc0); + out_8((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x03), 0x35); + return 0; +} + +int hush_init_var (void) +{ + ivm_read_eeprom (); return 0; } #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +extern int fdt_set_node_and_value (void *blob, + char *nodename, + char *regname, + void *var, + int size); + /* * update "memory" property in the blob */ -void ft_blob_update(void *blob, bd_t *bd) +void ft_blob_update (void *blob, bd_t *bd) { - int ret, nodeoffset = 0; ulong brg_data[1] = {0}; ulong memory_data[2] = {0}; ulong flash_data[4] = {0}; - memory_data[0] = cpu_to_be32(bd->bi_memstart); - memory_data[1] = cpu_to_be32(bd->bi_memsize); - - nodeoffset = fdt_path_offset (blob, "/memory"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, - sizeof(memory_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /memory/reg " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /memory node " - "err:%s\n", fdt_strerror(nodeoffset)); - } - - flash_data[2] = cpu_to_be32(bd->bi_flashstart); - flash_data[3] = cpu_to_be32(bd->bi_flashsize); - nodeoffset = fdt_path_offset (blob, "/localbus"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, - sizeof(flash_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /localbus/ranges " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /localbus node " - "err:%s\n", fdt_strerror(nodeoffset)); - } + memory_data[0] = cpu_to_be32 (bd->bi_memstart); + memory_data[1] = cpu_to_be32 (bd->bi_memsize); + fdt_set_node_and_value (blob, "/memory", "reg", memory_data, + sizeof (memory_data)); + + flash_data[2] = cpu_to_be32 (bd->bi_flashstart); + flash_data[3] = cpu_to_be32 (bd->bi_flashsize); + fdt_set_node_and_value (blob, "/localbus", "ranges", flash_data, + sizeof (flash_data)); + /* BRG */ - brg_data[0] = cpu_to_be32(bd->bi_busfreq); - nodeoffset = fdt_path_offset (blob, "/soc/cpm"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data, - sizeof(brg_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /soc/cpm node " - "err:%s\n", fdt_strerror(nodeoffset)); - } - /* MAC Adresse */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, - sizeof(uchar) * 6); - if (ret < 0) - printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /soc/cpm/ethernet node " - "err:%s\n", fdt_strerror(nodeoffset)); - } + brg_data[0] = cpu_to_be32 (bd->bi_busfreq); + fdt_set_node_and_value (blob, "/soc/cpm", "brg-frequency", brg_data, + sizeof (brg_data)); + + /* MAC adr */ + fdt_set_node_and_value (blob, "/soc/cpm/ethernet", "mac-address", + bd->bi_enetaddr, sizeof (u8) * 6); } void ft_board_setup(void *blob, bd_t *bd) { - ft_cpu_setup( blob, bd); - ft_blob_update(blob, bd); + ft_cpu_setup (blob, bd); + ft_blob_update (blob, bd); } #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + +int i2c_soft_read_pin (void) +{ + int val; + + *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF; + udelay(1); + val = *(unsigned char *)(I2C_BASE_PORT); + + return ((val & SDA_BIT) == SDA_BIT); +} diff --git a/board/keymile/mgsuvd/mgsuvd_hdlc_enet.c b/board/keymile/mgsuvd/mgsuvd_hdlc_enet.c new file mode 100644 index 000000000..9b93131f0 --- /dev/null +++ b/board/keymile/mgsuvd/mgsuvd_hdlc_enet.c @@ -0,0 +1,278 @@ +/* + * (C) Copyright 2008 + * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de. + * + * Based in part on cpu/mpc8xx/scc.c. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> /* commproc.h is included here */ +#include <malloc.h> +#include <net.h> + +#ifdef CONFIG_KEYMILE_HDLC_ENET + +#include "../common/keymile_hdlc_enet.h" + +char keymile_slot; /* our slot number in the backplane */ + +/* + * Since, except during initialization, ethact is always HDLC ETHERNET + * while we're in the driver, just use serial_printf() everywhere for + * output. This avoids possible conflicts when netconsole is being + * used. + */ +#define dprintf(fmt, args...) serial_printf(fmt, ##args) + +static int already_inited; + +/* + * SCC Ethernet Tx and Rx buffer descriptors allocated at the + * immr->udata_bd address on Dual-Port RAM + * Provide for Double Buffering + */ +typedef volatile struct CommonBufferDescriptor { + cbd_t txbd; /* Tx BD */ + cbd_t rxbd[HDLC_PKTBUFSRX]; /* Rx BD */ +} RTXBD; + +static RTXBD *rtx; + +int keymile_hdlc_enet_init(struct eth_device *, bd_t *); +void keymile_hdlc_enet_halt(struct eth_device *); +extern void keymile_hdlc_enet_init_bds(RTXBD *); +extern void initCachedNumbers(int); + +/* Use SCC4 */ +#define MGS_CPM_CR_HDLC CPM_CR_CH_SCC4 +#define MGS_PROFF_HDLC PROFF_SCC4 +#define MGS_SCC_HDLC 3 /* Index, not number! */ + +int keymile_hdlc_enet_init(struct eth_device *dev, bd_t *bis) +{ + /* int i; */ + /* volatile cbd_t *bdp; */ + volatile cpm8xx_t *cp; + volatile scc_t *sccp; + volatile hdlc_pram_t *hpr; + volatile iop8xx_t *iop; + + if (already_inited) + return 0; + + cp = (cpm8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm); + hpr = (hdlc_pram_t *)(&cp->cp_dparam[MGS_PROFF_HDLC]); + sccp = (volatile scc_t *)(&cp->cp_scc[MGS_SCC_HDLC]); + iop = (iop8xx_t *)&(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport); + + /* + * Disable receive and transmit just in case. + */ + sccp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); + +#ifndef CONFIG_SYS_ALLOC_DPRAM +#error "CONFIG_SYS_ALLOC_DPRAM must be defined" +#else + /* + * Avoid exhausting DPRAM, which would cause a panic. + * Actually this isn't really necessary, but leave it here + * for safety's sake. + */ + if (rtx == NULL) { + rtx = (RTXBD *) (cp->cp_dpmem + + dpram_alloc_align(sizeof(RTXBD), 8)); + if (rtx == (RTXBD *)CPM_DP_NOSPACE) + return -1; + memset((void *)rtx, 0, sizeof(RTXBD)); + } +#endif /* !CONFIG_SYS_ALLOC_DPRAM */ + + /* We need the slot number for addressing. */ + keymile_slot = *(char *)(CONFIG_SYS_SLOT_ID_BASE + + CONFIG_SYS_SLOT_ID_OFF) & CONFIG_SYS_SLOT_ID_MASK; + /* + * Be consistent with the Linux driver and set + * only enetaddr[0]. + * + * Always add 1 to the slot number so that + * there are no problems with an ethaddr which + * is all 0s. This should be acceptable because + * a board should never have a slot number of 255, + * which is the broadcast address. The HDLC addressing + * uses only the slot number. + */ + dev->enetaddr[0] = keymile_slot + 1; + +#ifdef TEST_IT + dprintf("slot %d\n", keymile_slot); +#endif + + /* use pa8, pa9 pins for TXD4, RXD4 respectively */ + iop->iop_papar |= ((0x8000 >> 8) | (0x8000 >> 9)); + iop->iop_padir &= ~((0x8000 >> 8) | (0x8000 >> 9)); + iop->iop_paodr &= ~((0x8000 >> 8) | (0x8000 >> 9)); + + /* also use pa0 as CLK8 */ + iop->iop_papar |= 0x8000; + iop->iop_padir &= ~0x8000; + iop->iop_paodr &= ~0x8000; + + /* use pc5 as CTS4 */ + iop->iop_pcpar &= ~(0x8000 >> 5); + iop->iop_pcdir &= ~(0x8000 >> 5); + iop->iop_pcso |= (0x8000 >> 5); + + /* + * SI clock routing + * use CLK8 + * this also connects SCC4 to NMSI + */ + cp->cp_sicr = (cp->cp_sicr & ~0xff000000) | 0x3f000000; + + /* keymile_rxIdx = 0; */ + + /* + * Initialize function code registers for big-endian. + */ + hpr->rfcr = SCC_EB; + hpr->tfcr = SCC_EB; + + /* + * Set maximum bytes per receive buffer. + */ + hpr->mrblr = MAX_FRAME_LENGTH; + + /* Setup CRC generator values for HDLC */ + hpr->c_mask = 0x0000F0B8; + hpr->c_pres = 0x0000FFFF; + + /* Initialize all error counters to 0 */ + hpr->disfc = 0; + hpr->crcec = 0; + hpr->abtsc = 0; + hpr->nmarc = 0; + hpr->retrc = 0; + + /* Set maximum frame length size */ + hpr->mflr = MAX_FRAME_LENGTH; + + /* set to 1 for per frame processing change later if needed */ + hpr->rfthr = 1; + + hpr->hmask = 0xff; + + hpr->haddr2 = SET_HDLC_UUA(keymile_slot); + hpr->haddr3 = hpr->haddr2; + hpr->haddr4 = hpr->haddr2; + /* broadcast */ + hpr->haddr1 = HDLC_BCAST; + + hpr->rbase = (unsigned int) &rtx->rxbd[0]; + hpr->tbase = (unsigned int) &rtx->txbd; + +#if 0 + /* + * Initialize the buffer descriptors. + */ + bdp = &rtx->txbd; + bdp->cbd_sc = 0; + bdp->cbd_bufaddr = 0; + bdp->cbd_sc = BD_SC_WRAP; + + /* + * Setup RX packet buffers, aligned correctly. + * Borrowed from net/net.c. + */ + MyRxPackets[0] = &MyPktBuf[0] + (PKTALIGN - 1); + MyRxPackets[0] -= (ulong)MyRxPackets[0] % PKTALIGN; + for (i = 1; i < HDLC_PKTBUFSRX; i++) + MyRxPackets[i] = MyRxPackets[0] + i * PKT_MAXBLR_SIZE; + + bdp = &rtx->rxbd[0]; + for (i = 0; i < HDLC_PKTBUFSRX; i++) { + bdp->cbd_sc = BD_SC_EMPTY; + /* Leave space at the start for INET header. */ + bdp->cbd_bufaddr = (unsigned int)(MyRxPackets[i] + + INET_HDR_ALIGN); + bdp++; + } + bdp--; + bdp->cbd_sc |= BD_SC_WRAP; +#else + keymile_hdlc_enet_init_bds(rtx); +#endif + + /* Let's re-initialize the channel now. We have to do it later + * than the manual describes because we have just now finished + * the BD initialization. + */ + cp->cp_cpcr = mk_cr_cmd(MGS_CPM_CR_HDLC, CPM_CR_INIT_TRX) | CPM_CR_FLG; + while (cp->cp_cpcr & CPM_CR_FLG); + + sccp->scc_gsmrl = SCC_GSMRL_MODE_HDLC; + /* CTSS=1 */ + sccp->scc_gsmrh = SCC_GSMRH_CTSS; + /* NOF=0, RTE=1, DRT=0, BUS=1 */ + sccp->scc_psmr = ((0x8000 >> 6) | (0x8000 >> 10)); + +/* loopback for local testing */ +#ifdef GJTEST + dprintf("LOOPBACK!\n"); + sccp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP; +#endif + + /* + * Disable all interrupts and clear all pending + * events. + */ + sccp->scc_sccm = 0; + sccp->scc_scce = 0xffff; + + /* + * And last, enable the transmit and receive processing. + */ + sccp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + + dprintf("%s: HDLC ENET Version 0.3 on SCC%d\n", dev->name, + MGS_SCC_HDLC + 1); + + /* + * We may not get an ARP packet because ARP was already done on + * a different interface, so initialize the cached values now. + */ + initCachedNumbers(1); + + already_inited = 1; + + return 0; +} + +void keymile_hdlc_enet_halt(struct eth_device *dev) +{ +#if 0 /* just return, but keep this for reference */ + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + + /* maybe should do a graceful stop here? */ + immr->im_cpm.cp_scc[MGS_SCC_HDLC].scc_gsmrl &= + ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); +#endif +} + +#endif /* CONFIG_KEYMILE_HDLC_ENET */ diff --git a/board/mgsuvd/u-boot.lds b/board/keymile/mgsuvd/u-boot.lds index 8c46e4677..5af36c97a 100644 --- a/board/mgsuvd/u-boot.lds +++ b/board/keymile/mgsuvd/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/korat/config.mk b/board/korat/config.mk index fa8374f17..73180dbd8 100644 --- a/board/korat/config.mk +++ b/board/korat/config.mk @@ -35,7 +35,7 @@ PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2 endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8CFF0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000 endif ifeq ($(perm),1) diff --git a/board/korat/init.S b/board/korat/init.S index bf8b2c808..ea43a1f89 100644 --- a/board/korat/init.S +++ b/board/korat/init.S @@ -50,27 +50,27 @@ tlbtab: * generated dynamically in the SPD DDR2 detection routine. */ -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif /* TLB-entry for PCI Memory */ - tlbentry( CFG_PCI_MEMBASE + 0x00000000, SZ_256M, - CFG_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M, + CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE + 0x10000000, SZ_256M, - CFG_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M, + CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE + 0x20000000, SZ_256M, - CFG_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M, + CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE + 0x30000000, SZ_256M, - CFG_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M, + CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for EBC */ - tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */ diff --git a/board/korat/korat.c b/board/korat/korat.c index 0d90fb31d..5ad75f74d 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size(ulong base, int banknum); @@ -46,11 +46,11 @@ ulong flash_get_size(ulong base, int banknum); void korat_buzzer(int const on) { if (on) { - out_8((u8 *) CFG_CPLD_BASE + 0x05, - in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80); } else { - out_8((u8 *) CFG_CPLD_BASE + 0x05, - in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80); } } #endif @@ -66,16 +66,16 @@ int board_early_init_f(void) extern void korat_branch_absolute(uint32_t addr); - for (mscount = 0; mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) { + for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) { udelay(1000); - if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) { + if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) { /* This call does not return. */ korat_branch_absolute( - CFG_FLASH1_TOP - 2 * CFG_ENV_SECT_SIZE - 4); + CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4); } } korat_buzzer(1); - while (!gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) + while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) udelay(1000); korat_buzzer(0); @@ -115,33 +115,33 @@ int board_early_init_f(void) * Take sim card reader and CF controller out of reset. Also enable PHY * auto-detect until board-specific PHY resets are available. */ - out_8((u8 *) CFG_CPLD_BASE + 0x02, 0xC0); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0); /* Configure the two Ethernet PHYs. For each PHY, configure for fiber * if the SFP module is present, and for copper if it is not present. */ for (eth = 0; eth < 2; ++eth) { - if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) { + if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) { /* SFP module not present: configure PHY for copper. */ /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ - out_8((u8 *) CFG_CPLD_BASE + 0x03, - in_8((u8 *) CFG_CPLD_BASE + 0x03) | + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x06 << (4 * eth)); } else { /* SFP module present: configure PHY for fiber and enable output */ - gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1); - gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1); + gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0); } } /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ - gpio_write_bit(CFG_GPIO_PHY0_EN, 1); - gpio_write_bit(CFG_GPIO_PHY1_EN, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1); /* Wait 1 ms, then enable Fiber signal detect to PHYs. */ udelay(1000); - out_8((u8 *) CFG_CPLD_BASE + 0x03, - in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x88); + out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03, + in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88); /* select Ethernet (and optionally IIC1) pins */ mfsdr(SDR0_PFC1, sdr0_pfc1); @@ -176,8 +176,8 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) if (1 != banknum) return 0; - info->size = CFG_FLASH0_SIZE; - info->sector_count = CFG_FLASH0_SIZE / 0x20000; + info->size = CONFIG_SYS_FLASH0_SIZE; + info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000; info->flash_id = 0x01000000; info->portwidth = 2; info->chipwidth = 2; @@ -192,12 +192,12 @@ ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) info->manufacturer_id = 1; info->device_id = 0x007E; -#if CFG_FLASH0_SIZE == 0x01000000 +#if CONFIG_SYS_FLASH0_SIZE == 0x01000000 info->device_id2 = 0x2101; -#elif CFG_FLASH0_SIZE == 0x04000000 +#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000 info->device_id2 = 0x2301; #else -#error Unable to set device_id2 for current CFG_FLASH0_SIZE +#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE #endif info->ext_addr = 0x0040; @@ -349,13 +349,13 @@ int misc_init_r(void) unsigned long usb2d0cr = 0; unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; - uint32_t const flash1_size = gd->bd->bi_flashsize - CFG_FLASH0_SIZE; + uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; char const *const act = getenv("usbact"); /* * Re-do FLASH1 sizing and adjust flash start and offset. */ - gd->bd->bi_flashstart = CFG_FLASH1_TOP - flash1_size; + gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size; gd->bd->bi_flashoffset = 0; mtdcr(ebccfga, pb1cr); @@ -375,31 +375,31 @@ int misc_init_r(void) * environment */ gd->bd->bi_flashoffset = - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - CFG_FLASH1_ADDR; + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR; mtdcr(ebccfga, pb1cr); pbcr = mfdcr(ebccfgd); - size_val = ffs(gd->bd->bi_flashsize - CFG_FLASH0_SIZE) - 21; + size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); mtdcr(ebccfga, pb1cr); mtdcr(ebccfgd, pbcr); /* Monitor protection ON by default */ #if defined(CONFIG_KORAT_PERMANENT) - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, flash_info + 1); #else - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, flash_info); #endif /* Env protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, flash_info); - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, flash_info); /* @@ -536,7 +536,7 @@ int misc_init_r(void) set_serial_number(); set_mac_addresses(); - gpio_write_bit(CFG_GPIO_ATMEGA_RESET_, 1); + gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1); return 0; } @@ -544,20 +544,20 @@ int misc_init_r(void) int checkboard(void) { char const *const s = getenv("serial#"); - u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); + u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0); printf("Board: Korat, Rev. %X", rev); if (s) printf(", serial# %s", s); printf(".\n Ethernet PHY 0: "); - if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL)) + if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL)) printf("fiber"); else printf("copper"); printf(", PHY 1: "); - if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL)) + if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL)) printf("fiber"); else printf("copper"); @@ -644,7 +644,7 @@ int pci_pre_init(struct pci_controller *hose) * inbound map (PIM). But the bootstrap config choices are limited and * may not be sufficient for a given board. */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /* @@ -660,9 +660,9 @@ void pci_target_init(struct pci_controller *hose) */ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ out32r(PCIX0_PMM0PCILA, - CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ @@ -670,9 +670,9 @@ void pci_target_init(struct pci_controller *hose) out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ out32r(PCIX0_PMM1LA, - CFG_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ + CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ out32r(PCIX0_PMM1PCILA, - CFG_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ + CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ @@ -688,8 +688,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -708,9 +708,9 @@ void pci_target_init(struct pci_controller *hose) */ pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -771,7 +771,7 @@ void ft_board_setup(void *blob, bd_t *bd) val[0] = 1; /* chip select number */ val[1] = 0; /* always 0 */ val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize - CFG_FLASH0_SIZE; + val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE; rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", val, sizeof(val), 1); if (rc) diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index 6dccf958f..9bed401b7 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -135,6 +135,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/korat/u-boot.lds b/board/korat/u-boot.lds index b20fb1c0a..05152b7f7 100644 --- a/board/korat/u-boot.lds +++ b/board/korat/u-boot.lds @@ -135,9 +135,10 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/kup/common/flash.c b/board/kup/common/flash.c index 903c88f06..134a9d591 100644 --- a/board/kup/common/flash.c +++ b/board/kup/common/flash.c @@ -24,13 +24,13 @@ #include <common.h> #include <mpc8xx.h> -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif #define CONFIG_FLASH_16BIT -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -43,13 +43,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -64,25 +64,25 @@ unsigned long flash_init (void) /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif @@ -325,7 +325,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) #else while ((sect_addr[0] & 0x00800080) != 0x00800080) { #endif - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -467,7 +467,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -507,7 +507,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { #endif - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c index d018e3cc5..fec5407bc 100644 --- a/board/kup/common/kup.c +++ b/board/kup/common/kup.c @@ -27,7 +27,7 @@ int misc_init_f (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile sysconf8xx_t *siu = &immap->im_siu_conf; while (siu->sc_sipend & 0x20000000) { @@ -47,7 +47,7 @@ int misc_init_f (void) #ifdef CONFIG_IDE_LED void ide_led (uchar led, uchar status) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* We have one led for both pcmcia slots */ if (status) { /* led on */ @@ -60,7 +60,7 @@ void ide_led (uchar led, uchar status) void poweron_key (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1); immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1); diff --git a/board/kup/common/load_sernum_ethaddr.c b/board/kup/common/load_sernum_ethaddr.c index b7b749985..741e9a536 100644 --- a/board/kup/common/load_sernum_ethaddr.c +++ b/board/kup/common/load_sernum_ethaddr.c @@ -33,8 +33,8 @@ * The KUP Hardware Information Block is defined as * follows: * - located in first flash bank - * - starts at offset CFG_HWINFO_OFFSET - * - size CFG_HWINFO_SIZE + * - starts at offset CONFIG_SYS_HWINFO_OFFSET + * - size CONFIG_SYS_HWINFO_SIZE * * Internal structure: * - sequence of ASCII character lines @@ -55,15 +55,15 @@ void load_sernum_ethaddr (void) { unsigned char *hwi; char *var; - unsigned char hwi_stack[CFG_HWINFO_SIZE]; + unsigned char hwi_stack[CONFIG_SYS_HWINFO_SIZE]; char *p; - hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET); - if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) { + hwi = (unsigned char *) (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); + if (*((unsigned long *) hwi) != (unsigned long) CONFIG_SYS_HWINFO_MAGIC) { printf ("HardwareInfo not found!\n"); return; } - memcpy (hwi_stack, hwi, CFG_HWINFO_SIZE); + memcpy (hwi_stack, hwi, CONFIG_SYS_HWINFO_SIZE); /* ** ethaddr @@ -72,7 +72,7 @@ void load_sernum_ethaddr (void) if (var) { var += sizeof (ETHADDR_TOKEN) - 1; p = strchr (var, '\r'); - if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) { + if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { *p = '\0'; setenv ("ethaddr", var); *p = '\r'; @@ -85,7 +85,7 @@ void load_sernum_ethaddr (void) if (var) { var += sizeof (LCD_TOKEN) - 1; p = strchr (var, '\r'); - if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) { + if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) { *p = '\0'; setenv ("lcd", var); *p = '\r'; diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c index 8f0cf17b9..ce6b1861d 100644 --- a/board/kup/common/pcmcia.c +++ b/board/kup/common/pcmcia.c @@ -30,10 +30,10 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure SIUMCR to enable PCMCIA port B @@ -125,9 +125,9 @@ int pcmcia_hardware_disable(int slot) debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* remove all power */ if (slot) @@ -162,9 +162,9 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) if (!slot) /* Slot A is not configurable */ return 0; - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Disable PCMCIA buffers (isolate the interface) diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 66d618072..df3ffb4d7 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -119,7 +119,7 @@ const uint sdram_table[] = { int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; uchar *latch,rev,mod; /* @@ -139,7 +139,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0 = 0; long int size_b1 = 0; @@ -154,7 +154,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000088; @@ -163,14 +163,14 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ -/* memctl->memc_or1 = CFG_OR1_PRELIM; */ -/* memctl->memc_br1 = CFG_BR1_PRELIM; */ +/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ +/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ -/* memctl->memc_or2 = CFG_OR2_PRELIM; */ -/* memctl->memc_br2 = CFG_BR2_PRELIM; */ +/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ +/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -204,7 +204,7 @@ phys_size_t initdram (int board_type) size_b0 = 0x00800000; size_b1 = 0x00800000; size_b2 = 0x00800000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; udelay (1000); memctl->memc_or1 = 0xFF800A00; memctl->memc_br1 = 0x00000081; @@ -216,7 +216,7 @@ phys_size_t initdram (int board_type) size_b0 = 0x01000000; size_b1 = 0x01000000; size_b2 = 0x01000000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; udelay (1000); memctl->memc_or1 = 0xFF000A00; memctl->memc_br1 = 0x00000081; @@ -236,7 +236,7 @@ phys_size_t initdram (int board_type) int misc_init_r (void) { #ifdef CONFIG_STATUS_LED - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #endif #ifdef CONFIG_KUP4K_LOGO bd_t *bd = gd->bd; @@ -263,7 +263,7 @@ void lcd_logo (bd_t * bd) FB_INFO_S1D13xxx fb_info; S1D_INDEX s1dReg; S1D_VALUE s1dValue; - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl; ushort i; uchar *fb; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index 2e9169c16..120ca00fd 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) */ *(.text) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index f6d153763..0f6ae696d 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c index f07ef1870..c5b742dd7 100644 --- a/board/kup/kup4x/kup4x.c +++ b/board/kup/kup4x/kup4x.c @@ -114,7 +114,7 @@ const uint sdram_table[] = { int checkboard (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile uchar *latch; uchar rev, mod; @@ -136,7 +136,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0 = 0; long int size_b1 = 0; @@ -151,7 +151,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000088; @@ -160,13 +160,13 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ -/* memctl->memc_or1 = CFG_OR1_PRELIM; */ -/* memctl->memc_br1 = CFG_BR1_PRELIM; */ +/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ +/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ -/* memctl->memc_or2 = CFG_OR2_PRELIM; */ -/* memctl->memc_br2 = CFG_BR2_PRELIM; */ +/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ +/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -207,7 +207,7 @@ phys_size_t initdram (int board_type) size_b1 = 0x00800000; size_b2 = 0x00800000; size_b3 = 0x00800000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; udelay (1000); memctl->memc_or1 = 0xFF800A00; memctl->memc_br1 = 0x00000081; @@ -222,7 +222,7 @@ phys_size_t initdram (int board_type) size_b1 = 0x01000000; size_b2 = 0x01000000; size_b3 = 0x01000000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; udelay (1000); memctl->memc_or1 = 0xFF000A00; memctl->memc_br1 = 0x00000081; @@ -251,7 +251,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile long int *addr; ulong cnt, val; @@ -294,7 +294,7 @@ static long int dram_size (long int mamr_value, long int *base, int misc_init_r (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #ifdef CONFIG_IDE_LED /* Configure PA8 as output port */ diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index 2e9169c16..120ca00fd 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) */ *(.text) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index f6d153763..0f6ae696d 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/lantec/flash.c b/board/lantec/flash.c index 0faa82cba..97ed0542b 100644 --- a/board/lantec/flash.c +++ b/board/lantec/flash.c @@ -29,15 +29,15 @@ #include <common.h> #include <mpc8xx.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -51,7 +51,7 @@ #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -65,13 +65,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -116,65 +116,65 @@ unsigned long flash_init (void) memctl->memc_br1, memctl->memc_or1); /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \ + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \ BR_MS_GPCM | BR_PS_32 | BR_V; DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b0; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or5 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br5 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_or5 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br5 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_PS_32 | BR_V; DEBUGF("## BR5: 0x%08x OR5: 0x%08x\n", memctl->memc_br5, memctl->memc_or5); /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); flash_info[1].size = size_b1; - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[1]); #endif } else { @@ -491,7 +491,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -614,7 +614,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c index 46f4da9e6..6d3486c48 100644 --- a/board/lantec/lantec.c +++ b/board/lantec/lantec.c @@ -111,7 +111,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0; int i; @@ -122,7 +122,7 @@ phys_size_t initdram (int board_type) upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ; /* burst length=4, burst type=sequential, CAS latency=2 */ memctl->memc_mar = 0x00000088; @@ -130,11 +130,11 @@ phys_size_t initdram (int board_type) /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; /* initialize memory address register */ - memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */ /* mode initialization (offset 5) */ udelay (200); /* 0x80006105 */ @@ -170,17 +170,17 @@ phys_size_t initdram (int board_type) /* * Check Bank 0 Memory Size for re-configuration */ - size_b0 = dram_size (CFG_MAMR_8COL, + size_b0 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE; /* * Final mapping: */ - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; udelay (1000); return (size_b0); @@ -199,7 +199,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds index 2d266434f..6028c2640 100644 --- a/board/lantec/u-boot.lds +++ b/board/lantec/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug index 7dc4408c6..d5e2c1d57 100644 --- a/board/lantec/u-boot.lds.debug +++ b/board/lantec/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/lart/flash.c b/board/lart/flash.c index 28c4531c0..29a331eff 100644 --- a/board/lart/flash.c +++ b/board/lart/flash.c @@ -41,7 +41,7 @@ extern u32 data_to_flash(u32); #define PUZZLE_FROM_FLASH(x) data_from_flash((x)) #define PUZZLE_TO_FLASH(x) data_to_flash((x)) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x00FF00FF @@ -74,15 +74,15 @@ ulong flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F160F3B & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -104,13 +104,13 @@ ulong flash_init(void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; @@ -305,7 +305,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) do { /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); result = BIT_TIMEOUT; @@ -383,7 +383,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) do { /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = PUZZLE_TO_FLASH(CMD_SUSPEND); result = BIT_TIMEOUT; diff --git a/board/lart/u-boot.lds b/board/lart/u-boot.lds index 6bd06270a..fce2533ce 100644 --- a/board/lart/u-boot.lds +++ b/board/lart/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/linkstation/avr.c b/board/linkstation/avr.c index a689c6330..fda1b913e 100644 --- a/board/linkstation/avr.c +++ b/board/linkstation/avr.c @@ -79,8 +79,8 @@ static char envbuffer[16]; void init_AVR_DUART (void) { - NS16550_t AVR_port = (NS16550_t) CFG_NS16550_COM2; - int clock_divisor = CFG_NS16550_CLK / 16 / 9600; + NS16550_t AVR_port = (NS16550_t) CONFIG_SYS_NS16550_COM2; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / 9600; /* * AVR port init sequence taken from @@ -105,12 +105,12 @@ void init_AVR_DUART (void) static inline int avr_tstc(void) { - return (NS16550_tstc((NS16550_t)CFG_NS16550_COM2)); + return (NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2)); } static inline char avr_getc(void) { - return (NS16550_getc((NS16550_t)CFG_NS16550_COM2)); + return (NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2)); } static int push_timeout(char button_code) diff --git a/board/linkstation/hwctl.c b/board/linkstation/hwctl.c index 2e5b5c83a..9fd56ae23 100644 --- a/board/linkstation/hwctl.c +++ b/board/linkstation/hwctl.c @@ -21,7 +21,7 @@ #define mdelay(n) udelay((n)*1000) -#define AVR_PORT CFG_NS16550_COM2 +#define AVR_PORT CONFIG_SYS_NS16550_COM2 /* 2005.5.10 BUFFALO add */ /*--------------------------------------------------------------*/ diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c index 02086a003..2c89d62f6 100644 --- a/board/linkstation/ide.c +++ b/board/linkstation/ide.c @@ -37,7 +37,7 @@ #define IT8212_PCI_IdeBusSkewCONTROL 0x4c #define IT8212_PCI_IdeDrivingCURRENT 0x42 -extern ulong ide_bus_offset[CFG_IDE_MAXBUS]; +extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS]; extern struct pci_controller hose; int ide_preinit (void) @@ -47,7 +47,7 @@ int ide_preinit (void) int l; status = 1; - for (l = 0; l < CFG_IDE_MAXBUS; l++) { + for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { ide_bus_offset[l] = -ATA_STATUS; } devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0); diff --git a/board/linkstation/linkstation.c b/board/linkstation/linkstation.c index 241cf032d..c0d43eb33 100644 --- a/board/linkstation/linkstation.c +++ b/board/linkstation/linkstation.c @@ -26,6 +26,7 @@ #include <mpc824x.h> #include <asm/io.h> #include <ns16550.h> +#include <netdev.h> #ifdef CONFIG_PCI #include <pci.h> @@ -52,7 +53,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - return (get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE)); + return (get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE)); } /* @@ -128,3 +129,8 @@ int board_early_init_f (void) out_8((volatile u8*)UART_DCR, 1); return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/logodl/flash.c b/board/logodl/flash.c index 0807b8091..593943ffd 100644 --- a/board/logodl/flash.c +++ b/board/logodl/flash.c @@ -28,7 +28,7 @@ #define FLASH_BANK_SIZE 0x1000000 #define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -59,7 +59,7 @@ static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); #define write_word(in, de, da) write_word_amd(in, de, da) static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION static void flash_sync_real_protect(flash_info_t *info); #endif @@ -73,15 +73,15 @@ ulong flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (FLASH_MAN_AMD & FLASH_VENDMASK) | (FLASH_AM640U & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: @@ -104,13 +104,13 @@ ulong flash_init(void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; @@ -373,7 +373,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info) return (info->size); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ @@ -510,7 +510,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -703,7 +703,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00F000F0; /* reset bank */ res = 1; } @@ -749,7 +749,7 @@ static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) start = get_timer (0); while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00B000B0; /* Suspend program */ res = 1; } @@ -764,7 +764,7 @@ static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) return (res); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ int flash_real_protect (flash_info_t * info, long sector, int prot) diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c index 897787bcf..c57210a95 100644 --- a/board/logodl/logodl.c +++ b/board/logodl/logodl.c @@ -77,17 +77,17 @@ void logodl_set_led(int led, int state) case 0: if (state==1) { - CFG_LED_A_CR = CFG_LED_A_BIT; + CONFIG_SYS_LED_A_CR = CONFIG_SYS_LED_A_BIT; } else if (state==0) { - CFG_LED_A_SR = CFG_LED_A_BIT; + CONFIG_SYS_LED_A_SR = CONFIG_SYS_LED_A_BIT; } break; case 1: if (state==1) { - CFG_LED_B_CR = CFG_LED_B_BIT; + CONFIG_SYS_LED_B_CR = CONFIG_SYS_LED_B_BIT; } else if (state==0) { - CFG_LED_B_SR = CFG_LED_B_BIT; + CONFIG_SYS_LED_B_SR = CONFIG_SYS_LED_B_BIT; } break; } diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S index 4c9f10ffb..9892430a1 100644 --- a/board/logodl/lowlevel_init.S +++ b/board/logodl/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -54,71 +54,71 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ -/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ +/* ldr r2, =CONFIG_SYS_MSC1_VAL / high - bank 3 Ethernet Controller */ /* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ /* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ /* */ @@ -168,17 +168,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -187,37 +187,37 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] @@ -239,7 +239,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 @@ -269,7 +269,7 @@ mem_init: /* Step 4a: assert MDREFR:K?RUN and configure */ /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] @@ -292,7 +292,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ @@ -325,7 +325,7 @@ mem_init: /* Jan 2003, Errata #116, page 30. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -345,7 +345,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] diff --git a/board/logodl/u-boot.lds b/board/logodl/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/logodl/u-boot.lds +++ b/board/logodl/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/lpc2292sodimm/flash.c b/board/lpc2292sodimm/flash.c index 0fb08430c..a7e175d8e 100644 --- a/board/lpc2292sodimm/flash.c +++ b/board/lpc2292sodimm/flash.c @@ -28,7 +28,7 @@ #define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1))) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong); extern int lpc2292_flash_erase(flash_info_t *, int, int); @@ -97,8 +97,8 @@ ulong flash_init (void) &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; diff --git a/board/lpc2292sodimm/u-boot.lds b/board/lpc2292sodimm/u-boot.lds index 418101ff8..49d18f7d6 100644 --- a/board/lpc2292sodimm/u-boot.lds +++ b/board/lpc2292sodimm/u-boot.lds @@ -50,6 +50,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c index d18720e5b..e3558d217 100644 --- a/board/lpd7a40x/flash.c +++ b/board/lpd7a40x/flash.c @@ -33,7 +33,7 @@ #define FLASH_BANK_SIZE 0x1000000 /* 16MB (2 x 8 MB) */ #define MAIN_SECT_SIZE 0x40000 /* 256KB (2 x 128kB) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x00FF00FF @@ -66,17 +66,17 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F640J3A & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) - flashbase = CFG_FLASH_BASE; + flashbase = CONFIG_SYS_FLASH_BASE; else panic ("configured too many flash banks!\n"); for (j = 0; j < flash_info[i].sector_count; j++) { @@ -92,18 +92,18 @@ ulong flash_init (void) * Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -297,7 +297,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_STATUS_RESET; result = BIT_TIMEOUT; break; @@ -392,7 +392,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_SUSPEND; result = BIT_TIMEOUT; break; diff --git a/board/lpd7a40x/u-boot.lds b/board/lpd7a40x/u-boot.lds index b5f8ff919..3c14437ec 100644 --- a/board/lpd7a40x/u-boot.lds +++ b/board/lpd7a40x/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c index ba82892dd..a4b201e01 100644 --- a/board/lubbock/flash.c +++ b/board/lubbock/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -65,7 +65,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -85,13 +85,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0] ); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); return size; } @@ -203,10 +203,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -276,7 +276,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -410,7 +410,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S index 2a9bcbf49..db6f69d36 100644 --- a/board/lubbock/lowlevel_init.S +++ b/board/lubbock/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -51,67 +51,67 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ---------------------------------------------------------------- */ @@ -149,17 +149,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -168,37 +168,37 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] @@ -214,7 +214,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 @@ -244,7 +244,7 @@ mem_init: /* set MDREFR according to user define with exception of a few bits */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL orr r4, r4, #(MDREFR_SLFRSH) bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ @@ -259,7 +259,7 @@ mem_init: /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] @@ -267,7 +267,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ @@ -294,7 +294,7 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -314,7 +314,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] diff --git a/board/lubbock/u-boot.lds b/board/lubbock/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/lubbock/u-boot.lds +++ b/board/lubbock/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c index b894887c9..f71cc242f 100644 --- a/board/lwmon/flash.c +++ b/board/lwmon/flash.c @@ -26,28 +26,28 @@ #include <common.h> #include <mpc8xx.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions */ static ulong flash_get_size (vu_long *addr, flash_info_t *info); static int write_data (flash_info_t *info, ulong dest, ulong data); -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len); #endif static void flash_get_offsets (ulong base, flash_info_t *info); @@ -57,13 +57,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -108,66 +108,66 @@ unsigned long flash_init (void) memctl->memc_br1, memctl->memc_or1); /* Remap FLASH according to real size */ - memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH | + memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH | OR_CSNT_SAM | OR_ACS_DIV1; - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V; + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V; debug ("## BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b0; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH | + memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH | OR_CSNT_SAM | OR_ACS_DIV1; - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_PS_32 | BR_V; debug ("## BR1: 0x%08x OR1: 0x%08x\n", memctl->memc_br1, memctl->memc_or1); /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); flash_info[1].size = size_b1; - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[1]); #endif } else { @@ -342,10 +342,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = 0x00FF00FF; /* restore read mode */ @@ -409,7 +409,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); /* This takes awfully long - up to 50 ms and more */ while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0x00FF00FF; /* reset to read mode */ return 1; @@ -435,7 +435,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0x00B000B0; /* suspend erase */ *addr = 0x00FF00FF; /* reset to read mode */ @@ -504,10 +504,10 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) /* * handle FLASH_WIDTH aligned part */ -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE while(cnt >= FLASH_WIDTH) { - i = CFG_FLASH_BUFFER_SIZE > cnt ? - (cnt & ~(FLASH_WIDTH - 1)) : CFG_FLASH_BUFFER_SIZE; + i = CONFIG_SYS_FLASH_BUFFER_SIZE > cnt ? + (cnt & ~(FLASH_WIDTH - 1)) : CONFIG_SYS_FLASH_BUFFER_SIZE; if((rc = write_data_buf(info, wp, src,i)) != 0) return rc; wp += i; @@ -526,7 +526,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp += FLASH_WIDTH; cnt -= FLASH_WIDTH; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); @@ -594,7 +594,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data) if (flag) enable_interrupts(); - if (flash_status_check(addr, CFG_FLASH_WRITE_TOUT, "write") != 0) { + if (flash_status_check(addr, CONFIG_SYS_FLASH_WRITE_TOUT, "write") != 0) { return (1); } @@ -603,7 +603,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data) return (0); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /*----------------------------------------------------------------------- * Write a buffer to Flash, returns: * 0 - OK @@ -627,7 +627,7 @@ static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len) *addr = 0x00500050; /* clear status */ *addr = 0x00e800e8; /* write buffer */ - if((retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT, + if((retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT, "write to buffer")) == 0) { cnt = len / FLASH_WIDTH; *addr = (cnt-1) | ((cnt-1) << 16); @@ -635,14 +635,14 @@ static int write_data_buf(flash_info_t * info, ulong dest, uchar * cp, int len) *dst++ = *src++; } *addr = 0x00d000d0; /* write buffer confirm */ - retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT, + retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT, "buffer write"); } *addr = 0x00FF00FF; /* restore read mode */ *addr = 0x00500050; /* clear status */ return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ /*----------------------------------------------------------------------- */ diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index 4a2d8e4a4..878752c66 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -66,7 +66,7 @@ extern void disable_putc(void); */ const uint sdram_table[] = { -#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E) +#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E) /* * Single Read. (Offset 0 in UPM RAM) */ @@ -114,7 +114,7 @@ const uint sdram_table[] = 0x7FFFFC07, /* last */ 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF, #endif -#ifdef CFG_MEMORY_7E +#ifdef CONFIG_SYS_MEMORY_7E /* * Single Read. (Offset 0 in UPM RAM) */ @@ -211,7 +211,7 @@ V* Verification: dzu@denx.de ***********************************************************************/ phys_size_t initdram (int board_type) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; long int size_b0; long int size8, size9; @@ -222,19 +222,19 @@ phys_size_t initdram (int board_type) */ upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = CFG_MAR; + memctl->memc_mar = CONFIG_SYS_MAR; /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; /* initialize memory address register */ - memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */ /* mode initialization (offset 5) */ udelay (200); /* 0x80006105 */ @@ -268,22 +268,22 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; - memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE; + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE; udelay (500); } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE; udelay (500); } @@ -293,7 +293,7 @@ phys_size_t initdram (int board_type) memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; udelay (1000); return (size_b0); @@ -327,7 +327,7 @@ V* Verification: dzu@denx.de ***********************************************************************/ static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; memctl->memc_mamr = mamr_value; @@ -359,7 +359,7 @@ V* Verification: dzu@denx.de ***********************************************************************/ int board_early_init_f (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* Disable Ethernet TENA on Port B * Necessary because of pull up in COM3 port. @@ -437,7 +437,7 @@ void reset_phy (void) /* maximum number of "magic" key codes that can be assigned */ -static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; +static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; static uchar *key_match (uchar *); @@ -481,7 +481,7 @@ static void kbd_init (void) uchar val, errcd; int i; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); gd->kbd_status = 0; @@ -759,6 +759,34 @@ static uchar *key_match (uchar *kbd_data) } #endif /* CONFIG_PREBOOT */ +#ifdef CONFIG_LCD_INFO +#include <lcd.h> +#include <version.h> +#include <timestamp.h> + +void lcd_show_board_info(void) +{ + char temp[32]; + + lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); + lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); + lcd_printf (" Wolfgang DENK, wd@denx.de\n"); +#ifdef CONFIG_LCD_INFO_BELOW_LOGO + lcd_printf ("MPC823 CPU at %s MHz\n", + strmhz(temp, gd->cpu_clk)); + lcd_printf (" %ld MB RAM, %ld MB Flash\n", + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#else + /* leave one blank line */ + lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", + strmhz(temp, gd->cpu_clk), + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ +} +#endif /* CONFIG_LCD_INFO */ + /*---------------Board Special Commands: PIC read/write ---------------*/ #if defined(CONFIG_CMD_BSP) @@ -862,7 +890,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i; #if 0 /* Done in kbd_init */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif /* Read keys */ @@ -887,7 +915,7 @@ U_BOOT_CMD( ); /* Read and set LSB switch */ -#define CFG_PC_TXD1_ENA 0x0008 /* PC.12 */ +#define CONFIG_SYS_PC_TXD1_ENA 0x0008 /* PC.12 */ /*********************************************************************** F* Function: int do_lsb (cmd_tbl_t *cmdtp, int flag, @@ -920,7 +948,7 @@ V* Verification: dzu@denx.de int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uchar val; - immap_t *immr = (immap_t *) CFG_IMMR; + immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; switch (argc) { case 1: /* lsb - print setting */ @@ -932,14 +960,14 @@ int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (strcmp (argv[1], "on") == 0) { val |= 0x20; - immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); - immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA; - immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA); + immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_TXD1_ENA; + immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA; } else if (strcmp (argv[1], "off") == 0) { val &= ~0x20; - immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA); - immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA); - immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA; + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA); + immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_TXD1_ENA); + immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA; } else { break; } @@ -980,7 +1008,7 @@ V* Verification: dzu@denx.de ***********************************************************************/ uchar pic_read (uchar reg) { - return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg)); + return (i2c_reg_read (CONFIG_SYS_I2C_PICIO_ADDR, reg)); } /*********************************************************************** @@ -1001,7 +1029,7 @@ V* Verification: dzu@denx.de ***********************************************************************/ void pic_write (uchar reg, uchar val) { - i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val); + i2c_reg_write (CONFIG_SYS_I2C_PICIO_ADDR, reg, val); } /*---------------------- Board Control Functions ----------------------*/ @@ -1022,7 +1050,7 @@ V* Verification: dzu@denx.de void board_poweroff (void) { /* Turn battery off */ - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13)); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13)); while (1); } diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c index 8825bd971..ad2e60d59 100644 --- a/board/lwmon/pcmcia.c +++ b/board/lwmon/pcmcia.c @@ -51,10 +51,10 @@ int pcmcia_hardware_enable(int slot) #endif udelay(10000); - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure SIUMCR to enable PCMCIA port B @@ -108,8 +108,8 @@ int pcmcia_hardware_enable(int slot) /* switch VCC on */ val |= MAX1604_OP_SUS | MAX1604_VCCBON; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); udelay(500000); @@ -137,13 +137,13 @@ int pcmcia_hardware_disable(int slot) debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* remove all power, put output in high impedance state */ val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); /* Configure PCMCIA General Control Register */ debug ("Disable PCMCIA buffers and assert RESET\n"); @@ -181,8 +181,8 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) * and assert RESET signal @@ -199,8 +199,8 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) */ debug ("PCMCIA power OFF\n"); val = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); val = 0; switch(vcc) { @@ -216,7 +216,7 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) pcmp->pcmc_pipr, (pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V"); - i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1); + i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1); if (val) { debug ("PCMCIA powered at %sV\n", (val & MAX1604_VCC_35) ? "3.3" : "5.0"); diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index bc1ea7372..319cc7bd0 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 2ee823745..bd9d76ce2 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk index bf2b8798c..3c6d04172 100644 --- a/board/lwmon5/config.mk +++ b/board/lwmon5/config.mk @@ -35,5 +35,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S index 5aade72b5..718cec6af 100644 --- a/board/lwmon5/init.S +++ b/board/lwmon5/init.S @@ -47,7 +47,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G) /* * TLB entries for SDRAM are not needed on this platform. @@ -55,28 +55,28 @@ tlbtab: * routine. */ -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) #endif /* TLB-entry for PCI Memory */ - tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I) /* TLB-entry for the FPGA Chip select 2 */ - tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G) /* TLB-entry for the FPGA Chip select 3 */ - tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G) /* TLB-entry for the LIME Controller */ - tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G) - tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G) - tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G) - tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G) /* TLB-entry for Internal Registers & OCM */ tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I) diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c index 1e5349a6e..0a8787a91 100644 --- a/board/lwmon5/kbd.c +++ b/board/lwmon5/kbd.c @@ -74,7 +74,7 @@ static int compare_magic (uchar *kbd_data, uchar *str); /* maximum number of "magic" key codes that can be assigned */ -static uchar kbd_addr = CFG_I2C_KEYBD_ADDR; +static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR; static uchar *key_match (uchar *); @@ -106,7 +106,7 @@ static void kbd_init (void) uchar val, errcd; int i; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); gd->kbd_status = 0; @@ -412,7 +412,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i; #if 0 /* Done in kbd_init */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif /* Read keys */ diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 85795b7c2..aa62f3790 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ ulong flash_get_size(ulong base, int banknum); int misc_init_r_kbd(void); @@ -94,24 +94,24 @@ int board_early_init_f(void) reg = 0; mtsdr(sdr_pci0, 0x00000000 | reg); - gpio_write_bit(CFG_GPIO_FLASH_WP, 1); + gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); -#if CONFIG_POST & CFG_POST_BSPEC1 - gpio_write_bit(CFG_GPIO_HIGHSIDE, 1); +#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 + gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1); reg = 0; /* reuse as counter */ - out_be32((void *)CFG_DSPIC_TEST_ADDR, - in_be32((void *)CFG_DSPIC_TEST_ADDR) - & ~CFG_DSPIC_TEST_MASK); - while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY) && reg++ < 1000) { + out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, + in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) + & ~CONFIG_SYS_DSPIC_TEST_MASK); + while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) { udelay(1000); } - gpio_write_bit(CFG_GPIO_HIGHSIDE, 0); - if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) { + gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0); + if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) { /* set "boot error" flag */ - out_be32((void *)CFG_DSPIC_TEST_ADDR, - in_be32((void *)CFG_DSPIC_TEST_ADDR) | - CFG_DSPIC_TEST_MASK); + out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR, + in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) | + CONFIG_SYS_DSPIC_TEST_MASK); } #endif @@ -123,14 +123,14 @@ int board_early_init_f(void) * MDIO address. A 2nd reset at this time will make sure, that the * correct address is latched. */ - gpio_write_bit(CFG_GPIO_PHY0_RST, 1); - gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); udelay(1000); - gpio_write_bit(CFG_GPIO_PHY0_RST, 0); - gpio_write_bit(CFG_GPIO_PHY1_RST, 0); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0); udelay(1000); - gpio_write_bit(CFG_GPIO_PHY0_RST, 1); - gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1); return 0; } @@ -194,14 +194,14 @@ int misc_init_r(void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[1]); /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[1]); /* @@ -338,7 +338,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -352,14 +352,14 @@ void pci_target_init(struct pci_controller *hose) | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ @@ -374,8 +374,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -389,13 +389,13 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -410,7 +410,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host @@ -460,8 +460,8 @@ void hw_watchdog_reset(void) /* * Toggle watchdog output */ - val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; - gpio_write_bit(CFG_GPIO_WATCHDOG, val); + val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0; + gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val); } int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -472,9 +472,9 @@ int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if ((strcmp(argv[1], "on") == 0)) { - gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1); + gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1); } else if ((strcmp(argv[1], "off") == 0)) { - gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0); + gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0); } else { printf("Usage:\n%s\n", cmdtp->usage); return 1; @@ -528,23 +528,23 @@ unsigned int board_video_init (void) /* * Reset Lime controller */ - gpio_write_bit(CFG_GPIO_LIME_S, 1); + gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1); udelay(500); - gpio_write_bit(CFG_GPIO_LIME_RST, 1); + gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); /* Lime memory clock adjusted to 100MHz */ - out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ); + out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ); /* Wait untill time expired. Because of requirements in lime manual */ udelay(300); /* Write lime controller memory parameters */ - out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); + out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); mb862xx.winSizeX = 640; mb862xx.winSizeY = 480; mb862xx.gdfBytesPP = 2; mb862xx.gdfIndex = GDF_15BIT_555RGB; - return CFG_LIME_BASE_0; + return CONFIG_SYS_LIME_BASE_0; } #define DEFAULT_BRIGHTNESS 0x64 @@ -553,12 +553,12 @@ static void board_backlight_brightness(int brightness) { if (brightness > 0) { /* pwm duty, lamp on */ - out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), brightness); - out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701); + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness); + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701); } else { /* lamp off */ - out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x00); - out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x00); + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00); + out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00); } } @@ -595,5 +595,5 @@ void video_get_info_str (int line_number, char *info) void board_reset(void) { - gpio_write_bit(CFG_GPIO_BOARD_RESET, 1); + gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1); } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 189e82407..72968d780 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -45,10 +45,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup * everything correctly. */ -#ifdef CFG_ENABLE_SDRAM_CACHE +#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ @@ -116,7 +116,7 @@ static void program_ecc(u32 start_address, * Because of 440EPx errata CHIP 11, we don't touch the last 256 * bytes of SDRAM. */ - bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE; + bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE; /* * We have to write the ECC bytes by zeroing and flushing in smaller @@ -252,29 +252,29 @@ phys_size_t initdram (int board_type) /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ - program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20, + program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); - remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); + remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* * Program tlb entries for this size (dynamic) */ - program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20, + program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual address * with cache enabled. This is done for fast ECC generation. */ - program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); + program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ - program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); + program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); #endif /* @@ -284,5 +284,5 @@ phys_size_t initdram (int board_type) */ set_mcsr(get_mcsr()); - return (CFG_MBYTES_SDRAM << 20); + return (CONFIG_SYS_MBYTES_SDRAM << 20); } diff --git a/board/lwmon5/u-boot.lds b/board/lwmon5/u-boot.lds index b20fb1c0a..05152b7f7 100644 --- a/board/lwmon5/u-boot.lds +++ b/board/lwmon5/u-boot.lds @@ -135,9 +135,10 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } - ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/m501sk/eeprom.c b/board/m501sk/eeprom.c index d86392f93..d1a46f348 100644 --- a/board/m501sk/eeprom.c +++ b/board/m501sk/eeprom.c @@ -23,13 +23,13 @@ #include <common.h> #include <i2c.h> -#ifdef CFG_EEPROM_AT24C16 +#ifdef CONFIG_SYS_EEPROM_AT24C16 #undef DEBUG void eeprom_init(void) { #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif } @@ -53,10 +53,10 @@ int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, } /* - * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is + * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. * - * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is + * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is * 0x00000nxx for EEPROM address selectors and page number at n. */ int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, @@ -76,8 +76,8 @@ int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, } } -#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); +#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) + udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); #endif return 0; @@ -89,11 +89,11 @@ int eeprom_probe(unsigned dev_addr, unsigned offset) unsigned char chip; /* Probe the chip address */ -#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) +#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) chip = offset >> 8; /* block number */ #else chip = offset >> 16; /* block number */ -#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ +#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ chip |= dev_addr; /* insert device address */ return (i2c_probe(chip)); diff --git a/board/m501sk/u-boot.lds b/board/m501sk/u-boot.lds index 99e2ac199..ae6caf598 100644 --- a/board/m501sk/u-boot.lds +++ b/board/m501sk/u-boot.lds @@ -50,6 +50,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss : { *(.bss) } + .bss : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c index 3332f5aca..a30034231 100644 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ b/board/matrix_vision/mvbc_p/mvbc_p.c @@ -35,6 +35,7 @@ #include <fpga.h> #include <environment.h> #include <fdt_support.h> +#include <netdev.h> #include <asm/io.h> #include "fpga.h" #include "mvbc_p.h" @@ -84,9 +85,9 @@ phys_addr_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -192,13 +193,13 @@ void flash_preinit(void) void flash_afterinit(ulong size) { - out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CFG_BOOTCS_START | + out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32*)MPC5XXX_CS0_START, START_REG(CFG_BOOTCS_START | + out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START | size)); - out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CFG_BOOTCS_START | size, + out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); - out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CFG_BOOTCS_START | size, + out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size, size)); } @@ -324,3 +325,9 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +} diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c index a60af019a..7527d161a 100644 --- a/board/matrix_vision/mvblm7/fpga.c +++ b/board/matrix_vision/mvblm7/fpga.c @@ -79,7 +79,7 @@ int fpga_null_fn(int cookie) int fpga_config_fn(int assert, int flush, int cookie) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; u32 dvo = gpio->dat; @@ -97,7 +97,7 @@ int fpga_config_fn(int assert, int flush, int cookie) int fpga_done_fn(int cookie) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; int result = 0; @@ -114,7 +114,7 @@ int fpga_done_fn(int cookie) int fpga_status_fn(int cookie) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; int result = 0; @@ -130,7 +130,7 @@ int fpga_status_fn(int cookie) int fpga_clk_fn(int assert_clk, int flush, int cookie) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; u32 dvo = gpio->dat; @@ -148,7 +148,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie) static inline int _write_fpga(u8 val, int dump) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; int i; u32 dvo = gpio->dat; diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c index b07f91393..6984af984 100644 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ b/board/matrix_vision/mvblm7/mvblm7.c @@ -38,50 +38,50 @@ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { if (ddr_size & 1) return -1; } - im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; udelay(300); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - return CFG_DDR_SIZE; + return CONFIG_SYS_DDR_SIZE; } phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; msize = fixed_sdram(); /* return total bus RAM size(bytes) */ @@ -132,14 +132,14 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { - volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; iopd->dat &= ~MVBLM7_MMC_CS; } void spi_cs_deactivate(struct spi_slave *slave) { - volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0]; iopd->dat |= ~MVBLM7_MMC_CS; } diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c index ef34a6b45..9f31719ae 100644 --- a/board/matrix_vision/mvblm7/pci.c +++ b/board/matrix_vision/mvblm7/pci.c @@ -52,21 +52,21 @@ int mvblm7_load_fpga(void) static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI1_MEM_BASE, - phys_start: CFG_PCI1_MEM_PHYS, - size: CFG_PCI1_MEM_SIZE, + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI1_MMIO_BASE, - phys_start: CFG_PCI1_MMIO_PHYS, - size: CFG_PCI1_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI1_IO_BASE, - phys_start: CFG_PCI1_IO_PHYS, - size: CFG_PCI1_IO_SIZE, + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, flags: PCI_REGION_IO } }; @@ -85,7 +85,7 @@ void pci_init_board(void) struct pci_region *reg[] = { pci_regions }; load_fpga = 1; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) &immr->clk; pci_ctrl = immr->pci_ctrl; pci_law = immr->sysconf.pcilaw; @@ -121,10 +121,10 @@ void pci_init_board(void) for (i = 0; i < 1000; ++i) udelay(1000); - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h index 832e9241f..d1a58b60c 100644 --- a/board/mbx8xx/csr.h +++ b/board/mbx8xx/csr.h @@ -54,7 +54,7 @@ #define SR2_RDY 0x02 /* Flash programming status bit */ #define SR2_FT 0x01 /* Reserved for Factory test purposes */ -#define MBX_CSR1 (*((uchar *)CFG_CSR_BASE)) -#define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1)) +#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE)) +#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1)) #endif /* __csr_h */ diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c index a491f7bf0..2ec420d51 100644 --- a/board/mbx8xx/flash.c +++ b/board/mbx8xx/flash.c @@ -32,7 +32,7 @@ #include <mpc8xx.h> #include "vpd.h" -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -51,13 +51,13 @@ unsigned long flash_init (void) ulong addr; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } totsize = 0; addr = 0xfc000000; - for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { size = flash_get_size((vu_long *)addr, &flash_info[i]); if (flash_info[i].flash_id == FLASH_UNKNOWN) break; @@ -66,7 +66,7 @@ unsigned long flash_init (void) } addr = 0xfe000000; - for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { size = flash_get_size((vu_long *)addr, &flash_info[i]); if (flash_info[i].flash_id == FLASH_UNKNOWN) @@ -75,11 +75,11 @@ unsigned long flash_init (void) addr += size; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif @@ -274,7 +274,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -397,7 +397,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c index 414d87919..af4f57df6 100644 --- a/board/mbx8xx/mbx8xx.c +++ b/board/mbx8xx/mbx8xx.c @@ -121,7 +121,7 @@ static unsigned int board_get_cpufreq(void); void mbx_init (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; ulong speed, refclock, plprcr, sccr; ulong br0_32 = memctl->memc_br0 & 0x400; @@ -147,21 +147,21 @@ void mbx_init (void) immr->im_clkrstk.cark_sccrk = KAPWR_KEY; sccr = immr->im_clkrst.car_sccr; sccr &= SCCR_MASK; - sccr |= CFG_SCCR; + sccr |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = sccr; speed = board_get_cpufreq (); refclock = get_reffreq (); -#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0) - plprcr = CFG_PLPRCR; +#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0) + plprcr = CONFIG_SYS_PLPRCR; #else plprcr = immr->im_clkrst.car_plprcr; plprcr &= PLPRCR_MF_MSK; /* isolate MF field */ - plprcr |= CFG_PLPRCR; /* reset control bits */ + plprcr |= CONFIG_SYS_PLPRCR; /* reset control bits */ #endif -#ifdef CFG_USE_OSCCLK /* See doc/README.MBX ! */ +#ifdef CONFIG_SYS_USE_OSCCLK /* See doc/README.MBX ! */ plprcr |= ((speed + refclock / 2) / refclock - 1) << 20; #endif @@ -181,24 +181,24 @@ void mbx_init (void) case 40: memctl->memc_br0 = 0xFE000000 | br0_32 | 1; memctl->memc_or0 = 0xFF800930; - memctl->memc_or4 = CFG_NVRAM_OR | 0x920; - memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; + memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920; + memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; break; case 50: memctl->memc_br0 = 0xFE000000 | br0_32 | 1; memctl->memc_or0 = 0xFF800940; - memctl->memc_or4 = CFG_NVRAM_OR | 0x930; - memctl->memc_br4 = CFG_NVRAM_BASE | 0x401; + memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930; + memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401; break; default: hang (); break; } #ifdef CONFIG_USE_PCI - memctl->memc_or5 = CFG_PCIMEM_OR; - memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001; - memctl->memc_or6 = CFG_PCIBRIDGE_OR; - memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001; + memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR; + memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001; + memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR; + memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001; #endif /* * FIXME: I do not understand why I have to call this to @@ -306,7 +306,7 @@ static ulong get_ramsize (dimm_t * dimm) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long ram_sz = 0; unsigned long dimm_sz = 0; @@ -354,24 +354,24 @@ phys_size_t initdram (int board_type) dimm_bank = dimm_sz / 2; if (!dimm_sz) { memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; memctl->memc_br2 = 0; memctl->memc_br3 = 0; } else if (ram_sz > dimm_bank) { memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = CFG_SDRAM_BASE | 0x81; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81; memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81; memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) \ + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \ | 0x81; } else { memctl->memc_or2 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br2 = CFG_SDRAM_BASE | 0x81; + memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81; memctl->memc_or3 = ~(dimm_bank - 1) | 0x400; - memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81; + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81; memctl->memc_or1 = ~(ram_sz - 1) | 0x400; - memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81; } } diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c index a02c84845..69368d875 100644 --- a/board/mbx8xx/pcmcia.c +++ b/board/mbx8xx/pcmcia.c @@ -88,10 +88,10 @@ int pcmcia_hardware_enable (int slot) udelay (10000); - immap = (immap_t *) CFG_IMMR; - sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm)); + immap = (immap_t *) CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm)); /* clear interrupt state, and disable interrupts */ pcmp->pcmc_pscr = PCMCIA_MASK (_slot_); diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index 2998e835e..24484c71a 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index fd2245f57..67d37ae33 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c index 6f883520c..3bc251d12 100644 --- a/board/mbx8xx/vpd.c +++ b/board/mbx8xx/vpd.c @@ -47,7 +47,7 @@ #define IIC_BD_FREE (BD_IIC_START + 3*sizeof(cbd_t)) /* FIXME -- replace 0x2000 with offsetof */ -#define VPD_P ((vpd_t *)(CFG_IMMR + 0x2000 + CFG_DPRAMVPD)) +#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD)) /* transmit/receive buffers */ #define IIC_RX_LENGTH 128 @@ -69,7 +69,7 @@ vpd_packet_t * vpd_find_packet(u_char ident) void vpd_init(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(im->im_cpm); volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); volatile iic_t *iip; @@ -120,7 +120,7 @@ void vpd_init(void) */ int vpd_read(uint iic_device, uchar *buf, int count, int offset) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(im->im_cpm); volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c); volatile iic_t *iip; diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c index 2ed66ddb4..49213d0b3 100644 --- a/board/mcc200/auto_update.c +++ b/board/mcc200/auto_update.c @@ -25,7 +25,7 @@ #include <usb.h> #include <part.h> -#ifdef CFG_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER #include <hush.h> #endif @@ -40,8 +40,8 @@ #error "must define CONFIG_USB_STORAGE" #endif -#ifndef CFG_HUSH_PARSER -#error "must define CFG_HUSH_PARSER" +#ifndef CONFIG_SYS_HUSH_PARSER +#error "must define CONFIG_SYS_HUSH_PARSER" #endif #if !defined(CONFIG_CMD_FAT) diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 77ee3d7ed..14cf08da3 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -47,7 +47,7 @@ extern flash_info_t flash_info[]; /* FLASH chips info */ extern int do_auto_update(void); ulong flash_get_size (ulong base, int banknum); -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -92,7 +92,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -101,7 +101,7 @@ phys_size_t initdram (int board_type) ulong dramsize = 0; ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -122,9 +122,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -150,10 +150,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -175,7 +175,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -193,7 +193,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -237,7 +237,7 @@ int misc_init_r (void) /* * Check if boot FLASH isn't max size */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) { + if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) { /* adjust mapping */ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = START_REG(gd->bd->bi_flashstart); @@ -247,31 +247,31 @@ int misc_init_r (void) /* * Re-check to get correct base address */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); /* * Re-do flash protection upon new addresses */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); } if (gd->bd->bi_flashsize > (32 << 20)) { @@ -323,9 +323,8 @@ void ide_set_reset (int idereset) #endif #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif diff --git a/board/mgcoge/mgcoge.c b/board/mgcoge/mgcoge.c deleted file mode 100644 index 51b6dc601..000000000 --- a/board/mgcoge/mgcoge.c +++ /dev/null @@ -1,360 +0,0 @@ -/* - * (C) Copyright 2007 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8260.h> -#include <ioports.h> - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#endif - -/* - * I/O Port configuration table - * - * if conf is 1, then that port pin will be configured at boot time - * according to the five values podr/pdir/ppar/psor/pdat for that entry - */ -const iop_conf_t iop_conf_tab[4][32] = { - - /* Port A */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */ - /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */ - /* PA29 */ { 0, 0, 0, 0, 0, 0 }, /* PA29 */ - /* PA28 */ { 0, 0, 0, 0, 0, 0 }, /* PA28 */ - /* PA27 */ { 0, 0, 0, 0, 0, 0 }, /* PA27 */ - /* PA26 */ { 0, 0, 0, 0, 0, 0 }, /* PA26 */ - /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ - /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ - /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ - /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ - /* PA21 */ { 0, 0, 0, 0, 0, 0 }, /* PA21 */ - /* PA20 */ { 0, 0, 0, 0, 0, 0 }, /* PA20 */ - /* PA19 */ { 0, 0, 0, 0, 0, 0 }, /* PA19 */ - /* PA18 */ { 0, 0, 0, 0, 0, 0 }, /* PA18 */ - /* PA17 */ { 0, 0, 0, 0, 0, 0 }, /* PA17 */ - /* PA16 */ { 0, 0, 0, 0, 0, 0 }, /* PA16 */ - /* PA15 */ { 0, 0, 0, 0, 0, 0 }, /* PA15 */ - /* PA14 */ { 0, 0, 0, 0, 0, 0 }, /* PA14 */ - /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ - /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ - /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ - /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */ - /* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ - /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ - /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ - /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ - /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ - }, - - /* Port B */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */ - /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */ - /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */ - /* PB28 */ { 0, 0, 0, 0, 0, 0 }, /* PB28 */ - /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */ - /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */ - /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */ - /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */ - /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */ - /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */ - /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */ - /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */ - /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */ - /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */ - /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ - /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ - /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ - /* PC25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RxClk */ - /* PC24 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 TxClk */ - /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ - /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */ - /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ - /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */ - /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ - /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ - /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */ - /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ - /* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CTS */ - /* PC8 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: CD */ - /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ - /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ - /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */ - /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ - /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ - /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ - /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ - /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */ - /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */ - /* PD20 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: RTS */ - /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ - /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */ - /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */ - /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */ - /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ - } -}; - -/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx - * - * This routine performs standard 8260 initialization sequence - * and calculates the available memory size. It may be called - * several times to try different SDRAM configurations on both - * 60x and local buses. - */ -static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, - ulong orx, volatile uchar * base) -{ - volatile uchar c = 0xff; - volatile uint *sdmr_ptr; - volatile uint *orx_ptr; - ulong maxsize, size; - int i; - - /* We must be able to test a location outsize the maximum legal size - * to find out THAT we are outside; but this address still has to be - * mapped by the controller. That means, that the initial mapping has - * to be (at least) twice as large as the maximum expected size. - */ - maxsize = (1 + (~orx | 0x7fff))/* / 2*/; - - sdmr_ptr = &memctl->memc_psdmr; - orx_ptr = &memctl->memc_or1; - - *orx_ptr = orx; - - /* - * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): - * - * "At system reset, initialization software must set up the - * programmable parameters in the memory controller banks registers - * (ORx, BRx, P/LSDMR). After all memory parameters are configured, - * system software should execute the following initialization sequence - * for each SDRAM device. - * - * 1. Issue a PRECHARGE-ALL-BANKS command - * 2. Issue eight CBR REFRESH commands - * 3. Issue a MODE-SET command to initialize the mode register - * - * The initial commands are executed by setting P/LSDMR[OP] and - * accessing the SDRAM with a single-byte transaction." - * - * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. - */ - - *sdmr_ptr = sdmr | PSDMR_OP_PREA; - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_CBRR; - for (i = 0; i < 8; i++) - *base = c; - - *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ - - *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; - *base = c; - - size = get_ram_size((long *)base, maxsize); - *orx_ptr = orx | ~(size - 1); - - return (size); -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *immap = (immap_t *) CFG_IMMR; - volatile memctl8260_t *memctl = &immap->im_memctl; - - long psize; - - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; - -#ifndef CFG_RAMBOOT - /* 60x SDRAM setup: - */ - psize = try_init (memctl, CFG_PSDMR, CFG_OR1, - (uchar *) CFG_SDRAM_BASE); -#endif /* CFG_RAMBOOT */ - - icache_enable (); - - return (psize); -} - -int checkboard(void) -{ - puts("Board: mgcoge\n"); - - return 0; -} - -/* - * Early board initalization. - */ -int board_early_init_r(void) -{ - /* setup the UPIOx */ - *(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0; - *(char *)(CFG_PIGGY_BASE + 0x03) = 0x15; - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) -/* - * update "memory" property in the blob - */ -void ft_blob_update(void *blob, bd_t *bd) -{ - int ret, nodeoffset = 0; - ulong memory_data[2] = {0}; - ulong flash_data[8] = {0}; - - memory_data[0] = cpu_to_be32(bd->bi_memstart); - memory_data[1] = cpu_to_be32(bd->bi_memsize); - - nodeoffset = fdt_path_offset (blob, "/memory"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, - sizeof(memory_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /memory/reg " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /memory node " - "err:%s\n", fdt_strerror(nodeoffset)); - } - /* update Flash addr, size */ - flash_data[2] = cpu_to_be32(CFG_FLASH_BASE); - flash_data[3] = cpu_to_be32(CFG_FLASH_SIZE); - flash_data[4] = cpu_to_be32(1); - flash_data[5] = cpu_to_be32(0); - flash_data[6] = cpu_to_be32(CFG_FLASH_BASE_1); - flash_data[7] = cpu_to_be32(CFG_FLASH_SIZE_1); - nodeoffset = fdt_path_offset (blob, "/localbus"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, - sizeof(flash_data)); - if (ret < 0) - printf("ft_blob_update(): cannot set /localbus/ranges " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /localbus node " - "err:%s\n", fdt_strerror(nodeoffset)); - } - /* MAC Adresse */ - nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); - if (nodeoffset >= 0) { - ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, - sizeof(uchar) * 6); - if (ret < 0) - printf("ft_blob_update(): cannot set /soc/cpm/ethernet/mac-address " - "property err:%s\n", fdt_strerror(ret)); - } - else { - /* memory node is required in dts */ - printf("ft_blob_update(): cannot find /soc/cpm/ethernet node " - "err:%s\n", fdt_strerror(nodeoffset)); - } - -} - -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup( blob, bd); - ft_blob_update(blob, bd); -} -#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index c30bcb6d3..1092cd036 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -20,6 +20,7 @@ * MA 02111-1307 USA */ #include <common.h> +#include <netdev.h> #include <asm/io.h> #include <asm/sdram.h> @@ -150,8 +151,6 @@ void spi_cs_deactivate(struct spi_slave *slave) #endif /* CONFIG_ATMEL_SPI */ #ifdef CONFIG_CMD_NET -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - int board_eth_init(bd_t *bi) { macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index 7fd078125..8b3e22cd9 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <netdev.h> #include <asm/io.h> #include <asm/sdram.h> @@ -49,8 +50,6 @@ static const struct sdram_config sdram_config = { .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000, }; -extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); - #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { diff --git a/board/ml2/flash.c b/board/ml2/flash.c index ad0f0752b..c125d418d 100644 --- a/board/ml2/flash.c +++ b/board/ml2/flash.c @@ -22,7 +22,7 @@ #define FLASH_BANK_SIZE (64*1024*1024) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define SECT_SIZE (512*1024) @@ -61,16 +61,16 @@ ulong flash_init(void) { int i, j; ulong size = 0; - for(i=0;i<CFG_MAX_FLASH_BANKS;i++) { + for(i=0;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F128J3A & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i==0) - flashbase = CFG_FLASH_BASE; + flashbase = CONFIG_SYS_FLASH_BASE; else panic("configured too many flash banks!\n"); for (j = 0; j < flash_info[i].sector_count; j++) diff --git a/board/ml2/serial.c b/board/ml2/serial.c index c18815bf8..d9113ab93 100644 --- a/board/ml2/serial.c +++ b/board/ml2/serial.c @@ -25,26 +25,26 @@ #include <command.h> #include <configs/ML2.h> -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) #include <ns16550.h> #endif DECLARE_GLOBAL_DATA_PTR; -#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2) -const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1, - (NS16550_t) CFG_NS16550_COM2 +#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2) +const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1, + (NS16550_t) CONFIG_SYS_NS16550_COM2 }; #endif int serial_init (void) { - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 (void) NS16550_init (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 (void) NS16550_init (COM_PORTS[1], clock_divisor); #endif return 0; @@ -54,29 +54,29 @@ int serial_init (void) void serial_putc (const char c) { if (c == '\n') - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r'); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } int serial_getc (void) { - return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } int serial_tstc (void) { - return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]); } void serial_setbrg (void) { - int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate; -#ifdef CFG_INIT_CHAN1 +#ifdef CONFIG_SYS_INIT_CHAN1 NS16550_reinit (COM_PORTS[0], clock_divisor); #endif -#ifdef CFG_INIT_CHAN2 +#ifdef CONFIG_SYS_INIT_CHAN2 NS16550_reinit (COM_PORTS[1], clock_divisor); #endif } diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds index c9406ad7f..13ceea042 100644 --- a/board/ml2/u-boot.lds +++ b/board/ml2/u-boot.lds @@ -63,14 +63,13 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -141,6 +140,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug index 0552994f4..338392a07 100644 --- a/board/ml2/u-boot.lds.debug +++ b/board/ml2/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c index a50639e09..4c3114328 100644 --- a/board/modnet50/flash.c +++ b/board/modnet50/flash.c @@ -76,7 +76,7 @@ #define AVAIL_SIZE (DEVICE_SIZE*MAX_FLASH_DEVICES - RESERVED_CELLS*CELL_SIZE) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static __u16 toggling_bits; @@ -120,8 +120,8 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info) case AMD_ID_LV160B: info->flash_id += (FLASH_AM160LV | FLASH_AM160B) & FLASH_TYPEMASK; - info->sector_count = CFG_MAX_FLASH_SECT; - info->size = CFG_FLASH_SIZE; + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; + info->size = CONFIG_SYS_FLASH_SIZE; /* 1*16K Boot Block 2*8K Parameter Block 1*32K Small Main Block */ @@ -130,7 +130,7 @@ ulong flash_get_size (ulong baseaddr, flash_info_t * info) info->start[2] = baseaddr + 0x6000; info->start[3] = baseaddr + 0x8000; for (i = 1; i < info->sector_count; i++) - info->start[3 + i] = baseaddr + i * CFG_MAIN_SECT_SIZE; + info->start[3 + i] = baseaddr + i * CONFIG_SYS_MAIN_SECT_SIZE; break; default: info->flash_id = FLASH_UNKNOWN; @@ -160,12 +160,12 @@ ulong flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size = flash_get_size (CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", @@ -176,13 +176,13 @@ ulong flash_init (void) * protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -345,7 +345,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* arm simple, non interrupt dependent timer */ reset_timer_masked (); while (flash_check_erase_amd (info->start[sect])) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("timeout!\n"); /* OOPS: reach timeout, * try to reset chip @@ -449,7 +449,7 @@ static int write_word (flash_info_t * info, ulong dest, ushort data) reset_timer_masked (); while (flash_check_write_amd (dest)) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { printf ("timeout! @ %08lX\n", dest); /* OOPS: reach timeout, * try to reset chip */ diff --git a/board/modnet50/u-boot.lds b/board/modnet50/u-boot.lds index b3c2bf950..a435466d4 100644 --- a/board/modnet50/u-boot.lds +++ b/board/modnet50/u-boot.lds @@ -51,7 +51,7 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c index 3b3406222..b3692190b 100644 --- a/board/motionpro/motionpro.c +++ b/board/motionpro/motionpro.c @@ -5,7 +5,7 @@ * modified for Promess PRO - by Andy Joseph, andy@promessdev.com * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3 - * Also changed the refresh for 100Mhz operation + * Also changed the refresh for 100MHz operation * * See file CREDITS for list of people who contributed to this * project. @@ -96,7 +96,7 @@ void reset_phy(void) return; } -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* * Helper function to initialize SDRAM controller. */ @@ -126,7 +126,7 @@ static void sdram_start(int hi_addr) /* normal operation */ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; } -#endif /* !CFG_RAMBOOT */ +#endif /* !CONFIG_SYS_RAMBOOT */ /* @@ -135,7 +135,7 @@ static void sdram_start(int hi_addr) phys_size_t initdram(int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* According to AN3221 (MPC5200B SDRAM Initialization and @@ -153,9 +153,9 @@ phys_size_t initdram(int board_type) *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -178,14 +178,14 @@ phys_size_t initdram(int board_type) /* let SDRAM CS1 start right after CS0 and disable it */ *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; -#else /* !CFG_RAMBOOT */ +#else /* !CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; if (dramsize >= 0x13) dramsize = (1 << (dramsize - 0x13)) << 20; else dramsize = 0; -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* return total ram size */ return dramsize; diff --git a/board/mousse/flash.c b/board/mousse/flash.c index 2c32b8ffa..d729f33f9 100644 --- a/board/mousse/flash.c +++ b/board/mousse/flash.c @@ -50,7 +50,7 @@ int flashLibInited = 0; #define PRIVATE #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define SLEEP_DELAY 166 #define FLASH_SECTOR_SIZE (64*1024) diff --git a/board/mousse/m48t59y.c b/board/mousse/m48t59y.c index 2c1e6cf8b..beb26fe2d 100644 --- a/board/mousse/m48t59y.c +++ b/board/mousse/m48t59y.c @@ -299,8 +299,7 @@ rtc_get( struct rtc_time *tmp ) return 0; } -void -rtc_set( struct rtc_time *tmp ) +int rtc_set( struct rtc_time *tmp ) { m48_tod_set(tmp->tm_year, /* 1980-2079 */ tmp->tm_mon, /* 01-12 */ @@ -315,6 +314,7 @@ rtc_set( struct rtc_time *tmp ) tmp->tm_hour, tmp->tm_min, tmp->tm_sec); #endif + return 0; } void diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c index f8f152976..bd8d1c6f0 100644 --- a/board/mousse/mousse.c +++ b/board/mousse/mousse.c @@ -28,7 +28,9 @@ #include <common.h> #include <mpc824x.h> +#include <netdev.h> #include <asm/processor.h> +#include <timestamp.h> #include "mousse.h" #include "m48t59y.h" @@ -41,7 +43,7 @@ int checkboard (void) char buf[32]; puts ("Board: MOUSSE MPC8240/KAHLUA - CHRP (MAP B)\n"); - printf ("Built: %s at %s\n", __DATE__, __TIME__); + printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); printf ("MPLD: Revision %d\n", SYS_REVID_GET ()); printf ("Local Bus: %s MHz\n", strmhz (buf, busfreq)); @@ -57,7 +59,7 @@ int checkflash (void) phys_size_t initdram (int board_type) { - return CFG_RAM_SIZE; + return CONFIG_SYS_RAM_SIZE; } @@ -84,3 +86,8 @@ int misc_init_f (void) get_tod (); return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h index 5468314eb..10a0062a8 100644 --- a/board/mousse/mousse.h +++ b/board/mousse/mousse.h @@ -204,17 +204,17 @@ #define PROMISE_MBAR5 (PROMISE_MBAR0 + 0x5000) /* ATA/66 Controller offsets */ -#define CFG_ATA_BASE_ADDR PROMISE_MBAR0 -#define CFG_IDE_MAXBUS 2 /* ide0/ide1 */ -#define CFG_IDE_MAXDEVICE 2 /* 2 drives per controller */ -#define CFG_ATA_IDE0_OFFSET 0 -#define CFG_ATA_IDE1_OFFSET 0x3000 +#define CONFIG_SYS_ATA_BASE_ADDR PROMISE_MBAR0 +#define CONFIG_SYS_IDE_MAXBUS 2 /* ide0/ide1 */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 2 drives per controller */ +#define CONFIG_SYS_ATA_IDE0_OFFSET 0 +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x3000 /* * Definitions for accessing IDE controller registers */ -#define CFG_ATA_DATA_OFFSET 0 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_ALT_OFFSET (0x1000) +#define CONFIG_SYS_ATA_DATA_OFFSET 0 +#define CONFIG_SYS_ATA_REG_OFFSET 0 +#define CONFIG_SYS_ATA_ALT_OFFSET (0x1000) /* * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 86a1d85ed..818887380 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram index 46b98a04a..d048e52d3 100644 --- a/board/mousse/u-boot.lds.ram +++ b/board/mousse/u-boot.lds.ram @@ -96,7 +96,7 @@ SECTIONS .ppcenv : { - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) } > ram _end = . ; diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom index 3ba7c3c9a..27d10b6d6 100644 --- a/board/mousse/u-boot.lds.rom +++ b/board/mousse/u-boot.lds.rom @@ -60,7 +60,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c index c19d445e2..21a8ef9e5 100644 --- a/board/mp2usb/flash.c +++ b/board/mp2usb/flash.c @@ -30,10 +30,10 @@ #include <common.h> #include <linux/byteorder/swab.h> -#define CFG_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define FLASH_PORT_WIDTH ushort #define FLASH_PORT_WIDTHV vu_short @@ -77,7 +77,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -93,13 +93,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0] ); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); return size; } @@ -220,10 +220,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) INTEL_RESET; /* restore read mode */ @@ -303,7 +303,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW) INTEL_CONFIRM; /* erase confirm */ while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) INTEL_SUSPEND; /* suspend erase */ *addr = (FPW) INTEL_RESET; /* reset to read mode */ @@ -449,7 +449,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) INTEL_RESET; /* restore read mode */ return (1); } @@ -500,7 +500,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) reset_timer_masked (); while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; break; @@ -532,7 +532,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) *addr = (FPW) INTEL_PROTECT; /* set */ while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) + if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; diff --git a/board/mp2usb/u-boot.lds b/board/mp2usb/u-boot.lds index 3b7977672..d0666ac73 100644 --- a/board/mp2usb/u-boot.lds +++ b/board/mp2usb/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/mpc8540eval/ddr.c b/board/mpc8540eval/ddr.c index 45372f427..7850794d6 100644 --- a/board/mpc8540eval/ddr.c +++ b/board/mpc8540eval/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c index 79eb04ca8..9df5bd9a4 100644 --- a/board/mpc8540eval/flash.c +++ b/board/mpc8540eval/flash.c @@ -31,19 +31,19 @@ #include <common.h> -#if !defined(CFG_NO_FLASH) +#if !defined(CONFIG_SYS_NO_FLASH) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -74,7 +74,7 @@ unsigned long flash_init (void) /* Init: enable write, * or we cannot even write flash commands */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; /* set the default sector offset */ @@ -82,7 +82,7 @@ unsigned long flash_init (void) /* Static FLASH Bank configuration here - FIXME XXX */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", @@ -90,24 +90,24 @@ unsigned long flash_init (void) } /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size; #if !defined(CONFIG_RAM_AS_FLASH) -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif #endif @@ -177,8 +177,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) udelay(20); asm("sync"); -#ifndef CFG_FLASH_CFI - printf("Not define CFG_FLASH_CFI\n"); +#ifndef CONFIG_SYS_FLASH_CFI + printf("Not define CONFIG_SYS_FLASH_CFI\n"); return (0); #else value = addr[0]; @@ -237,7 +237,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) break; } #endif -#endif /*#ifdef CFG_FLASH_CFI*/ +#endif /*#ifdef CONFIG_SYS_FLASH_CFI*/ if (big_endian==0) value = (addr[0] & 0xFF000000) >>8; else value = (addr[0] & 0x00FF0000); @@ -453,7 +453,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) asm("sync"); return 1; } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr16 = 0xFFFF; /* reset bank */ asm("sync"); @@ -505,7 +505,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) asm("sync"); return 1; } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xFFFFFFFF; /* reset bank */ asm("sync"); @@ -693,7 +693,7 @@ static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt) /* data polling for D7 */ flag = 0; while (((csr = *addr) & ready) != ready) { - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { flag = 1; break; } @@ -751,7 +751,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) /* data polling for D7 */ flag = 0; while (((csr = *addr) & ready) != ready) { - if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { flag = 1; break; } @@ -815,7 +815,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); flag = 0; while (((csr = *addr) & ready) != ready) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flag = 1; break; } @@ -881,7 +881,7 @@ static int clear_block_lock_bit(flash_info_t * info, vu_long * addr) *addr = 0x70707070; /* read status */ start = get_timer (0); while((*addr & ready) != ready){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout on clearing Block Lock Bit\n"); *addr = 0xFFFFFFFF; /* reset bank */ asm("sync"); @@ -891,4 +891,4 @@ static int clear_block_lock_bit(flash_info_t * info, vu_long * addr) return 0; } -#endif /* !CFG_NO_FLASH */ +#endif /* !CONFIG_SYS_NO_FLASH */ diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c index cfcd73e9e..9926d25ef 100644 --- a/board/mpc8540eval/law.c +++ b/board/mpc8540eval/law.c @@ -43,11 +43,11 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), #ifndef CONFIG_RAM_AS_FLASH - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 7c54458a5..fa0a33686 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <netdev.h> #include <asm/processor.h> #include <asm/mmu.h> #include <asm/immap_85xx.h> @@ -35,7 +36,7 @@ long int fixed_sdram (void); int board_pre_init (void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -52,10 +53,10 @@ int checkboard (void) printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); - if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ - || (CFG_LBC_LCRR & 0x0f) == 8) { + if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ + || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) { printf ("\tLBC: %lu MHz\n", - sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f)); + sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f)); } else { printf("\tLBC: unknown\n"); } @@ -68,12 +69,12 @@ phys_size_t initdram (int board_type) long dram_size = 0; #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) @@ -93,42 +94,42 @@ phys_size_t initdram (int board_type) dram_size = fixed_sdram (); #endif -#if defined(CFG_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) return dram_size; #endif #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; + /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ + if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { - lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; + lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; udelay(200); temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; - lbc->lsdmr = CFG_LBC_LSDMR_1; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ + lbc->br2 = CONFIG_SYS_BR2_PRELIM; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_3; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_5; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); - lbc->lsrt = CFG_LBC_LSRT; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); #endif @@ -138,7 +139,7 @@ phys_size_t initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -180,11 +181,11 @@ phys_size_t initdram (int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); @@ -220,15 +221,15 @@ int testdram (void) ************************************************************************/ long int fixed_sdram (void) { -#ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; +#ifndef CONFIG_SYS_RAMBOOT + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000000D; ddr->err_sbe = 0x00ff0000; @@ -237,13 +238,24 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); #endif - return (CFG_SDRAM_SIZE * 1024 * 1024); + return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024); } #endif /* !defined(CONFIG_SPD_EEPROM) */ + +int board_eth_init(bd_t *bis) +{ + /* + * This board either has PCI NICs or uses the CPU's TSECs + * pci_eth_init() will return 0 if no NICs found, so in that case + * returning -1 will force cpu_eth_init() to be called. + */ + int num = pci_eth_init(bis); + return (num <= 0 ? -1 : num); +} diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c index 1003bf613..06092f89b 100644 --- a/board/mpc8540eval/tlb.c +++ b/board/mpc8540eval/tlb.c @@ -27,34 +27,34 @@ #include <asm/mmu.h> struct fsl_e_tlb_entry tlb_table[] = { - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), - #if defined(CFG_FLASH_PORT_WIDTH_16) - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + #if defined(CONFIG_SYS_FLASH_PORT_WIDTH_16) + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_4M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x400000, CFG_FLASH_BASE + 0x400000, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x400000, CONFIG_SYS_FLASH_BASE + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_4M, 1), #else - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_16M, 1), #endif #if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_64M, 1), #endif - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, #if defined(CONFIG_RAM_AS_FLASH) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, #else @@ -62,15 +62,15 @@ struct fsl_e_tlb_entry tlb_table[] = { #endif 0, 6, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_16K, 1), - SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR, + SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_16K, 1), }; diff --git a/board/mpc8540eval/u-boot.lds b/board/mpc8540eval/u-boot.lds index dadfc7dee..d65ccbef4 100644 --- a/board/mpc8540eval/u-boot.lds +++ b/board/mpc8540eval/u-boot.lds @@ -133,6 +133,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 24ce80785..877a2d004 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -53,7 +53,7 @@ extern int gunzip(void *, int, uchar *, unsigned long *); extern int mem_test(ulong start, ulong ramsize, int quiet); #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ -#define IMAGE_SIZE CFG_MONITOR_LEN /* ugly, but it works for now */ +#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN /* ugly, but it works for now */ extern flash_info_t flash_info[]; /* info for FLASH chips */ @@ -270,7 +270,7 @@ mpl_prg_image(uchar *ld_addr) #if !defined(CONFIG_PATI) void get_backup_values(backup_t *buf) { - i2c_read(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); + i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t)); } void set_backup_values(int overwrite) @@ -298,7 +298,7 @@ void set_backup_values(int overwrite) return; } back.eth_addr[20]=0; - i2c_write(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); + i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); } void clear_env_values(void) @@ -308,8 +308,8 @@ void clear_env_values(void) memset(&back,0xff,sizeof(backup_t)); memset(env_crc,0x00,4); - i2c_write(CFG_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); - i2c_write(CFG_DEF_EEPROM_ADDR,CFG_ENV_OFFSET,2,(void *)env_crc,4); + i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t)); + i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4); } /* @@ -322,8 +322,8 @@ int check_env_old_size(ulong oldsize) uchar buf[64]; /* read old CRC */ - eeprom_read (CFG_DEF_EEPROM_ADDR, - CFG_ENV_OFFSET, + eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, + CONFIG_ENV_OFFSET, (uchar *)&crc, sizeof(ulong)); new = 0; @@ -333,7 +333,7 @@ int check_env_old_size(ulong oldsize) while (len > 0) { int n = (len > sizeof(buf)) ? sizeof(buf) : len; - eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, buf, n); + eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n); new = crc32 (new, buf, n); len -= n; off += n; @@ -362,7 +362,7 @@ void copy_old_env(ulong size) len=size; off = sizeof(long); while (len > off) { - eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1); + eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1); if(c != '=') { *name++=c; off++; @@ -371,7 +371,7 @@ void copy_old_env(ulong size) *name++='\0'; off++; do { - eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, &c, 1); + eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1); *value++=c; off++; if(c == '\0') @@ -485,7 +485,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else { local_args[1] = NULL; - ld_addr=CFG_LOAD_ADDR; + ld_addr=CONFIG_SYS_LOAD_ADDR; result=do_fdcboot(cmdtp, 0, 1, local_args); } result=mpl_prg_image((uchar *)ld_addr); @@ -519,14 +519,14 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) result = (int)simple_strtol(argv[2], NULL, 16); } src=(unsigned long)&result; - src-=CFG_MEMTEST_START; + src-=CONFIG_SYS_MEMTEST_START; src-=(100*1024); /* - 100k */ src&=0xfff00000; size=0; do { size++; printf("\n\nPass %ld\n",size); - mem_test(CFG_MEMTEST_START,src,1); + mem_test(CONFIG_SYS_MEMTEST_START,src,1); if(ctrlc()) break; if(result>0) @@ -565,7 +565,6 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_CMD_DOC) -extern void doc_probe(ulong physadr); void doc_init (void) { doc_probe(MULTI_PURPOSE_SOCKET_ADDR); @@ -592,7 +591,7 @@ void video_get_info_str (int line_number, char *info) int i,boot; unsigned long pvr; char buf[64]; - char tmp[16]; + char buf1[32], buf2[32], buf3[32], buf4[32]; char cpustr[16]; char *s, *e, bc; switch (line_number) @@ -645,11 +644,12 @@ void video_get_info_str (int line_number, char *info) } buf[i++]=0; } - sprintf (info," %s %s %s MHz (%lu/%lu/%lu MHz)", + sprintf (info," %s %s %s MHz (%s/%s/%s MHz)", buf, cpustr, - strmhz (tmp, gd->cpu_clk), sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - sys_info.freqPLB / sys_info.pllExtBusDiv / 1000000); + strmhz (buf1, gd->cpu_clk), + strmhz (buf2, sys_info.freqPLB), + strmhz (buf3, sys_info.freqPLB / sys_info.pllOpbDiv), + strmhz (buf4, sys_info.freqPLB / sys_info.pllExtBusDiv)); return; case 3: /* Memory Info */ diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index eb2702b6d..302d7a3d5 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -52,7 +52,7 @@ #include <mpc5xx.h> #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions */ @@ -89,7 +89,7 @@ void unlock_intel_sectors(flash_info_t *info,ulong addr,ulong cnt); * The board_init_r will fill in wrong values in the board init structure, * but this will be fixed in the misc_init_r routine: * bd->bi_flashstart=0-flash_info[0].size - * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN + * bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN * bd->bi_flashoffset=0 * */ @@ -174,13 +174,13 @@ unsigned long flash_init (void) "MPS" : "Flash"); #endif /* #if !defined(CONFIG_PATI) */ /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here - FIXME XXX */ - size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_MONITOR_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", @@ -188,10 +188,10 @@ unsigned long flash_init (void) } /* protect the bootloader */ /* Monitor protection ON by default */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif #if !defined(CONFIG_PATI) @@ -256,11 +256,11 @@ unsigned long flash_init (void) p++; } #else /* #if !defined(CONFIG_PATI) */ -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif #endif /* #if !defined(CONFIG_PATI) */ @@ -555,7 +555,7 @@ int wait_for_DQ7(flash_info_t *info, int sect) start = get_timer (0); last = start; while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return ERR_TIMOUT; } @@ -576,7 +576,7 @@ int intel_wait_for_DQ7(flash_info_t *info, int sect) start = get_timer (0); last = start; while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return ERR_TIMOUT; } @@ -848,7 +848,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) udelay(10); while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */ @@ -869,7 +869,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c index 51b2773c7..91829d44f 100644 --- a/board/mpl/common/isa.c +++ b/board/mpl/common/isa.c @@ -113,9 +113,9 @@ const SIO_LOGDEV_TABLE sio_keyboard[] = { ********************************************************************************/ unsigned char open_cfg_super_IO(int address) { - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */ - if(in8(CFG_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */ + if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */ return TRUE; else return FALSE; @@ -123,26 +123,26 @@ unsigned char open_cfg_super_IO(int address) void close_cfg_super_IO(int address) { - out8(CFG_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */ } unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr) { /* assuming config reg is open */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ - out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ - return in8(CFG_ISA_IO_BASE_ADDRESS | address | 1); + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ + return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1); } void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data) { /* assuming config reg is open */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ - out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ - out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ - out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */ + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */ } void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev) @@ -208,12 +208,12 @@ static unsigned int cached_irq_mask = 0xfff9; #define cached_imr1 (unsigned char)cached_irq_mask #define cached_imr2 (unsigned char)(cached_irq_mask>>8) -#define IMR_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1 -#define IMR_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1 -#define ICW1_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1 -#define ICW1_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1 -#define ICW2_1 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2 -#define ICW2_2 CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2 +#define IMR_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1 +#define IMR_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1 +#define ICW1_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1 +#define ICW1_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1 +#define ICW2_1 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2 +#define ICW2_2 CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2 #define ICW3_1 ICW2_1 #define ICW3_2 ICW2_2 #define ICW4_1 ICW2_1 diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c index b20b9532b..a457635d4 100644 --- a/board/mpl/common/kbd.c +++ b/board/mpl/common/kbd.c @@ -203,7 +203,7 @@ int isa_kbd_init(void) } } -#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE +#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE extern int overwrite_console (void); #else int overwrite_console (void) @@ -452,22 +452,22 @@ unsigned char handle_kbd_event(void) */ unsigned char kbd_read_status(void) { - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); + return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT)); } unsigned char kbd_read_input(void) { - return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); + return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT)); } void kbd_write_command(unsigned char cmd) { - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd); } void kbd_write_output(unsigned char data) { - out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); + out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data); } int kbd_read_data(void) diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c index 666b999e3..a0094372a 100644 --- a/board/mpl/common/usb_uhci.c +++ b/board/mpl/common/usb_uhci.c @@ -621,7 +621,7 @@ int usb_lowlevel_init(void) pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr); USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr); usb_base_addr&=0xFFFFFFF0; - usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS; + usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS; rh.devnum = 0; usb_init_skel(); reset_hc(); @@ -792,7 +792,7 @@ int uhci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer, unsigned short wIndex; unsigned short wLength; - if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) { + if (usb_pipeint(pipe)) { printf("Root-Hub submit IRQ: NOT implemented\n"); #if 0 uhci->rh.urb = urb; diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index cf0afd1ad..5eb90e590 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -250,7 +250,7 @@ int init_sdram (void) unsigned char bc; unsigned long sdram_tim, sdram_bank; - /*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/ + /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/ (void) get_clocks (); gd->baudrate = 9600; serial_init (); @@ -320,7 +320,7 @@ int init_sdram (void) serial_puts ("\n"); #endif i = 0; - baseaddr = CFG_SDRAM_BASE; + baseaddr = CONFIG_SYS_SDRAM_BASE; while (sdram_table[i].sz != 0xff) { if (sdram_table[i].boardtype == bc) break; @@ -679,7 +679,7 @@ int misc_init_r (void) { /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; + gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; gd->bd->bi_flashoffset=0; /* check, if RTC is running */ diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds index 7932b9fc0..8714c2bdf 100644 --- a/board/mpl/mip405/u-boot.lds +++ b/board/mpl/mip405/u-boot.lds @@ -72,14 +72,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -150,6 +150,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c index 91683a38d..9d9531b54 100644 --- a/board/mpl/pati/cmd_pati.c +++ b/board/mpl/pati/cmd_pati.c @@ -37,7 +37,7 @@ extern void user_led0(int led_on); extern void user_led1(int led_on); /* ------------------------------------------------------------------------- */ -#if defined(CFG_PCI_CON_DEVICE) +#if defined(CONFIG_SYS_PCI_CON_DEVICE) extern void pci_con_disc(void); extern void pci_con_connect(void); #endif @@ -378,7 +378,7 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) user_led1(led_on); return 0; } -#if defined(CFG_PCI_CON_DEVICE) +#if defined(CONFIG_SYS_PCI_CON_DEVICE) if (strcmp(argv[1], "con") == 0) { pci_con_connect(); return 0; diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 475741d2a..85c5af956 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -224,7 +224,7 @@ phys_size_t initdram(int board_type) /* rest standard operation programmed write burst length */ /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */ lmr<<=2; - in32(CFG_SDRAM_BASE + lmr); + in32(CONFIG_SYS_SDRAM_BASE + lmr); /* ok, we're done, return SDRAM size */ return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */ } @@ -287,7 +287,7 @@ void show_pld_regs(void) ****************************************************************/ void init_ios(void) { - volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; unsigned long reg; reg=sysconf->sc_sgpiocr; /* Data direction register */ @@ -304,7 +304,7 @@ void show_pld_regs(void) void user_led0(int led_on) { - volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; unsigned long reg; reg=sysconf->sc_sgpiodt2; /* Data register */ @@ -317,7 +317,7 @@ void user_led0(int led_on) void user_led1(int led_on) { - volatile immap_t * immr = (immap_t *) CFG_IMMR; + volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR; volatile sysconf5xx_t *sysconf = &immr->im_siu_conf; unsigned long reg; reg=sysconf->sc_sgpiodt2; /* Data register */ @@ -370,7 +370,7 @@ int checkboard (void) } -#ifdef CFG_PCI_CON_DEVICE +#ifdef CONFIG_SYS_PCI_CON_DEVICE /************************************************************************ * PCI Communication * @@ -610,9 +610,9 @@ void pci_con_disc(void) irq_free_handler(0x02); pci_con_connect(); } -#endif /* #ifdef CFG_PCI_CON_DEVICE */ +#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */ /* * Absolute environment address for linker file. */ -GEN_ABS(env_start, CFG_ENV_OFFSET + CFG_FLASH_BASE); +GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE); diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 6cba892e7..8724e27af 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -208,7 +208,7 @@ int board_early_init_f (void) #endif /* Read Serial Presence Detect Information */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); dataout[0] = 0; for (i = 0; i < 128; i++) datain[i] = 127; @@ -252,7 +252,7 @@ int board_early_init_f (void) (datain[2] != 0x04) || /* if not SDRAM */ (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ - (datain[126] == 0x66)) /* or a 66Mhz modules */ + (datain[126] == 0x66)) /* or a 66MHz modules */ SDRAM_err ("unsupported SDRAM"); #ifdef SDRAM_DEBUG serial_puts ("SDRAM sanity ok\n"); @@ -386,7 +386,7 @@ int board_early_init_f (void) /* write SDRAM timing register */ mtdcr (memcfga, mem_sdtr1); mtdcr (memcfgd, tmp); - baseaddr = CFG_SDRAM_BASE; + baseaddr = CONFIG_SYS_SDRAM_BASE; bank_size = (((unsigned long) density) << 22) / 2; /* insert AM value */ tmp = ((unsigned long) t->mode - 1) << 13; @@ -663,7 +663,7 @@ int misc_init_r (void) { /* adjust flash start and size as well as the offset */ gd->bd->bi_flashstart=0-flash_info[0].size; - gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN; + gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; gd->bd->bi_flashoffset=0; /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h index 5815786eb..704ab2c71 100644 --- a/board/mpl/pip405/pip405.h +++ b/board/mpl/pip405/pip405.h @@ -35,7 +35,7 @@ void user_led0(unsigned char on); void user_led1(unsigned char on); -#define PLD_BASE_ADDRESS CFG_ISA_IO_BASE_ADDRESS + 0x800 +#define PLD_BASE_ADDRESS CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800 #define PLD_PART_REG PLD_BASE_ADDRESS + 0 #define PLD_VERS_REG PLD_BASE_ADDRESS + 1 #define PLD_BOARD_CFG_REG PLD_BASE_ADDRESS + 2 diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds index fb710649a..afe203b22 100644 --- a/board/mpl/pip405/u-boot.lds +++ b/board/mpl/pip405/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -145,6 +145,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index 0552994f4..338392a07 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c index d15a19115..7abf9cfba 100644 --- a/board/mpl/vcma9/flash.c +++ b/board/mpl/vcma9/flash.c @@ -30,7 +30,7 @@ ulong myflush (void); #define FLASH_BANK_SIZE PHYS_FLASH_SIZE #define MAIN_SECT_SIZE 0x10000 /* 64 KB */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x000000F0 @@ -41,8 +41,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define CMD_PROGRAM 0x000000A0 #define CMD_UNLOCK_BYPASS 0x00000020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) #define BIT_ERASE_DONE 0x00000080 #define BIT_RDY_MASK 0x00000080 @@ -61,7 +61,7 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = @@ -75,8 +75,8 @@ ulong flash_init (void) #error "Unknown flash configured" #endif flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -111,13 +111,13 @@ ulong flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -236,7 +236,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* check timeout */ if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip = TMO; break; @@ -331,7 +331,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { chip = ERR | TMO; break; } diff --git a/board/mpl/vcma9/u-boot.lds b/board/mpl/vcma9/u-boot.lds index 14cd22800..987b07d94 100644 --- a/board/mpl/vcma9/u-boot.lds +++ b/board/mpl/vcma9/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c index 98557b400..0ec0c198b 100644 --- a/board/mpr2/mpr2.c +++ b/board/mpr2/mpr2.c @@ -154,8 +154,8 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } diff --git a/board/mpr2/u-boot.lds b/board/mpr2/u-boot.lds index eda6b442a..b1f0e1d6d 100644 --- a/board/mpr2/u-boot.lds +++ b/board/mpr2/u-boot.lds @@ -53,9 +53,9 @@ SECTIONS { cpu/sh3/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c index af62cdfd2..f83c1208a 100644 --- a/board/ms7720se/ms7720se.c +++ b/board/ms7720se/ms7720se.c @@ -47,9 +47,9 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } diff --git a/board/ms7720se/u-boot.lds b/board/ms7720se/u-boot.lds index ba71a9195..2156f6a57 100644 --- a/board/ms7720se/u-boot.lds +++ b/board/ms7720se/u-boot.lds @@ -52,9 +52,9 @@ SECTIONS { cpu/sh3/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index 332f65a4c..8b46595f3 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -43,48 +43,61 @@ lowlevel_init: - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D, r0 ! Instruction Cache Invalidate + /* Address of Cache Control Register */ + mov.l CCR_A, r1 + /*Instruction Cache Invalidate */ + mov.l CCR_D, r0 mov.l r0, @r1 - mov.l MMUCR_A, r1 ! Address of MMU Control Register - mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit + /* Address of MMU Control Register */ + mov.l MMUCR_A, r1 + /* TI == TLB Invalidate bit */ + mov.l MMUCR_D, r0 mov.l r0, @r1 - mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 - mov.l MSTPCR0_D, r0 ! + /* Address of Power Control Register 0 */ + mov.l MSTPCR0_A, r1 + mov.l MSTPCR0_D, r0 mov.l r0, @r1 - mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 - mov.l MSTPCR2_D, r0 ! + /* Address of Power Control Register 2 */ + mov.l MSTPCR2_A, r1 + mov.l MSTPCR2_D, r0 mov.l r0, @r1 - mov.l SBSCR_A, r1 ! - mov.w SBSCR_D, r0 ! + mov.l SBSCR_A, r1 + mov.w SBSCR_D, r0 mov.w r0, @r1 - mov.l PSCR_A, r1 ! - mov.w PSCR_D, r0 ! + mov.l PSCR_A, r1 + mov.w PSCR_D, r0 mov.w r0, @r1 -! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) -! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max + /* 0xA4520004 (Watchdog Control / Status Register) */ +! mov.l RWTCSR_A, r1 + /* 0xA507 -> timer_STOP/WDT_CLK=max */ +! mov.w RWTCSR_D_1, r0 ! mov.w r0, @r1 - mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) - mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear + /* 0xA4520000 (Watchdog Count Register) */ + mov.l RWTCNT_A, r1 + /*0x5A00 -> Clear */ + mov.w RWTCNT_D, r0 mov.w r0, @r1 - mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms + /* 0xA4520004 (Watchdog Control / Status Register) */ + mov.l RWTCSR_A, r1 + /* 0xA504 -> timer_STOP/CLK=500ms */ + mov.w RWTCSR_D_2, r0 mov.w r0, @r1 - mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register + /* 0xA4150000 Frequency control register */ + mov.l FRQCR_A, r1 mov.l FRQCR_D, r0 ! mov.l r0, @r1 - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D_2, r0 ! ?? + mov.l CCR_A, r1 + mov.l CCR_D_2, r0 mov.l r0, @r1 bsc_init: @@ -290,5 +303,6 @@ PSCR_D: .word 0x0000 RWTCSR_D_1: .word 0xA507 RWTCSR_D_2: .word 0xA507 RWTCNT_D: .word 0x5A00 + .align 2 SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c index cf0224229..32234d3e0 100644 --- a/board/ms7722se/ms7722se.c +++ b/board/ms7722se/ms7722se.c @@ -47,9 +47,9 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } diff --git a/board/ms7722se/u-boot.lds b/board/ms7722se/u-boot.lds index 88b4f5c45..7dffe008a 100644 --- a/board/ms7722se/u-boot.lds +++ b/board/ms7722se/u-boot.lds @@ -49,9 +49,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/ms7750se/ms7750se.c b/board/ms7750se/ms7750se.c index d2d824c5a..02ff0a3df 100644 --- a/board/ms7750se/ms7750se.c +++ b/board/ms7750se/ms7750se.c @@ -39,9 +39,9 @@ int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } diff --git a/board/ms7750se/u-boot.lds b/board/ms7750se/u-boot.lds index 88b4f5c45..7dffe008a 100644 --- a/board/ms7750se/u-boot.lds +++ b/board/ms7750se/u-boot.lds @@ -49,9 +49,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index 49aed037c..6b1e59f97 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -163,8 +163,13 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ - /* PD15 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SCL */ +#if defined(CONFIG_HARD_I2C) + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ +#else + /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */ + /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */ +#endif /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ @@ -227,7 +232,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -238,7 +243,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -251,20 +256,30 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - long psize; +#ifndef CONFIG_SYS_RAMBOOT + long sizelittle, sizebig; +#endif - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - psize = try_init (memctl, CFG_PSDMR, CFG_OR1, - (uchar *) CFG_SDRAM_BASE); -#endif /* CFG_RAMBOOT */ + sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, + (uchar *) CONFIG_SYS_SDRAM_BASE); + sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG, + (uchar *) CONFIG_SYS_SDRAM_BASE); + if (sizelittle < sizebig) { + psize = sizebig; + } else { + psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, + (uchar *) CONFIG_SYS_SDRAM_BASE); + } +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -314,8 +329,8 @@ void ft_blob_update (void *blob, bd_t *bd) "err:%s\n", fdt_strerror(nodeoffset)); } /* update Flash addr, size */ - flash_data[2] = cpu_to_be32 (CFG_FLASH_BASE); - flash_data[3] = cpu_to_be32 (CFG_FLASH_SIZE); + flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE); + flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE); nodeoffset = fdt_path_offset (blob, "/localbus"); if (nodeoffset >= 0) { ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data, diff --git a/board/mucmc52/mucmc52.c b/board/mucmc52/mucmc52.c index ae3ca2422..7181bd8a4 100644 --- a/board/mucmc52/mucmc52.c +++ b/board/mucmc52/mucmc52.c @@ -37,7 +37,7 @@ #include <asm/processor.h> #include <asm/io.h> -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -86,7 +86,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -96,7 +96,7 @@ phys_size_t initdram (int board_type) ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -117,9 +117,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start (0); - test1 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start (0); dramsize = test1; @@ -146,10 +146,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start (0); - test2 = test1 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); if (!dramsize) { sdram_start (1); - test2 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); } if (test1 > test2) { sdram_start (0); @@ -171,7 +171,7 @@ phys_size_t initdram (int board_type) out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; @@ -189,25 +189,25 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM - * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: - * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing - * parameters." - */ - svr = get_svr(); - pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && - (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { - - out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04); - __asm__ volatile ("sync"); - } + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04); + __asm__ volatile ("sync"); + } return dramsize + dramsize2; } @@ -239,8 +239,8 @@ struct kbd_data_t { struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) { - kbd_data->s1 = in_8 ((volatile uchar*)CFG_STATUS1_BASE); - kbd_data->s2 = in_8 ((volatile uchar*)CFG_STATUS2_BASE); + kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE); + kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE); return kbd_data; } @@ -339,14 +339,14 @@ int misc_init_r (void) free (str); #endif /* CONFIG_PREBOOT */ - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' '); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' '); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' '); return 0; } @@ -354,27 +354,27 @@ int misc_init_r (void) int board_early_init_r (void) { out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1); - out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CFG_FLASH_BASE)); - out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CFG_FLASH_BASE)); + out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE)); + out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE)); out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP, - STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)); + STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)); out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP, - STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE)); + STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)); return 0; } int last_stage_init (void) { - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5'); - out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2'); - - return 0; + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M'); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U'); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C'); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.'); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M'); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C'); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5'); + out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2'); + + return 0; } #if defined(CONFIG_HW_WATCHDOG) diff --git a/board/munices/munices.c b/board/munices/munices.c index 162f89c50..c1207f196 100644 --- a/board/munices/munices.c +++ b/board/munices/munices.c @@ -27,7 +27,7 @@ #include "mt48lc16m16a2-75.h" -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -70,7 +70,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -78,7 +78,7 @@ phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -99,9 +99,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000); + test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000); sdram_start(1); - test2 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000); + test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -121,7 +121,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -139,7 +139,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize + dramsize2; } diff --git a/board/munices/u-boot.lds b/board/munices/u-boot.lds index e9b3be8ea..0a1a6ad43 100644 --- a/board/munices/u-boot.lds +++ b/board/munices/u-boot.lds @@ -116,6 +116,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/musenki/flash.c b/board/musenki/flash.c index cd33d8ed3..40965be45 100644 --- a/board/musenki/flash.c +++ b/board/musenki/flash.c @@ -24,15 +24,15 @@ #include <common.h> #include <mpc824x.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -46,7 +46,7 @@ #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -118,15 +118,15 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here - FIXME XXX */ - DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CFG_FLASH_BASE0_PRELIM); + DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE0_PRELIM); - size_b0 = flash_get_size((vu_char *)CFG_FLASH_BASE0_PRELIM, &flash_info[0]); + size_b0 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE0_PRELIM, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0: " @@ -135,50 +135,50 @@ unsigned long flash_init (void) size_b0, size_b0<<20); } - DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CFG_FLASH_BASE1_PRELIM); - size_b1 = flash_get_size((vu_char *)CFG_FLASH_BASE1_PRELIM, &flash_info[1]); + DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE1_PRELIM); + size_b1 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE1_PRELIM, &flash_info[1]); DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b0; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, monitor_flash_len); +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, monitor_flash_len); /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ - DEBUGF("protect environtment %x @ %x\n", CFG_ENV_ADDR, CFG_ENV_SECT_SIZE); + DEBUGF("protect environtment %x @ %x\n", CONFIG_ENV_ADDR, CONFIG_ENV_SECT_SIZE); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif if (size_b1) { flash_info[1].size = size_b1; - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[1]); #endif } else { @@ -343,10 +343,10 @@ static ulong flash_get_size (vu_char *addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = BS(0xFF); /* restore read mode */ @@ -414,7 +414,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = BS(0xB0); /* suspend erase */ *addr = BS(0xFF); /* reset to read mode */ @@ -497,7 +497,7 @@ static int write_data (flash_info_t *info, uchar *dest, uchar data) start = get_timer (0); while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = BS(0xFF); /* restore read mode */ return 1; } diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c index b2b70e756..30b95ce1d 100644 --- a/board/musenki/musenki.c +++ b/board/musenki/musenki.c @@ -24,6 +24,7 @@ #include <common.h> #include <mpc824x.h> #include <pci.h> +#include <netdev.h> int checkboard (void) { @@ -52,7 +53,7 @@ phys_size_t initdram (int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -102,3 +103,8 @@ void pci_init_board(void) { pci_mpc824x_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c index 0c0738cf2..2d6acf5a7 100644 --- a/board/mvblue/flash.c +++ b/board/mvblue/flash.c @@ -31,7 +31,7 @@ #define mvdebug(p) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define FLASH_BUS_WIDTH 8 @@ -65,7 +65,7 @@ unsigned long flash_init (void) unsigned long size_b0; int i; - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -416,7 +416,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr = (FDT *)(info->start[l_sect]); while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -554,7 +554,7 @@ static int write_char (flash_info_t *info, ulong dest, uchar data) start = get_timer (0); addr = (vu_char *)dest; while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf(" *** ERROR: Flash write timeout !"); return (1); } diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c index a979102ab..69abb0625 100644 --- a/board/mvblue/mvblue.c +++ b/board/mvblue/mvblue.c @@ -9,6 +9,7 @@ #include <mpc824x.h> #include <asm/io.h> #include <ns16550.h> +#include <netdev.h> #ifdef CONFIG_PCI #include <pci.h> @@ -37,8 +38,8 @@ u32 get_BoardType () void init_2nd_DUART (void) { - NS16550_t console = (NS16550_t) CFG_NS16550_COM2; - int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE; + NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2; + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE; *(u8 *) (0xfc004511) = 0x1; NS16550_init (console, clock_divisor); @@ -83,7 +84,7 @@ phys_size_t initdram (int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -146,12 +147,12 @@ void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev) void duart_setup (u32 base, u16 divisor) { printf ("duart setup ..."); - out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80); - out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff); - out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8); - out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03); - out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03); - out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07); + out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80); + out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff); + out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8); + out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03); + out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03); + out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07); printf ("done\n"); } @@ -245,4 +246,9 @@ void pci_init_board (void) { pci_mpc824x_init (&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} #endif diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c index fae9fbb39..47f613c7f 100644 --- a/board/mx1ads/syncflash.c +++ b/board/mx1ads/syncflash.c @@ -31,7 +31,7 @@ typedef unsigned long * p_u32; /* 4Mx16x2 IAM=0 CSD1 */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Following Setting is for CSD1 */ #define SFCTL 0x00221004 @@ -46,7 +46,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ #define CMD_PROGRAM (CMD_NORMAL + 0x70000000) -#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ +#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ /* LCR Command */ #define LCR_READSTATUS (0x0001C000) /* 0x70 */ @@ -60,12 +60,12 @@ u32 SF_SR(void) { u32 tmp,tmp1; reg_SFCTL = CMD_PROGRAM; - tmp = __REG(CFG_FLASH_BASE); + tmp = __REG(CONFIG_SYS_FLASH_BASE); reg_SFCTL = CMD_NORMAL; reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ - tmp1 = __REG(CFG_FLASH_BASE + LCR_SR_CLEAR); + tmp1 = __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); return tmp; } @@ -96,7 +96,7 @@ void SF_PrechargeAll(void) { u32 tmp; reg_SFCTL = CMD_PREC; /* Set Precharge Command */ - tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ + tmp = __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */ } /* set SyncFlash to normal mode */ @@ -130,10 +130,10 @@ void SF_NvmodeErase(void) { SF_PrechargeAll(); reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ + __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ + __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ while(!SF_Ready()); } @@ -142,10 +142,10 @@ void SF_NvmodeWrite(void) { SF_PrechargeAll(); reg_SFCTL = CMD_LCR; /* Set to LCR mode */ - __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ + __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ - __REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ + __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ } /****************************************************************************************/ @@ -169,22 +169,22 @@ ulong flash_init(void) { flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000; + flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000; } flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return FLASH_BANK_SIZE; @@ -281,7 +281,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) { SF_NvmodeErase(); SF_NvmodeWrite(); - SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect)); + SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect)); SF_Normal(); printf("ok.\n"); diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds index f2f8afca1..5460c8c0d 100644 --- a/board/mx1ads/u-boot.lds +++ b/board/mx1ads/u-boot.lds @@ -53,6 +53,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c index 73ce8957e..da4ebe6e7 100644 --- a/board/mx1fs2/flash.c +++ b/board/mx1fs2/flash.c @@ -28,7 +28,7 @@ #define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE #define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it @@ -62,7 +62,7 @@ static void flash_reset(flash_info_t * info); static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data); static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); #define write_word(in, de, da) write_word_amd(in, de, da) -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION static void flash_sync_real_protect(flash_info_t * info); #endif @@ -77,14 +77,14 @@ flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (FLASH_MAN_AMD & FLASH_VENDMASK) | (FLASH_AM640U & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: flashbase = MX1FS2_FLASH_BASE; @@ -101,13 +101,13 @@ flash_init(void) /* Protect monitor and environment sectors */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _bss_start - _armboot_start, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -389,7 +389,7 @@ flash_get_size(FPWV * addr, flash_info_t * info) } #endif /* 0 */ -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ @@ -528,7 +528,7 @@ flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(0)) - start > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); if (intel) { @@ -720,7 +720,7 @@ write_word_amd(flash_info_t * info, FPWV * dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) { + if (get_timer(0) - start > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ printf("SHA timeout\n"); res = 1; @@ -768,7 +768,7 @@ write_word_intel(flash_info_t * info, FPWV * dest, FPW data) start = get_timer(0); while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00B000B0; /* Suspend program */ res = 1; } @@ -783,7 +783,7 @@ write_word_intel(flash_info_t * info, FPWV * dest, FPW data) return (res); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ int diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S index 4b2cb487a..56a4819b0 100644 --- a/board/mx1fs2/lowlevel_init.S +++ b/board/mx1fs2/lowlevel_init.S @@ -29,19 +29,19 @@ lowlevel_init: /* Change PERCLK1DIV to 14 ie 14+1 */ ldr r0, =PCDR - ldr r1, =CFG_PCDR_VAL + ldr r1, =CONFIG_SYS_PCDR_VAL str r1, [r0] /* set MCU PLL Control Register 0 */ ldr r0, =MPCTL0 - ldr r1, =CFG_MPCTL0_VAL + ldr r1, =CONFIG_SYS_MPCTL0_VAL str r1, [r0] /* set MCU PLL Control Register 1 */ ldr r0, =MPCTL1 - ldr r1, =CFG_MPCTL1_VAL + ldr r1, =CONFIG_SYS_MPCTL1_VAL str r1, [r0] /* set mpll restart bit */ @@ -63,13 +63,13 @@ lowlevel_init: /* set System PLL Control Register 0 */ ldr r0, =SPCTL0 - ldr r1, =CFG_SPCTL0_VAL + ldr r1, =CONFIG_SYS_SPCTL0_VAL str r1, [r0] /* set System PLL Control Register 1 */ ldr r0, =SPCTL1 - ldr r1, =CFG_SPCTL1_VAL + ldr r1, =CONFIG_SYS_SPCTL1_VAL str r1, [r0] /* set spll restart bit */ @@ -89,11 +89,11 @@ lowlevel_init: bne 1b ldr r0, =CSCR - ldr r1, =CFG_CSCR_VAL + ldr r1, =CONFIG_SYS_CSCR_VAL str r1, [r0] ldr r0, =GPCR - ldr r1, =CFG_GPCR_VAL + ldr r1, =CONFIG_SYS_GPCR_VAL str r1, [r0] /* @@ -122,43 +122,43 @@ lowlevel_init: MCR p15,0,r0,c1,c0,0 ldr r0, =GIUS(0) - ldr r1, =CFG_GIUS_A_VAL + ldr r1, =CONFIG_SYS_GIUS_A_VAL str r1, [r0] ldr r0, =FMCR - ldr r1, =CFG_FMCR_VAL + ldr r1, =CONFIG_SYS_FMCR_VAL str r1, [r0] ldr r0, =CS0U - ldr r1, =CFG_CS0U_VAL + ldr r1, =CONFIG_SYS_CS0U_VAL str r1, [r0] ldr r0, =CS0L - ldr r1, =CFG_CS0L_VAL + ldr r1, =CONFIG_SYS_CS0L_VAL str r1, [r0] ldr r0, =CS1U - ldr r1, =CFG_CS1U_VAL + ldr r1, =CONFIG_SYS_CS1U_VAL str r1, [r0] ldr r0, =CS1L - ldr r1, =CFG_CS1L_VAL + ldr r1, =CONFIG_SYS_CS1L_VAL str r1, [r0] ldr r0, =CS4U - ldr r1, =CFG_CS4U_VAL + ldr r1, =CONFIG_SYS_CS4U_VAL str r1, [r0] ldr r0, =CS4L - ldr r1, =CFG_CS4L_VAL + ldr r1, =CONFIG_SYS_CS4L_VAL str r1, [r0] ldr r0, =CS5U - ldr r1, =CFG_CS5U_VAL + ldr r1, =CONFIG_SYS_CS5U_VAL str r1, [r0] ldr r0, =CS5L - ldr r1, =CFG_CS5L_VAL + ldr r1, =CONFIG_SYS_CS5L_VAL str r1, [r0] /* SDRAM Setup */ diff --git a/board/mx1fs2/u-boot.lds b/board/mx1fs2/u-boot.lds index 46ed451ee..c96e58a84 100644 --- a/board/mx1fs2/u-boot.lds +++ b/board/mx1fs2/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/nc650/flash.c b/board/nc650/flash.c index 8d7c17265..8a0eab55f 100644 --- a/board/nc650/flash.c +++ b/board/nc650/flash.c @@ -34,22 +34,22 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ -#define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ +#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ +#define CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_2_CLK | OR_EHTR | OR_BI) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -90,15 +90,15 @@ static void flash_get_offsets (ulong base, flash_info_t * info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; -#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ +#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ int scy, trlx, flash_or_timing, clk_diff; - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { trlx = OR_TRLX; scy *= 2; } else @@ -134,11 +134,11 @@ unsigned long flash_init (void) scy = 1; flash_or_timing = (scy << 4) | trlx | - (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); + (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); #endif /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -151,31 +151,31 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); +#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); #else memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); #endif - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V; + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -316,10 +316,10 @@ static ulong flash_get_size (FPWV * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -390,7 +390,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) udelay (1000); while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -530,7 +530,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) start = get_timer (0); while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c index 657abc46d..056230da6 100644 --- a/board/nc650/nc650.c +++ b/board/nc650/nc650.c @@ -130,7 +130,7 @@ static long int dram_size (long int, long int *, long int); phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size_b0 = 0; @@ -145,7 +145,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -154,10 +154,10 @@ phys_size_t initdram (int board_type) * preliminary address - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -177,14 +177,14 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -192,7 +192,7 @@ phys_size_t initdram (int board_type) size_b0 = size9; } else { size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); } @@ -202,7 +202,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -210,12 +210,12 @@ phys_size_t initdram (int board_type) * Final mapping */ - memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; udelay (10000); @@ -224,7 +224,7 @@ phys_size_t initdram (int board_type) upmconfig (UPMB, (uint *) nand_flash_table, sizeof (nand_flash_table) / sizeof (uint)); - memctl->memc_mbmr = CFG_MBMR_NAND; + memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND; return (size_b0); } @@ -241,7 +241,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -269,7 +269,7 @@ int misc_init_r(void) 0 - cp850 1 - kp852 */ - pParam = (char*)(CFG_CPLD_BASE); + pParam = (char*)(CONFIG_SYS_CPLD_BASE); if( *pParam != 0) iCompatMode = 1; diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds index 09a442aee..ca91ac451 100644 --- a/board/nc650/u-boot.lds +++ b/board/nc650/u-boot.lds @@ -122,6 +122,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/netphone/flash.c b/board/netphone/flash.c index 0c81140f2..8852127e6 100644 --- a/board/netphone/flash.c +++ b/board/netphone/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,7 +38,7 @@ static void flash_get_offsets(ulong base, flash_info_t * info); unsigned long flash_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; #if CONFIG_NETPHONE_VERSION == 2 @@ -47,7 +47,7 @@ unsigned long flash_init(void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); @@ -58,28 +58,28 @@ unsigned long flash_init(void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -92,13 +92,13 @@ unsigned long flash_init(void) printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20); /* Remap FLASH according to real size */ - memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000); - memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK)); + memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000); + memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK)); /* Re-do sizing to get full correct info */ - size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]); + size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]); - flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]); size += size1; } else @@ -448,7 +448,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) last = start; addr = (vu_char *) (info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return 1; } @@ -521,7 +521,7 @@ static int write_byte(flash_info_t * info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer(0); while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c index 38eb7c811..53d317206 100644 --- a/board/netphone/netphone.c +++ b/board/netphone/netphone.c @@ -356,7 +356,7 @@ static const uint nandcs_table[0x40] = { #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) /* 8 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) @@ -406,7 +406,7 @@ void check_ram(unsigned int addr, unsigned int size) phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -422,10 +422,10 @@ phys_size_t initdram(int board_type) /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ udelay(200); @@ -546,7 +546,7 @@ void reset_phys(void) int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *ioport = &immap->im_ioport; volatile cpm8xx_t *cpm = &immap->im_cpm; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -602,13 +602,13 @@ int board_early_init_f(void) #include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; void nand_init(void) { unsigned long totlen; - totlen = nand_probe(CFG_NAND_BASE); + totlen = nand_probe(CONFIG_SYS_NAND_BASE); printf ("%4lu MB\n", totlen >> 20); } #endif @@ -626,7 +626,7 @@ void hw_watchdog_reset(void) static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */ -/* called from timer interrupt every 1/CFG_HZ sec */ +/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */ void board_show_activity(ulong timestamp) { if (left_to_poll > -PHONE_CONSOLE_POLL_HZ) @@ -656,7 +656,7 @@ void show_activity(int arg) #endif -#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) { /* printf("overwrite_console called\n"); */ @@ -679,16 +679,16 @@ int last_stage_init(void) #if CONFIG_NETPHONE_VERSION == 2 /* assert peripheral reset */ - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); for (i = 0; i < 10; i++) udelay(1000); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); #endif reset_phys(); /* check in order to enable the local console */ left_to_poll = PHONE_CONSOLE_POLL_HZ; - i = CFG_HZ * 2; + i = CONFIG_SYS_HZ * 2; while (i > 0) { if (tstc()) { @@ -702,7 +702,7 @@ int last_stage_init(void) status_led_set(0, STATUS_LED_ON); while (!drv_phone_is_idle()) { do_poll(); - udelay(1000000 / CFG_HZ); + udelay(1000000 / CONFIG_SYS_HZ); } console_assign(stdin, "phone"); @@ -712,7 +712,7 @@ int last_stage_init(void) break; } - udelay(1000000 / CFG_HZ); + udelay(1000000 / CONFIG_SYS_HZ); i--; left_to_poll--; } diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c index 408ada016..d9b0ad376 100644 --- a/board/netphone/phone_console.c +++ b/board/netphone/phone_console.c @@ -46,43 +46,43 @@ #define ROWS 24 #define COLS 80 -#define REFRESH_HZ (CFG_HZ/50) /* refresh every 20ms */ -#define BLINK_HZ (CFG_HZ/2) /* cursor blink every 500ms */ +#define REFRESH_HZ (CONFIG_SYS_HZ/50) /* refresh every 20ms */ +#define BLINK_HZ (CONFIG_SYS_HZ/2) /* cursor blink every 500ms */ /*************************************************************************************************/ -#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat +#define DISPLAY_BACKLIT_PORT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat #define DISPLAY_BACKLIT_MASK 0x0010 /*************************************************************************************************/ -#define KP_STABLE_HZ (CFG_HZ/100) /* stable for 10ms */ -#define KP_REPEAT_DELAY_HZ (CFG_HZ/4) /* delay before repeat 250ms */ -#define KP_REPEAT_HZ (CFG_HZ/20) /* repeat every 50ms */ -#define KP_FORCE_DELAY_HZ (CFG_HZ/2) /* key was force pressed */ -#define KP_IDLE_DELAY_HZ (CFG_HZ/2) /* key was released and idle */ +#define KP_STABLE_HZ (CONFIG_SYS_HZ/100) /* stable for 10ms */ +#define KP_REPEAT_DELAY_HZ (CONFIG_SYS_HZ/4) /* delay before repeat 250ms */ +#define KP_REPEAT_HZ (CONFIG_SYS_HZ/20) /* repeat every 50ms */ +#define KP_FORCE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was force pressed */ +#define KP_IDLE_DELAY_HZ (CONFIG_SYS_HZ/2) /* key was released and idle */ #if CONFIG_NETPHONE_VERSION == 1 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) #define KP_SPI_RXD_MASK 0x0008 -#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) #define KP_SPI_TXD_MASK 0x0004 -#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) +#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) #define KP_SPI_CLK_MASK 0x0001 #elif CONFIG_NETPHONE_VERSION == 2 -#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) #define KP_SPI_RXD_MASK 0x00000008 -#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) #define KP_SPI_TXD_MASK 0x00000004 -#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) #define KP_SPI_CLK_MASK 0x00000002 #endif -#define KP_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat) +#define KP_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) #define KP_CS_MASK 0x00000010 #define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK) @@ -983,7 +983,7 @@ unsigned int kp_get_col_mask(unsigned int row_mask) #if CONFIG_NETPHONE_VERSION == 1 col_mask = kp_data_transfer(val) & 0x0F; #elif CONFIG_NETPHONE_VERSION == 2 - col_mask = ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & 0x0f; + col_mask = ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & 0x0f; /* XXX FUCK FUCK FUCK FUCK FUCK!!!! */ col_mask = ((col_mask & 0x08) >> 3) | /* BKBR1 */ ((col_mask & 0x04) << 1) | /* BKBR2 */ diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index 271102b77..88365605d 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index 5bf1a6628..d47c4082a 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index c14474182..aa8a0975c 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -134,7 +134,7 @@ u32 hcu_get_slot(void) */ u32 get_serial_number(void) { - u32 serial = in_be32((u32 *)CFG_FLASH_BASE); + u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE); if (serial == 0xffffffff) return 0; diff --git a/board/netstal/hcu4/u-boot.lds b/board/netstal/hcu4/u-boot.lds index 3bcfea2a8..d9abcd674 100644 --- a/board/netstal/hcu4/u-boot.lds +++ b/board/netstal/hcu4/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -133,6 +133,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt index c205108ff..f64987637 100644 --- a/board/netstal/hcu5/README.txt +++ b/board/netstal/hcu5/README.txt @@ -33,7 +33,7 @@ vector and start running. On-Chip Memory -------------- -0xe0010000- 0xe0013fff CFG_OCM_BASE +0xe0010000- 0xe0013fff CONFIG_SYS_OCM_BASE The 440EPx includes a 16K on-chip memory that can be placed however software chooses. @@ -149,10 +149,10 @@ From now on our copy is in RAM and we will run from there, setup bd flash info cpu_init_r: (cpu/ppc4xx/cpu_init.c) peripheral chip select in using defines like - CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h + CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h mem_malloc_init malloc_bin_reloc - spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM) + spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM) env_relocated misc_init_r(bd): (board/netstal/hcu5.c) ethaddr mit serial number ergänzen @@ -168,4 +168,4 @@ include/ppc440.h Drivers for serial etc are found under drivers/ Don't ask question if you did not look at the README !! -Most CFG_* and CONFIG_* switches are mentioned/explained there. +Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there. diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 4ecdb25da..6f4ec296c 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #undef BOOTSTRAP_OPTION_A_ACTIVE @@ -40,9 +40,9 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define SDR0_ECID2 0x0082 #define SDR0_ECID3 0x0083 -#define SYS_IO_ADDRESS (CFG_CS_2 + 0x00e00000) -#define SYS_SLOT_ADDRESS (CFG_CPLD + 0x00400000) -#define HCU_DIGITAL_IO_REGISTER (CFG_CPLD + 0x0500000) +#define SYS_IO_ADDRESS (CONFIG_SYS_CS_2 + 0x00e00000) +#define SYS_SLOT_ADDRESS (CONFIG_SYS_CPLD + 0x00400000) +#define HCU_DIGITAL_IO_REGISTER (CONFIG_SYS_CPLD + 0x0500000) #define HCU_SW_INSTALL_REQUESTED 0x10 /* @@ -212,7 +212,7 @@ void hcu_led_set(u32 value) */ u32 get_serial_number(void) { - u32 *serial = (u32 *)CFG_FLASH_BASE; + u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE; if (in_be32(serial) == 0xffffffff) return 0; @@ -240,18 +240,18 @@ int misc_init_r(void) unsigned long usb2phy0cr, usb2h0cr = 0; unsigned long sdr0_pfc1; -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif #endif @@ -399,18 +399,18 @@ void pci_target_init(struct pci_controller *hose) */ /* PMM0 Mask/Attribute - disabled b4 setting */ out32r(PCIX0_PMM0MA, 0x00000000); - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM0MA, 0xE0000001); /* PMM0 Mask/Attribute - disabled b4 setting */ out32r(PCIX0_PMM1MA, 0x00000000); - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0xE0000001); @@ -426,8 +426,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S index d73c861e6..05b5e389c 100644 --- a/board/netstal/hcu5/init.S +++ b/board/netstal/hcu5/init.S @@ -42,7 +42,7 @@ tlbtab: /* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */ tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */ - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB#2: TLB-entry for EBC */ @@ -53,7 +53,7 @@ tlbtab: * off to use the speed up boot process. It is patched after relocation * to enable SA_I */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G) /* @@ -63,13 +63,13 @@ tlbtab: */ /* TLB#4: */ - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB#5: */ - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB#6: */ - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) /* TLB-entry for Internal Registers & OCM */ @@ -87,20 +87,20 @@ tlbtab: /* CAN */ /* TLB#10: */ - tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB#11: CPLD and IMC-Standard 32 MB */ - tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB#12: */ - tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, + tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* IMC-Fast 32 MB */ /* TLB#13: */ - tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) /* TLB#14: */ - tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3, 1, + tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) tlbtab_end diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 66a958c78..f59bd7d18 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -122,7 +122,7 @@ void sdram_panic(const char *reason) } #ifdef CONFIG_DDR_ECC -static void blank_string(int size) +void blank_string(int size) { int i; @@ -263,20 +263,20 @@ phys_size_t initdram (int board_type) /* * Program tlb entries for this size (dynamic) */ - remove_tlb(CFG_SDRAM_BASE, 256 << 20); + remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual * address with cache enabled. This is done for fast ECC generation. */ - program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); + program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0); #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ - program_ecc(CFG_DDR_CACHED_ADDR, dram_size); + program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size); #endif return (dram_size); diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds index c72e5ba69..c3009bb70 100644 --- a/board/netstal/hcu5/u-boot.lds +++ b/board/netstal/hcu5/u-boot.lds @@ -134,9 +134,10 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } - ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index ed171bfeb..66ed95fb9 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -74,9 +74,9 @@ int board_early_init_f (void) mtdcr(cntrl1, CPC0_CR1_VALUE); mtdcr(ecr, 0x60606000); mtdcr(CPC0_EIRR, 0x7C000000); - out32(GPIO0_OR, CFG_GPIO0_OR ); - out32(GPIO0_TCR, CFG_GPIO0_TCR); - out32(GPIO0_ODR, CFG_GPIO0_ODR); + out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR ); + out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); + out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); mtspr(ccr0, 0x00700000); return 0; @@ -141,7 +141,7 @@ u32 hcu_get_slot(void) */ u32 get_serial_number(void) { - u32 serial = in_be32((u32 *)CFG_FLASH_BASE); + u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE); if (serial == 0xffffffff) return 0; diff --git a/board/netstal/mcu25/u-boot.lds b/board/netstal/mcu25/u-boot.lds index 740bc9c97..a00f570f3 100644 --- a/board/netstal/mcu25/u-boot.lds +++ b/board/netstal/mcu25/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -133,6 +133,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c index 0de594b65..5806128cf 100644 --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -26,6 +26,7 @@ #include <common.h> #include <exports.h> +#include <timestamp.h> #include "../drivers/net/smc91111.h" #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE @@ -173,7 +174,7 @@ int eeprom(int argc, char *argv[]) /* Print help message */ if (argv[1][1] == 'h') { printf("VoiceBlue EEPROM writer\n"); - printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); return 0; } diff --git a/board/netstar/eeprom.lds b/board/netstar/eeprom.lds index 89b0a8209..f3be320df 100644 --- a/board/netstar/eeprom.lds +++ b/board/netstar/eeprom.lds @@ -46,6 +46,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/netstar/flash.c b/board/netstar/flash.c index 692c41678..e9eca35e0 100644 --- a/board/netstar/flash.c +++ b/board/netstar/flash.c @@ -33,11 +33,11 @@ #include "crcek.h" -#if (CFG_MAX_FLASH_BANKS > 1) +#if (CONFIG_SYS_MAX_FLASH_BANKS > 1) #error There is always only _one_ flash chip #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x000000f0 #define CMD_UNLOCK1 0x000000aa @@ -47,8 +47,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define CMD_PROGRAM 0x000000a0 #define CMD_UNLOCK_BYPASS 0x00000020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002aa << 1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002aa << 1))) #define BIT_ERASE_DONE 0x00000080 #define BIT_RDY_MASK 0x00000080 @@ -65,27 +65,27 @@ ulong flash_init(void) flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | (AMD_ID_LV800B & FLASH_TYPEMASK); flash_info[0].size = PHYS_FLASH_1_SIZE; - flash_info[0].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); for (i = 0; i < flash_info[0].sector_count; i++) { switch (i) { case 0: /* 16kB */ - flash_info[0].start[0] = CFG_FLASH_BASE; + flash_info[0].start[0] = CONFIG_SYS_FLASH_BASE; break; case 1: /* 8kB */ - flash_info[0].start[1] = CFG_FLASH_BASE + 0x4000; + flash_info[0].start[1] = CONFIG_SYS_FLASH_BASE + 0x4000; break; case 2: /* 8kB */ - flash_info[0].start[2] = CFG_FLASH_BASE + 0x4000 + + flash_info[0].start[2] = CONFIG_SYS_FLASH_BASE + 0x4000 + 0x2000; break; case 3: /* 32 KB */ - flash_info[0].start[3] = CFG_FLASH_BASE + 0x4000 + + flash_info[0].start[3] = CONFIG_SYS_FLASH_BASE + 0x4000 + 2 * 0x2000; break; case 4: - flash_info[0].start[4] = CFG_FLASH_BASE + 0x4000 + + flash_info[0].start[4] = CONFIG_SYS_FLASH_BASE + 0x4000 + 2 * 0x2000 + 0x8000; break; default: /* 64kB */ @@ -196,7 +196,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; rc = ERR_TIMOUT; break; @@ -254,7 +254,7 @@ static int write_hword(flash_info_t *info, ulong dest, ushort data) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { rc = ERR_TIMOUT; break; } diff --git a/board/netstar/u-boot.lds b/board/netstar/u-boot.lds index 39646e6e8..5823f62f7 100644 --- a/board/netstar/u-boot.lds +++ b/board/netstar/u-boot.lds @@ -50,6 +50,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/netta/codec.c b/board/netta/codec.c index 01ab14bc5..844aa184a 100644 --- a/board/netta/codec.c +++ b/board/netta/codec.c @@ -339,9 +339,9 @@ /************************************************/ -#define PORTB (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) -#define PORTC (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) -#define PORTD (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) +#define PORTB (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) +#define PORTC (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) +#define PORTD (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat) #define _PORTD_SET(mask, state) \ do { \ diff --git a/board/netta/dsp.c b/board/netta/dsp.c index 3739e16d6..cd576476e 100644 --- a/board/netta/dsp.c +++ b/board/netta/dsp.c @@ -95,7 +95,7 @@ static volatile u32 *ti6711_delay = &dummy_delay; static inline void dsp_go_slow(void) { - volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; + volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl; #if defined(CONFIG_NETTA_6412) memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX; #else @@ -108,7 +108,7 @@ static inline void dsp_go_slow(void) static inline void dsp_go_fast(void) { - volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl; + volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl; #if defined(CONFIG_NETTA_6412) memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK; #else @@ -148,14 +148,14 @@ static inline void dsp_write_hpic(u16 val) static inline void dsp_reset(void) { #if defined(CONFIG_NETTA_6412) - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15)); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15)); udelay(500); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15)); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 15)); udelay(500); #else - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7)); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7)); udelay(250); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7)); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |= (1 << (15 - 7)); udelay(250); #endif } diff --git a/board/netta/flash.c b/board/netta/flash.c index ca3e061c2..45e6b3010 100644 --- a/board/netta/flash.c +++ b/board/netta/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets(ulong base, flash_info_t * info); unsigned long flash_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); @@ -54,28 +54,28 @@ unsigned long flash_init(void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -427,7 +427,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) last = start; addr = (vu_char *) (info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return 1; } @@ -500,7 +500,7 @@ static int write_byte(flash_info_t * info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer(0); while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/netta/netta.c b/board/netta/netta.c index bc31386ec..02fd94cc2 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -289,7 +289,7 @@ const uint sdram_table[0x40] = { #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) /* 8 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) @@ -339,7 +339,7 @@ void check_ram(unsigned int addr, unsigned int size) phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -355,10 +355,10 @@ phys_size_t initdram(int board_type) /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ udelay(200); @@ -505,7 +505,7 @@ int last_stage_init(void) int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *ioport = &immap->im_ioport; volatile cpm8xx_t *cpm = &immap->im_cpm; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -560,11 +560,11 @@ int board_early_init_f(void) #include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; void nand_init(void) { - unsigned long totlen = nand_probe(CFG_NAND_BASE); + unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE); printf ("%4lu MB\n", totlen >> 20); } diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c index 66e6e511e..ed58f2c85 100644 --- a/board/netta/pcmcia.c +++ b/board/netta/pcmcia.c @@ -33,7 +33,7 @@ static const unsigned short vppd_masks[2] = { _BW(14), _BW(15) }; static void cfg_vppd(int no) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask; if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) @@ -48,7 +48,7 @@ static void cfg_vppd(int no) static void set_vppd(int no, int what) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask; if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0])) @@ -66,7 +66,7 @@ static const unsigned short vccd_masks[2] = { _BW(10), _BW(6) }; static void cfg_vccd(int no) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask; if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) @@ -81,7 +81,7 @@ static void cfg_vccd(int no) static void set_vccd(int no, int what) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask; if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0])) @@ -99,7 +99,7 @@ static const unsigned short oc_mask = _BW(8); static void cfg_oc(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask = oc_mask; immap->im_ioport.iop_pcdir &= ~mask; @@ -110,7 +110,7 @@ static void cfg_oc(void) static int get_oc(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask = oc_mask; int what; @@ -122,7 +122,7 @@ static const unsigned short shdn_mask = _BW(12); static void cfg_shdn(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask; mask = shdn_mask; @@ -134,7 +134,7 @@ static void cfg_shdn(void) static void set_shdn(int what) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; unsigned short mask; mask = shdn_mask; @@ -150,8 +150,8 @@ static void cfg_ports (void) volatile immap_t *immap; volatile cpm8xx_t *cp; - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); cfg_vppd(0); cfg_vppd(1); /* VPPD0,VPPD1 VAVPP => Hi-Z */ @@ -184,10 +184,10 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ cfg_ports (); @@ -273,8 +273,8 @@ int pcmcia_hardware_disable(int slot) debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* Configure PCMCIA General Control Register */ debug ("Disable PCMCIA buffers and assert RESET\n"); @@ -307,9 +307,9 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CFG_IMMR; - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) * and assert RESET signal diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index f560189c0..4966f4d4d 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index 5bf1a6628..d47c4082a 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/netta2/flash.c b/board/netta2/flash.c index a1c87f513..b63f45951 100644 --- a/board/netta2/flash.c +++ b/board/netta2/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets(ulong base, flash_info_t * info); unsigned long flash_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); @@ -55,28 +55,28 @@ unsigned long flash_init(void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -425,7 +425,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) last = start; addr = (vu_char *) (info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return 1; } @@ -498,7 +498,7 @@ static int write_byte(flash_info_t * info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer(0); while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index a97c14cee..2ce33cfdd 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -354,7 +354,7 @@ static const uint nandcs_table[0x40] = { #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) /* 8 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) @@ -404,7 +404,7 @@ void check_ram(unsigned int addr, unsigned int size) phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -420,10 +420,10 @@ phys_size_t initdram(int board_type) /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ udelay(200); @@ -544,7 +544,7 @@ void reset_phys(void) int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *ioport = &immap->im_ioport; volatile cpm8xx_t *cpm = &immap->im_cpm; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -600,13 +600,13 @@ int board_early_init_f(void) #include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; void nand_init(void) { unsigned long totlen; - totlen = nand_probe(CFG_NAND_BASE); + totlen = nand_probe(CONFIG_SYS_NAND_BASE); printf ("%4lu MB\n", totlen >> 20); } #endif @@ -620,21 +620,7 @@ void hw_watchdog_reset(void) #endif -#ifdef CONFIG_SHOW_ACTIVITY - -/* called from timer interrupt every 1/CFG_HZ sec */ -void board_show_activity(ulong timestamp) -{ -} - -/* called when looping */ -void show_activity(int arg) -{ -} - -#endif - -#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) { /* printf("overwrite_console called\n"); */ @@ -659,10 +645,10 @@ int last_stage_init(void) #if CONFIG_NETTA2_VERSION == 2 /* assert peripheral reset */ - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12); for (i = 0; i < 10; i++) udelay(1000); - ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12); + ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12); #endif reset_phys(); diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index f560189c0..4966f4d4d 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index 5bf1a6628..d47c4082a 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/netvia/flash.c b/board/netvia/flash.c index d31f7707f..98479a50b 100644 --- a/board/netvia/flash.c +++ b/board/netvia/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets(ulong base, flash_info_t * info); unsigned long flash_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); @@ -54,28 +54,28 @@ unsigned long flash_init(void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK)); /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -427,7 +427,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) last = start; addr = (vu_char *) (info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return 1; } @@ -500,7 +500,7 @@ static int write_byte(flash_info_t * info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer(0); while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index 4140bac86..0b032c4a7 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -247,7 +247,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -256,17 +256,17 @@ phys_size_t initdram(int board_type) /* * Preliminary prescaler for refresh */ - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */ /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */ udelay(200); @@ -282,7 +282,7 @@ phys_size_t initdram(int board_type) udelay(1000); - memctl->memc_mamr = CFG_MAMR_9COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; size = SDRAM_MAX_SIZE; @@ -358,7 +358,7 @@ int misc_init_r(void) int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *ioport = &immap->im_ioport; volatile cpm8xx_t *cpm = &immap->im_cpm; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -421,11 +421,11 @@ int board_early_init_f(void) #include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; void nand_init(void) { - unsigned long totlen = nand_probe(CFG_NAND_BASE); + unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE); printf ("%4lu MB\n", totlen >> 20); } diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index b4f210e48..6bc57682f 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 1014ec6e8..9210c43d5 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c index e7d65157f..5b56b9839 100644 --- a/board/ns9750dev/flash.c +++ b/board/ns9750dev/flash.c @@ -32,7 +32,7 @@ #include <linux/byteorder/swab.h> #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #undef FLASH_PORT_WIDTH32 @@ -88,7 +88,7 @@ unsigned long flash_init (void) { int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -104,12 +104,12 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -227,10 +227,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -322,7 +322,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ *addr = (FPW) 0x00B000B0; @@ -458,7 +458,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/ns9750dev/u-boot.lds b/board/ns9750dev/u-boot.lds index a3de6ac61..c6567014e 100644 --- a/board/ns9750dev/u-boot.lds +++ b/board/ns9750dev/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = . ; } diff --git a/board/nx823/flash.c b/board/nx823/flash.c index 581925e48..194d841e4 100644 --- a/board/nx823/flash.c +++ b/board/nx823/flash.c @@ -27,7 +27,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ extern u_long *my_sernum; /* from nx823.c */ /*----------------------------------------------------------------------- @@ -63,13 +63,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -82,18 +82,18 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE+monitor_flash_len-1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE+monitor_flash_len-1, &flash_info[0]); flash_info[0].size = size_b0; @@ -220,10 +220,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW)0x00FF00FF; /* restore read mode */ @@ -294,7 +294,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW)0x00B000B0; /* suspend erase */ *addr = (FPW)0x00FF00FF; /* reset to read mode */ @@ -343,9 +343,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) #endif /* save sernum if needed */ - if (addr >= CFG_FLASH_SN_SECTOR && addr < CFG_FLASH_SN_BASE) + if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE) { - u_long dest = CFG_FLASH_SN_BASE; + u_long dest = CONFIG_SYS_FLASH_SN_BASE; u_short *sn = (u_short *)my_sernum; printf("(saving sernum)"); @@ -452,7 +452,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) start = get_timer (0); while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW)0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c index 18840ff48..df9aaab7a 100644 --- a/board/nx823/nx823.c +++ b/board/nx823/nx823.c @@ -159,7 +159,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1, size8, size9; @@ -170,22 +170,22 @@ phys_size_t initdram (int board_type) * Up to 2 Banks of 64Mbit x 2 devices * Initial builds only have 1 */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; memctl->memc_mar = 0x00000088; /* * Map controller SDRAM bank 0 */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* * Map controller SDRAM bank 1 */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; /* * Perform SDRAM initializsation sequence @@ -209,7 +209,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -219,7 +219,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -227,7 +227,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -235,7 +235,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -258,7 +258,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -268,9 +268,9 @@ phys_size_t initdram (int board_type) if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ memctl->memc_or2 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* @@ -278,9 +278,9 @@ phys_size_t initdram (int board_type) */ memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; + CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { @@ -295,16 +295,16 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */ memctl->memc_or1 = - ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br1 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b1 > 0) { /* @@ -312,9 +312,9 @@ phys_size_t initdram (int board_type) */ memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | - CFG_OR_TIMING_SDRAM; + CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b0; } else { @@ -329,7 +329,7 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } @@ -352,7 +352,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -387,7 +387,7 @@ void load_sernum_ethaddr (void) bd_t *bd = gd->bd; for (i = 0; i < 8; i++) { - bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i); + bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i); } bd->bi_enetaddr[0] = 0x10; bd->bi_enetaddr[1] = 0x20; diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index 85117aa56..759b41290 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -124,6 +124,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index 85072feda..dbec9860a 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/o2dnt/flash.c b/board/o2dnt/flash.c index 349086ffb..9f3088004 100644 --- a/board/o2dnt/flash.c +++ b/board/o2dnt/flash.c @@ -55,7 +55,7 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV; #define FLASH_CYCLE1 0x0555 #define FLASH_CYCLE2 0x02aa -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -82,33 +82,33 @@ unsigned long flash_init (void) flash_preinit(); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { memset(&flash_info[i], 0, sizeof(flash_info_t)); flash_info[i].flash_id = FLASH_UNKNOWN; } /* Query flash chip */ flash_info[0].size = - flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); size += flash_info[0].size; /* get the h/w and s/w protection status in sync */ flash_sync_real_protect(&flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif @@ -135,7 +135,7 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->size && info->start[0] <= base && @@ -143,7 +143,7 @@ static flash_info_t *flash_get_info(ulong base) break; } - return (i == CFG_MAX_FLASH_BANKS ? 0 : info); + return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info); } /*----------------------------------------------------------------------- @@ -328,7 +328,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) INTEL_SUSPEND;/* suspend erase */ flash_reset(info); /* reset to read mode */ @@ -337,7 +337,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) } /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = get_timer(0); } @@ -425,7 +425,7 @@ static int write_data (flash_info_t *info, FPWV *dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) INTEL_RESET; /* restore read mode */ return (1); } @@ -464,7 +464,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) start = get_timer (0); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf ("Flash lock bit operation timed out\n"); rc = 1; break; @@ -494,7 +494,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { if (get_timer (start) > - CFG_FLASH_UNLOCK_TOUT) { + CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf ("Flash lock bit operation timed out\n"); rc = 1; break; @@ -550,7 +550,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) /* * first, wait for the WSM to be finished. The rationale for * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy * because of: (1) erase, (2) program or (3) lock bit * configuration. So we just wait for the longest timeout of * the (1)-(3), i.e. the erase timeout. @@ -563,7 +563,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) start = get_timer (0); while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = (FPW) INTEL_RESET; /* restore read mode */ printf("WSM busy too long, can't get prot status\n"); return 1; diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c index a4eed3a43..c72a7414e 100644 --- a/board/o2dnt/o2dnt.c +++ b/board/o2dnt/o2dnt.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <netdev.h> #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 @@ -64,7 +65,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ phys_size_t initdram (int board_type) @@ -85,9 +86,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -113,11 +114,11 @@ phys_size_t initdram (int board_type) if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { @@ -163,10 +164,10 @@ void flash_afterinit(ulong size) { if (size == 0x800000) { /* adjust mapping */ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } @@ -180,3 +181,9 @@ void pci_init_board(void) pci_mpc5xxx_init(&hose); } #endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +} diff --git a/board/omap1510inn/u-boot.lds b/board/omap1510inn/u-boot.lds index e0c7920df..1c70fcdf3 100644 --- a/board/omap1510inn/u-boot.lds +++ b/board/omap1510inn/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/omap1610inn/flash.c b/board/omap1610inn/flash.c index c8e4c9e25..36200ad85 100644 --- a/board/omap1610inn/flash.c +++ b/board/omap1610inn/flash.c @@ -32,7 +32,7 @@ #include <linux/byteorder/swab.h> #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #undef FLASH_PORT_WIDTH32 @@ -90,11 +90,11 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: - flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]); + flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]); /* to reset the lock bit */ flash_unlock(&flash_info[i]); break; @@ -108,12 +108,12 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -123,7 +123,7 @@ unsigned long flash_init (void) void flash_unlock(flash_info_t * info) { int j; - for (j=2;j<CFG_MAX_FLASH_SECT;j++){ + for (j=2;j<CONFIG_SYS_MAX_FLASH_SECT;j++){ FPWV *addr = (FPWV *) (info->start[j]); flash_unprotect_sectors (addr); *addr = (FPW) 0x00500050;/* clear status register */ @@ -244,10 +244,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -339,7 +339,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ *addr = (FPW) 0x00B000B0; @@ -474,7 +474,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/omap1610inn/u-boot.lds b/board/omap1610inn/u-boot.lds index a4fcd1a9b..d86eb3621 100644 --- a/board/omap1610inn/u-boot.lds +++ b/board/omap1610inn/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c index a3295fd4e..c8b4186dc 100644 --- a/board/omap2420h4/mem.c +++ b/board/omap2420h4/mem.c @@ -327,7 +327,7 @@ void gpmc_init(void) __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ __raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */ -#ifdef CFG_NAND_BOOT +#ifdef CONFIG_SYS_NAND_BOOT __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */ #else __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */ @@ -343,7 +343,7 @@ void gpmc_init(void) __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */ sdelay(1000); -#ifdef CFG_NAND_BOOT +#ifdef CONFIG_SYS_NAND_BOOT __raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0); #else __raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0); diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c index 09b070dc1..0fe9380cc 100644 --- a/board/omap2420h4/omap2420h4.c +++ b/board/omap2420h4/omap2420h4.c @@ -33,7 +33,7 @@ #include <asm/mach-types.h> #if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; #endif DECLARE_GLOBAL_DATA_PTR; @@ -201,7 +201,7 @@ int dram_init (void) u8 vmode_on = 0x8C; #define NOT_EARLY 0 - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */ + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */ btype = get_board_type(); mtype = get_mem_type(); @@ -267,7 +267,7 @@ void peripheral_enable(void) __raw_writel(v, CM_CLKSEL2_CORE); __raw_writel(0x1, CM_CLKSEL_WKUP); -#ifdef CFG_NS16550 +#ifdef CONFIG_SYS_NS16550 /* Enable UART1 clock */ func_clks |= BIT21; if_clks |= BIT21; @@ -852,16 +852,16 @@ void nand_init(void) { extern flash_info_t flash_info[]; - nand_probe(CFG_NAND_ADDR); + nand_probe(CONFIG_SYS_NAND_ADDR); if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { print_size(nand_dev_desc[0].totlen, "\n"); } -#ifdef CFG_JFFS2_MEM_NAND - flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; - flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ - flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ - flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ +#ifdef CONFIG_SYS_JFFS2_MEM_NAND + flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; + flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ + flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ + flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ #endif } #endif diff --git a/board/omap2420h4/u-boot.lds b/board/omap2420h4/u-boot.lds index aae716cb2..89e627b4a 100644 --- a/board/omap2420h4/u-boot.lds +++ b/board/omap2420h4/u-boot.lds @@ -54,6 +54,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/omap5912osk/u-boot.lds b/board/omap5912osk/u-boot.lds index 9a34e46ee..0bf6eff8c 100644 --- a/board/omap5912osk/u-boot.lds +++ b/board/omap5912osk/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/omap730p2/flash.c b/board/omap730p2/flash.c index e7d65157f..5b56b9839 100644 --- a/board/omap730p2/flash.c +++ b/board/omap730p2/flash.c @@ -32,7 +32,7 @@ #include <linux/byteorder/swab.h> #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #undef FLASH_PORT_WIDTH32 @@ -88,7 +88,7 @@ unsigned long flash_init (void) { int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -104,12 +104,12 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -227,10 +227,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -322,7 +322,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ *addr = (FPW) 0x00B000B0; @@ -458,7 +458,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/omap730p2/u-boot.lds b/board/omap730p2/u-boot.lds index a4fcd1a9b..d86eb3621 100644 --- a/board/omap730p2/u-boot.lds +++ b/board/omap730p2/u-boot.lds @@ -47,6 +47,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/oxc/flash.c b/board/oxc/flash.c index 296c01dc8..36e0fcac7 100644 --- a/board/oxc/flash.c +++ b/board/oxc/flash.c @@ -31,7 +31,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -49,7 +49,7 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -59,27 +59,27 @@ unsigned long flash_init (void) * and the size of flash using 0xFF800000 as the base address, * and then call flash_get_size() again to fill flash_info. */ - size = flash_get_size((vu_char *)CFG_FLASH_PRELIMBASE, &flash_info[0]); + size = flash_get_size((vu_char *)CONFIG_SYS_FLASH_PRELIMBASE, &flash_info[0]); if (size) { flash_get_size((vu_char *)(-size), &flash_info[0]); } -#if (CFG_MONITOR_BASE >= CFG_FLASH_PRELIMBASE) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_PRELIMBASE) /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -286,7 +286,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_char *)(info->start[l_sect]); while ((addr[0] & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -361,7 +361,7 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c index b61d39951..1a2bdf430 100644 --- a/board/oxc/oxc.c +++ b/board/oxc/oxc.c @@ -25,6 +25,7 @@ #include <mpc824x.h> #include <pci.h> #include <i2c.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -36,13 +37,13 @@ int checkboard (void) phys_size_t initdram (int board_type) { -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size; long new_bank0_end; long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -91,14 +92,14 @@ void pci_init_board (void) int board_early_init_f (void) { - *(volatile unsigned char *)(CFG_CPLD_RESET) = 0x89; + *(volatile unsigned char *)(CONFIG_SYS_CPLD_RESET) = 0x89; return 0; } #ifdef CONFIG_WATCHDOG void oxc_wdt_reset(void) { - *(volatile unsigned char *)(CFG_CPLD_WATCHDOG) = 0xff; + *(volatile unsigned char *)(CONFIG_SYS_CPLD_WATCHDOG) = 0xff; } void watchdog_reset(void) @@ -134,7 +135,7 @@ void oxc_toggle_activeled(void) void board_show_activity (ulong timestamp) { - if ((timestamp % (CFG_HZ / 10)) == 0) + if ((timestamp % (CONFIG_SYS_HZ / 10)) == 0) oxc_toggle_activeled (); } @@ -147,9 +148,9 @@ void show_activity(int arg) if ((ledtoggle > (2 * arg)) && ledstatus) { led ^= 0x80; - oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); + oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val); udelay(200); - oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, (val & 0x7F) | led); + oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, (val & 0x7F) | led); ledtoggle = 0; } } @@ -164,13 +165,13 @@ void show_boot_progress(int arg) if (arg > 0 && ledstatus) { ledstatus = 0; - oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); + oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val); udelay(200); - oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val | 0x80); + oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, val | 0x80); } else if (arg < 0) { - oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val); + oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val); udelay(200); - oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val & 0x7F); + oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, val & 0x7F); ledstatus = 1; } } @@ -179,21 +180,21 @@ void show_boot_progress(int arg) int misc_init_r (void) { /* check whether the i2c expander #0 is accessible */ - if (!oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, 0x7F)) { + if (!oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, 0x7F)) { udelay(200); expander0alive = 1; } -#ifdef CFG_OXC_GENERATE_IP +#ifdef CONFIG_SYS_OXC_GENERATE_IP { char str[32]; - unsigned long ip = CFG_OXC_IPMASK; + unsigned long ip = CONFIG_SYS_OXC_IPMASK; bd_t *bd = gd->bd; if (expander0alive) { unsigned char val; - if (!oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val)) { + if (!oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val)) { ip = (ip & 0xffffff00) | ((val & 0x7c) >> 2); } } @@ -215,3 +216,8 @@ int misc_init_r (void) #endif return (0); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c index 3cf29e844..a2fed1d71 100644 --- a/board/pb1x00/flash.c +++ b/board/pb1x00/flash.c @@ -23,7 +23,7 @@ #include <common.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * flash_init() diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index 82e2613e2..773e446c0 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -100,19 +100,19 @@ int checkboard (void) /* We dont need theese unless we run whole pcmcia package */ write_one_tlb(20, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_IO_BASE, /* Hi */ + CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */ 0x3C000017, /* Lo0 */ 0x3C200017); /* Lo1 */ write_one_tlb(21, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_ATTR_BASE, /* Hi */ + CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */ 0x3D000017, /* Lo0 */ 0x3D200017); /* Lo1 */ #endif /* 0 */ write_one_tlb(22, /* index */ 0x01ffe000, /* Pagemask, 16 MB pages */ - CFG_PCMCIA_MEM_ADDR, /* Hi */ + CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */ 0x3E000017, /* Lo0 */ 0x3E200017); /* Lo1 */ #endif /* CONFIG_IDE_PCMCIA */ diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 1e1c5590d..da20de1ad 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -65,6 +65,6 @@ SECTIONS . = ALIGN(4); .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } uboot_end = .; } diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c index 171f06c58..8945351a4 100644 --- a/board/pcippc2/cpc710_init_ram.c +++ b/board/pcippc2/cpc710_init_ram.c @@ -81,7 +81,7 @@ unsigned long cpc710_ram_init (void) unsigned long bank_size; u32 mcer; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* Clear memory banks */ out32 (REG (SDRAM0, MCER0), 0); @@ -107,14 +107,14 @@ unsigned long cpc710_ram_init (void) hang (); } memsize += bank_size; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* Enable bank, zero start */ out32 (REG (SDRAM0, MCER0), mcer | 0x80000000); iobarrier_rw (); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* Enable memory */ out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000); diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c index 8c01415fa..ec604e0d6 100644 --- a/board/pcippc2/flash.c +++ b/board/pcippc2/flash.c @@ -39,7 +39,7 @@ #endif /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static ulong flash_get_size (ulong addr, flash_info_t *info); static int flash_get_offsets (ulong base, flash_info_t *info); @@ -52,33 +52,33 @@ unsigned long flash_init (void) unsigned long flash_size = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = 0; flash_info[i].size = 0; } - DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE); + DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE); - flash_size = flash_get_size (CFG_FLASH_BASE, flash_info); + flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info); DEBUGF("## Flash bank size: %08lx\n", flash_size); if (flash_size) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \ - CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \ + CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); #endif @@ -231,10 +231,10 @@ static ulong flash_get_size (ulong addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } if (! flash_get_offsets (addr, info)) { @@ -356,10 +356,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = info->start[l_sect]; - DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT); + DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT); while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); flash_reset (info->start[0]); return 1; @@ -488,7 +488,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flash_reset (addr); return (1); } diff --git a/board/pcippc2/i2c.c b/board/pcippc2/i2c.c index 36b1d0f44..ab52562e6 100644 --- a/board/pcippc2/i2c.c +++ b/board/pcippc2/i2c.c @@ -85,7 +85,7 @@ static inline void i2c_udelay ( { int v; - asm volatile("mtdec %0" : : "r" (time * ((CFG_BUS_CLK / 4) / 1000000))); + asm volatile("mtdec %0" : : "r" (time * ((CONFIG_SYS_BUS_CLK / 4) / 1000000))); do { diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index c1917c11b..a3dbdc846 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -28,6 +28,7 @@ #include <linux/mtd/doc2000.h> #include <watchdog.h> #include <pci.h> +#include <netdev.h> #include "hardware.h" #include "pcippc2.h" @@ -243,3 +244,8 @@ U_BOOT_CMD( #endif #endif /* CONFIG_WATCHDOG */ + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c index 3b190699f..6ef38f437 100644 --- a/board/pcippc2/sconsole.c +++ b/board/pcippc2/sconsole.c @@ -41,7 +41,7 @@ int serial_init (void) sb->pos = 0; sb->size = 0; sb->baud = gd->baudrate; - sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); + sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); return (0); } diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h index 5d850a589..ff0ccabcd 100644 --- a/board/pcippc2/sconsole.h +++ b/board/pcippc2/sconsole.h @@ -34,7 +34,7 @@ typedef struct sconsole_buffer_s { char data[1]; } sconsole_buffer_t; -#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) +#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR) extern void (* sconsole_putc) (char); extern void (* sconsole_puts) (const char *); diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds index ebb1b6d46..53951083c 100644 --- a/board/pcippc2/u-boot.lds +++ b/board/pcippc2/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk index 4d942ebc7..0844e98e8 100644 --- a/board/pcs440ep/config.mk +++ b/board/pcs440ep/config.mk @@ -43,5 +43,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c index c5a62e254..f90a22112 100644 --- a/board/pcs440ep/flash.c +++ b/board/pcs440ep/flash.c @@ -24,13 +24,13 @@ #include <common.h> #include <asm/processor.h> -#ifndef CFG_FLASH_READ0 -#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ -#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ -#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ +#ifndef CONFIG_SYS_FLASH_READ0 +#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ +#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ +#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Functions @@ -45,7 +45,7 @@ unsigned long flash_init(void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -130,7 +130,7 @@ void flash_print_info(flash_info_t *info) printf (" Sector Start Addresses:"); for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO /* * Check if whole sector is erased */ @@ -175,34 +175,34 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; short n; - volatile CFG_FLASH_WORD_SIZE value; + volatile CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong)addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (volatile CFG_FLASH_WORD_SIZE *)addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)addr; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - value = addr2[CFG_FLASH_READ0]; + value = addr2[CONFIG_SYS_FLASH_READ0]; switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; - case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; - case (CFG_FLASH_WORD_SIZE)MX_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)MX_MANUFACT: info->flash_id = FLASH_MAN_MX; break; default: @@ -212,99 +212,99 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) return (0); /* no or unknown flash */ } - value = addr2[CFG_FLASH_READ1]; /* device ID */ + value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV040B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 0.5 MB */ break; - case (CFG_FLASH_WORD_SIZE)STM_ID_M29W040B: + case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_M29W040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 0,5 MB */ break; - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: info->flash_id += FLASH_AMDL322T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: info->flash_id += FLASH_AMDL322B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: info->flash_id += FLASH_AMDL323T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: info->flash_id += FLASH_AMDL323B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF020: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020: info->flash_id += FLASH_SST020; info->sector_count = 64; info->size = 0x00040000; break; /* => 256 kB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF040: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040: info->flash_id += FLASH_SST040; info->sector_count = 128; info->size = 0x00080000; @@ -381,19 +381,19 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) info->protect[i] = 0; else - info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; } /* * Prevent writes to uninitialized FLASH. */ if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ } return (info->size); @@ -402,8 +402,8 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) int flash_erase(flash_info_t *info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; ulong start, now, last; @@ -438,14 +438,14 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ /* re-enable interrupts if necessary */ if (flag) { @@ -455,20 +455,20 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) /* data polling for D7 */ start = get_timer (0); - while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (CFG_FLASH_WORD_SIZE)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } else { if (sect == s_first) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; } - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ } l_sect = sect; } @@ -489,9 +489,9 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) start = get_timer (0); last = start; - addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -504,8 +504,8 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) DONE: /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ printf (" done\n"); return 0; @@ -585,9 +585,9 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word(flash_info_t *info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; ulong start; int flag; int i; @@ -599,10 +599,10 @@ static int write_word(flash_info_t *info, ulong dest, ulong data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; dest2[i] = data2[i]; @@ -612,9 +612,9 @@ static int write_word(flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S index 36a40c97a..25e7f4f70 100644 --- a/board/pcs440ep/init.S +++ b/board/pcs440ep/init.S @@ -93,10 +93,10 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) /* * TLB entries for SDRAM are not needed on this platform. @@ -104,15 +104,15 @@ tlbtab: * routine. */ - tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) /* USB 2.0 Device */ - tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index f66f3f233..271005f0f 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ unsigned char sha1_checksum[SHA1_SUM_LEN]; @@ -193,7 +193,7 @@ void load_sernum_ethaddr (void) /* read the MACs from EEprom */ status_led_set (0, STATUS_LED_ON); status_led_set (1, STATUS_LED_ON); - ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN); + ret = eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN); if (ret == 0) { checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2); /* check, if the EEprom is programmed: @@ -379,8 +379,8 @@ static int pcs440ep_sha1 (int docheck) unsigned char org[20]; int i, len = CONFIG_SHA1_LEN; - memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len); - data = (unsigned char *)CFG_LOAD_ADDR; + memcpy ((char *)CONFIG_SYS_LOAD_ADDR, (char *)CONFIG_SHA1_START, len); + data = (unsigned char *)CONFIG_SYS_LOAD_ADDR; ptroff = &data[len + SHA1_SUM_POS]; for (i = 0; i < SHA1_SUM_LEN; i++) { @@ -485,14 +485,14 @@ int misc_init_r (void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[1]); /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[1]); pcs440ep_readinputs (); @@ -616,7 +616,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -630,14 +630,14 @@ void pci_target_init(struct pci_controller *hose) | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ @@ -652,8 +652,8 @@ void pci_target_init(struct pci_controller *hose) /* Program the board's subsystem id/vendor id */ pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, - CFG_PCI_SUBSYS_VENDORID); - pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); /* Configure command register as bus master */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); @@ -667,13 +667,13 @@ void pci_target_init(struct pci_controller *hose) pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { unsigned short temp_short; @@ -688,7 +688,7 @@ void pci_master_init(struct pci_controller *hose) temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ /************************************************************************* * is_pci_host diff --git a/board/pcs440ep/u-boot.lds b/board/pcs440ep/u-boot.lds index ed6135987..6b7dd2110 100644 --- a/board/pcs440ep/u-boot.lds +++ b/board/pcs440ep/u-boot.lds @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c index 5a1eba6b3..abaf0b4d2 100644 --- a/board/pleb2/flash.c +++ b/board/pleb2/flash.c @@ -23,12 +23,12 @@ #include <common.h> #include <mpc8xx.h> -/* environment.h defines the various CFG_ENV_... values in terms +/* environment.h defines the various CONFIG_ENV_... values in terms * of whichever ones are given in the configuration file. */ #include <environment.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -59,7 +59,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); static void flash_get_offsets (ulong base, flash_info_t * info); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION static void flash_sync_real_protect (flash_info_t * info); #endif @@ -74,11 +74,11 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size_b = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); + size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b; @@ -90,33 +90,33 @@ unsigned long flash_init (void) /* Do this again (was done already in flast_get_size), just * in case we move it when remap the FLASH. */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /* read the hardware protection status (if any) into the * protection array in flash_info. */ flash_sync_real_protect (&flash_info[0]); #endif -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_ADDR +#ifdef CONFIG_ENV_ADDR flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -418,7 +418,7 @@ ulong flash_get_size (FPWV * addr, flash_info_t * info) return (info->size); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ @@ -559,7 +559,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { if ((now = - get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) { + get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -573,7 +573,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } /* show that we're waiting */ - if ((now - last) > 1 * CFG_HZ) { /* every second */ + if ((now - last) > 1 * CONFIG_SYS_HZ) { /* every second */ putc ('.'); last = now; } @@ -609,7 +609,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* combine source and destination data so can program * an entire word of 16 or 32 bits */ -#ifdef CFG_LITTLE_ENDIAN +#ifdef CONFIG_SYS_LITTLE_ENDIAN for (i = 0; i < sizeof (data); i++) { data >>= 8; if (i < bytes || i - bytes >= left) @@ -688,7 +688,7 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00F000F0; /* reset bank */ res = 1; } @@ -733,7 +733,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) reset_timer_masked (); while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW) 0x00B000B0; /* Suspend program */ res = 1; } @@ -748,7 +748,7 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) return (res); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ int flash_real_protect (flash_info_t * info, long sector, int prot) diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S index add2c531a..b95ff9cf2 100644 --- a/board/pleb2/lowlevel_init.S +++ b/board/pleb2/lowlevel_init.S @@ -24,7 +24,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -41,92 +41,92 @@ lowlevel_init: /* Set up GPIO pins first */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL + ldr r1, =CONFIG_SYS_GRER0_VAL str r1, [r0] ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL + ldr r1, =CONFIG_SYS_GRER1_VAL str r1, [r0] ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL + ldr r1, =CONFIG_SYS_GRER2_VAL str r1, [r0] ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL + ldr r1, =CONFIG_SYS_GFER0_VAL str r1, [r0] ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL + ldr r1, =CONFIG_SYS_GFER1_VAL str r1, [r0] ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL + ldr r1, =CONFIG_SYS_GFER2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] /* enable GPIO pins */ ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] @@ -161,61 +161,61 @@ mem_init: @ Step 2a @ write msc0, read back to ensure data latches @ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] @ write msc1 - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] @ write msc2 - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @ Step 2b @ write mecr - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] @ write mcmem0 - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] @ write mcmem1 - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] @ write mcatt0 - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] @ write mcatt1 - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] @ write mcio0 - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] @ write mcio1 - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] @ Step 2c @ fly-by-dma is defeatured on this part @ write flycnfg - @ldr r2, =CFG_FLYCNFG_VAL + @ldr r2, =CONFIG_SYS_FLYCNFG_VAL @str r2, [r1, #FLYCNFG_OFFSET] /* FIXME Does this sequence really make sense */ #ifdef REDBOOT_WAY @ Step 2d @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL @ extract DRI field (we need a valid DRI field) @ @@ -296,7 +296,7 @@ mem_init: #else @ Step 2d @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL @ write back mdrefr @ @@ -340,7 +340,7 @@ mem_init: @ Step 4d @ fetch platform value of mdcnfg @ - ldr r2, =CFG_MDCNFG_VAL + ldr r2, =CONFIG_SYS_MDCNFG_VAL @ disable all sdram banks @ @@ -375,7 +375,7 @@ mem_init: @ Access memory *not yet enabled* for CBR refresh cycles (8) @ - CBR is generated for all banks - ldr r2, =CFG_DRAM_BASE + ldr r2, =CONFIG_SYS_DRAM_BASE str r2, [r2] str r2, [r2] str r2, [r2] @@ -405,7 +405,7 @@ mem_init: @ Step 4h @ write mdmrs @ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] @ Done Memory Init @@ -424,7 +424,7 @@ mem_init: @ Set interrupt mask register @ - ldr r1, =CFG_ICMR_VAL + ldr r1, =CONFIG_SYS_ICMR_VAL ldr r2, =ICMR str r1, [r2] @@ -440,7 +440,7 @@ mem_init: @ set core clocks @ - ldr r2, =CFG_CCCR_VAL + ldr r2, =CONFIG_SYS_CCCR_VAL ldr r1, =CCCR str r2, [r1] @@ -463,7 +463,7 @@ mem_init: @ Turn on needed clocks @ ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL + ldr r2, =CONFIG_SYS_CKEN_VAL str r2, [r1] /*SET_LED 7 */ diff --git a/board/pleb2/u-boot.lds b/board/pleb2/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/pleb2/u-boot.lds +++ b/board/pleb2/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/pm520/flash.c b/board/pm520/flash.c index 4301b8c23..64c862415 100644 --- a/board/pm520/flash.c +++ b/board/pm520/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -87,11 +87,11 @@ unsigned long flash_init (void) ulong size = 0; extern void flash_preinit(void); extern void flash_afterinit(ulong, ulong); - ulong flashbase = CFG_FLASH_BASE; + ulong flashbase = CONFIG_SYS_FLASH_BASE; flash_preinit(); - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: memset(&flash_info[i], 0, sizeof(flash_info_t)); @@ -110,19 +110,19 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE #ifndef CONFIG_BOOT_ROM flash_protect ( FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] ); #endif #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); #endif flash_afterinit(flash_info[0].start[0], flash_info[0].size); @@ -245,28 +245,28 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) /* In U-Boot we support only 32 MB (no bank-switching) */ info->sector_count = 256 / 2; info->size = 0x04000000 / 2; - info->start[0] = CFG_FLASH_BASE + 0x02000000; + info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000; break; /* => 32 MB */ case (FPW) INTEL_ID_28F128J3A: info->flash_id += FLASH_28F128J3A; info->sector_count = 128; info->size = 0x02000000; - info->start[0] = CFG_FLASH_BASE + 0x02000000; + info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000; break; /* => 32 MB */ case (FPW) INTEL_ID_28F640J3A: info->flash_id += FLASH_28F640J3A; info->sector_count = 64; info->size = 0x01000000; - info->start[0] = CFG_FLASH_BASE + 0x03000000; + info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000; break; /* => 16 MB */ case (FPW) INTEL_ID_28F320J3A: info->flash_id += FLASH_28F320J3A; info->sector_count = 32; info->size = 0x800000; - info->start[0] = CFG_FLASH_BASE + 0x03800000; + info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000; break; /* => 8 MB */ default: @@ -274,10 +274,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -328,7 +328,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) /* * first, wait for the WSM to be finished. The rationale for * waiting for the WSM to become idle for at most - * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy + * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy * because of: (1) erase, (2) program or (3) lock bit * configuration. So we just wait for the longest timeout of * the (1)-(3), i.e. the erase timeout. @@ -341,7 +341,7 @@ static unsigned char intel_sector_protected (flash_info_t *info, ushort sector) start = get_timer (0); while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) { - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = (FPW) INTEL_RESET; /* restore read mode */ printf("WSM busy too long, can't get prot status\n"); return 1; @@ -425,7 +425,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -560,7 +560,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -606,7 +606,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot) start = get_timer(0); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; break; @@ -643,7 +643,7 @@ int flash_real_protect (flash_info_t *info, long sector, int prot) *addr = INTEL_PROTECT; /* set */ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c index 83d9bcd02..9da104173 100644 --- a/board/pm520/pm520.c +++ b/board/pm520/pm520.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <netdev.h> #if defined(CONFIG_MPC5200_DDR) #include "mt46v16m16-75.h" @@ -36,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -79,7 +80,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -88,7 +89,7 @@ phys_size_t initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -109,9 +110,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -137,10 +138,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -162,7 +163,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -180,7 +181,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize + dramsize2; } @@ -190,7 +191,7 @@ phys_size_t initdram (int board_type) phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup and enable SDRAM chip selects */ @@ -209,9 +210,9 @@ phys_size_t initdram (int board_type) /* find RAM size */ sdram_start(0); - test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -222,12 +223,12 @@ phys_size_t initdram (int board_type) /* set SDRAM end address according to size */ *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* Retrieve amount of SDRAM available */ dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize; } @@ -315,9 +316,14 @@ void ide_set_reset (int idereset) #endif #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +} diff --git a/board/pm826/flash.c b/board/pm826/flash.c index fee07cf35..010f59a6b 100644 --- a/board/pm826/flash.c +++ b/board/pm826/flash.c @@ -28,7 +28,7 @@ #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ @@ -116,13 +116,13 @@ unsigned long flash_init (void) /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 >> 20); @@ -132,25 +132,25 @@ unsigned long flash_init (void) */ #ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE + /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE * but we shouldn't protect it. */ -# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] ); # endif #endif /* CONFIG_BOOT_ROM */ -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return (size_b0); @@ -267,7 +267,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) last = start; while ((addr[0] & 0x00800080) != 0x00800080 || (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (erase suspended!)\n"); /* Suspend erase */ @@ -362,7 +362,7 @@ static int write_word (flash_info_t * info, volatile unsigned long *addr, start = get_timer (0); while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { /* Suspend program */ *addr = 0x00B000B0; diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c index 7ee3ab65c..19e7a0002 100644 --- a/board/pm826/pm826.c +++ b/board/pm826/pm826.c @@ -25,6 +25,7 @@ #include <ioports.h> #include <mpc8260.h> #include <pci.h> +#include <netdev.h> /* * I/O Port configuration table @@ -255,7 +256,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -266,7 +267,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -281,29 +282,29 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong size8, size9; #endif ulong psize = 32 * 1024 * 1024; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); +#ifndef CONFIG_SYS_RAMBOOT + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL) "); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL) "); } #endif @@ -311,10 +312,9 @@ phys_size_t initdram (int board_type) } #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif @@ -328,3 +328,8 @@ void pci_init_board(void) pci_mpc8250_init(&hose); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/pm828/flash.c b/board/pm828/flash.c index 1f21b3e9c..4958a95ff 100644 --- a/board/pm828/flash.c +++ b/board/pm828/flash.c @@ -28,7 +28,7 @@ #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ @@ -116,13 +116,13 @@ unsigned long flash_init (void) /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 >> 20); @@ -132,25 +132,25 @@ unsigned long flash_init (void) */ #ifndef CONFIG_BOOT_ROM - /* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE + /* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE * but we shouldn't protect it. */ -# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0] ); # endif #endif /* CONFIG_BOOT_ROM */ -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return (size_b0); @@ -267,7 +267,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) last = start; while ((addr[0] & 0x00800080) != 0x00800080 || (addr[1] & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout (erase suspended!)\n"); /* Suspend erase */ @@ -362,7 +362,7 @@ static int write_word (flash_info_t * info, volatile unsigned long *addr, start = get_timer (0); while ((*addr & 0x00800080) != 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { /* Suspend program */ *addr = 0x00B000B0; diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c index 6038e9758..4a3b2fd89 100644 --- a/board/pm828/pm828.c +++ b/board/pm828/pm828.c @@ -25,6 +25,7 @@ #include <ioports.h> #include <mpc8260.h> #include <pci.h> +#include <netdev.h> /* * I/O Port configuration table @@ -258,7 +259,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -269,7 +270,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -314,29 +315,29 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong size8, size9; #endif ulong psize = 32 * 1024 * 1024; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL, - (uchar *) CFG_SDRAM_BASE); +#ifndef CONFIG_SYS_RAMBOOT + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL) "); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL) "); } #endif @@ -344,10 +345,9 @@ phys_size_t initdram (int board_type) } #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif @@ -361,3 +361,8 @@ void pci_init_board(void) pci_mpc8250_init(&hose); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/pm854/ddr.c b/board/pm854/ddr.c index 45372f427..7850794d6 100644 --- a/board/pm854/ddr.c +++ b/board/pm854/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/pm854/law.c b/board/pm854/law.c index d74d17abd..39e8dbbd5 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 7dbafb9a8..fed0ed431 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -27,6 +27,7 @@ #include <common.h> #include <pci.h> +#include <netdev.h> #include <asm/processor.h> #include <asm/mmu.h> #include <asm/immap_85xx.h> @@ -45,7 +46,7 @@ long int fixed_sdram(void); int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -82,7 +83,7 @@ initdram(int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int i,x; x = 10; @@ -132,8 +133,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -143,8 +144,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ @@ -153,10 +154,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ } else { /* @@ -171,7 +172,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ udelay(200); /* @@ -185,11 +186,11 @@ local_bus_init(void) } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); @@ -226,15 +227,15 @@ int testdram (void) ************************************************************************/ long int fixed_sdram (void) { - #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; + #ifndef CONFIG_SYS_RAMBOOT + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000000D; ddr->err_sbe = 0x00ff0000; @@ -243,14 +244,14 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ @@ -289,3 +290,9 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Intialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index a7f381350..5e74e2ded 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -95,7 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -108,7 +108,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/pm854/u-boot.lds b/board/pm854/u-boot.lds index f200810f0..18cb27a7c 100644 --- a/board/pm854/u-boot.lds +++ b/board/pm854/u-boot.lds @@ -141,6 +141,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/pm856/ddr.c b/board/pm856/ddr.c index 45372f427..7850794d6 100644 --- a/board/pm856/ddr.c +++ b/board/pm856/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/pm856/law.c b/board/pm856/law.c index d74d17abd..39e8dbbd5 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index bd4c0651a..932f1121e 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -34,6 +34,7 @@ #include <ioports.h> #include <spd_sdram.h> #include <miiphy.h> +#include <netdev.h> #if defined(CONFIG_DDR_ECC) extern void ddr_enable_ecc(unsigned int dram_size); @@ -237,7 +238,7 @@ initdram(int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int i,x; x = 10; @@ -288,8 +289,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -299,8 +300,8 @@ local_bus_init(void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ @@ -309,10 +310,10 @@ local_bus_init(void) lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */ } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */ } else { /* @@ -327,7 +328,7 @@ local_bus_init(void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */ udelay(200); /* @@ -340,11 +341,11 @@ local_bus_init(void) } } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); @@ -381,15 +382,15 @@ int testdram (void) ************************************************************************/ long int fixed_sdram (void) { - #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); - - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; + #ifndef CONFIG_SYS_RAMBOOT + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; #if defined (CONFIG_DDR_ECC) ddr->err_disable = 0x0000000D; ddr->err_sbe = 0x00ff0000; @@ -398,14 +399,14 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ @@ -444,3 +445,9 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif /* CONFIG_PCI */ } + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Intialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index a7f381350..5e74e2ded 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -95,7 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -108,7 +108,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 7, BOOKE_PAGESZ_256M, 1), #endif diff --git a/board/pm856/u-boot.lds b/board/pm856/u-boot.lds index 01727d177..e9c6a12d0 100644 --- a/board/pm856/u-boot.lds +++ b/board/pm856/u-boot.lds @@ -141,6 +141,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c index d905b2965..1b545bfa9 100644 --- a/board/pn62/pn62.c +++ b/board/pn62/pn62.c @@ -23,6 +23,7 @@ #include <common.h> #include <mpc824x.h> #include <pci.h> +#include <netdev.h> #include "pn62.h" @@ -84,7 +85,7 @@ phys_size_t initdram (int board_type) show_startup_phase (2); - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg (MEAR1); @@ -186,3 +187,8 @@ static int get_mac_address (int id, u8 * mac, char *string, int size) mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c index 4be6f1364..e7242271d 100644 --- a/board/ppmc7xx/flash.c +++ b/board/ppmc7xx/flash.c @@ -19,7 +19,7 @@ static int write_dword (flash_info_t* info, ulong dest, unsigned char *pdata); static void write_via_fpu (volatile DWORD* addr, DWORD* data); -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ @@ -177,12 +177,12 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 >> 20); @@ -191,19 +191,19 @@ unsigned long flash_init (void) /* * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return (size_b0); @@ -359,7 +359,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL ) != 0x0080008000800080LL ) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -477,7 +477,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) /* data polling for D7 */ start = get_timer (0); while (*(volatile DWORD*)dest != data ) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c index 5b115ea61..bf133b77d 100644 --- a/board/ppmc7xx/pci.c +++ b/board/ppmc7xx/pci.c @@ -42,37 +42,37 @@ void pci_init_board(void) hose->last_busno = 0xff; pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI_MEM_BUS, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, + CONFIG_SYS_PCI_MEM_BUS, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); /* ISA/PCI memory space */ pci_set_region(hose->regions + 2, - CFG_ISA_MEM_BUS, - CFG_ISA_MEM_PHYS, - CFG_ISA_MEM_SIZE, + CONFIG_SYS_ISA_MEM_BUS, + CONFIG_SYS_ISA_MEM_PHYS, + CONFIG_SYS_ISA_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region(hose->regions + 3, - CFG_PCI_IO_BUS, - CFG_PCI_IO_PHYS, - CFG_PCI_IO_SIZE, + CONFIG_SYS_PCI_IO_BUS, + CONFIG_SYS_PCI_IO_PHYS, + CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* ISA/PCI I/O space */ pci_set_region(hose->regions + 4, - CFG_ISA_IO_BUS, - CFG_ISA_IO_PHYS, - CFG_ISA_IO_SIZE, + CONFIG_SYS_ISA_IO_BUS, + CONFIG_SYS_ISA_IO_PHYS, + CONFIG_SYS_ISA_IO_SIZE, PCI_REGION_IO); hose->region_count = 5; diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c index 061e01ec4..944cd4ddc 100644 --- a/board/ppmc7xx/ppmc7xx.c +++ b/board/ppmc7xx/ppmc7xx.c @@ -10,6 +10,7 @@ #include <common.h> #include <command.h> +#include <netdev.h> /* Define some MPC107 (memory controller) registers */ @@ -31,7 +32,7 @@ extern void _start_warm(void); */ phys_size_t initdram( int board_type ) { - return CFG_SDRAM_SIZE; + return CONFIG_SYS_SDRAM_SIZE; } @@ -102,3 +103,8 @@ void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) /* Should never get here */ while(1); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/ppmc7xx/u-boot.lds b/board/ppmc7xx/u-boot.lds index 5239b35af..ca2e30016 100644 --- a/board/ppmc7xx/u-boot.lds +++ b/board/ppmc7xx/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -128,6 +128,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c index f3c85096b..1808abdcb 100644 --- a/board/ppmc8260/ppmc8260.c +++ b/board/ppmc8260/ppmc8260.c @@ -201,14 +201,14 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar c = 0xff; - volatile uchar *ramaddr0 = (uchar *) (CFG_SDRAM0_BASE); - volatile uchar *ramaddr1 = (uchar *) (CFG_SDRAM1_BASE); - ulong psdmr = CFG_PSDMR; - volatile uchar *ramaddr2 = (uchar *) (CFG_SDRAM2_BASE); - ulong lsdmr = CFG_LSDMR; + volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE); + volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE); + ulong psdmr = CONFIG_SYS_PSDMR; + volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE); + ulong lsdmr = CONFIG_SYS_LSDMR; int i; /* @@ -228,13 +228,13 @@ phys_size_t initdram (int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr0++ = c; *ramaddr1++ = c; @@ -246,8 +246,8 @@ phys_size_t initdram (int board_type) } memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; - ramaddr0 = (uchar *) (CFG_SDRAM0_BASE + 0x110); - ramaddr1 = (uchar *) (CFG_SDRAM1_BASE + 0x110); + ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110); + ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110); *ramaddr0 = c; *ramaddr1 = c; @@ -271,15 +271,15 @@ phys_size_t initdram (int board_type) #endif /* return total ram size */ - return ((CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) * 1024 * 1024); + return ((CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) * 1024 * 1024); } #ifdef CONFIG_MISC_INIT_R /* ------------------------------------------------------------------------- */ int misc_init_r (void) { -#ifdef CFG_LED_BASE - uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); +#ifdef CONFIG_SYS_LED_BASE + uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1); uchar ss; uchar tmp[64]; int res; @@ -298,10 +298,10 @@ int misc_init_r (void) tmp[17] = '\0'; setenv ("ethaddr", (char *)tmp); /* set the led to show the address */ - *((unsigned char *) (CFG_LED_BASE + 1)) = ds; + *((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds; } } -#endif /* CFG_LED_BASE */ +#endif /* CONFIG_SYS_LED_BASE */ return (0); } #endif /* CONFIG_MISC_INIT_R */ diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c index f9abfac73..cc91627f0 100644 --- a/board/ppmc8260/strataflash.c +++ b/board/ppmc8260/strataflash.c @@ -104,7 +104,7 @@ typedef union { #define NUM_ERASE_REGIONS 4 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- @@ -121,7 +121,7 @@ static int flash_detect_cfi(flash_info_t * info); static ulong flash_get_size (ulong base, int banknum); static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); #endif /*----------------------------------------------------------------------- @@ -181,15 +181,15 @@ unsigned long flash_init (void) * */ - address = CFG_FLASH_BASE; + address = CONFIG_SYS_FLASH_BASE; size = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; + address += CONFIG_SYS_FLASH_INCREMENT; if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, flash_info[0].size, flash_info[i].size<<20); @@ -197,8 +197,8 @@ unsigned long flash_init (void) } /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1; i++) (void)flash_real_protect(&flash_info[0], i, 1); #endif @@ -319,7 +319,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp = cp; } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE while(cnt >= info->portwidth) { i = info->buffer_size > cnt? cnt: info->buffer_size; if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) @@ -340,7 +340,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp += info->portwidth; cnt -= info->portwidth; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); } @@ -679,7 +679,7 @@ static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) return flash_full_status_check(info, 0, info->write_tout, "write"); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* loop through the sectors from the highest address * when the passed address is greater or equal to the sector address @@ -749,4 +749,4 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, in flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index cc491d05b..dc3431961 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -92,8 +92,8 @@ int board_early_init_f (void) mtdcr (uic0vr, 0x00000001); /* */ /* Setup shutdown/SSD empty interrupt as inputs */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY)); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); /* Setup GPIO/IRQ multiplexing */ mtsdr(sdr_pfc0, 0x01a33e00); @@ -124,8 +124,8 @@ int last_stage_init(void) static int board_rev(void) { /* Setup as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1)); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); + out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1)); return (in32(GPIO0_IR) >> 16) & 0x3; } @@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -201,7 +201,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -210,12 +210,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host @@ -239,11 +239,11 @@ static void wait_for_pci_ready(void) /* * Configure EREADY as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY); udelay(1000); for (;;) { - if (in32(GPIO0_IR) & CFG_GPIO_EREADY) + if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY) return; } @@ -260,7 +260,7 @@ int is_pci_host(struct pci_controller *hose) * pci_master_init * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) void pci_master_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -274,19 +274,19 @@ void pci_master_init(struct pci_controller *hose) out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ - out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ - out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ #ifdef CONFIG_POST /* diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk index 9e1833591..b62e776d3 100644 --- a/board/prodrive/alpr/config.mk +++ b/board/prodrive/alpr/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index e94360f81..0ecebc943 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -61,10 +61,10 @@ static unsigned long regval; #define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit) #define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit) -#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN) -#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG) -#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA) -#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK) +#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN) +#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG) +#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA) +#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK) #define OLD_VAL (FPGA_PRG | FPGA_CONFIG) #define SET_FPGA(data) out32(GPIO0_OR, data) @@ -87,43 +87,43 @@ int fpga_pre_fn (int cookie) reg = in32(GPIO0_IR); /* Enable the FPGA Chain */ - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN); - SET_GPIO_1(CFG_GPIO_PROG_EN); - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR); - SET_GPIO_0((CFG_GPIO_SEL_DPR)); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN); + SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR); + SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR)); /* initialize the GPIO Pins */ /* output */ - SET_GPIO_0(CFG_GPIO_CLK); - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK); + SET_GPIO_0(CONFIG_SYS_GPIO_CLK); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK); /* output */ - SET_GPIO_0(CFG_GPIO_DATA); - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA); + SET_GPIO_0(CONFIG_SYS_GPIO_DATA); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA); /* First we set STATUS to 0 then as an input */ - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); - SET_GPIO_0(CFG_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS); + SET_GPIO_0(CONFIG_SYS_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS); /* output */ - SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG); - SET_GPIO_0(CFG_GPIO_CONFIG); + SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG); + SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); /* input */ - SET_GPIO_0(CFG_GPIO_CON_DON); - SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON); - SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON); + SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON); + SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON); /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ - SET_GPIO_0(CFG_GPIO_CONFIG); + SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); return FPGA_SUCCESS; } @@ -131,9 +131,9 @@ int fpga_pre_fn (int cookie) int fpga_config_fn (int assert_config, int flush, int cookie) { if (assert_config) { - SET_GPIO_1(CFG_GPIO_CONFIG); + SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG); } else { - SET_GPIO_0(CFG_GPIO_CONFIG); + SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG); } return FPGA_SUCCESS; } @@ -144,7 +144,7 @@ int fpga_status_fn (int cookie) unsigned long reg; reg = in32(GPIO0_IR); - if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) { + if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) { PRINTF("STATUS = HIGH\n"); return FPGA_FAIL; } @@ -157,7 +157,7 @@ int fpga_done_fn (int cookie) { unsigned long reg; reg = in32(GPIO0_IR); - if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) { + if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) { PRINTF("CONF_DON = HIGH\n"); return FPGA_FAIL; } @@ -189,10 +189,10 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) i --; } while (i > 0); -#ifdef CFG_FPGA_PROG_FEEDBACK +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % len_40 == 0) { putc ('.'); /* let them know we are alive */ -#ifdef CFG_FPGA_CHECK_CTRLC +#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC if (ctrlc ()) return FPGA_FAIL; #endif @@ -205,7 +205,7 @@ int fpga_write_fn (void *buf, size_t len, int flush, int cookie) /* called, when programming is aborted */ int fpga_abort_fn (int cookie) { - SET_GPIO_1((CFG_GPIO_SEL_DPR)); + SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR)); return FPGA_SUCCESS; } diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 76164ce1d..4af7d13bf 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -87,26 +87,26 @@ tlbtab: tlbtab_start tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) #ifdef CONFIG_4xx_DCACHE - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G) #else - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) #endif -#ifdef CFG_INIT_RAM_DCACHE +#ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) #endif - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I ) /* NAND */ - tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) tlbtab_end diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c index 99f5737b8..b18c96b29 100644 --- a/board/prodrive/alpr/nand.c +++ b/board/prodrive/alpr/nand.c @@ -137,7 +137,7 @@ static int alpr_nand_dev_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { - alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE; + alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE; nand->ecc.mode = NAND_ECC_SOFT; diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds index d114bd61c..33b03af24 100644 --- a/board/prodrive/alpr/u-boot.lds +++ b/board/prodrive/alpr/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c index 363631fd8..c42fa837f 100644 --- a/board/prodrive/common/flash.c +++ b/board/prodrive/common/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * Functions @@ -91,7 +91,7 @@ void flash_print_info(flash_info_t *info) printf (" Sector Start Addresses:"); for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO /* * Check if whole sector is erased */ @@ -136,31 +136,31 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) { short i; short n; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong)addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090; - value = addr2[CFG_FLASH_READ0]; + value = addr2[CONFIG_SYS_FLASH_READ0]; switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; - case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; - case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT: info->flash_id = FLASH_MAN_STM; break; - case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; default: @@ -170,82 +170,82 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) return (0); /* no or unknown flash */ } - value = addr2[CFG_FLASH_READ1]; /* device ID */ + value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */ switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T: info->flash_id += FLASH_AM400T; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B: info->flash_id += FLASH_AM400B; info->sector_count = 11; info->size = 0x00080000; break; /* => 0.5 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B: info->flash_id += FLASH_AM800B; info->sector_count = 19; info->size = 0x00100000; break; /* => 1 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T: info->flash_id += FLASH_AM160T; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B: info->flash_id += FLASH_AM160B; info->sector_count = 35; info->size = 0x00200000; break; /* => 2 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T: info->flash_id += FLASH_AMDL322T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B: info->flash_id += FLASH_AMDL322B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T: info->flash_id += FLASH_AMDL323T; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B: info->flash_id += FLASH_AMDL323B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF020: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020: info->flash_id += FLASH_SST020; info->sector_count = 64; info->size = 0x00040000; break; /* => 256 kB */ - case (CFG_FLASH_WORD_SIZE)SST_ID_xF040: + case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040: info->flash_id += FLASH_SST040; info->sector_count = 128; info->size = 0x00080000; @@ -318,19 +318,19 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) info->protect[i] = 0; else - info->protect[i] = addr2[CFG_FLASH_READ2] & 1; + info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1; } /* * Prevent writes to uninitialized FLASH. */ if (info->flash_id != FLASH_UNKNOWN) { - addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0]; - *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ } return (info->size); @@ -339,8 +339,8 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) int flash_erase(flash_info_t *info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; ulong start, now, last; @@ -375,14 +375,14 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect<=s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]); if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ /* re-enable interrupts if necessary */ if (flag) { @@ -392,20 +392,20 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) /* data polling for D7 */ start = get_timer (0); - while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (CFG_FLASH_WORD_SIZE)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } else { if (sect == s_first) { - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; } - addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */ + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */ } l_sect = sect; } @@ -426,9 +426,9 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) start = get_timer (0); last = start; - addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]); - while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]); + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -441,8 +441,8 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) DONE: /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *)info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ printf (" done\n"); return 0; @@ -522,9 +522,9 @@ int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) */ static int write_word(flash_info_t *info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data; ulong start; int flag; int i; @@ -536,10 +536,10 @@ static int write_word(flash_info_t *info, ulong dest, ulong data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) { - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0; + for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0; dest2[i] = data2[i]; @@ -549,9 +549,9 @@ static int write_word(flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } diff --git a/board/prodrive/common/fpga.c b/board/prodrive/common/fpga.c index f9412a21e..14bff07bf 100644 --- a/board/prodrive/common/fpga.c +++ b/board/prodrive/common/fpga.c @@ -37,11 +37,11 @@ #define DBG(x...) #endif /* DEBUG */ -#define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (cpu output)*/ -#define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (cpu output) */ -#define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (cpu output) */ -#define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (cpu input) */ -#define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (cpu input) */ +#define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/ +#define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output) */ +#define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output) */ +#define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input) */ +#define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input) */ #define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ #define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ diff --git a/board/prodrive/p3mx/misc.S b/board/prodrive/p3mx/misc.S index 160b1d31f..233fd83bc 100644 --- a/board/prodrive/p3mx/misc.S +++ b/board/prodrive/p3mx/misc.S @@ -16,7 +16,7 @@ board_relocate_rom: mflr r7 /* update the location of the GT registers */ - lis r11, CFG_GT_REGS@h + lis r11, CONFIG_SYS_GT_REGS@h /* if we're using ECC, we must use the DMA engine to copy ourselves */ bl start_idma_transfer_0 bl wait_for_idma_0 @@ -29,12 +29,12 @@ board_relocate_rom: board_init_ecc: mflr r7 /* NOTE: r10 still contains the location we've been relocated to - * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */ + * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */ /* now that we're running from ram, init the rest of main memory * for ECC use */ - lis r8, CFG_MONITOR_LEN@h - ori r8, r8, CFG_MONITOR_LEN@l + lis r8, CONFIG_SYS_MONITOR_LEN@h + ori r8, r8, CONFIG_SYS_MONITOR_LEN@l divw r3, r10, r8 @@ -120,15 +120,15 @@ stop_idma_engine_0: blr #endif -#ifdef CFG_BOARD_ASM_INIT +#ifdef CONFIG_SYS_BOARD_ASM_INIT /* NOTE: trashes r3-r7 */ .globl board_asm_init board_asm_init: /* just move the GT registers to where they belong */ - lis r3, CFG_DFL_GT_REGS@h - ori r3, r3, CFG_DFL_GT_REGS@l - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r3, CONFIG_SYS_DFL_GT_REGS@h + ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTERNAL_SPACE_DECODE /* test to see if we've already moved */ @@ -153,11 +153,11 @@ board_asm_init: cmp cr0, r7, r6 bne 1b - lis r3, CFG_INT_SRAM_BASE@h - ori r3, r3, CFG_INT_SRAM_BASE@l + lis r3, CONFIG_SYS_INT_SRAM_BASE@h + ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l rlwinm r3, r3, 16, 16, 31 - lis r4, CFG_GT_REGS@h - ori r4, r4, CFG_GT_REGS@l + lis r4, CONFIG_SYS_GT_REGS@h + ori r4, r4, CONFIG_SYS_GT_REGS@l li r5, INTEGRATED_SRAM_BASE_ADDR stwbrx r3, r5, r4 diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c index 2494ec6df..cc05b4503 100644 --- a/board/prodrive/p3mx/mpsc.c +++ b/board/prodrive/p3mx/mpsc.c @@ -422,7 +422,7 @@ void mpsc_sdma_init (void) (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2))); /* Setup MPSC internal address space base address */ - GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS); + GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS); /* no high address remap*/ GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00); @@ -512,9 +512,9 @@ int galbrg_set_baudrate (int channel, int rate) #ifdef ZUMA_NTL /* from tclk */ - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #else - clock = (CFG_TCLK / (16 * rate)) - 1; + clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1; #endif galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */ diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c index 69d7c9b28..0247bb80a 100644 --- a/board/prodrive/p3mx/p3mx.c +++ b/board/prodrive/p3mx/p3mx.c @@ -67,7 +67,7 @@ extern flash_info_t flash_info[]; /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ -/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */ +/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */ /* Unfortunately, we cant change it while we are in flash, so we initialize it * to the "final" value. This means that any debug_led calls before @@ -76,7 +76,7 @@ extern flash_info_t flash_info[]; */ void board_prebootm_init (void); -unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; +unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); void set_led(int); @@ -129,7 +129,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */ @@ -138,7 +138,7 @@ static void gt_pci_config (void) GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val); GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG, - (stat & 0xffff0000) | CFG_PCI_IDSEL); + (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL); } /* Enable master */ @@ -157,21 +157,21 @@ static void gt_pci_config (void) * in 64360 when writing to pci base go and overide remap automaticaly, * in 64460 it doesn't */ - GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16); - GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16); + GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16); - GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16); + GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16); - GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16); - GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16); + GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16); + GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16); - GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16); + GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16); /* PCI interface settings */ /* Timeout set to retry forever */ @@ -189,7 +189,7 @@ static void gt_pci_config (void) for (stat = 0; stat <= PCI_HOST1; stat++) pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CFG_GT_REGS); + SELF, CONFIG_SYS_GT_REGS); #endif } @@ -204,7 +204,7 @@ static void gt_cpu_config (void) /* cpu configuration register */ tmp = GTREGREAD (CPU_CONFIGURATION); /* set the SINGLE_CPU bit see MV64460 */ -#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ +#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */ tmp |= CPU_CONF_SINGLE_CPU; #endif tmp &= ~CPU_CONF_AACK_DELAY_2; @@ -246,7 +246,7 @@ int board_early_init_f (void) * that if it's not at the power-on location, it's where we put * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); + my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS); #ifdef CONFIG_PCI gt_pci_config (); @@ -274,17 +274,17 @@ int board_early_init_f (void) memoryMapDeviceSpace(DEVICE3, 0, 0); GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0); - GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR); + GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR); gt_cpu_config(); /* MPP setup */ - GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0); - GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1); - GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2); - GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3); + GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0); + GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1); + GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2); + GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3); - GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL); set_led(LED_RED); @@ -298,7 +298,7 @@ int misc_init_r () u8 val; icache_enable (); -#ifdef CFG_L2 +#ifdef CONFIG_SYS_L2 l2cache_enable (); #endif #ifdef CONFIG_MPSC @@ -311,7 +311,7 @@ int misc_init_r () * No diode, 250 ohm series resistor */ val = 0xa5; - i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1); + i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1); return 0; } @@ -328,7 +328,7 @@ int board_early_init_r(void) void after_reloc (ulong dest_addr, gd_t * gd) { - memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE); + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); /* display_mem_map(); */ @@ -347,7 +347,7 @@ int checkboard (void) { char *s = getenv("serial#"); - printf("Board: %s", CFG_BOARD_NAME); + printf("Board: %s", CONFIG_SYS_BOARD_NAME); if (s != NULL) { puts(", serial# "); @@ -458,7 +458,7 @@ int display_mem_map (void) /* DRAM check routines copied from gw8260 */ -#if defined (CFG_DRAM_TEST) +#if defined (CONFIG_SYS_DRAM_TEST) /*********************************************************************/ /* NAME: move64() - moves a double word (64-bit) */ @@ -489,7 +489,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest) } -#if defined (CFG_DRAM_TEST_DATA) +#if defined (CONFIG_SYS_DRAM_TEST_DATA) unsigned long long pattern[] = { 0xaaaaaaaaaaaaaaaaULL, @@ -552,7 +552,7 @@ unsigned long long pattern[] = { /*********************************************************************/ int mem_test_data (void) { - unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START; + unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START; unsigned long long temp64 = 0; int num_patterns = sizeof (pattern) / sizeof (pattern[0]); int i; @@ -579,9 +579,9 @@ int mem_test_data (void) return 0; } -#endif /* CFG_DRAM_TEST_DATA */ +#endif /* CONFIG_SYS_DRAM_TEST_DATA */ -#if defined (CFG_DRAM_TEST_ADDRESS) +#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS) /*********************************************************************/ /* NAME: mem_test_address() - test address lines */ /* */ @@ -606,8 +606,8 @@ int mem_test_data (void) int mem_test_address (void) { volatile unsigned int *pmem = - (volatile unsigned int *) CFG_MEMTEST_START; - const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4; + (volatile unsigned int *) CONFIG_SYS_MEMTEST_START; + const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4; unsigned int i; /* write address to each location */ @@ -623,9 +623,9 @@ int mem_test_address (void) } return 0; } -#endif /* CFG_DRAM_TEST_ADDRESS */ +#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */ -#if defined (CFG_DRAM_TEST_WALK) +#if defined (CONFIG_SYS_DRAM_TEST_WALK) /*********************************************************************/ /* NAME: mem_march() - memory march */ /* */ @@ -683,7 +683,7 @@ int mem_march (volatile unsigned long long *base, } return 0; } -#endif /* CFG_DRAM_TEST_WALK */ +#endif /* CONFIG_SYS_DRAM_TEST_WALK */ /*********************************************************************/ /* NAME: mem_test_walk() - a simple walking ones test */ @@ -715,8 +715,8 @@ int mem_test_walk (void) { unsigned long long mask; volatile unsigned long long *pmem = - (volatile unsigned long long *) CFG_MEMTEST_START; - const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8; + (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START; + const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8; unsigned int i; @@ -782,15 +782,15 @@ int testdram (void) int runaddress = 0; int runwalk = 0; -#ifdef CFG_DRAM_TEST_DATA +#ifdef CONFIG_SYS_DRAM_TEST_DATA s = getenv ("testdramdata"); rundata = (s && (*s == 'y')) ? 1 : 0; #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS s = getenv ("testdramaddress"); runaddress = (s && (*s == 'y')) ? 1 : 0; #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK s = getenv ("testdramwalk"); runwalk = (s && (*s == 'y')) ? 1 : 0; #endif @@ -798,8 +798,8 @@ int testdram (void) if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) printf ("Testing RAM from 0x%08x to 0x%08x ... " "(don't panic... that will take a moment !!!!)\n", - CFG_MEMTEST_START, CFG_MEMTEST_END); -#ifdef CFG_DRAM_TEST_DATA + CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END); +#ifdef CONFIG_SYS_DRAM_TEST_DATA if (rundata == 1) { printf ("Test DATA ... "); if (mem_test_data () == 1) { @@ -809,7 +809,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_ADDRESS +#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS if (runaddress == 1) { printf ("Test ADDRESS ... "); if (mem_test_address () == 1) { @@ -819,7 +819,7 @@ int testdram (void) printf ("ok \n"); } #endif -#ifdef CFG_DRAM_TEST_WALK +#ifdef CONFIG_SYS_DRAM_TEST_WALK if (runwalk == 1) { printf ("Test WALKING ONEs ... "); if (mem_test_walk () == 1) { @@ -834,7 +834,7 @@ int testdram (void) return 0; } -#endif /* CFG_DRAM_TEST */ +#endif /* CONFIG_SYS_DRAM_TEST */ /* ronen - the below functions are used by the bootm function */ /* - we map the base register to fbe00000 (same mapping as in the LSP) */ diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c index 137739bed..e36b67664 100644 --- a/board/prodrive/p3mx/pci.c +++ b/board/prodrive/p3mx/pci.c @@ -66,13 +66,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host) printf ("PCI %d bus mode: Conventional PCI\n", host); break; case 1: - printf ("PCI %d bus mode: 66 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 66 MHz PCIX\n", host); break; case 2: - printf ("PCI %d bus mode: 100 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 100 MHz PCIX\n", host); break; case 3: - printf ("PCI %d bus mode: 133 Mhz PCIX\n", host); + printf ("PCI %d bus mode: 133 MHz PCIX\n", host); break; default: printf ("Unknown BUS %d\n", mode); @@ -932,14 +932,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci0_hose.regions + 0, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_0_MEM_SPACE, - CFG_PCI0_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_0_MEM_SPACE, + CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci0_hose.regions + 1, - CFG_PCI0_IO_SPACE_PCI, - CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI0_IO_SPACE_PCI, + CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci0_hose, pci_hose_read_config_byte_via_dword, @@ -981,14 +981,14 @@ void pci_init_board (void) /* PCI memory space */ pci_set_region (pci1_hose.regions + 0, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_0_MEM_SPACE, - CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_0_MEM_SPACE, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region (pci1_hose.regions + 1, - CFG_PCI1_IO_SPACE_PCI, - CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI1_IO_SPACE_PCI, + CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); pci_set_ops (&pci1_hose, pci_hose_read_config_byte_via_dword, diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c index d881d3807..bac6c12b9 100644 --- a/board/prodrive/p3mx/sdram_init.c +++ b/board/prodrive/p3mx/sdram_init.c @@ -243,9 +243,9 @@ phys_size_t initdram (int board_type) udelay(2); /* FIXME make this dynamic for the system clock */ /* SDRAM init done */ - memory_map_bank(0, CFG_SDRAM_BASE, (256 << 20)); -#ifdef CFG_SDRAM1_BASE - memory_map_bank(1, CFG_SDRAM1_BASE, (256 << 20)); + memory_map_bank(0, CONFIG_SYS_SDRAM_BASE, (256 << 20)); +#ifdef CONFIG_SYS_SDRAM1_BASE + memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20)); #endif /* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4 diff --git a/board/prodrive/p3mx/u-boot.lds b/board/prodrive/p3mx/u-boot.lds index 1a95755ab..ff2d8b7fe 100644 --- a/board/prodrive/p3mx/u-boot.lds +++ b/board/prodrive/p3mx/u-boot.lds @@ -60,7 +60,7 @@ SECTIONS /* store the environment in a seperate sector in the boot flash */ /* . = env_offset; */ -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) @@ -131,6 +131,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk index e5722dd36..60d3bf4d2 100644 --- a/board/prodrive/p3p440/config.mk +++ b/board/prodrive/p3p440/config.mk @@ -40,5 +40,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S index ee6b7066e..8c1a79c4b 100644 --- a/board/prodrive/p3p440/init.S +++ b/board/prodrive/p3p440/init.S @@ -90,10 +90,10 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 1a8aacbdf..1a0486f5c 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -35,29 +35,29 @@ void set_led(int color) { switch (color) { case LED_OFF: - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED); break; case LED_GREEN: - out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED); + out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED); break; case LED_RED: - out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN); + out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN); break; case LED_ORANGE: - out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED); + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED); break; } } static int is_monarch(void) { - out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY); + out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY); udelay(1000); - if (in32(GPIO0_IR) & CFG_MONARCH_IO) + if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO) return 0; else return 1; @@ -68,11 +68,11 @@ static void wait_for_pci_ready(void) /* * Configure EREADY_IO as input */ - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO); + out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO); udelay(1000); for (;;) { - if (in32(GPIO0_IR) & CFG_EREADY_IO) + if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO) return; } @@ -95,8 +95,8 @@ int board_early_init_f(void) mtdcr(cpc0_gpio, 0x03F01F80); out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN); - out32(GPIO0_OR, CFG_GPIO_RDY); + out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); + out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -152,7 +152,7 @@ int misc_init_r (void) /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { mtebc(pb1cr, 0); /* disable cs */ mtebc(pb1ap, 0); mtebc(pb2cr, 0); /* disable cs */ @@ -203,7 +203,7 @@ int pci_pre_init(struct pci_controller *hose) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller *hose) { /*--------------------------------------------------------------------------+ @@ -218,7 +218,7 @@ void pci_target_init(struct pci_controller *hose) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE); + out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); out32r(PCIX0_PIM0LAH, 0); out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); @@ -227,12 +227,12 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID); + out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* * is_pci_host diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h index e4e87d1f5..47e901894 100644 --- a/board/prodrive/p3p440/p3p440.h +++ b/board/prodrive/p3p440/p3p440.h @@ -24,11 +24,11 @@ #ifndef __P3P440_H__ #define __P3P440_H__ -#define CFG_GPIO_RDY (0x80000000 >> 11) -#define CFG_MONARCH_IO (0x80000000 >> 18) -#define CFG_EREADY_IO (0x80000000 >> 20) -#define CFG_LED_GREEN (0x80000000 >> 21) -#define CFG_LED_RED (0x80000000 >> 22) +#define CONFIG_SYS_GPIO_RDY (0x80000000 >> 11) +#define CONFIG_SYS_MONARCH_IO (0x80000000 >> 18) +#define CONFIG_SYS_EREADY_IO (0x80000000 >> 20) +#define CONFIG_SYS_LED_GREEN (0x80000000 >> 21) +#define CONFIG_SYS_LED_RED (0x80000000 >> 22) #define LED_OFF 1 #define LED_GREEN 2 diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds index 0e6c878a4..17cfde8f2 100644 --- a/board/prodrive/p3p440/u-boot.lds +++ b/board/prodrive/p3p440/u-boot.lds @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c index 0786324fb..351aed1e1 100644 --- a/board/prodrive/pdnb3/flash.c +++ b/board/prodrive/pdnb3/flash.c @@ -52,7 +52,7 @@ unsigned long flash_init(void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; i++) + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++) flash_info[i].flash_id = FLASH_UNKNOWN; size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); @@ -66,20 +66,20 @@ unsigned long flash_init(void) /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Redundant environment protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); flash_info[0].size = size; diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c index 1ce3c8c61..2efe027ec 100644 --- a/board/prodrive/pdnb3/nand.c +++ b/board/prodrive/pdnb3/nand.c @@ -136,7 +136,7 @@ static int pdnb3_nand_dev_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { - pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE; + pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE; nand->ecc.mode = NAND_ECC_SOFT; diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c index 3445a3abf..3773ba181 100644 --- a/board/prodrive/pdnb3/pdnb3.c +++ b/board/prodrive/pdnb3/pdnb3.c @@ -34,8 +34,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* predefine these here for FPGA programming (before including fpga.c) */ #define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data) -#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_DONE) -#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_INIT) +#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE) +#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT) #define OLD_VAL old_val static unsigned long old_val = 0; @@ -56,46 +56,46 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; - GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET); - GPIO_OUTPUT_ENABLE(CFG_GPIO_FPGA_RESET); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET); - GPIO_OUTPUT_SET(CFG_GPIO_SYS_RUNNING); - GPIO_OUTPUT_ENABLE(CFG_GPIO_SYS_RUNNING); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING); /* * Setup GPIO's for FPGA programming */ - GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG); - GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK); - GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA); - GPIO_OUTPUT_ENABLE(CFG_GPIO_PRG); - GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK); - GPIO_OUTPUT_ENABLE(CFG_GPIO_DATA); - GPIO_OUTPUT_DISABLE(CFG_GPIO_INIT); - GPIO_OUTPUT_DISABLE(CFG_GPIO_DONE); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE); /* * Setup GPIO's for interrupts */ - GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB); - GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB); - GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTORE_INT); - GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTORE_INT); - GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTART_INT); - GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTART_INT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT); + GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT); + GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT); /* * Setup GPIO's for 33MHz clock output */ *IXP425_GPIO_GPCLKR = 0x01FF0000; - GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK_33M); + GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M); /* * Setup other chip select's */ - *IXP425_EXP_CS1 = CFG_EXP_CS1; + *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1; return 0; } @@ -132,14 +132,14 @@ int do_fpga_boot(unsigned char *fpgadata) int status; int index; int i; - ulong len = CFG_MALLOC_LEN; + ulong len = CONFIG_SYS_MALLOC_LEN; /* * Setup GPIO's for FPGA programming */ - GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG); - GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK); - GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); /* * Save value so no readback is required upon programming @@ -149,8 +149,8 @@ int do_fpga_boot(unsigned char *fpgadata) /* * First try to decompress fpga image (gzip compressed?) */ - dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); + if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { printf("Error: Image has to be gzipp'ed!\n"); return -1; } @@ -204,9 +204,9 @@ int do_fpga_boot(unsigned char *fpgadata) /* * Reset FPGA */ - GPIO_OUTPUT_CLEAR(CFG_GPIO_FPGA_RESET); + GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET); udelay(10); - GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET); + GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); return (0); } diff --git a/board/prodrive/pdnb3/u-boot.lds b/board/prodrive/pdnb3/u-boot.lds index 638edbeee..dc59119e8 100644 --- a/board/prodrive/pdnb3/u-boot.lds +++ b/board/prodrive/pdnb3/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c index 8a7b14ee2..0fcf354cd 100644 --- a/board/psyent/common/AMDLV065D.c +++ b/board/psyent/common/AMDLV065D.c @@ -30,7 +30,7 @@ #endif #define SECTSZ (64 * 1024) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------*/ unsigned long flash_init (void) @@ -39,18 +39,18 @@ unsigned long flash_init (void) unsigned long addr; flash_info_t *fli = &flash_info[0]; - fli->size = CFG_FLASH_SIZE; - fli->sector_count = CFG_MAX_FLASH_SECT; + fli->size = CONFIG_SYS_FLASH_SIZE; + fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D; - addr = CFG_FLASH_BASE; + addr = CONFIG_SYS_FLASH_BASE; for (i = 0; i < fli->sector_count; ++i) { fli->start[i] = addr; addr += SECTSZ; fli->protect[i] = 1; } - return (CFG_FLASH_SIZE); + return (CONFIG_SYS_FLASH_SIZE); } /*--------------------------------------------------------------------*/ void flash_print_info (flash_info_t * info) @@ -135,7 +135,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ( readb (addr2) != 0xff) { udelay (1000 * 1000); putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("timeout\n"); return 1; } @@ -177,7 +177,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) /* Verify write */ start = get_timer (0); while (readb (dst) != b) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return 1; } } diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c index c75fe8c57..e5e770576 100644 --- a/board/psyent/pk1c20/led.c +++ b/board/psyent/pk1c20/led.c @@ -33,7 +33,7 @@ static led_id_t val = 0; void __led_init (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; @@ -44,7 +44,7 @@ void __led_init (led_id_t mask, int state) void __led_set (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; if (state == STATUS_LED_ON) val &= ~mask; @@ -55,7 +55,7 @@ void __led_set (led_id_t mask, int state) void __led_toggle (led_id_t mask) { - nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; val ^= mask; writel (&pio->data, val); diff --git a/board/purple/flash.c b/board/purple/flash.c index 1baae35eb..37c7becba 100644 --- a/board/purple/flash.c +++ b/board/purple/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/inca-ip.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ typedef unsigned long FLASH_PORT_WIDTH; typedef volatile unsigned long FLASH_PORT_WIDTHV; @@ -207,7 +207,7 @@ unsigned long flash_init (void) load_cmd(IN_RAM_CMD_READ); /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { ulong flashbase = PHYS_FLASH_1; ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0; @@ -229,20 +229,20 @@ unsigned long flash_init (void) size += flash_info[i].size; } -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CFG_MONITOR_BASE)); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, + flash_get_info(CONFIG_SYS_MONITOR_BASE)); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, + flash_get_info(CONFIG_ENV_ADDR)); #endif return size; @@ -282,13 +282,13 @@ static flash_info_t *flash_get_info(ulong base) int i; flash_info_t * info; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { info = & flash_info[i]; if (info->start[0] <= base && base < info->start[0] + info->size) break; } - return i == CFG_MAX_FLASH_BANKS ? 0 : info; + return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; } /*----------------------------------------------------------------------- @@ -507,10 +507,10 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) start = get_timer(0); - while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) { + while ((now = get_timer(start)) <= CONFIG_SYS_FLASH_ERASE_TOUT) { /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ + if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */ putc ('.'); last = get_timer(0); } diff --git a/board/purple/purple.c b/board/purple/purple.c index 977559112..54bef651c 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> +#include <netdev.h> #include <asm/inca-ip.h> #include <asm/regdef.h> #include <asm/mipsregs.h> @@ -128,14 +129,14 @@ phys_size_t initdram(int board_type) { /* The only supported number of SDRAM banks is 4. */ -#define CFG_NB 4 +#define CONFIG_SYS_NB 4 ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0; ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW; int cols = cfgpb0 & 0xF; int rows = (cfgpb0 & 0xF0) >> 4; int dw = cfgdw & 0xF; - ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB; + ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB; void (* sdram_init) (ulong); sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init); @@ -252,25 +253,32 @@ void copy_code (ulong dest_addr) /* copy u-boot code */ - copyLongs((ulong *)CFG_MONITOR_BASE, + copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE, (ulong *)dest_addr, - ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4); + ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4); /* flush caches */ start = CKSEG0; - end = start + CFG_DCACHE_SIZE; + end = start + CONFIG_SYS_DCACHE_SIZE; while(start < end) { cache_unroll(start,Index_Writeback_Inv_D); - start += CFG_CACHELINE_SIZE; + start += CONFIG_SYS_CACHELINE_SIZE; } start = CKSEG0; - end = start + CFG_ICACHE_SIZE; + end = start + CONFIG_SYS_ICACHE_SIZE; while(start < end) { cache_unroll(start,Index_Invalidate_I); - start += CFG_CACHELINE_SIZE; + start += CONFIG_SYS_CACHELINE_SIZE; } } + +#ifdef CONFIG_PLB2800_ETHER +int board_eth_init(bd_t *bis) +{ + return plb2800_eth_initialize(bis); +} +#endif diff --git a/board/purple/sconsole.c b/board/purple/sconsole.c index f52d50d0a..cd9d871b5 100644 --- a/board/purple/sconsole.c +++ b/board/purple/sconsole.c @@ -38,7 +38,7 @@ int serial_init (void) sb->pos = 0; sb->size = 0; - sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); + sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); return (0); } diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h index e130ad4c1..baed5fbb8 100644 --- a/board/purple/sconsole.h +++ b/board/purple/sconsole.h @@ -33,7 +33,7 @@ typedef struct sconsole_buffer_s { char data[1]; } sconsole_buffer_t; -#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR) +#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR) extern void (* sconsole_putc) (char); extern void (* sconsole_puts) (const char *); diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 972e6e720..bf1394b2a 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -42,7 +42,7 @@ SECTIONS common/cmd_boot.o (.text) lib_generic/zlib.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) } @@ -75,6 +75,6 @@ SECTIONS . = ALIGN(4); .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } uboot_end = .; } diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S index 80b5182cf..a50760fea 100644 --- a/board/pxa255_idp/lowlevel_init.S +++ b/board/pxa255_idp/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -53,67 +53,67 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] #ifdef DEBUG_BLINK_ENABLE @@ -156,17 +156,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -175,37 +175,37 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] @@ -225,7 +225,7 @@ mem_init: /* Before accessing MDREFR we need a valid DRI field, so we set */ /* this to power on defaults + DRI field. */ - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL ldr r2, =0xFFF and r3, r3, r2 ldr r4, =0x03ca4000 @@ -253,7 +253,7 @@ mem_init: /* set MDREFR according to user define with exception of a few bits */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL orr r4, r4, #(MDREFR_SLFRSH) bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ @@ -267,7 +267,7 @@ mem_init: /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ ldr r4, [r1, #MDREFR_OFFSET] @@ -275,7 +275,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ @@ -300,7 +300,7 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -319,7 +319,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] /* We are finished with Intel's memory controller initialisation */ diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index 5765c5532..b0aa8dda8 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -127,7 +127,7 @@ int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -U_BOOT_CMD(idpcmd, CFG_MAXARGS, 0, do_idpcmd, +U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd, "idpcmd - custom IDP command\n", "no args at this time\n" ); diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out index bda9946c1..39295fb67 100644 --- a/board/pxa255_idp/pxa_reg_calcs.out +++ b/board/pxa255_idp/pxa_reg_calcs.out @@ -15,21 +15,21 @@ gpsr1: 0x3f0002 gpsr2: 0x1c000 -#define CFG_GAFR0_L_VAL 0x80001005 -#define CFG_GAFR0_U_VAL 0xa5128012 -#define CFG_GAFR1_L_VAL 0x699a9558 -#define CFG_GAFR1_U_VAL 0xaaa5aa6a -#define CFG_GAFR2_L_VAL 0xaaaaaaaa -#define CFG_GAFR2_U_VAL 0x2 -#define CFG_GPCR0_VAL 0x1800400 -#define CFG_GPCR1_VAL 0x0 -#define CFG_GPCR2_VAL 0x0 -#define CFG_GPDR0_VAL 0xc1818440 -#define CFG_GPDR1_VAL 0xfcffab82 -#define CFG_GPDR2_VAL 0x1ffff -#define CFG_GPSR0_VAL 0x8000 -#define CFG_GPSR1_VAL 0x3f0002 -#define CFG_GPSR2_VAL 0x1c000 +#define CONFIG_SYS_GAFR0_L_VAL 0x80001005 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012 +#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x2 +#define CONFIG_SYS_GPCR0_VAL 0x1800400 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPDR0_VAL 0xc1818440 +#define CONFIG_SYS_GPDR1_VAL 0xfcffab82 +#define CONFIG_SYS_GPDR2_VAL 0x1ffff +#define CONFIG_SYS_GPSR0_VAL 0x8000 +#define CONFIG_SYS_GPSR1_VAL 0x3f0002 +#define CONFIG_SYS_GPSR2_VAL 0x1c000 GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET# diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py index c4bcb4b0a..2f89e3162 100644 --- a/board/pxa255_idp/pxa_reg_calcs.py +++ b/board/pxa255_idp/pxa_reg_calcs.py @@ -246,12 +246,12 @@ pxa_regs = { # U-boot define names uboot_reg_names = { - 'gpdr0':'CFG_GPDR0_VAL', 'gpdr1':'CFG_GPDR1_VAL', 'gpdr2':'CFG_GPDR2_VAL', - 'gpsr0':'CFG_GPSR0_VAL', 'gpsr1':'CFG_GPSR1_VAL', 'gpsr2':'CFG_GPSR2_VAL', - 'gpcr0':'CFG_GPCR0_VAL', 'gpcr1':'CFG_GPCR1_VAL', 'gpcr2':'CFG_GPCR2_VAL', - 'gafr0_l':'CFG_GAFR0_L_VAL', 'gafr0_u':'CFG_GAFR0_U_VAL', - 'gafr1_l':'CFG_GAFR1_L_VAL', 'gafr1_u':'CFG_GAFR1_U_VAL', - 'gafr2_l':'CFG_GAFR2_L_VAL', 'gafr2_u':'CFG_GAFR2_U_VAL', + 'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL', + 'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL', + 'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL', + 'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL', + 'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL', + 'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL', } # bit mappings diff --git a/board/pxa255_idp/u-boot.lds b/board/pxa255_idp/u-boot.lds index 381b6b746..96ac25c7c 100644 --- a/board/pxa255_idp/u-boot.lds +++ b/board/pxa255_idp/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index c2a85661e..03bcb093f 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -67,6 +67,6 @@ SECTIONS . = ALIGN(4); .sbss : { *(.sbss) } - .bss : { *(.bss) } + .bss : { *(.bss) . = ALIGN(4); } uboot_end = .; } diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c index 766ee95bb..35525bc3b 100644 --- a/board/quad100hd/nand.c +++ b/board/quad100hd/nand.c @@ -37,9 +37,9 @@ static void quad100hd_hwcontrol(struct mtd_info *mtd, struct nand_chip *this = mtd->priv; if (ctrl & NAND_CTRL_CHANGE) { - gpio_write_bit(CFG_NAND_CLE, !!(ctrl & NAND_CLE)); - gpio_write_bit(CFG_NAND_ALE, !!(ctrl & NAND_ALE)); - gpio_write_bit(CFG_NAND_CE, !(ctrl & NAND_NCE)); + gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE)); + gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE)); + gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE)); } if (cmd != NAND_CMD_NONE) @@ -48,7 +48,7 @@ static void quad100hd_hwcontrol(struct mtd_info *mtd, static int quad100hd_nand_ready(struct mtd_info *mtd) { - return gpio_read_in_bit(CFG_NAND_RDY); + return gpio_read_in_bit(CONFIG_SYS_NAND_RDY); } /* diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c index 81186782b..ffc47de25 100644 --- a/board/quad100hd/quad100hd.c +++ b/board/quad100hd/quad100hd.c @@ -86,8 +86,3 @@ int checkboard(void) return 0; } - -phys_size_t initdram(int board_type) -{ - return CFG_SDRAM_SIZE; -} diff --git a/board/quad100hd/u-boot.lds b/board/quad100hd/u-boot.lds index 195d91b71..7cf4d4f30 100644 --- a/board/quad100hd/u-boot.lds +++ b/board/quad100hd/u-boot.lds @@ -127,6 +127,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c index 75c2658e8..092aaab6b 100644 --- a/board/quantum/fpga.c +++ b/board/quantum/fpga.c @@ -62,11 +62,11 @@ int fpga_boot (unsigned char *fpgadata, int size) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; int i, index, len; int count; -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 int j; unsigned char data; #else @@ -89,7 +89,7 @@ int fpga_boot (unsigned char *fpgadata, int size) index = 0; -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* search for preamble 0xFFFFFFFF */ while (1) { if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) @@ -159,12 +159,12 @@ int fpga_boot (unsigned char *fpgadata, int size) debug ("write configuration data into fpga\n"); /* write configuration-data into fpga... */ -#ifdef CFG_FPGA_SPARTAN2 +#ifdef CONFIG_SYS_FPGA_SPARTAN2 /* * Load uncompressed image into fpga */ for (i = index; i < size; i++) { -#ifdef CFG_FPGA_PROG_FEEDBACK +#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if ((i % 1024) == 0) printf ("%6d out of %6d\r", i, size); /* let them know we are alive */ #endif diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c index 345f127b6..d94b5d72a 100644 --- a/board/quantum/quantum.c +++ b/board/quantum/quantum.c @@ -104,7 +104,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size9; @@ -112,15 +112,15 @@ phys_size_t initdram (int board_type) sizeof (sdram_table) / sizeof (uint)); /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000088; /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -136,12 +136,12 @@ phys_size_t initdram (int board_type) /* Check Bank 0 Memory Size, * 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); /* * Final mapping: */ - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; udelay (1000); return (size9); @@ -160,7 +160,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile ulong *addr; ulong cnt, val, size; @@ -224,14 +224,14 @@ int misc_init_r (void) void *fpga_data; int fpga_size; int status; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; int flash_size; /* Remap FLASH according to real size */ flash_size = flash_init (); - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; if (fpga_data_str && fpga_size_str) { fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index 1f9a191d4..55cb5eca3 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS /* XXX ? . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -135,6 +135,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug index 0cd053a8b..016048dae 100644 --- a/board/quantum/u-boot.lds.debug +++ b/board/quantum/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/r360mpi/flash.c b/board/r360mpi/flash.c index 9b42960c7..45cccf712 100644 --- a/board/r360mpi/flash.c +++ b/board/r360mpi/flash.c @@ -29,17 +29,17 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -76,13 +76,13 @@ static void flash_get_offsets (ulong base, flash_info_t * info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0; int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -95,27 +95,27 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ (void) flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -261,10 +261,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -335,7 +335,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) udelay (1000); while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -472,7 +472,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) start = get_timer (0); while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c index 4fd9d1298..85da41bd2 100644 --- a/board/r360mpi/pcmcia.c +++ b/board/r360mpi/pcmcia.c @@ -28,10 +28,10 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* * Configure SIUMCR to enable PCMCIA port B @@ -132,8 +132,8 @@ int pcmcia_hardware_disable(int slot) debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* remove all power */ immap->im_ioport.iop_pcdat |= 0x0400; @@ -164,8 +164,8 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) * and assert RESET signal diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c index c51e412f4..b502e4d78 100644 --- a/board/r360mpi/r360mpi.c +++ b/board/r360mpi/r360mpi.c @@ -105,7 +105,7 @@ static long int dram_size (long int, long int *, long int); phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size_b0 = 0; @@ -120,7 +120,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -129,10 +129,10 @@ phys_size_t initdram (int board_type) * preliminary address - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -152,7 +152,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); @@ -160,7 +160,7 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -168,7 +168,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -181,7 +181,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -189,20 +189,20 @@ phys_size_t initdram (int board_type) * Final mapping */ - memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; udelay (10000); #ifdef CONFIG_CAN_DRIVER /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; /* switch GPLB_5 to GPLA_5 */ - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; /* switch GPLB_5 to GPLA_5 */ + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; /* Initialize MBMR */ memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */ @@ -256,7 +256,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -268,7 +268,7 @@ static long int dram_size (long int mamr_value, void r360_i2c_lcd_write (uchar data0, uchar data1) { - if (i2c_write (CFG_I2C_LCD_ADDR, data0, 1, &data1, 1)) { + if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) { printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1); } } @@ -292,9 +292,9 @@ int misc_init_r (void) char *str; int i; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_read (CFG_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN); + i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN); for (i = 0; i < KEYBD_DATALEN; ++i) { sprintf (keybd_env + i + i, "%02X", kbd_data[i]); @@ -397,10 +397,10 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) uchar keybd_env[2 * KEYBD_DATALEN + 1]; int i; - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Read keys */ - i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN); + i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN); puts ("Keys:"); for (i = 0; i < KEYBD_DATALEN; ++i) { diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 5fcd5c9f1..db28544ba 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS cpu/mpc8xx/traps.o (.text) /*** . = env_offset; - common/environment.o (.text) + common/env_embedded.o (.text) ***/ *(.text) *(.fixup) @@ -132,12 +132,13 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); . = ALIGN(128 * 1024); .ppcenv : { - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) } } diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c index ad75c2156..80f57dc42 100644 --- a/board/rattler/rattler.c +++ b/board/rattler/rattler.c @@ -35,31 +35,31 @@ * according to the five values podr/pdir/ppar/psor/pdat for that entry */ -#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1) -#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) +#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) const iop_conf_t iop_conf_tab[4][32] = { /* Port A */ { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ + /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ + /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ + /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ + /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ + /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ + /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */ /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */ /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */ - /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ + /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ + /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ + /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ + /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ + /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ + /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ + /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ + /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */ /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ @@ -78,20 +78,20 @@ const iop_conf_t iop_conf_tab[4][32] = { /* Port B */ { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ @@ -123,12 +123,12 @@ const iop_conf_t iop_conf_tab[4][32] = { /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ - /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */ - /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */ + /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */ + /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */ /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ - /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ - /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */ + /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */ + /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */ /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */ /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ @@ -187,26 +187,26 @@ const iop_conf_t iop_conf_tab[4][32] = { phys_size_t initdram(int board_type) { - long int msize = CFG_SDRAM_SIZE; + long int msize = CONFIG_SYS_SDRAM_SIZE; -#ifndef CFG_RAMBOOT - volatile immap_t *immap = (immap_t *)CFG_IMMR; +#ifndef CONFIG_SYS_RAMBOOT + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE; + vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE; uchar c = 0xFF; - uint psdmr = CFG_PSDMR; + uint psdmr = CONFIG_SYS_PSDMR; int i; immap->im_siu_conf.sc_ppc_acr = 0x02; immap->im_siu_conf.sc_ppc_alrh = 0x30126745; immap->im_siu_conf.sc_tescr1 = 0x00004000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or1 = CFG_SDRAM_OR; - memctl->memc_br1 = CFG_SDRAM_BR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_or1 = CONFIG_SYS_SDRAM_OR; + memctl->memc_br1 = CONFIG_SYS_SDRAM_BR; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */ *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */ @@ -216,7 +216,7 @@ phys_size_t initdram(int board_type) *ramaddr = c; memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */ *ramaddr = c; -#endif /* !CFG_RAMBOOT */ +#endif /* !CONFIG_SYS_RAMBOOT */ /* Return total 60x bus SDRAM size */ return msize * 1024 * 1024; @@ -224,7 +224,7 @@ phys_size_t initdram(int board_type) int checkboard(void) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40); return 0; diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c index 26ebcae86..cb1e089f3 100644 --- a/board/rbc823/flash.c +++ b/board/rbc823/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -42,20 +42,20 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; /* Detect size */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* Setup offsets */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* Monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif @@ -322,7 +322,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr[0] & 0xFF) != 0xFF) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -454,7 +454,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((*cdest ^ *cdata) & 0x80) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c index 6d530f6b4..1d48f6d0b 100644 --- a/board/rbc823/kbd.c +++ b/board/rbc823/kbd.c @@ -48,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR; void smc1_setbrg (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cp = &(im->im_cpm); /* Set up the baud rate generator. @@ -65,7 +65,7 @@ void smc1_setbrg (void) int smc1_init (void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile smc_t *sp; volatile smc_uart_t *up; volatile cbd_t *tbdf, *rbdf; @@ -86,15 +86,15 @@ int smc1_init (void) im->im_siu_conf.sc_sdcr = 1; /* clear error conditions */ -#ifdef CFG_SDSR - im->im_sdma.sdma_sdsr = CFG_SDSR; +#ifdef CONFIG_SYS_SDSR + im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR; #else im->im_sdma.sdma_sdsr = 0x83; #endif /* clear SDMA interrupt mask */ -#ifdef CFG_SDMR - im->im_sdma.sdma_sdmr = CFG_SDMR; +#ifdef CONFIG_SYS_SDMR + im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR; #else im->im_sdma.sdma_sdmr = 0x00; #endif @@ -109,7 +109,7 @@ int smc1_init (void) * the buffer descriptors. */ -#ifdef CFG_ALLOC_DPRAM +#ifdef CONFIG_SYS_ALLOC_DPRAM dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ; #else dpaddr = CPM_KEYBOARD_BASE ; @@ -182,7 +182,7 @@ void smc1_putc(const char c) volatile cbd_t *tbdf; volatile char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; @@ -210,7 +210,7 @@ int smc1_getc(void) volatile cbd_t *rbdf; volatile unsigned char *buf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); unsigned char c; @@ -235,7 +235,7 @@ int smc1_tstc(void) { volatile cbd_t *rbdf; volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; volatile cpm8xx_t *cpmp = &(im->im_cpm); up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC]; diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c index 5b62af614..b2949060c 100644 --- a/board/rbc823/rbc823.c +++ b/board/rbc823/rbc823.c @@ -144,7 +144,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size8, size9; @@ -154,15 +154,15 @@ phys_size_t initdram (int board_type) /* * 1 Bank of 64Mbit x 2 devices */ - memctl->memc_mptpr = CFG_MPTPR_1BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K; memctl->memc_mar = 0x00000088; /* * Map controller SDRAM bank 0 */ - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); /* @@ -170,11 +170,11 @@ phys_size_t initdram (int board_type) */ memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */ udelay (1); - memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; + memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X; udelay (200); memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */ udelay (1); - memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; + memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X; udelay (200); memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ @@ -186,21 +186,21 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; /* 16: but should be: CFG_MPTPR_1BK_4K */ + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; /* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */ /* * Check Bank 0 Memory Size for re-configuration * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM, + size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ @@ -208,7 +208,7 @@ phys_size_t initdram (int board_type) /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ } @@ -221,14 +221,14 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } /* SDRAM Bank 0 is bigger - map first */ - memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; udelay (10000); @@ -248,7 +248,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -258,7 +258,7 @@ static long int dram_size (long int mamr_value, long int *base, void doc_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; upmconfig (UPMB, (uint *) static_table, diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index e41782554..63bd21bc3 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -133,6 +133,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/MigoR/Makefile b/board/renesas/MigoR/Makefile index 661b59d00..661b59d00 100644 --- a/board/MigoR/Makefile +++ b/board/renesas/MigoR/Makefile diff --git a/board/MigoR/config.mk b/board/renesas/MigoR/config.mk index 2c5085a91..2c5085a91 100644 --- a/board/MigoR/config.mk +++ b/board/renesas/MigoR/config.mk diff --git a/board/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index e48f7b3b1..4c1900ec2 100644 --- a/board/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 + * Copyright (C) 2007-2008 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> * * Copyright (C) 2007 @@ -211,25 +211,25 @@ PFC_PULCR_D: .long 0x6000 PFC_DRVCR_D: .long 0x0464 FRQCR_D: .long 0x07033639 PLLCR_D: .long 0x00005000 -DLLFRQ_D: .long 0x000004F6 ! 20080115 +DLLFRQ_D: .long 0x000004F6 CMNCR_A: .long CMNCR -CMNCR_D: .long 0x0000001B ! 20080115 -CS0BCR_A: .long CS0BCR ! Flash bank 1 +CMNCR_D: .long 0x0000001B +CS0BCR_A: .long CS0BCR CS0BCR_D: .long 0x24920400 -CS4BCR_A: .long CS4BCR ! -CS4BCR_D: .long 0x10003400 ! 20080115 -CS5ABCR_A: .long CS5ABCR ! +CS4BCR_A: .long CS4BCR +CS4BCR_D: .long 0x00003400 +CS5ABCR_A: .long CS5ABCR CS5ABCR_D: .long 0x24920400 -CS5BBCR_A: .long CS5BBCR ! +CS5BBCR_A: .long CS5BBCR CS5BBCR_D: .long 0x24920400 -CS6ABCR_A: .long CS6ABCR ! +CS6ABCR_A: .long CS6ABCR CS6ABCR_D: .long 0x24920400 CS0WCR_A: .long CS0WCR CS0WCR_D: .long 0x00000380 CS4WCR_A: .long CS4WCR -CS4WCR_D: .long 0x00100A81 ! 20080115 +CS4WCR_D: .long 0x00110080 CS5AWCR_A: .long CS5AWCR CS5AWCR_D: .long 0x00000300 CS5BWCR_A: .long CS5BWCR @@ -238,20 +238,20 @@ CS6AWCR_A: .long CS6AWCR CS6AWCR_D: .long 0x00000300 SDCR_A: .long SBSC_SDCR -SDCR_D: .long 0x80160809 ! 20080115 +SDCR_D: .long 0x80160809 SDWCR_A: .long SBSC_SDWCR -SDWCR_D: .long 0x0014450C ! 20080115 +SDWCR_D: .long 0x0014450C SDPCR_A: .long SBSC_SDPCR SDPCR_D: .long 0x00000087 RTCOR_A: .long SBSC_RTCOR RTCNT_A: .long SBSC_RTCNT RTCNT_D: .long 0xA55A0012 -RTCOR_D: .long 0xA55A001C ! 20080115 +RTCOR_D: .long 0xA55A001C RTCSR_A: .long SBSC_RTCSR RFCR_A: .long SBSC_RFCR RFCR_D: .long 0xA55A0221 -RTCSR_D: .long 0xA55A009a ! 20080115 -SDMR3_A: .long 0xFE581180 ! 20080115 +RTCSR_D: .long 0xA55A009a +SDMR3_A: .long 0xFE581180 SR_MASK_D: .long 0xEFFFFF0F @@ -260,5 +260,5 @@ SR_MASK_D: .long 0xEFFFFF0F SBSCR_D: .word 0x0044 PSCR_D: .word 0x0000 RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA504 ! 20080115 +RWTCSR_D_2: .word 0xA504 RWTCNT_D: .word 0x5A00 diff --git a/board/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c index b31f37d0f..204ca78fa 100644 --- a/board/MigoR/migo_r.c +++ b/board/renesas/MigoR/migo_r.c @@ -42,9 +42,9 @@ int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } diff --git a/board/MigoR/u-boot.lds b/board/renesas/MigoR/u-boot.lds index 692bc6291..f9c1effa4 100644 --- a/board/MigoR/u-boot.lds +++ b/board/renesas/MigoR/u-boot.lds @@ -49,9 +49,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile index 21f3e6e29..21f3e6e29 100644 --- a/board/ap325rxa/Makefile +++ b/board/renesas/ap325rxa/Makefile diff --git a/board/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c index cfa02617a..9f1112a43 100644 --- a/board/ap325rxa/ap325rxa.c +++ b/board/renesas/ap325rxa/ap325rxa.c @@ -144,9 +144,9 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } diff --git a/board/ap325rxa/config.mk b/board/renesas/ap325rxa/config.mk index b52a5e5cb..b52a5e5cb 100644 --- a/board/ap325rxa/config.mk +++ b/board/renesas/ap325rxa/config.mk diff --git a/board/ap325rxa/cpld-ap325rxa.c b/board/renesas/ap325rxa/cpld-ap325rxa.c index 16fadcbca..16fadcbca 100644 --- a/board/ap325rxa/cpld-ap325rxa.c +++ b/board/renesas/ap325rxa/cpld-ap325rxa.c diff --git a/board/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 4f6658879..4f6658879 100644 --- a/board/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S diff --git a/board/ap325rxa/u-boot.lds b/board/renesas/ap325rxa/u-boot.lds index a67037458..e9f8dc0de 100644 --- a/board/ap325rxa/u-boot.lds +++ b/board/renesas/ap325rxa/u-boot.lds @@ -49,9 +49,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); @@ -103,4 +103,3 @@ SECTIONS PROVIDE (_end = .); } - diff --git a/board/r2dplus/Makefile b/board/renesas/r2dplus/Makefile index e96a8aa98..e96a8aa98 100644 --- a/board/r2dplus/Makefile +++ b/board/renesas/r2dplus/Makefile diff --git a/board/r2dplus/config.mk b/board/renesas/r2dplus/config.mk index 1ec7dcc60..1ec7dcc60 100644 --- a/board/r2dplus/config.mk +++ b/board/renesas/r2dplus/config.mk diff --git a/board/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 5755de87b..28d2b3769 100644 --- a/board/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -11,7 +11,7 @@ .global lowlevel_init .text - .align 2 + .align 2 lowlevel_init: @@ -21,7 +21,7 @@ lowlevel_init: mov.l MMUCR_A,r1 mov.l MMUCR_D,r0 - mov.w r0,@r1 + mov.l r0,@r1 mov.l BCR1_A,r1 mov.l BCR1_D,r0 @@ -118,34 +118,34 @@ CCR_D_E: .long 0x8000090B FRQCR_A: .long FRQCR /* FRQCR Address */ FRQCR_D: .long 0x00000e0a /* 03/07/15 modify */ -BCR1_A: .long BCR1 /* BCR1 Address */ -BCR1_D: .long 0x00180008 -BCR2_A: .long BCR2 /* BCR2 Address */ -BCR2_D: .long 0xabe8 -BCR3_A: .long BCR3 /* BCR3 Address */ -BCR3_D: .long 0x0000 -BCR4_A: .long BCR4 /* BCR4 Address */ -BCR4_D: .long 0x00000010 -WCR1_A: .long WCR1 /* WCR1 Address */ -WCR1_D: .long 0x33343333 -WCR2_A: .long WCR2 /* WCR2 Address */ -WCR2_D: .long 0xcff86fbf -WCR3_A: .long WCR3 /* WCR3 Address */ -WCR3_D: .long 0x07777707 +BCR1_A: .long BCR1 /* BCR1 Address */ +BCR1_D: .long 0x00180008 +BCR2_A: .long BCR2 /* BCR2 Address */ +BCR2_D: .long 0xabe8 +BCR3_A: .long BCR3 /* BCR3 Address */ +BCR3_D: .long 0x0000 +BCR4_A: .long BCR4 /* BCR4 Address */ +BCR4_D: .long 0x00000010 +WCR1_A: .long WCR1 /* WCR1 Address */ +WCR1_D: .long 0x33343333 +WCR2_A: .long WCR2 /* WCR2 Address */ +WCR2_D: .long 0xcff86fbf +WCR3_A: .long WCR3 /* WCR3 Address */ +WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ RTCNT_A: .long RTCNT /* RTCNT Address */ RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCOR_D: .long 0xA534 /* RTCOR Write Code */ RTCSR_A: .long RTCSR /* RTCSR Address */ RTCSR_D: .long 0xA510 /* RTCSR Write Code */ -SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ +SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ SDMR3_D: .long 0x55 MCR_A: .long MCR /* MCR Address */ -MCR_D1: .long 0x081901F4 /* MRSET:'0' */ -MCR_D2: .long 0x481901F4 /* MRSET:'1' */ -RFCR_A: .long RFCR /* RFCR Address */ -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +MCR_D1: .long 0x081901F4 /* MRSET:'0' */ +MCR_D2: .long 0x481901F4 /* MRSET:'1' */ +RFCR_A: .long RFCR /* RFCR Address */ +RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ PCR_A: .long PCR /* PCR Address */ PCR_D: .long 0x0000 MMUCR_A: .long MMUCR /* MMUCCR Address */ diff --git a/board/r2dplus/r2dplus.c b/board/renesas/r2dplus/r2dplus.c index 8fb8ff667..0c08d6859 100644 --- a/board/r2dplus/r2dplus.c +++ b/board/renesas/r2dplus/r2dplus.c @@ -23,6 +23,7 @@ #include <common.h> #include <ide.h> +#include <netdev.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/pci.h> @@ -42,9 +43,9 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } @@ -76,3 +77,8 @@ void pci_init_board(void) { pci_sh7751_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/r2dplus/u-boot.lds b/board/renesas/r2dplus/u-boot.lds index 96d8d81ac..040e53017 100644 --- a/board/r2dplus/u-boot.lds +++ b/board/renesas/r2dplus/u-boot.lds @@ -49,9 +49,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/r7780mp/Makefile b/board/renesas/r7780mp/Makefile index c100e7e2a..c100e7e2a 100644 --- a/board/r7780mp/Makefile +++ b/board/renesas/r7780mp/Makefile diff --git a/board/r7780mp/config.mk b/board/renesas/r7780mp/config.mk index 6a045a15c..6a045a15c 100644 --- a/board/r7780mp/config.mk +++ b/board/renesas/r7780mp/config.mk diff --git a/board/r7780mp/lowlevel_init.S b/board/renesas/r7780mp/lowlevel_init.S index 05c075b6c..ab0499a3a 100644 --- a/board/r7780mp/lowlevel_init.S +++ b/board/renesas/r7780mp/lowlevel_init.S @@ -325,8 +325,9 @@ repeat2: RWTCSR_D_1: .word 0xA507 RWTCSR_D_2: .word 0xA507 RWTCNT_D: .word 0x5A00 + .align 2 -BBG_PMMR_A: .long 0xFF800010 +BBG_PMMR_A: .long 0xFF800010 BBG_PMSR1_A: .long 0xFF800014 BBG_PMSR2_A: .long 0xFF800018 BBG_PMSR3_A: .long 0xFF80001C diff --git a/board/r7780mp/r7780mp.c b/board/renesas/r7780mp/r7780mp.c index 19c35d349..396e4b6db 100644 --- a/board/r7780mp/r7780mp.c +++ b/board/renesas/r7780mp/r7780mp.c @@ -23,6 +23,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/pci.h> +#include <netdev.h> #include "r7780mp.h" int checkboard(void) @@ -47,9 +48,9 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } @@ -77,3 +78,8 @@ void pci_init_board(void) { pci_sh7780_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/r7780mp/r7780mp.h b/board/renesas/r7780mp/r7780mp.h index 476a41354..476a41354 100644 --- a/board/r7780mp/r7780mp.h +++ b/board/renesas/r7780mp/r7780mp.h diff --git a/board/r7780mp/u-boot.lds b/board/renesas/r7780mp/u-boot.lds index e7499e5cd..eaa05d0d5 100644 --- a/board/r7780mp/u-boot.lds +++ b/board/renesas/r7780mp/u-boot.lds @@ -49,9 +49,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/rsk7203/Makefile b/board/renesas/rsk7203/Makefile index 7365d1930..7365d1930 100644 --- a/board/rsk7203/Makefile +++ b/board/renesas/rsk7203/Makefile diff --git a/board/rsk7203/config.mk b/board/renesas/rsk7203/config.mk index 61aa51f2b..61aa51f2b 100644 --- a/board/rsk7203/config.mk +++ b/board/renesas/rsk7203/config.mk diff --git a/board/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index e4d6f9e7d..e4d6f9e7d 100644 --- a/board/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S diff --git a/board/rsk7203/rsk7203.c b/board/renesas/rsk7203/rsk7203.c index beb943e85..2cbd45e04 100644 --- a/board/rsk7203/rsk7203.c +++ b/board/renesas/rsk7203/rsk7203.c @@ -39,12 +39,33 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } void led_set_state(unsigned short value) { } + +/* + * The RSK board has the SMSC9118 wired up 'incorrectly'. + * Byte-swapping is necessary, and so poor performance is inevitable. + * This problem cannot evade by the swap function of CHIP, this can + * evade by software Byte-swapping. + * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push + * functions necessary to solve this problem. + */ +u32 pkt_data_pull(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\ + | swab16(*(addr_16 + 1)); +} + +void pkt_data_push(u32 addr, u32 val) +{ + *(volatile u16 *)(addr + 2) = swab16((u16)val); + *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); +} diff --git a/board/rsk7203/u-boot.lds b/board/renesas/rsk7203/u-boot.lds index bf4433a23..63e5b9744 100644 --- a/board/rsk7203/u-boot.lds +++ b/board/renesas/rsk7203/u-boot.lds @@ -46,9 +46,9 @@ SECTIONS { cpu/sh2/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/sh7763rdp/Makefile b/board/renesas/sh7763rdp/Makefile index 62a683d57..62a683d57 100644 --- a/board/sh7763rdp/Makefile +++ b/board/renesas/sh7763rdp/Makefile diff --git a/board/sh7763rdp/config.mk b/board/renesas/sh7763rdp/config.mk index c52dbfd7b..c52dbfd7b 100644 --- a/board/sh7763rdp/config.mk +++ b/board/renesas/sh7763rdp/config.mk diff --git a/board/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 2a44eee1a..2a44eee1a 100644 --- a/board/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S diff --git a/board/sh7763rdp/sh7763rdp.c b/board/renesas/sh7763rdp/sh7763rdp.c index 92ac7b7a9..88bab70e3 100644 --- a/board/sh7763rdp/sh7763rdp.c +++ b/board/renesas/sh7763rdp/sh7763rdp.c @@ -66,9 +66,9 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } diff --git a/board/sh7763rdp/u-boot.lds b/board/renesas/sh7763rdp/u-boot.lds index c07f0d80e..7177416c2 100644 --- a/board/sh7763rdp/u-boot.lds +++ b/board/renesas/sh7763rdp/u-boot.lds @@ -49,9 +49,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/board/sh7785lcr/Makefile b/board/renesas/sh7785lcr/Makefile index b1b538c9d..b1b538c9d 100644 --- a/board/sh7785lcr/Makefile +++ b/board/renesas/sh7785lcr/Makefile diff --git a/board/sh7785lcr/config.mk b/board/renesas/sh7785lcr/config.mk index 93761eec8..20807dfc5 100644 --- a/board/sh7785lcr/config.mk +++ b/board/renesas/sh7785lcr/config.mk @@ -23,4 +23,3 @@ # NOTE: Must match value used in u-boot.lds (in this directory). # TEXT_BASE = 0x0ff80000 - diff --git a/board/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 8126296e5..50e1789cc 100644 --- a/board/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -315,4 +315,3 @@ CS_I2C_WCR_D: .long 0x00000003 CCR_A: .long 0xff00001c CCR_D: .long 0x0000090b - diff --git a/board/sh7785lcr/rtl8169.h b/board/renesas/sh7785lcr/rtl8169.h index d1c0d64b1..ca9c0bd94 100644 --- a/board/sh7785lcr/rtl8169.h +++ b/board/renesas/sh7785lcr/rtl8169.h @@ -55,4 +55,3 @@ const unsigned short EEPROM_W_Data_8169_B[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; - diff --git a/board/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c index 2bc873bd1..bf0ba145d 100644 --- a/board/sh7785lcr/rtl8169_mac.c +++ b/board/renesas/sh7785lcr/rtl8169_mac.c @@ -346,4 +346,3 @@ U_BOOT_CMD( "\n" " - print MAC address for RTL8110\n" ); - diff --git a/board/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c index 9c228e5f6..ce0620f68 100644 --- a/board/sh7785lcr/selfcheck.c +++ b/board/renesas/sh7785lcr/selfcheck.c @@ -84,7 +84,7 @@ static void test_net(void) if (data == 0x816910ec) printf("Ethernet OK\n"); else - printf("Ethernet NG, data = %08x\n", data); + printf("Ethernet NG, data = %08x\n", (unsigned int)data); } static void test_sata(void) @@ -96,7 +96,7 @@ static void test_sata(void) if (data == 0x35121095) printf("SATA OK\n"); else - printf("SATA NG, data = %08x\n", data); + printf("SATA NG, data = %08x\n", (unsigned int)data); } static void test_pci(void) @@ -170,4 +170,3 @@ U_BOOT_CMD( "hwtest sata - check SiI3512 ID\n" "hwtest pci - output PCI slot device ID\n" ); - diff --git a/board/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c index 5b9c40374..786c758a9 100644 --- a/board/sh7785lcr/sh7785lcr.c +++ b/board/renesas/sh7785lcr/sh7785lcr.c @@ -21,6 +21,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/pci.h> +#include <netdev.h> int checkboard(void) { @@ -37,9 +38,9 @@ int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; - gd->bd->bi_memstart = CFG_SDRAM_BASE; - gd->bd->bi_memsize = CFG_SDRAM_SIZE; - printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024)); + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); return 0; } @@ -49,3 +50,7 @@ void pci_init_board(void) pci_sh7780_init(&hose); } +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/sh7785lcr/u-boot.lds b/board/renesas/sh7785lcr/u-boot.lds index f0109eb24..231769f3b 100644 --- a/board/sh7785lcr/u-boot.lds +++ b/board/renesas/sh7785lcr/u-boot.lds @@ -40,9 +40,9 @@ SECTIONS { cpu/sh4/start.o (.text) . = ALIGN(8192); - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) . = ALIGN(8192); - common/environment.o (.ppcenvr) + common/env_embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); @@ -94,4 +94,3 @@ SECTIONS PROVIDE (_end = .); } - diff --git a/board/rmu/flash.c b/board/rmu/flash.c index 0f2c327a1..a3ab851d2 100644 --- a/board/rmu/flash.c +++ b/board/rmu/flash.c @@ -26,7 +26,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -40,13 +40,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0 ; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -64,39 +64,39 @@ unsigned long flash_init (void) memctl->memc_br0, memctl->memc_or0); /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; debug ("## BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif -#if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) +#if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND) debug ("Protect redundand environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR_REDUND, - (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE - 1); + (ulong)CONFIG_ENV_ADDR_REDUND, + (ulong)CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE - 1); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -406,7 +406,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long *)(info->start[l_sect]); while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -529,7 +529,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c index e22dc5258..cd02b9c6e 100644 --- a/board/rmu/rmu.c +++ b/board/rmu/rmu.c @@ -94,7 +94,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size9; @@ -102,15 +102,15 @@ phys_size_t initdram (int board_type) sizeof (sdram_table) / sizeof (uint)); /* Refresh clock prescalar */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000088; /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -127,14 +127,14 @@ phys_size_t initdram (int board_type) * 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, + size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); /* * Final mapping: */ - memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; udelay (1000); return (size9); @@ -153,7 +153,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds index 1f9a191d4..55cb5eca3 100644 --- a/board/rmu/u-boot.lds +++ b/board/rmu/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS /* XXX ? . = env_offset; */ - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -135,6 +135,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug index 0cd053a8b..016048dae 100644 --- a/board/rmu/u-boot.lds.debug +++ b/board/rmu/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c index d80e77862..be29b65cf 100644 --- a/board/rpxsuper/flash.c +++ b/board/rpxsuper/flash.c @@ -33,7 +33,7 @@ #include <mpc8xx.h> #include <asm/io.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define RD_SWP32(x) in_le32((volatile u32*)x) @@ -53,35 +53,35 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); /* * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif - return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); + return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); } /*----------------------------------------------------------------------- @@ -292,7 +292,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) addr = (vu_long*)(info->start[l_sect]); while ( (addr[0] & 0x80808080) != 0x80808080 || (addr[1] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -423,7 +423,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c index ef99affff..12e23f487 100644 --- a/board/rpxsuper/mii_phy.c +++ b/board/rpxsuper/mii_phy.c @@ -54,7 +54,7 @@ mii_phy_read(unsigned short reg) { int i; unsigned short tmp, val = 0, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; tmp = 0x6002 | (adr << 7) | (reg << 2); regs->bcsr4 = 0xC3; @@ -83,7 +83,7 @@ mii_phy_write(unsigned short reg, unsigned short val) { int i; unsigned short tmp, adr = 0; - t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; tmp = 0x5002 | (adr << 7) | (reg << 2); regs->bcsr4 = 0xC3; diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c index f633c5c47..aa59803de 100644 --- a/board/rpxsuper/rpxsuper.c +++ b/board/rpxsuper/rpxsuper.c @@ -193,11 +193,11 @@ const iop_conf_t iop_conf_tab[4][32] = { */ int board_early_init_f (void) { - volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - memctl->memc_br4 = CFG_BR4_PRELIM; - memctl->memc_or4 = CFG_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */ regs->bcsr2 = 0x20; /* mut be written to enable writing FLASH */ return 0; @@ -206,7 +206,7 @@ int board_early_init_f (void) void reset_phy(void) { - volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; regs->bcsr4 = 0xC3; } @@ -216,7 +216,7 @@ reset_phy(void) int checkboard(void) { - volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE; + volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE; printf ("Board: Embedded Planet RPX Super, Revision %d\n", regs->bcsr0 >> 4); @@ -227,15 +227,15 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar c = 0, *ramaddr; ulong psdmr, lsdmr, bcr; long size = 0; int i; - psdmr = CFG_PSDMR; - lsdmr = CFG_LSDMR; + psdmr = CONFIG_SYS_PSDMR; + lsdmr = CONFIG_SYS_LSDMR; /* * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): @@ -254,17 +254,17 @@ phys_size_t initdram(int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - size = CFG_SDRAM0_SIZE; + size = CONFIG_SYS_SDRAM0_SIZE; bcr = immap->im_siu_conf.sc_bcr; immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM); - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; - ramaddr = (uchar *)(CFG_SDRAM0_BASE); - memctl->memc_psrt = CFG_PSRT; + ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE); + memctl->memc_psrt = CONFIG_SYS_PSRT; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; @@ -281,10 +281,10 @@ phys_size_t initdram(int board_type) immap->im_siu_conf.sc_bcr = bcr; -#ifndef CFG_RAMBOOT -/* size += CFG_SDRAM1_SIZE; */ - ramaddr = (uchar *)(CFG_SDRAM1_BASE); - memctl->memc_lsrt = CFG_LSRT; +#ifndef CONFIG_SYS_RAMBOOT +/* size += CONFIG_SYS_SDRAM1_SIZE; */ + ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE); + memctl->memc_lsrt = CONFIG_SYS_LSRT; memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA; *ramaddr = c; diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c index 4e43b2966..e99c2a6f6 100644 --- a/board/rsdproto/flash.c +++ b/board/rsdproto/flash.c @@ -41,7 +41,7 @@ */ #undef WITH_AUTOSELECT -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #if 1 #define D(x) @@ -94,7 +94,7 @@ unsigned long flash_init (void) #endif /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -120,28 +120,28 @@ unsigned long flash_init (void) * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= PHYS_FLASH +#if CONFIG_SYS_MONITOR_BASE >= PHYS_FLASH flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); #endif @@ -259,7 +259,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) start = get_timer (0); do { - if (get_timer(start) > CFG_FLASH_ERASE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { /* write reset command, command address is unimportant */ /* this command turns the flash back to read mode */ f_addr = @@ -387,7 +387,7 @@ static unsigned char write_ull(flash_info_t *info, start = get_timer (0); do { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { /* write reset command, command address is unimportant */ /* this command turns the flash back to read mode */ diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c index eeec3b4dc..26edb2e4f 100644 --- a/board/rsdproto/rsdproto.c +++ b/board/rsdproto/rsdproto.c @@ -253,7 +253,7 @@ int checkboard (void) puts ("Board: Rohde & Schwarz 8260 Protocol Board\n"); /* initialise i2c */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); read_RS5C372_time (&timedate); printf (" Time: %02d:%02d:%02d\n", @@ -284,7 +284,7 @@ int misc_init_f (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; #ifdef INIT_LOCAL_BUS_SDRAM @@ -317,7 +317,7 @@ phys_size_t initdram (int board_type) * * The appropriate BRx/ORx registers have already * been set when we get here (see cpu_init_f). The - * SDRAM can be accessed at the address CFG_SDRAM_BASE. + * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ memctl->memc_mptpr = 0x2000; memctl->memc_mar = 0x0200; @@ -330,7 +330,7 @@ phys_size_t initdram (int board_type) memctl->memc_lsrt = 0x0b; memctl->memc_lurt = 0x00; ramaddr = (uchar *) PHYS_SDRAM_LOCAL; - sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); + sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA; *ramaddr = 0xff; for (i = 0; i < 8; i++) { @@ -339,13 +339,13 @@ phys_size_t initdram (int board_type) } memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW; *ramaddr = 0xff; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM; #endif /* initialise 60x bus ram */ memctl->memc_psrt = 0x0b; memctl->memc_purt = 0x08; ramaddr32 = (ulong *) PHYS_SDRAM_60X; - sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); + sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI); memctl->memc_psdmr = sdmr | PSDMR_OP_PREA; ramaddr32[0] = 0x00ff00ff; ramaddr32[1] = 0x00ff00ff; diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index 07a7277c8..b2bd57641 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c index edb775df2..4a7f362c5 100644 --- a/board/sacsng/clkinit.c +++ b/board/sacsng/clkinit.c @@ -37,7 +37,7 @@ int Daq64xSampling = 0; void Daq_BRG_Reset(uint brg) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -53,7 +53,7 @@ void Daq_BRG_Reset(uint brg) void Daq_BRG_Disable(uint brg) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -68,7 +68,7 @@ void Daq_BRG_Disable(uint brg) void Daq_BRG_Enable(uint brg) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -82,7 +82,7 @@ void Daq_BRG_Enable(uint brg) uint Daq_BRG_Get_Div16(uint brg) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -104,7 +104,7 @@ uint Daq_BRG_Get_Div16(uint brg) void Daq_BRG_Set_Div16(uint brg, uint div16) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -126,7 +126,7 @@ void Daq_BRG_Set_Div16(uint brg, uint div16) uint Daq_BRG_Get_Count(uint brg) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint *brg_ptr; uint brg_cnt; @@ -153,7 +153,7 @@ uint Daq_BRG_Get_Count(uint brg) void Daq_BRG_Set_Count(uint brg, uint brg_cnt) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -183,7 +183,7 @@ void Daq_BRG_Set_Count(uint brg, uint brg_cnt) uint Daq_BRG_Get_ExtClk(uint brg) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -243,7 +243,7 @@ char* Daq_BRG_Get_ExtClk_Description(uint brg) void Daq_BRG_Set_ExtClk(uint brg, uint extc) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint *brg_ptr; brg_ptr = (uint *)&immr->im_brgc1; @@ -259,7 +259,7 @@ void Daq_BRG_Set_ExtClk(uint brg, uint extc) uint Daq_BRG_Rate(uint brg) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint *brg_ptr; uint brg_cnt; uint brg_freq = 0; @@ -296,7 +296,7 @@ uint Daq_Get_SampleRate(void) void Daq_Init_Clocks(int sample_rate, int sample_64x) { - volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); + volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */); uint mclk_divisor; /* MCLK divisor */ int flag; /* Interrupt state */ @@ -378,7 +378,7 @@ void Daq_Stop_Clocks(void) { #ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; register uint mclk_brg; /* MCLK BRG value */ register uint sclk_brg; /* SCLK BRG value */ register uint lrclk_brg; /* LRCLK BRG value */ @@ -663,7 +663,7 @@ void Daq_Start_Clocks(int sample_rate) { #ifdef TIGHTEN_UP_BRG_TIMING - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; register uint mclk_brg; /* MCLK BRG value */ register uint sclk_brg; /* SCLK BRG value */ @@ -914,7 +914,7 @@ void Daq_Start_Clocks(int sample_rate) void Daq_Display_Clocks(void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; uint mclk_divisor; /* Detected MCLK divisor */ uint sclk_divisor; /* Detected SCLK divisor */ diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c index 52e01def5..8b30f50cc 100644 --- a/board/sacsng/flash.c +++ b/board/sacsng/flash.c @@ -27,15 +27,15 @@ #undef DEBUG -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -#ifndef CFG_ENV_SIZE -#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#ifndef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -52,49 +52,49 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size_b0 = flash_get_size((vu_short *)CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_short *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0<<20); } - size_b1 = flash_get_size((vu_short *)CFG_FLASH1_BASE, &flash_info[1]); + size_b1 = flash_get_size((vu_short *)CONFIG_SYS_FLASH1_BASE, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif if (size_b1) { -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[1]); #endif } else { @@ -247,7 +247,7 @@ static ulong flash_get_size (vu_short *addr, flash_info_t *info) } else { #ifdef DEBUG printf("Unknown flash type 0x%04X\n", value); - info->size = CFG_FLASH_SIZE; + info->size = CONFIG_SYS_FLASH_SIZE; #else info->flash_id = FLASH_UNKNOWN; return (0); /* => no or unknown flash */ @@ -374,7 +374,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_short*)(info->start[l_sect]); while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); addr[0] = 0xF0F0; /* reset bank */ __asm__ __volatile__(" sync\n "); @@ -509,7 +509,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while (*(vu_short *)dest != (ushort)data) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c index c00f14ee6..2513937ed 100644 --- a/board/sacsng/sacsng.c +++ b/board/sacsng/sacsng.c @@ -161,16 +161,16 @@ int checkboard(void) phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; volatile uchar c = 0; - volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8); - uint psdmr = CFG_PSDMR; + volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8); + uint psdmr = CONFIG_SYS_PSDMR; int i; uint psrt = 14; /* for no SPD */ uint chipselects = 1; /* for no SPD */ - uint sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ - uint or = CFG_OR2_PRELIM; /* for no SPD */ + uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */ + uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */ #ifdef SDRAM_SPD_ADDR uint data_width; uint rows; @@ -383,10 +383,10 @@ phys_size_t initdram(int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_psrt = psrt; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; @@ -409,7 +409,7 @@ phys_size_t initdram(int board_type) if(chipselects > 1) { ramaddr += sdram_size; - memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size; memctl->memc_or3 = or; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; @@ -446,8 +446,8 @@ int misc_init_r(void) /* * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization. */ - volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */); - volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT); + volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */); + volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT); int reg; /* I2C register value */ char *ep; /* Environment pointer */ @@ -854,14 +854,14 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); + volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); iopd->pdat &= ~cs_mask[slave->cs]; } void spi_cs_deactivate(struct spi_slave *slave) { - volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */); + volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */); iopd->pdat |= cs_mask[slave->cs]; } diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 034c810f7..e0119a771 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -2,7 +2,7 @@ * Memory Setup stuff - taken from blob memsetup.S * * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * * Modified for the Samsung SMDK2410 by * (C) Copyright 2002 @@ -73,8 +73,8 @@ lowlevel_init: ldr r1, [r0] str r1, [r0] - ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 - ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 + ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 + ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 /* Disable all interrupts (VIC0 and VIC1) */ mvn r3, #0x0 @@ -107,11 +107,11 @@ lowlevel_init: bl mem_ctrl_asm_init /* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset + ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) + ldr r1, [r0] + bic r1, r1, #0xfffffff7 + cmp r1, #0x8 + beq wakeup_reset 1: mov lr, r12 @@ -124,10 +124,10 @@ wakeup_reset: ldr r1, [r0] str r1, [r0] - /* LED test */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x3000 - str r1, [r0, #GPNDAT_OFFSET] + /* LED test */ + ldr r0, =ELFIN_GPIO_BASE + ldr r1, =0x3000 + str r1, [r0, #GPNDAT_OFFSET] /* Load return address and jump to kernel */ ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) @@ -201,7 +201,7 @@ wait_for_async: str r1, [r0, #MPLL_LOCK_OFFSET] /* Set Clock Divider */ - ldr r1, [r0, #CLK_DIV0_OFFSET] + ldr r1, [r0, #CLK_DIV0_OFFSET] bic r1, r1, #0x30000 bic r1, r1, #0xff00 bic r1, r1, #0xff @@ -252,7 +252,7 @@ uart_asm_init: /* set GPIO to enable UART */ ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x220022 - str r1, [r0, #GPACON_OFFSET] + str r1, [r0, #GPACON_OFFSET] mov pc, lr #endif @@ -265,11 +265,11 @@ nand_asm_init: ldr r1, [r0, #NFCONF_OFFSET] orr r1, r1, #0x70 orr r1, r1, #0x7700 - str r1, [r0, #NFCONF_OFFSET] + str r1, [r0, #NFCONF_OFFSET] ldr r1, [r0, #NFCONT_OFFSET] orr r1, r1, #0x07 - str r1, [r0, #NFCONT_OFFSET] + str r1, [r0, #NFCONT_OFFSET] mov pc, lr #endif diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index 77fd2c8a2..bd2e45ac2 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -107,12 +107,12 @@ ulong virt_to_phy_smdk6400(ulong addr) } #endif -#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY) #include <linux/mtd/nand.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; void nand_init(void) { - nand_probe(CFG_NAND_BASE); + nand_probe(CONFIG_SYS_NAND_BASE); if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) print_size(nand_dev_desc[0].totlen, "\n"); } diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds index 132ab21ff..bd6b24f95 100644 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ b/board/samsung/smdk6400/u-boot-nand.lds @@ -57,6 +57,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss : { *(.bss) } + .bss : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c index 762fb738f..dd712e3a3 100644 --- a/board/sandburst/common/flash.c +++ b/board/sandburst/common/flash.c @@ -41,9 +41,9 @@ #endif /* DEBUG */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xfff80000} /* Boot Flash */ }; @@ -65,7 +65,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); unsigned long flash_init (void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; @@ -74,7 +74,7 @@ unsigned long flash_init (void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -284,7 +284,7 @@ int wait_for_DQ7(flash_info_t *info, int sect) start = get_timer (0); last = start; while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return -1; } @@ -502,7 +502,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c index 1e3dffb1e..9af6b8d88 100644 --- a/board/sandburst/common/ppc440gx_i2c.c +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -43,8 +43,8 @@ #define IIC_NOK_TOUT 6 /* Transfer timeout */ #define IIC_TIMEOUT 1 /* 1 second */ -#if defined(CFG_I2C_NOPROBES) -static uchar i2c_no_probes[] = CFG_I2C_NOPROBES; +#if defined(CONFIG_SYS_I2C_NOPROBES) +static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; #endif static void _i2c_bus1_reset (void) @@ -105,7 +105,7 @@ void i2c1_init (int speed, int slaveadd) unsigned long freqOPB; int val, divisor; -#ifdef CFG_I2C_INIT_BOARD +#ifdef CONFIG_SYS_I2C_INIT_BOARD /* call board specific i2c bus reset routine before accessing the */ /* environment, which might be in a chip on that bus. For details */ /* about this problem see doc/I2C_Edge_Conditions. */ @@ -384,7 +384,7 @@ int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -397,7 +397,7 @@ int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { printf( "I2c read: failed %d\n", ret); @@ -422,7 +422,7 @@ int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) xaddr[3] = addr & 0xFF; } -#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW +#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* * EEPROM chips that implement "address overflow" are ones * like Catalyst 24WC04/08/16 which has 9/10/11 bits of @@ -435,7 +435,7 @@ int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); #endif return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); @@ -465,13 +465,13 @@ void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val) int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int j; -#if defined(CFG_I2C_NOPROBES) +#if defined(CONFIG_SYS_I2C_NOPROBES) int k, skip; #endif puts ("Valid chip addresses:"); for(j = 0; j < 128; j++) { -#if defined(CFG_I2C_NOPROBES) +#if defined(CONFIG_SYS_I2C_NOPROBES) skip = 0; for (k = 0; k < sizeof(i2c_no_probes); k++){ if (j == i2c_no_probes[k]){ @@ -488,7 +488,7 @@ int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } putc ('\n'); -#if defined(CFG_I2C_NOPROBES) +#if defined(CONFIG_SYS_I2C_NOPROBES) puts ("Excluded chip addresses:"); for( k = 0; k < sizeof(i2c_no_probes); k++ ) printf(" %02X", i2c_no_probes[k] ); diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h index 10000f5ba..328abd64b 100644 --- a/board/sandburst/common/ppc440gx_i2c.h +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -32,7 +32,7 @@ #ifdef CONFIG_HARD_I2C -#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500) +#define I2C_BUS1_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500) #define I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR #define IIC_MDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF) #define IIC_SDBUF1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF) diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 51b1c7514..f6ea16f0a 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -43,7 +43,7 @@ int sbcommon_get_master(void) { ppc440_gpio_regs_t *gpio_regs; - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) { return 0; @@ -63,7 +63,7 @@ int sbcommon_secondary_present(void) { ppc440_gpio_regs_t *gpio_regs; - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES) return 0; @@ -84,7 +84,7 @@ unsigned short sbcommon_get_serial_number(void) /* Get the board serial number from eeprom */ /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Read 256 bytes in EEPROM */ i2c_read (0x50, 0, 1, buff, 0x100); @@ -218,11 +218,11 @@ phys_size_t initdram (int board_type) * * ************************************************************************/ -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("Testing SDRAM: "); @@ -340,7 +340,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -355,7 +355,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -364,12 +364,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* @@ -405,7 +405,7 @@ void board_get_enetaddr (uchar * enet) if (0 == macaddr_idx) { /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Read 256 bytes in EEPROM */ i2c_read (0x50, 0, 1, buff, 0x100); diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk index 65c1e4865..f2f94c5f6 100644 --- a/board/sandburst/karef/config.mk +++ b/board/sandburst/karef/config.mk @@ -39,5 +39,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S index b1d47a4c7..3198dfdfa 100644 --- a/board/sandburst/karef/init.S +++ b/board/sandburst/karef/init.S @@ -90,12 +90,12 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 72ce97635..8d97a9c35 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -26,6 +26,7 @@ #include <command.h> #include "karef.h" #include "karef_version.h" +#include <timestamp.h> #include <asm/processor.h> #include <asm/io.h> #include <spd_sdram.h> @@ -65,7 +66,7 @@ int board_early_init_f (void) mtsdr(sdr_pfc0, 0x00103E00); /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; @@ -93,7 +94,7 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. @@ -259,8 +260,8 @@ int checkboard (void) KAREF_FPGA_REGS_ST *karef_ps; OFEM_FPGA_REGS_ST *ofem_ps; - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; scan_id = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK) @@ -299,7 +300,7 @@ int checkboard (void) "Serial Number: %d\n", sernum); printf ("%s\n", KAREF_U_BOOT_REL_STR); - printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); if (sbcommon_get_master()) { printf("Slot 0 - Master\nSlave board"); if (sbcommon_secondary_present()) @@ -319,7 +320,7 @@ int checkboard (void) /* Fix the ack in the bme 32 */ udelay(5000); - out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); asm("eieio"); @@ -335,7 +336,7 @@ int misc_init_f (void) { /* Turn on i2c bus 1 */ puts ("I2C1: "); - i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); puts ("ready\n"); /* Turn on fans 3 & 4 */ @@ -366,7 +367,8 @@ int misc_init_r (void) setenv("ubrelver", KAREF_U_BOOT_REL_STR); memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + sprintf (envstr, "Built %s %s by %s", + U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); setenv("bldstr", envstr); saveenv(); @@ -397,8 +399,8 @@ int misc_init_r (void) } if( getenv("fakeled")) { - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK; karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK; setenv("bootdelay", "-1"); @@ -417,7 +419,7 @@ void ide_set_reset(int on) { KAREF_FPGA_REGS_ST *karef_ps; /* TODO: ide reset */ - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; if (on) { karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK; @@ -440,7 +442,7 @@ void fpga_init(void) /* Ensure we have power all around */ udelay(500); - karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE; + karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE; tmp = SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK | SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK | @@ -470,7 +472,7 @@ void fpga_init(void) SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK | SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK; - ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE; + ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE; ofem_ps->reset_ul = tmp; ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT; diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds index 216f9c64d..6223f4e8d 100644 --- a/board/sandburst/karef/u-boot.lds +++ b/board/sandburst/karef/u-boot.lds @@ -74,14 +74,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -152,6 +152,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index af7d5c08a..d00e25271 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -64,13 +64,13 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk index 91aee2fc7..565e826b8 100644 --- a/board/sandburst/metrobox/config.mk +++ b/board/sandburst/metrobox/config.mk @@ -34,5 +34,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S index e398f0008..ccdec46ee 100644 --- a/board/sandburst/metrobox/init.S +++ b/board/sandburst/metrobox/init.S @@ -88,12 +88,12 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index c38850d6c..19302dc61 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -25,6 +25,7 @@ #include <command.h> #include "metrobox.h" #include "metrobox_version.h" +#include <timestamp.h> #include <asm/processor.h> #include <asm/io.h> #include <spd_sdram.h> @@ -55,7 +56,7 @@ int board_early_init_f (void) mtsdr(sdr_pfc0, 0x00103E00); /* Setup access for LEDs, and system topology info */ - gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE; + gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS; gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS; @@ -83,7 +84,7 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | + mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. @@ -246,7 +247,7 @@ int checkboard (void) unsigned char opto_rev, opto_id; OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; opto_rev = (unsigned char)((opto_ps->revision_ul & SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK) @@ -270,7 +271,7 @@ int checkboard (void) printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum); printf ("%s\n", METROBOX_U_BOOT_REL_STR); - printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER); + printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); if (sbcommon_get_master()) { printf("Slot 0 - Master\nSlave board"); if (sbcommon_secondary_present()) @@ -286,7 +287,7 @@ int checkboard (void) /* Fix the ack in the bme 32 */ udelay(5000); - out32(CFG_BME32_BASE + 0x0000000C, 0x00000001); + out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001); asm("eieio"); @@ -302,7 +303,7 @@ int misc_init_f (void) { /* Turn on i2c bus 1 */ puts ("I2C1: "); - i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); puts ("ready\n"); /* Turn on fans */ @@ -323,7 +324,7 @@ int misc_init_r (void) unsigned char opto_rev; OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; if(NULL != getenv("secondserial")) { puts("secondserial is set, switching to second serial port\n"); @@ -335,7 +336,8 @@ int misc_init_r (void) setenv("ubrelver", METROBOX_U_BOOT_REL_STR); memset(envstr, 0, 255); - sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER); + sprintf (envstr, "Built %s %s by %s", + U_BOOT_DATE, U_BOOT_TIME, BUILDUSER); setenv("bldstr", envstr); saveenv(); @@ -387,7 +389,7 @@ int misc_init_r (void) void ide_set_reset(int on) { OPTO_FPGA_REGS_ST *opto_ps; - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; if (on) { /* assert RESET */ opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK; @@ -412,7 +414,7 @@ void fpga_init(void) /* * Take appropriate hw bits out of reset */ - opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE; + opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE; tmp = SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK | diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds index 6abf3f390..54e18e053 100644 --- a/board/sandburst/metrobox/u-boot.lds +++ b/board/sandburst/metrobox/u-boot.lds @@ -74,14 +74,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -152,6 +152,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 527c26432..a3350f279 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -64,13 +64,13 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S index 07dafb716..531dcdf4a 100644 --- a/board/sandpoint/early_init.S +++ b/board/sandpoint/early_init.S @@ -32,68 +32,68 @@ #if defined(USE_DINK32) /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */ - #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) + #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO) #else - #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) + #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) #endif .text /* Values to program into memory controller registers */ tbl: .long MCCR1, MCCR1VAL - .long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT + .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT .long MCCR3 - .long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ - (CFG_REFREC << MCCR3_REFREC_SHIFT) | \ - (CFG_RDLAT << MCCR3_RDLAT_SHIFT) + .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \ + (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \ + (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT) .long MCCR4 - .long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ - (CFG_REGISTERD_TYPE_BUFFER << 20) | \ - (((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ - ((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \ - (CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ - (CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ - ((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) + .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \ + (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \ + (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \ + ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \ + (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \ + (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \ + ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT ) .long MSAR1 - .long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMSAR1 - .long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MSAR2 - .long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMSAR2 - .long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MEAR1 - .long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMEAR1 - .long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long MEAR2 - .long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24) .long EMEAR2 - .long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ - (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ - (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ - (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) + .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \ + (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \ + (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \ + (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24) .long 0 @@ -123,7 +123,7 @@ loop: lwz r1, 4(r5) /* set bank enable bits */ lis r0, MBER@h ori r0, 0, MBER@l - li r1, CFG_BANK_ENABLE + li r1, CONFIG_SYS_BANK_ENABLE stwbrx r0, 0, r3 eieio stb r1, 0(r4) @@ -145,8 +145,8 @@ delay: bdnz delay eieio /* set up stack pointer */ - lis r1, CFG_INIT_SP_OFFSET@h - ori r1, r1, CFG_INIT_SP_OFFSET@l + lis r1, CONFIG_SYS_INIT_SP_OFFSET@h + ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l mtlr r10 blr diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c index a9f73ff0d..e366cc699 100644 --- a/board/sandpoint/flash.c +++ b/board/sandpoint/flash.c @@ -30,17 +30,17 @@ #define ROM_CS0_START 0xFF800000 #define ROM_CS1_START 0xFF000000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -140,10 +140,10 @@ flash_init(void) { unsigned long i; unsigned char j; - static const ulong flash_banks[] = CFG_FLASH_BANKS; + static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { flash_info_t * const pflinfo = &flash_info[i]; pflinfo->flash_id = FLASH_UNKNOWN; @@ -154,9 +154,9 @@ flash_init(void) /* Enable writes to Sandpoint flash */ { register unsigned char temp; - CONFIG_READ_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); + CONFIG_READ_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); temp &= ~0x20; /* clear BIOSWP bit */ - CONFIG_WRITE_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); + CONFIG_WRITE_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp); } for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) @@ -223,17 +223,17 @@ flash_init(void) } /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif @@ -612,7 +612,7 @@ flash_erase(flash_info_t *info, int s_first, int s_last) addr = (FLASH_WORD_SIZE *)(info->start[0] + ( (info->start[l_sect] - info->start[0]) << sh8b)); while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -751,7 +751,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) != (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c index 7429647b8..bb01d73bd 100644 --- a/board/sandpoint/sandpoint.c +++ b/board/sandpoint/sandpoint.c @@ -24,6 +24,7 @@ #include <common.h> #include <mpc824x.h> #include <pci.h> +#include <netdev.h> int checkboard (void) { @@ -57,7 +58,7 @@ phys_size_t initdram (int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -99,3 +100,8 @@ void pci_init_board(void) { pci_mpc824x_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c index 0c669e4d7..abb093558 100644 --- a/board/sbc2410x/flash.c +++ b/board/sbc2410x/flash.c @@ -29,7 +29,7 @@ ulong myflush (void); #define FLASH_BANK_SIZE PHYS_FLASH_SIZE #define MAIN_SECT_SIZE 0x10000 /* 64 KB */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x000000F0 #define CMD_UNLOCK1 0x000000AA @@ -39,8 +39,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define CMD_PROGRAM 0x000000A0 #define CMD_UNLOCK_BYPASS 0x00000020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) #define BIT_ERASE_DONE 0x00000080 #define BIT_RDY_MASK 0x00000080 @@ -59,7 +59,7 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = @@ -73,8 +73,8 @@ ulong flash_init (void) #error "Unknown flash configured" #endif flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -109,13 +109,13 @@ ulong flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -234,7 +234,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* check timeout */ if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip = TMO; break; @@ -330,7 +330,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { chip = ERR | TMO; break; } diff --git a/board/sbc2410x/u-boot.lds b/board/sbc2410x/u-boot.lds index 3b7977672..d0666ac73 100644 --- a/board/sbc2410x/u-boot.lds +++ b/board/sbc2410x/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c index d21d885fa..e5863d6ce 100644 --- a/board/sbc405/strataflash.c +++ b/board/sbc405/strataflash.c @@ -103,7 +103,7 @@ typedef union { #define NUM_ERASE_REGIONS 4 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- @@ -120,7 +120,7 @@ static int flash_detect_cfi(flash_info_t * info); static ulong flash_get_size (ulong base, int banknum); static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); #endif /*----------------------------------------------------------------------- @@ -180,14 +180,14 @@ unsigned long flash_init (void) * */ - address = CFG_FLASH_BASE; + address = CONFIG_SYS_FLASH_BASE; size = 0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; + address += CONFIG_SYS_FLASH_INCREMENT; if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, flash_info[0].size, flash_info[i].size<<20); @@ -196,14 +196,14 @@ unsigned long flash_init (void) #if 0 /* test-only */ /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) + for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++) (void)flash_real_protect(&flash_info[0], i, 1); #endif #else /* monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - - CFG_MONITOR_LEN, + - CONFIG_SYS_MONITOR_LEN, - 1, &flash_info[1]); #endif @@ -277,7 +277,7 @@ void flash_print_info (flash_info_t *info) printf (" Sector Start Addresses:"); for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO +#ifdef CONFIG_SYS_FLASH_EMPTY_INFO int k; int size; int erased; @@ -357,7 +357,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp = cp; } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE while(cnt >= info->portwidth) { i = info->buffer_size > cnt? cnt: info->buffer_size; if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) @@ -378,7 +378,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) wp += info->portwidth; cnt -= info->portwidth; } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ +#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ if (cnt == 0) { return (0); } @@ -720,7 +720,7 @@ static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) return flash_full_status_check(info, 0, info->write_tout, "write"); } -#ifdef CFG_FLASH_USE_BUFFER_WRITE +#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* loop through the sectors from the highest address * when the passed address is greater or equal to the sector address @@ -790,4 +790,4 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, in flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */ diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds index 7b1c6b211..d6f34c992 100644 --- a/board/sbc405/u-boot.lds +++ b/board/sbc405/u-boot.lds @@ -66,14 +66,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sbc8240/flash.c b/board/sbc8240/flash.c index dec615683..a095753a4 100644 --- a/board/sbc8240/flash.c +++ b/board/sbc8240/flash.c @@ -32,10 +32,10 @@ #include <mpc824x.h> #include <asm/processor.h> -#if CFG_MAX_FLASH_BANKS != 1 -#error "CFG_MAX_FLASH_BANKS must be 1" +#if CONFIG_SYS_MAX_FLASH_BANKS != 1 +#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1" #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -399,7 +399,7 @@ int wait_for_DQ7 (flash_info_t * info, int sect) last = start; while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return -1; } @@ -628,7 +628,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c index 175720d90..01abe26a4 100644 --- a/board/sbc8240/sbc8240.c +++ b/board/sbc8240/sbc8240.c @@ -28,6 +28,7 @@ #include <mpc824x.h> #include <asm/processor.h> #include <pci.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,7 +53,7 @@ phys_size_t initdram(int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -96,10 +97,15 @@ void pci_init_board(void) /* ------------------------------------------------------------------------- */ int misc_init_r (void) { -#ifdef CFG_LED_BASE - *((unsigned char *) (CFG_LED_BASE)) = 0xFF; -#endif /* CFG_LED_BASE */ +#ifdef CONFIG_SYS_LED_BASE + *((unsigned char *) (CONFIG_SYS_LED_BASE)) = 0xFF; +#endif /* CONFIG_SYS_LED_BASE */ return (0); } #endif /* CONFIG_MISC_INIT_R */ + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/sbc8260/flash.c b/board/sbc8260/flash.c index 9a8b95225..645c67f43 100644 --- a/board/sbc8260/flash.c +++ b/board/sbc8260/flash.c @@ -31,7 +31,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- * Functions @@ -49,35 +49,35 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* for now, only support the 4 MB Flash SIMM */ - size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]); /* * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif - return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024); + return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024); } /*----------------------------------------------------------------------- @@ -258,7 +258,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -381,7 +381,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c index 5781f6281..f5f23be27 100644 --- a/board/sbc8260/sbc8260.c +++ b/board/sbc8260/sbc8260.c @@ -210,10 +210,10 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; - volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8); - ulong psdmr = CFG_PSDMR; + volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8); + ulong psdmr = CONFIG_SYS_PSDMR; int i; /* @@ -233,11 +233,11 @@ phys_size_t initdram (int board_type) * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; *ramaddr = c; @@ -253,15 +253,15 @@ phys_size_t initdram (int board_type) *ramaddr = c; /* return total ram size */ - return (CFG_SDRAM0_SIZE * 1024 * 1024); + return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024); } #ifdef CONFIG_MISC_INIT_R /* ------------------------------------------------------------------------- */ int misc_init_r (void) { -#ifdef CFG_LED_BASE - uchar ds = *(unsigned char *) (CFG_LED_BASE + 1); +#ifdef CONFIG_SYS_LED_BASE + uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1); uchar ss; uchar tmp[64]; int res; @@ -280,10 +280,10 @@ int misc_init_r (void) tmp[17] = '\0'; setenv ("ethaddr", tmp); /* set the led to show the address */ - *((unsigned char *) (CFG_LED_BASE + 1)) = ds; + *((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds; } } -#endif /* CFG_LED_BASE */ +#endif /* CONFIG_SYS_LED_BASE */ return (0); } #endif /* CONFIG_MISC_INIT_R */ diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c index 527f7e434..9022c55d5 100644 --- a/board/sbc8349/pci.c +++ b/board/sbc8349/pci.c @@ -40,8 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_PCI /* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc8349emds_config_table[] = { @@ -90,7 +90,7 @@ pci_init_board(void) u32 dev; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -132,10 +132,10 @@ pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; /* @@ -143,18 +143,18 @@ pci_init_board(void) */ /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* @@ -173,23 +173,23 @@ pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI1_MMIO_BASE, - CFG_PCI1_MMIO_PHYS, - CFG_PCI1_MMIO_SIZE, + CONFIG_SYS_PCI1_MMIO_BASE, + CONFIG_SYS_PCI1_MMIO_PHYS, + CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -202,8 +202,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR+0x8300), - (CFG_IMMR+0x8304)); + (CONFIG_SYS_IMMR+0x8300), + (CONFIG_SYS_IMMR+0x8304)); pci_register_hose(hose); @@ -239,18 +239,18 @@ pci_init_board(void) */ /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI2 IO space */ - pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); /* @@ -269,23 +269,23 @@ pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, - CFG_PCI2_MMIO_BASE, - CFG_PCI2_MMIO_PHYS, - CFG_PCI2_MMIO_SIZE, + CONFIG_SYS_PCI2_MMIO_BASE, + CONFIG_SYS_PCI2_MMIO_PHYS, + CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -298,8 +298,8 @@ pci_init_board(void) hose->region_count = 4; pci_setup_indirect(hose, - (CFG_IMMR+0x8380), - (CFG_IMMR+0x8384)); + (CONFIG_SYS_IMMR+0x8380), + (CONFIG_SYS_IMMR+0x8384)); pci_register_hose(hose); diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index 4a44fda31..e01cb037f 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -54,14 +54,14 @@ int board_early_init_f (void) phys_size_t initdram (int board_type) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else @@ -88,12 +88,12 @@ phys_size_t initdram (int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size>>1, ddr_size_log2++) { @@ -101,22 +101,22 @@ int fixed_sdram(void) return -1; } } - im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) +#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currently any ddr size other than 256 is not supported #endif im->ddr.csbnds[2].csbnds = 0x0000000f; - im->ddr.cs_config[2] = CFG_DDR_CONFIG; + im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG; /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; im->ddr.cs_config[1] = 0; im->ddr.cs_config[3] = 0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; im->ddr.sdram_cfg = SDRAM_CFG_SREN @@ -128,16 +128,16 @@ int fixed_sdram(void) /* for 32-bit mode burst length is 8 */ im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE); #endif - im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; udelay(200); /* enable DDR controller */ im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; return msize; } -#endif/*!CFG_SPD_EEPROM*/ +#endif/*!CONFIG_SYS_SPD_EEPROM*/ int checkboard (void) @@ -149,44 +149,44 @@ int checkboard (void) /* * if board is fitted with SDRAM */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#if defined(CONFIG_SYS_BR2_PRELIM) \ + && defined(CONFIG_SYS_OR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWAR2_PRELIM) /* * Initialize SDRAM memory on the Local Bus. */ void sdram_init(void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile lbus83xx_t *lbc= &immap->lbus; - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; + volatile fsl_lbus_t *lbc = &immap->lbus; + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; puts("\n SDRAM on Local Bus: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ /* setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ - lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */ asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */ asm("sync"); /*1 times*/ *sdram_addr = 0xff; @@ -214,12 +214,12 @@ void sdram_init(void) udelay(100); /* 0x58636733; mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *sdram_addr = 0xff; udelay(100); - lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */ asm("sync"); *sdram_addr = 0xff; udelay(100); diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index f07d746c2..ab64fa88f 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index ab54260b0..e8c7ae2a2 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -46,12 +46,12 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index f31d7d647..8c073cb4b 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -36,10 +36,6 @@ #include <libfdt.h> #include <fdt_support.h> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - DECLARE_GLOBAL_DATA_PTR; void local_bus_init(void); @@ -53,9 +49,9 @@ int board_early_init_f (void) int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); - volatile u_char *rev= (void *)CFG_BD_REV; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", (*rev) >> 4); @@ -66,13 +62,6 @@ int checkboard (void) local_bus_init (); /* - * Fix CPU2 errata: A core hang possible while executing a - * msync instruction and a snoopable transaction from an I/O - * master tagged to make quick forward progress is present. - */ - ecm->eebpcr |= (1 << 16); - - /* * Hack TSEC 3 and 4 IO voltages. */ gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ @@ -98,7 +87,7 @@ initdram(int board_type) * Override DLL = 1, Course Adj = 1, Tap Select = 0 */ - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); gur->ddrdllcr = 0x81000000; asm("sync;isync;msync"); @@ -114,12 +103,6 @@ initdram(int board_type) dram_size = fixed_sdram (); #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif /* * SDRAM Initialization */ @@ -135,8 +118,8 @@ initdram(int board_type) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint clkdiv; uint lbc_hz; @@ -169,44 +152,44 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) +#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) uint idx; - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE; uint lsdmr_common; puts(" SDRAM: "); - print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); + print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); /* * Setup SDRAM Base and Option Registers */ - lbc->or3 = CFG_OR3_PRELIM; + lbc->or3 = CONFIG_SYS_OR3_PRELIM; asm("msync"); - lbc->br3 = CFG_BR3_PRELIM; + lbc->br3 = CONFIG_SYS_BR3_PRELIM; asm("msync"); - lbc->lbcr = CFG_LBC_LBCR; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync"); - lbc->lsrt = CFG_LBC_LSRT; - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("msync"); /* * MPC8548 uses "new" 15-16 style addressing. */ - lsdmr_common = CFG_LBC_LSDMR_COMMON; - lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; + lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; + lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -216,7 +199,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -226,7 +209,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -235,7 +218,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; + lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -244,17 +227,17 @@ sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); + CONFIG_SYS_MEMTEST_START, + CONFIG_SYS_MEMTEST_END); printf("DRAM test phase 1:\n"); for (p = pstart; p < pend; p++) @@ -290,9 +273,9 @@ testdram(void) ************************************************************************/ long int fixed_sdram (void) { - #define CFG_DDR_CONTROL 0xc300c000 + #define CONFIG_SYS_DDR_CONTROL 0xc300c000 - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); ddr->cs0_bnds = 0x0000007f; ddr->cs1_bnds = 0x008000ff; @@ -319,12 +302,12 @@ long int fixed_sdram (void) #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif @@ -364,17 +347,20 @@ static struct pci_controller pcie1_hose; int first_free_busno=0; +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCI1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_config_table *table; + struct pci_region *r = hose->regions; uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ @@ -396,27 +382,22 @@ pci_init_board(void) /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; /* relocate config table pointers */ hose->config_table = \ @@ -431,7 +412,7 @@ pci_init_board(void) first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); @@ -466,10 +447,10 @@ pci_init_board(void) #ifdef CONFIG_PCIE1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; @@ -485,27 +466,27 @@ pci_init_board(void) printf ("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI_MEMORY_BUS, + CONFIG_SYS_PCI_MEMORY_PHYS, + CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -531,41 +512,17 @@ int last_stage_init(void) } #if defined(CONFIG_OF_BOARD_SETUP) -void -ft_pci_setup(void *blob, bd_t *bd) -{ - int node, tmp[2]; +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI1 - const char *path; - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCIE1 - const char *path; - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } -#endif - } -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); #endif } #endif diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 6314005ca..18d11f6dc 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff800000 16M TLB for 8MB FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -71,7 +71,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0x0 256M DDR SDRAM */ #if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 3, BOOKE_PAGESZ_256M, 1), #endif @@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), @@ -89,7 +89,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -100,7 +100,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf8300000 1M Board revision * 0xf8b00000 1M EEPROM */ - SET_TLB_ENTRY(1, CFG_EPLD_BASE, CFG_EPLD_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), }; diff --git a/board/sbc8548/u-boot.lds b/board/sbc8548/u-boot.lds index eba7e8a9d..70d11f265 100644 --- a/board/sbc8548/u-boot.lds +++ b/board/sbc8548/u-boot.lds @@ -140,6 +140,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c index 45372f427..7850794d6 100644 --- a/board/sbc8560/ddr.c +++ b/board/sbc8560/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c index 10dedb481..4e6baed2f 100644 --- a/board/sbc8560/law.c +++ b/board/sbc8560/law.c @@ -51,10 +51,10 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index dc661702c..3d4008b00 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -197,7 +197,7 @@ const iop_conf_t iop_conf_tab[4][32] = { int board_early_init_f (void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -207,7 +207,7 @@ int board_early_init_f (void) void reset_phy (void) { #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */ - volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR; + volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR; #endif /* reset Giga bit Ethernet port if needed here */ @@ -238,6 +238,7 @@ void reset_phy (void) int checkboard (void) { sys_info_t sysinfo; + char buf[32]; get_sys_info (&sysinfo); @@ -246,16 +247,17 @@ int checkboard (void) #else printf ("Board: Wind River SBC8540 Board\n"); #endif - printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); - printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); - printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); - if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ - || (CFG_LBC_LCRR & 0x0f) == 8) { - printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f)); + printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor)); + printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus)); + printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2)); + if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ + || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) { + printf ("\tLBC: %s MHz\n", + strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f))); } else { printf("\tLBC: unknown\n"); } - printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus)); printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n"); return (0); } @@ -267,13 +269,13 @@ phys_size_t initdram (int board_type) #if 0 #if !defined(CONFIG_RAM_AS_FLASH) - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; #endif #endif /* 0 */ #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_DDR_DLL) uint temp_ddrdll = 0; @@ -295,39 +297,39 @@ phys_size_t initdram (int board_type) #if 0 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ get_sys_info(&sysinfo); - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000; + /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ + if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { + lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; } else { #if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */ lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */ #endif - lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff; + lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; udelay(200); temp_lbcdll = gur->lbcdllcr; gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; asm("sync;isync;msync"); } - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */ - lbc->br2 = CFG_BR2_PRELIM; - lbc->lbcr = CFG_LBC_LBCR; - lbc->lsdmr = CFG_LBC_LSDMR_1; + lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */ + lbc->br2 = CONFIG_SYS_BR2_PRELIM; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_3; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CFG_LBC_LSDMR_5; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; asm("sync"); - lbc->lsrt = CFG_LBC_LSRT; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); - lbc->mrtpr = CFG_LBC_MRTPR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); #endif #endif @@ -338,7 +340,7 @@ phys_size_t initdram (int board_type) * enable errors */ uint *p = 0; uint i = 0; - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); dma_init(); for (*p = 0; p < (uint *)(8 * 1024); p++) { if (((unsigned int)p & 0x1f) == 0) { dcbz(p); } @@ -381,11 +383,11 @@ phys_size_t initdram (int board_type) } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); @@ -422,12 +424,12 @@ int testdram (void) long int fixed_sdram (void) { -#define CFG_DDR_CONTROL 0xc2000000 +#define CONFIG_SYS_DDR_CONTROL 0xc2000000 - #ifndef CFG_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); + #ifndef CONFIG_SYS_RAMBOOT + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); -#if (CFG_SDRAM_SIZE == 512) +#if (CONFIG_SYS_SDRAM_SIZE == 512) ddr->cs0_bnds = 0x0000000f; #else ddr->cs0_bnds = 0x00000007; @@ -452,14 +454,14 @@ long int fixed_sdram (void) udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CFG_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; #endif asm("sync; isync; msync"); udelay(500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c index d07339960..fe0ac763a 100644 --- a/board/sbc8560/tlb.c +++ b/board/sbc8560/tlb.c @@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB for CCSRBAR (IMMR) */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), @@ -44,20 +44,20 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 3, BOOKE_PAGESZ_256M, 1), #if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 4, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_256M, 1), #endif - SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_16K, 1), - SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), }; diff --git a/board/sbc8560/u-boot.lds b/board/sbc8560/u-boot.lds index 237a3b60b..759ee82c9 100644 --- a/board/sbc8560/u-boot.lds +++ b/board/sbc8560/u-boot.lds @@ -146,6 +146,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index 5163abf05..23497f982 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -45,7 +46,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c index 801c5b75f..de47fcd63 100644 --- a/board/sbc8641d/law.c +++ b/board/sbc8641d/law.c @@ -44,15 +44,15 @@ struct law_entry law_table[] = { - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), - SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), + SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), - SET_LAW(CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 62b48c836..1471e581e 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -38,10 +38,6 @@ #include <libfdt.h> #include <fdt_support.h> -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc (unsigned int dram_size); -#endif - long int fixed_sdram (void); int board_early_init_f (void) @@ -66,27 +62,20 @@ phys_size_t initdram (int board_type) dram_size = fixed_sdram (); #endif -#if defined(CFG_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) puts (" DDR: "); return dram_size; #endif -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc (dram_size); -#endif - puts (" DDR: "); return dram_size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; puts ("SDRAM test phase 1:\n"); @@ -122,72 +111,72 @@ int testdram (void) */ long int fixed_sdram (void) { -#if !defined(CFG_RAMBOOT) - volatile immap_t *immap = (immap_t *) CFG_IMMR; +#if !defined(CONFIG_SYS_RAMBOOT) + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile ccsr_ddr_t *ddr = &immap->im_ddr1; - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs1_bnds = CFG_DDR_CS1_BNDS; - ddr->cs2_bnds = CFG_DDR_CS2_BNDS; - ddr->cs3_bnds = CFG_DDR_CS3_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->cs1_config = CFG_DDR_CS1_CONFIG; - ddr->cs2_config = CFG_DDR_CS2_CONFIG; - ddr->cs3_config = CFG_DDR_CS3_CONFIG; - ddr->timing_cfg_3 = CFG_DDR_TIMING_3; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_cfg_1 = CFG_DDR_CFG_1A; - ddr->sdram_cfg_2 = CFG_DDR_CFG_2; - ddr->sdram_mode_1 = CFG_DDR_MODE_1; - ddr->sdram_mode_2 = CFG_DDR_MODE_2; - ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL; - ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_data_init = CFG_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; + ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; + ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; + ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; + ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; + ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; + ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; + ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; asm ("sync;isync"); udelay (500); - ddr->sdram_cfg_1 = CFG_DDR_CFG_1B; + ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B; asm ("sync; isync"); udelay (500); ddr = &immap->im_ddr2; - ddr->cs0_bnds = CFG_DDR2_CS0_BNDS; - ddr->cs1_bnds = CFG_DDR2_CS1_BNDS; - ddr->cs2_bnds = CFG_DDR2_CS2_BNDS; - ddr->cs3_bnds = CFG_DDR2_CS3_BNDS; - ddr->cs0_config = CFG_DDR2_CS0_CONFIG; - ddr->cs1_config = CFG_DDR2_CS1_CONFIG; - ddr->cs2_config = CFG_DDR2_CS2_CONFIG; - ddr->cs3_config = CFG_DDR2_CS3_CONFIG; - ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH; - ddr->timing_cfg_0 = CFG_DDR2_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR2_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR2_TIMING_2; - ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A; - ddr->sdram_cfg_2 = CFG_DDR2_CFG_2; - ddr->sdram_mode_1 = CFG_DDR2_MODE_1; - ddr->sdram_mode_2 = CFG_DDR2_MODE_2; - ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL; - ddr->sdram_interval = CFG_DDR2_INTERVAL; - ddr->sdram_data_init = CFG_DDR2_DATA_INIT; - ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL; + ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS; + ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS; + ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS; + ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG; + ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG; + ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG; + ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG; + ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH; + ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; + ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; + ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1; + ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; + ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; + ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; + ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; asm ("sync;isync"); udelay (500); - ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B; + ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B; asm ("sync; isync"); udelay (500); #endif - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ @@ -220,9 +209,12 @@ static struct pci_controller pci2_hose; int first_free_busno = 0; +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + void pci_init_board(void) { - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) @@ -230,9 +222,9 @@ void pci_init_board(void) #ifdef CONFIG_PCI1 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; #ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) >> MPC8641_PORBMSR_HA_SHIFT; @@ -251,27 +243,23 @@ void pci_init_board(void) debug("\n"); /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -292,33 +280,29 @@ void pci_init_board(void) #ifdef CONFIG_PCI2 { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; struct pci_controller *hose = &pci2_hose; + struct pci_region *r = hose->regions; /* inbound */ - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region(hose->regions + 1, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI2_MEM_BASE, + CONFIG_SYS_PCI2_MEM_PHYS, + CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, + pci_set_region(r++, + CONFIG_SYS_PCI2_IO_BASE, + CONFIG_SYS_PCI2_IO_PHYS, + CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); @@ -337,33 +321,19 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); -void -ft_board_setup (void *blob, bd_t *bd) +void ft_board_setup (void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - ft_cpu_setup(blob, bd); - node = fdt_path_offset(blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #ifdef CONFIG_PCI1 - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); #endif #ifdef CONFIG_PCI2 - path = fdt_getprop(blob, node, "pci1", NULL); - if (path) { - tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno; - do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); - } + ft_fsl_pci_setup(blob, "pci1", &pci2_hose); #endif - } } #endif diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds index a9e9d80a1..adfa816b4 100644 --- a/board/sbc8641d/u-boot.lds +++ b/board/sbc8641d/u-boot.lds @@ -128,6 +128,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 3d1a6542d..6c82fe7e9 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -37,6 +37,7 @@ #include <pci.h> #include <i2c.h> #include <malloc.h> +#include <netdev.h> #undef writel #undef writeb @@ -779,3 +780,8 @@ void pci_init_board(void) hose.config_table = pci_solidcard3_config_table; pci_405gp_init(&hose); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c index 45eff28c0..62b40f167 100644 --- a/board/sc3/sc3nand.c +++ b/board/sc3/sc3nand.c @@ -77,7 +77,7 @@ int board_nand_init(struct nand_chip *nand) { nand->ecc.mode = NAND_ECC_SOFT; - sc3_io_base = (void *) CFG_NAND_BASE; + sc3_io_base = (void *) CONFIG_SYS_NAND_BASE; /* Set address of NAND IO lines (Using Linear Data Access Region) */ nand->IO_ADDR_R = (void __iomem *) sc3_io_base; nand->IO_ADDR_W = (void __iomem *) sc3_io_base; diff --git a/board/sc3/u-boot.lds b/board/sc3/u-boot.lds index 27cc0b928..d729f2e0e 100644 --- a/board/sc3/u-boot.lds +++ b/board/sc3/u-boot.lds @@ -74,7 +74,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -143,6 +143,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c index d52a847c7..dcb8c57e8 100644 --- a/board/sc520_cdp/flash.c +++ b/board/sc520_cdp/flash.c @@ -222,7 +222,7 @@ ulong flash_init(void) ulong flashbase = 0; int sectsize = 0; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: flashbase = SC520_FLASH_BANK0_BASE; @@ -276,10 +276,10 @@ ulong flash_init(void) i386boot_start, i386boot_end, &flash_info[0]); -#ifdef CFG_ENV_ADDR +#ifdef CONFIG_ENV_ADDR flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return size; @@ -370,7 +370,7 @@ static u32 _amd_erase_flash(u32 addr, u32 sector) while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) { elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) { *(volatile u32*)(addr) = 0xf0f0f0f0; return 1; } @@ -493,7 +493,7 @@ static int _amd_write_word(unsigned start, unsigned dest, unsigned data) /* data polling for D7 */ while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) { elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) { addr2[0] = 0xf0f0f0f0; return 1; } diff --git a/board/sc520_cdp/flash_old.c b/board/sc520_cdp/flash_old.c index 3c0f6d6a6..9491ca296 100644 --- a/board/sc520_cdp/flash_old.c +++ b/board/sc520_cdp/flash_old.c @@ -89,7 +89,7 @@ ulong flash_init(void) flash_info[i].sector_count = 0; sectsize=0; } - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: flashbase = SC520_FLASH_BANK0_BASE; @@ -119,10 +119,10 @@ ulong flash_init(void) i386boot_end-SC520_FLASH_BANK0_BASE, &flash_info[0]); -#ifdef CFG_ENV_ADDR +#ifdef CONFIG_ENV_ADDR flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return size; @@ -240,7 +240,7 @@ int flash_erase(flash_info_t *info, int s_first, int s_last) result = readl(addr); /* check timeout */ - if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer(0) > CONFIG_SYS_FLASH_ERASE_TOUT) { writel(CMD_READ_ARRAY, addr + 1); chip1 = TMO; break; @@ -342,7 +342,7 @@ volatile static int write_word(flash_info_t *info, ulong dest, ulong data) result = readl(addr); /* check timeout */ - if (get_timer(0) > CFG_FLASH_ERASE_TOUT) { + if (get_timer(0) > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; } diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index 8050aa6fe..779f957d6 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -29,6 +29,7 @@ #include <asm/ic/sc520.h> #include <asm/ic/ali512x.h> #include <spi.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -86,7 +87,7 @@ static void irq_init(void) write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1); /* Set ICE Debug Serielport INT to IRQ1 */ write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13); /* Set FP error INT to IRQ13 */ - if (CFG_USE_SIO_UART) { + if (CONFIG_SYS_USE_SIO_UART) { write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */ write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */ write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3); /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */ @@ -113,7 +114,7 @@ static void irq_init(void) } - +#ifdef CONFIG_PCI /* PCI stuff */ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { @@ -121,14 +122,14 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) * when we need one (a board with more pci interrupt pins * would use a larger table */ static int irq_list[] = { - CFG_FIRST_PCI_IRQ, - CFG_SECOND_PCI_IRQ, - CFG_THIRD_PCI_IRQ, - CFG_FORTH_PCI_IRQ + CONFIG_SYS_FIRST_PCI_IRQ, + CONFIG_SYS_SECOND_PCI_IRQ, + CONFIG_SYS_THIRD_PCI_IRQ, + CONFIG_SYS_FORTH_PCI_IRQ }; static int next_irq_index=0; - char tmp_pin; + uchar tmp_pin; int pin; pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); @@ -192,7 +193,7 @@ void pci_init_board(void) { pci_sc520_init(&sc520_cdp_hose); } - +#endif static void silence_uart(int port) { @@ -278,7 +279,7 @@ static void bus_init(void) asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */ - if (CFG_USE_SIO_UART) { + if (CONFIG_SYS_USE_SIO_UART) { write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS); setup_ali_sio(1); } else { @@ -562,12 +563,12 @@ void spi_eeprom_probe(int x) { } -int spi_eeprom_read(int x, int offset, char *buffer, int len) +int spi_eeprom_read(int x, int offset, uchar *buffer, int len) { return 0; } -int spi_eeprom_write(int x, int offset, char *buffer, int len) +int spi_eeprom_write(int x, int offset, uchar *buffer, int len) { return 0; } @@ -629,3 +630,8 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) #endif return res; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S index 6ac5a5de9..3a8a03f50 100644 --- a/board/sc520_cdp/sc520_cdp_asm.S +++ b/board/sc520_cdp/sc520_cdp_asm.S @@ -76,8 +76,8 @@ done: movb $0x88, %al jmp *%ebp /* return to caller */ -.globl show_boot_progress -show_boot_progress: +.globl show_boot_progress_asm +show_boot_progress_asm: out %al, $0x80 xchg %al, %ah movw $0x680, %dx diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds index 96093263e..719ecbaa1 100644 --- a/board/sc520_cdp/u-boot.lds +++ b/board/sc520_cdp/u-boot.lds @@ -45,7 +45,7 @@ SECTIONS . = ALIGN(4); _i386boot_bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _i386boot_bss_size = SIZEOF(.bss); diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c index 0b4bf6889..d702046f9 100644 --- a/board/sc520_spunk/flash.c +++ b/board/sc520_spunk/flash.c @@ -228,7 +228,7 @@ ulong flash_init(void) ulong flashbase = 0; int sectsize = 0; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); switch (i) { case 0: flashbase = SC520_FLASH_BANK0_BASE; @@ -323,10 +323,10 @@ ulong flash_init(void) i386boot_start, i386boot_end, &flash_info[0]); -#ifdef CFG_ENV_ADDR +#ifdef CONFIG_ENV_ADDR flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return size; @@ -419,7 +419,7 @@ static u32 _amd_erase_flash(u32 addr, u32 sector) while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) { *(volatile u16*)(addr) = 0x00f0; return 1; } @@ -467,7 +467,7 @@ static u32 _intel_erase_flash(u32 addr, u32 sector) elapsed = 0; while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) { elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) { + if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) { *(volatile u16*)(addr + sector) = 0x00B0; /* suspend erase */ *(volatile u16*)(addr + sector) = 0x00FF; /* reset to read mode */ return 1; @@ -602,7 +602,7 @@ static int _amd_write_word(unsigned start, unsigned dest, u16 data) /* data polling for D7 */ while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) { elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) { addr2[i] = 0x00f0; return 1; } @@ -639,7 +639,7 @@ static int _intel_write_word(unsigned start, unsigned dest, unsigned data) /* data polling for D7 */ while ((*(volatile u16*)dest & 0x0080) != 0x0080) { elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); - if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) { + if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) { *(volatile u16*)dest = 0x00ff; return 1; } diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c index 038d47995..d3bd86930 100644 --- a/board/sc520_spunk/sc520_spunk.c +++ b/board/sc520_spunk/sc520_spunk.c @@ -25,6 +25,7 @@ #include <common.h> #include <pci.h> #include <ssi.h> +#include <netdev.h> #include <asm/io.h> #include <asm/pci.h> #include <asm/ic/sc520.h> @@ -104,10 +105,10 @@ static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev * when we need one (a board with more pci interrupt pins * would use a larger table */ static int irq_list[] = { - CFG_FIRST_PCI_IRQ, - CFG_SECOND_PCI_IRQ, - CFG_THIRD_PCI_IRQ, - CFG_FORTH_PCI_IRQ + CONFIG_SYS_FIRST_PCI_IRQ, + CONFIG_SYS_SECOND_PCI_IRQ, + CONFIG_SYS_THIRD_PCI_IRQ, + CONFIG_SYS_FORTH_PCI_IRQ }; static int next_irq_index=0; @@ -676,3 +677,8 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) spi_eeprom_write(1, offset, buffer, len) : mw_eeprom_write(1, offset, buffer, len); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S index 3430b6adb..eda7e9110 100644 --- a/board/sc520_spunk/sc520_spunk_asm.S +++ b/board/sc520_spunk/sc520_spunk_asm.S @@ -73,8 +73,8 @@ done: movl $0xfffefc32,%edx jmp *%ebp /* return to caller */ -.globl show_boot_progress -show_boot_progress: +.globl show_boot_progress_asm +show_boot_progress_asm: movl $0xfffefc32,%edx xorw $0xffff, %ax movw %ax,(%edx) diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds index 33480d328..4d6603cb5 100644 --- a/board/sc520_spunk/u-boot.lds +++ b/board/sc520_spunk/u-boot.lds @@ -46,7 +46,7 @@ SECTIONS . = ALIGN(4); _i386boot_bss_start = ABSOLUTE(.); - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _i386boot_bss_size = SIZEOF(.bss); diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c index 304190cbf..c6f94aebb 100644 --- a/board/scb9328/flash.c +++ b/board/scb9328/flash.c @@ -82,7 +82,7 @@ #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static FLASH_BUS_RET flash_status_reg (void) { @@ -109,7 +109,7 @@ static int flash_ready (ulong timeout) return ok; } -#if ( CFG_MAX_FLASH_BANKS != 1 ) +#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 ) # error "SCB9328 platform has only one flash bank!" #endif @@ -120,11 +120,11 @@ ulong flash_init (void) unsigned long address = SCB9328_FLASH_BASE; flash_info[0].size = SCB9328_FLASH_BANK_SIZE; - flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; flash_info[0].flash_id = INTEL_MANUFACT; - memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) { flash_info[0].start[i] = address; #ifdef SCB9328_FLASH_UNLOCK /* Some devices are hw locked after start. */ @@ -137,13 +137,13 @@ ulong flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return SCB9328_FLASH_BANK_SIZE; } @@ -209,7 +209,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); - if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) { *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); printf ("ok.\n"); } else { @@ -257,7 +257,7 @@ static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); *address = data; - if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) { *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); rc = ERR_TIMOUT; printf ("timeout! Aborting...\n"); diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S index ba3b6d241..8e6a49e32 100644 --- a/board/scb9328/lowlevel_init.S +++ b/board/scb9328/lowlevel_init.S @@ -29,13 +29,13 @@ lowlevel_init: /* Change PERCLK1DIV to 14 ie 14+1 */ ldr r0, =PCDR - ldr r1, =CFG_PCDR_VAL + ldr r1, =CONFIG_SYS_PCDR_VAL str r1, [r0] /* set MCU PLL Control Register 0 */ ldr r0, =MPCTL0 - ldr r1, =CFG_MPCTL0_VAL + ldr r1, =CONFIG_SYS_MPCTL0_VAL str r1, [r0] /* set mpll restart bit */ @@ -57,7 +57,7 @@ lowlevel_init: /* set System PLL Control Register 0 */ ldr r0, =SPCTL0 - ldr r1, =CFG_SPCTL0_VAL + ldr r1, =CONFIG_SYS_SPCTL0_VAL str r1, [r0] /* set spll restart bit */ @@ -77,7 +77,7 @@ lowlevel_init: bne 1b ldr r0, =CSCR - ldr r1, =CFG_CSCR_VAL + ldr r1, =CONFIG_SYS_CSCR_VAL str r1, [r0] /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon @@ -102,65 +102,65 @@ lowlevel_init: MCR p15,0,r0,c1,c0,0 ldr r0, =GPR(0) - ldr r1, =CFG_GPR_A_VAL + ldr r1, =CONFIG_SYS_GPR_A_VAL str r1, [r0] ldr r0, =GIUS(0) - ldr r1, =CFG_GIUS_A_VAL + ldr r1, =CONFIG_SYS_GIUS_A_VAL str r1, [r0] /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ ldr r0, =FMCR - ldr r1, =CFG_FMCR_VAL + ldr r1, =CONFIG_SYS_FMCR_VAL str r1, [r0] ldr r0, =CS0U - ldr r1, =CFG_CS0U_VAL + ldr r1, =CONFIG_SYS_CS0U_VAL str r1, [r0] ldr r0, =CS0L - ldr r1, =CFG_CS0L_VAL + ldr r1, =CONFIG_SYS_CS0L_VAL str r1, [r0] ldr r0, =CS1U - ldr r1, =CFG_CS1U_VAL + ldr r1, =CONFIG_SYS_CS1U_VAL str r1, [r0] ldr r0, =CS1L - ldr r1, =CFG_CS1L_VAL + ldr r1, =CONFIG_SYS_CS1L_VAL str r1, [r0] ldr r0, =CS2U - ldr r1, =CFG_CS2U_VAL + ldr r1, =CONFIG_SYS_CS2U_VAL str r1, [r0] ldr r0, =CS2L - ldr r1, =CFG_CS2L_VAL + ldr r1, =CONFIG_SYS_CS2L_VAL str r1, [r0] ldr r0, =CS3U - ldr r1, =CFG_CS3U_VAL + ldr r1, =CONFIG_SYS_CS3U_VAL str r1, [r0] ldr r0, =CS3L - ldr r1, =CFG_CS3L_VAL + ldr r1, =CONFIG_SYS_CS3L_VAL str r1, [r0] ldr r0, =CS4U - ldr r1, =CFG_CS4U_VAL + ldr r1, =CONFIG_SYS_CS4U_VAL str r1, [r0] ldr r0, =CS4L - ldr r1, =CFG_CS4L_VAL + ldr r1, =CONFIG_SYS_CS4L_VAL str r1, [r0] ldr r0, =CS5U - ldr r1, =CFG_CS5U_VAL + ldr r1, =CONFIG_SYS_CS5U_VAL str r1, [r0] ldr r0, =CS5L - ldr r1, =CFG_CS5L_VAL + ldr r1, =CONFIG_SYS_CS5L_VAL str r1, [r0] /* SDRAM Setup */ diff --git a/board/scb9328/u-boot.lds b/board/scb9328/u-boot.lds index 46ed451ee..c96e58a84 100644 --- a/board/scb9328/u-boot.lds +++ b/board/scb9328/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/shannon/flash.c b/board/shannon/flash.c index 475b76b30..0455afa93 100644 --- a/board/shannon/flash.c +++ b/board/shannon/flash.c @@ -30,7 +30,7 @@ ulong myflush(void); #define FLASH_BANK_SIZE 0x400000 /* 4 MB */ #define MAIN_SECT_SIZE 0x20000 /* 128 KB */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x00F000F0 @@ -41,8 +41,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define CMD_PROGRAM 0x00A000A0 #define CMD_UNLOCK_BYPASS 0x00200020 -#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2))) -#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2))) +#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2))) +#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2))) #define BIT_ERASE_DONE 0x00800080 #define BIT_RDY_MASK 0x00800080 @@ -61,15 +61,15 @@ ulong flash_init(void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | (AMD_ID_LV160B & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -112,24 +112,24 @@ ulong flash_init(void) #ifdef CONFIG_INFERNO /* first one, 0x00000 to 0x07fff */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE + 0x00000, - CFG_FLASH_BASE + 0x08000 - 1, + CONFIG_SYS_FLASH_BASE + 0x00000, + CONFIG_SYS_FLASH_BASE + 0x08000 - 1, &flash_info[0]); /* third to 10th, 0x0c000 - 0xdffff */ flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE + 0x0c000, - CFG_FLASH_BASE + 0xe0000 - 1, + CONFIG_SYS_FLASH_BASE + 0x0c000, + CONFIG_SYS_FLASH_BASE + 0xe0000 - 1, &flash_info[0]); #else flash_protect(FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return size; @@ -253,7 +253,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; @@ -358,7 +358,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) + if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { chip1 = ERR | TMO; break; diff --git a/board/shannon/u-boot.lds b/board/shannon/u-boot.lds index 6bd06270a..fce2533ce 100644 --- a/board/shannon/u-boot.lds +++ b/board/shannon/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c index d65376328..8053da481 100644 --- a/board/siemens/CCM/ccm.c +++ b/board/siemens/CCM/ccm.c @@ -133,7 +133,7 @@ int checkboard (void) int power_on_reset(void) { /* Test Reset Status Register */ - return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; + return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1; } #define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */ @@ -142,7 +142,7 @@ int power_on_reset(void) static void init_leds (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; immap->im_cpm.cp_pbpar &= ~PB_LEDS; immap->im_cpm.cp_pbodr &= ~PB_LEDS; @@ -157,7 +157,7 @@ static void init_leds (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9; long int size = 0; @@ -171,7 +171,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; memctl->memc_mar = 0x00000088; @@ -180,10 +180,10 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay(200); @@ -203,21 +203,21 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size = size9; /* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */ } else { /* back to 8 columns */ size = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay(500); /* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */ } @@ -230,7 +230,7 @@ phys_size_t initdram (int board_type) */ if (size < 0x02000000) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay(1000); } @@ -238,13 +238,13 @@ phys_size_t initdram (int board_type) * Final mapping */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; can_driver_enable (); @@ -263,7 +263,7 @@ phys_size_t initdram (int board_type) */ void can_driver_enable (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* Initialize MBMR */ @@ -302,13 +302,13 @@ void can_driver_enable (void) memctl->memc_mcr = 0x011C | UPMB; /* Initialize OR3 / BR3 for CAN Bus Controller */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; } void can_driver_disable (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* Reset OR3 / BR3 to disable CAN Bus Controller */ @@ -331,7 +331,7 @@ void can_driver_disable (void) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -341,24 +341,24 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize /* ------------------------------------------------------------------------- */ -#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) -#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN) +#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN) void reset_phy(void) { - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; ulong value; /* Configure all needed port pins for GPIO */ -#ifdef CFG_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +#ifdef CONFIG_SYS_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; #else - immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* Set low */ + immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */ #endif - immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET; /* output */ + immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */ + immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */ immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ @@ -366,23 +366,23 @@ void reset_phy(void) value = immr->im_cpm.cp_pbdat; /* Assert Powerdown and Reset signals */ - value |= CFG_PB_ETH_POWERDOWN; + value |= CONFIG_SYS_PB_ETH_POWERDOWN; /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ -#ifdef CFG_ETH_CFG1_VALUE - value |= CFG_PB_ETH_CFG1; +#ifdef CONFIG_SYS_ETH_CFG1_VALUE + value |= CONFIG_SYS_PB_ETH_CFG1; #else - value &= ~(CFG_PB_ETH_CFG1); + value &= ~(CONFIG_SYS_PB_ETH_CFG1); #endif -#ifdef CFG_ETH_CFG2_VALUE - value |= CFG_PB_ETH_CFG2; +#ifdef CONFIG_SYS_ETH_CFG2_VALUE + value |= CONFIG_SYS_PB_ETH_CFG2; #else - value &= ~(CFG_PB_ETH_CFG2); + value &= ~(CONFIG_SYS_PB_ETH_CFG2); #endif -#ifdef CFG_ETH_CFG3_VALUE - value |= CFG_PB_ETH_CFG3; +#ifdef CONFIG_SYS_ETH_CFG3_VALUE + value |= CONFIG_SYS_PB_ETH_CFG3; #else - value &= ~(CFG_PB_ETH_CFG3); + value &= ~(CONFIG_SYS_PB_ETH_CFG3); #endif /* Drive output signals to initial state */ @@ -391,11 +391,11 @@ void reset_phy(void) udelay (10000); /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ udelay (10000); /* de-assert RESET signal of PHY */ - immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET; + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET; udelay (1000); } diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c index 9c32785b4..ad1ed793d 100644 --- a/board/siemens/CCM/flash.c +++ b/board/siemens/CCM/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -75,38 +75,38 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif } else { @@ -419,7 +419,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -542,7 +542,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c index 11b97bcaa..50b08abce 100644 --- a/board/siemens/CCM/fpga_ccm.c +++ b/board/siemens/CCM/fpga_ccm.c @@ -31,7 +31,7 @@ fpga_t fpga_list[] = { { "PUMA" , PUMA_CONF_BASE , - CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE } + CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE } }; int fpga_count = sizeof(fpga_list) / sizeof(fpga_t); @@ -90,7 +90,7 @@ const uint puma_table[] = ulong fpga_control (fpga_t* fpga, int cmd) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; switch (cmd) { diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds index 10b38ec35..ef9a2515c 100644 --- a/board/siemens/CCM/u-boot.lds +++ b/board/siemens/CCM/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug index bf6399197..88dbd3810 100644 --- a/board/siemens/CCM/u-boot.lds.debug +++ b/board/siemens/CCM/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) /* . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) */ *(.text) *(.fixup) diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c index 9c0ff0278..e21bb245a 100644 --- a/board/siemens/IAD210/IAD210.c +++ b/board/siemens/IAD210/IAD210.c @@ -102,7 +102,7 @@ const uint sdram_table[] = { phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile iop8xx_t *iop = &immap->im_ioport; volatile fec_t *fecp = &immap->im_cpm.cp_fec; @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; memctl->memc_mar = 0x00000088; @@ -126,10 +126,10 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -155,20 +155,20 @@ phys_size_t initdram (int board_type) * Check Bank 0 Memory Size for re-configuration * */ - size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM, + size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); udelay (1000); - memctl->memc_mamr = CFG_MAMR; + memctl->memc_mamr = CONFIG_SYS_MAMR; udelay (1000); /* * Final mapping */ - memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); + memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V); udelay (10000); @@ -195,7 +195,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -219,7 +219,7 @@ void board_serial_init (void) void board_ether_init (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *iop = &immap->im_ioport; volatile fec_t *fecp = &immap->im_cpm.cp_fec; @@ -230,7 +230,7 @@ void board_ether_init (void) int board_early_init_f (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile iop8xx_t *iop = &immap->im_ioport; @@ -240,7 +240,7 @@ int board_early_init_f (void) iop->iop_padir = 0x0800; /* start timer 2 for the 4hz LED blink rate */ - timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */ + timers->cpmt_tmr2 = 0xff2c; /* 4HZ for 64MHz */ timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */ timers->cpmt_tgcr = 0x00000810; /* run timer 2 */ @@ -261,7 +261,7 @@ int board_early_init_f (void) void board_get_enetaddr (uchar * addr) { int i; - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile cpm8xx_t *cpm = &immap->im_cpm; unsigned int rccrtmp; diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c index 1b27f336b..e599c1061 100644 --- a/board/siemens/IAD210/atm.c +++ b/board/siemens/IAD210/atm.c @@ -57,7 +57,7 @@ void atmUtpInit(void); ****************************************************************************/ int atmLoad() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; volatile iop8xx_t *iop = &immap->im_ioport; @@ -91,7 +91,7 @@ int atmLoad() ****************************************************************************/ void atmUnload() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer; volatile iop8xx_t *iop = &immap->im_ioport; @@ -141,11 +141,11 @@ void atmUnload() int atmMemInit() { int i; - unsigned immr = CFG_IMMR; + unsigned immr = CONFIG_SYS_IMMR; int total_num_rbd = 0; int total_num_tbd = 0; - memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); + memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE); g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY; @@ -226,11 +226,11 @@ void atmIntInit() void atmApcInit() { int i; - /* unsigned immr = CFG_IMMR; */ - uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR); - struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR); - uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR); - uint16 * tq_ptr = TQ_PTR(CFG_IMMR); + /* unsigned immr = CONFIG_SYS_IMMR; */ + uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR); + struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR); + uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR); + uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR); /***************************************************/ /* Initialize MPHY Pointing Table (only one entry) */ /***************************************************/ @@ -290,7 +290,7 @@ void atmApcInit() ****************************************************************************/ void atmAmtInit() { - unsigned immr = CFG_IMMR; + unsigned immr = CONFIG_SYS_IMMR; g_atm.am_top = AM_PTR(immr); g_atm.ap_top = AP_PTR(immr); @@ -315,7 +315,7 @@ void atmAmtInit() ****************************************************************************/ void atmCpmInit() { - unsigned immr = CFG_IMMR; + unsigned immr = CONFIG_SYS_IMMR; memset((char *)immr + 0x3F00, 0x00, 0xC0); @@ -551,7 +551,7 @@ void atmCpmInit() ****************************************************************************/ void atmUtpInit() { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile iop8xx_t *iop = &immap->im_ioport; volatile car8xx_t *car = &immap->im_clkrst; volatile cpm8xx_t *cpm = &immap->im_cpm; @@ -579,7 +579,7 @@ void atmUtpInit() /* 11 = divide by 7 */ /* */ /* Note that the UTOPIA clock must be programmed as to operate */ - /* within the range SYSCLK/10 .. 50Mhz. */ + /* within the range SYSCLK/10 .. 50MHz. */ /*-----------------------------------------------------------------*/ car->car_sccr &= 0xFFFFFFE0; car->car_sccr |= 0x00000008; /* UTPCLK = SYSCLK / 4 */ diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h index 71b049725..cd5b45e86 100644 --- a/board/siemens/IAD210/atm.h +++ b/board/siemens/IAD210/atm.h @@ -6,9 +6,9 @@ typedef volatile unsigned short vuint16; typedef volatile unsigned int vuint32; -#define DPRAM_ATM CFG_IMMR + 0x3000 +#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000 -#define ATM_DPRAM_BEGIN (DPRAM_ATM - CFG_IMMR - 0x2000) +#define ATM_DPRAM_BEGIN (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000) #define NUM_CONNECTIONS 1 #define SAR_RXB_SIZE 1584 #define AM_HMASK 0x0FFFFFF0 diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c index 110858d3c..c262e0f83 100644 --- a/board/siemens/IAD210/flash.c +++ b/board/siemens/IAD210/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -59,13 +59,13 @@ unsigned long flash_init (void) /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size; @@ -368,7 +368,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -491,7 +491,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds index 291f6b368..47677c6ee 100644 --- a/board/siemens/IAD210/u-boot.lds +++ b/board/siemens/IAD210/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS cpu/mpc8xx/interrupts.o (.text) lib_ppc/time.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -132,6 +132,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/siemens/SCM/config.mk b/board/siemens/SCM/config.mk index 855ae38f8..5d0898be6 100644 --- a/board/siemens/SCM/config.mk +++ b/board/siemens/SCM/config.mk @@ -25,7 +25,7 @@ # Siemens SCM boards # -# This should be equal to the CFG_FLASH_BASE define in config_SCM.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_SCM.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c index 056fe810b..4a6d5382b 100644 --- a/board/siemens/SCM/flash.c +++ b/board/siemens/SCM/flash.c @@ -31,7 +31,7 @@ #define V_BYTE(a) (*(volatile unsigned char *)( a )) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- @@ -185,13 +185,13 @@ unsigned long flash_init (void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here (only one bank) */ - size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); + size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 >> 20); @@ -201,19 +201,19 @@ unsigned long flash_init (void) * protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif return (size_b0); @@ -364,7 +364,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -480,7 +480,7 @@ static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) start = get_timer (0); while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c index 661bf66c6..acd9c1570 100644 --- a/board/siemens/SCM/fpga_scm.c +++ b/board/siemens/SCM/fpga_scm.c @@ -28,18 +28,18 @@ #include "../common/fpga.h" fpga_t fpga_list[] = { - {"FIOX", CFG_FIOX_BASE, - CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE} + {"FIOX", CONFIG_SYS_FIOX_BASE, + CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE} , - {"FDOHM", CFG_FDOHM_BASE, - CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE} + {"FDOHM", CONFIG_SYS_FDOHM_BASE, + CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE} }; int fpga_count = sizeof (fpga_list) / sizeof (fpga_t); ulong fpga_control (fpga_t * fpga, int cmd) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; switch (cmd) { case FPGA_INIT_IS_HIGH: @@ -74,11 +74,11 @@ ulong fpga_control (fpga_t * fpga, int cmd) break; case FPGA_GET_ID: - if (fpga->conf_base == CFG_FIOX_BASE) { + if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) { ulong ver = *(volatile ulong *) (fpga->conf_base + 0x10); return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0); - } else if (fpga->conf_base == CFG_FDOHM_BASE) { + } else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) { return (*(volatile ushort *) fpga->conf_base) & 0xff; } else { return *(volatile ulong *) fpga->conf_base; diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c index 6a9dd2583..e0611fe37 100644 --- a/board/siemens/SCM/scm.c +++ b/board/siemens/SCM/scm.c @@ -249,7 +249,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; @@ -274,7 +274,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -285,7 +285,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -308,10 +308,10 @@ int power_on_reset (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif long psize, lsize; @@ -319,8 +319,8 @@ phys_size_t initdram (int board_type) psize = 16 * 1024 * 1024; lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; #if 0 /* Just for debugging */ #define prt_br_or(brX,orX) do { \ @@ -338,37 +338,37 @@ phys_size_t initdram (int board_type) prt_br_or (br3, or3); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL - %ld MB, ", psize >> 20); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL - %ld MB, ", psize >> 20); } /* Local SDRAM setup: */ -#ifdef CFG_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CFG_LSRT; - size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, +#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CONFIG_SYS_LSRT; + size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, (uchar *) SDRAM_BASE2_PRELIM); if (size8 < size9) { lsize = size9; printf ("Local:9COL - %ld MB) using ", lsize >> 20); } else { - lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); printf ("Local:8COL - %ld MB) using ", lsize >> 20); } @@ -377,11 +377,11 @@ phys_size_t initdram (int board_type) /* Set up BR2 so that the local SDRAM goes * right after the 60x SDRAM */ - memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | - (CFG_SDRAM_BASE + psize); + memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | + (CONFIG_SYS_SDRAM_BASE + psize); #endif -#endif /* CFG_INIT_LOCAL_SDRAM */ -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -394,17 +394,17 @@ phys_size_t initdram (int board_type) static void config_scoh_cs (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; - volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE; + volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE; volatile uint tmp, i; /* Initialize OR3 / BR3 for CAN Bus Controller 0 */ - memctl->memc_or3 = CFG_CAN0_OR3; - memctl->memc_br3 = CFG_CAN0_BR3; + memctl->memc_or3 = CONFIG_SYS_CAN0_OR3; + memctl->memc_br3 = CONFIG_SYS_CAN0_BR3; /* Initialize OR4 / BR4 for CAN Bus Controller 1 */ - memctl->memc_or4 = CFG_CAN1_OR4; - memctl->memc_br4 = CFG_CAN1_BR4; + memctl->memc_or4 = CONFIG_SYS_CAN1_OR4; + memctl->memc_br4 = CONFIG_SYS_CAN1_BR4; /* Initialize MAMR to write in the array at address 0x0 */ memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS; @@ -487,19 +487,19 @@ static void config_scoh_cs (void) /* Initialize OR5 / BR5 for the extended EEPROM Bank0 */ - memctl->memc_or5 = CFG_EXTPROM_OR5; - memctl->memc_br5 = CFG_EXTPROM_BR5; + memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5; + memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5; /* Initialize OR6 / BR6 for the extended EEPROM Bank1 */ - memctl->memc_or6 = CFG_EXTPROM_OR6; - memctl->memc_br6 = CFG_EXTPROM_BR6; + memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6; + memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6; /* Initialize OR7 / BR7 for the Glue Logic */ - memctl->memc_or7 = CFG_FIOX_OR7; - memctl->memc_br7 = CFG_FIOX_BR7; + memctl->memc_or7 = CONFIG_SYS_FIOX_OR7; + memctl->memc_br7 = CONFIG_SYS_FIOX_BR7; /* Initialize OR8 / BR8 for the DOH Logic */ - memctl->memc_or8 = CFG_FDOHM_OR8; - memctl->memc_br8 = CFG_FDOHM_BR8; + memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8; + memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8; DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0); DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1); diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c index 7d4977e02..8cf17b857 100644 --- a/board/siemens/SMN42/flash.c +++ b/board/siemens/SMN42/flash.c @@ -25,8 +25,8 @@ #include <asm/byteorder.h> #include <asm/arch/hardware.h> -static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +static unsigned long flash_addr_table[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS_LIST; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong); extern int lpc2292_flash_erase(flash_info_t *, int, int); @@ -70,8 +70,8 @@ ulong flash_init (void) &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); size += ext_flash_init(); @@ -172,19 +172,19 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * From here on is code for the external S29GL128N taken from cam5200_flash.c */ -#define CFG_FLASH_WORD_SIZE unsigned short +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short static int wait_for_DQ7_32(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -199,8 +199,8 @@ static int wait_for_DQ7_32(flash_info_t * info, int sect) int ext_flash_erase(flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect, ret; ret = 0; @@ -236,14 +236,14 @@ int ext_flash_erase(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ l_sect = sect; /* @@ -269,8 +269,8 @@ int ext_flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ if (ret) printf(" error\n"); @@ -282,20 +282,20 @@ int ext_flash_erase(flash_info_t * info, int s_first, int s_last) static ulong flash_get_size(vu_long * addr, flash_info_t * info) { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; default: @@ -308,12 +308,12 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) value = addr2[1]; /* device ID */ switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_MIRROR: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_MIRROR: value = addr2[14]; switch(value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_2: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_2: value = addr2[15]; - if (value != (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_3) { + if (value != (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_3) { info->flash_id = FLASH_UNKNOWN; } else { info->flash_id += FLASH_S29GL128N; @@ -340,13 +340,13 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); info->protect[i] = addr2[2] & 1; } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -354,11 +354,11 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) static unsigned long ext_flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; int i; /* Init: no FLASHes known */ - for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -384,9 +384,9 @@ static unsigned long ext_flash_init(void) static int write_word(flash_info_t * info, ulong dest, ushort data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) &data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) &data; ulong start; int flag; @@ -398,9 +398,9 @@ static int write_word(flash_info_t * info, ulong dest, ushort data) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; *dest2 = *data2; /* re-enable interrupts if necessary */ @@ -409,10 +409,10 @@ static int write_word(flash_info_t * info, ulong dest, ushort data) /* data polling for D7 */ start = get_timer(0); - while ((*dest2 & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (*data2 & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((*dest2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (*data2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf("WRITE_TOUT\n"); return (1); } diff --git a/board/siemens/SMN42/u-boot.lds b/board/siemens/SMN42/u-boot.lds index 418101ff8..49d18f7d6 100644 --- a/board/siemens/SMN42/u-boot.lds +++ b/board/siemens/SMN42/u-boot.lds @@ -50,6 +50,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c index 05c364bb2..3ce7bb329 100644 --- a/board/siemens/pcu_e/flash.c +++ b/board/siemens/pcu_e/flash.c @@ -24,15 +24,15 @@ #include <common.h> #include <mpc8xx.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -47,7 +47,7 @@ /*---------------------------------------------------------------------*/ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -68,20 +68,20 @@ static void flash_get_offsets (ulong base, flash_info_t *info); */ #define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \ - - (0xFFFFFFFF - CFG_MONITOR_BASE) ) + - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) ) /*----------------------------------------------------------------------- */ unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long base, size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -131,7 +131,7 @@ unsigned long flash_init (void) /* Remap FLASH according to real size */ base = 0 - size_b0; - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", @@ -151,18 +151,18 @@ unsigned long flash_init (void) PCU_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif if (size_b1) { flash_info_t tmp_info; - memctl->memc_or6 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; @@ -178,11 +178,11 @@ unsigned long flash_init (void) flash_info[1].size = size_b1; -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[1]); #endif /* @@ -437,10 +437,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) #endif } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } saddr = (vu_short *)info->start[0]; @@ -526,7 +526,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_short*)(info->start[l_sect]); while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -660,7 +660,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); - for (passed=0; passed < CFG_FLASH_WRITE_TOUT; passed=get_timer(start)) { + for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) { sval = *sdest; @@ -683,7 +683,7 @@ static int write_data (flash_info_t *info, ulong dest, ulong data) dest, sval, sdata); } - if (passed >= CFG_FLASH_WRITE_TOUT) { + if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) { DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n", dest, sval, sdata); rc = 1; diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c index 5647f7af0..a60c825b2 100644 --- a/board/siemens/pcu_e/pcu_e.c +++ b/board/siemens/pcu_e/pcu_e.c @@ -158,7 +158,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; long int size_b0, reg; int i; @@ -169,7 +169,7 @@ phys_size_t initdram (int board_type) upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* burst length=4, burst type=sequential, CAS latency=2 */ memctl->memc_mar = 0x00000088; @@ -178,15 +178,15 @@ phys_size_t initdram (int board_type) * Map controller bank 2 to the SDRAM bank at preliminary address. */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ - memctl->memc_or5 = CFG_OR5_PRELIM; - memctl->memc_br5 = CFG_BR5_PRELIM; + memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM; + memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM; #else /* XXX */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #endif /* XXX */ /* initialize memory address register */ - memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */ /* mode initialization (offset 5) */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ @@ -241,12 +241,12 @@ phys_size_t initdram (int board_type) * Check Bank 0 Memory Size for re-configuration */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ - size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); + size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE); #else /* XXX */ - size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); #endif /* XXX */ - memctl->memc_mamr = CFG_MAMR | MAMR_PTAE; + memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE; /* * Final mapping: @@ -254,10 +254,10 @@ phys_size_t initdram (int board_type) #if PCU_E_WITH_SWAPPED_CS /* XXX */ memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; #else /* XXX */ memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING; - memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; #endif /* XXX */ udelay (1000); @@ -283,7 +283,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; memctl->memc_mamr = mamr_value; @@ -294,29 +294,29 @@ static long int dram_size (long int mamr_value, long int *base, /* ------------------------------------------------------------------------- */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ -#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) #else /* XXX */ -#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \ - CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 ) +#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \ + CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 ) #endif /* XXX */ -#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET) +#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET) void reset_phy (void) { - immap_t *immr = (immap_t *) CFG_IMMR; + immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ulong value; /* Configure all needed port pins for GPIO */ #if PCU_E_WITH_SWAPPED_CS /* XXX */ -# ifdef CFG_ETH_MDDIS_VALUE - immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS; +# ifdef CONFIG_SYS_ETH_MDDIS_VALUE + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS; # else - immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */ + immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */ # endif - immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */ + immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */ + immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */ + immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */ #endif /* XXX */ immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */ immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */ @@ -324,31 +324,31 @@ void reset_phy (void) value = immr->im_cpm.cp_pbdat; /* Assert Powerdown and Reset signals */ - value |= CFG_PB_ETH_POWERDOWN; - value &= ~(CFG_PB_ETH_RESET); + value |= CONFIG_SYS_PB_ETH_POWERDOWN; + value &= ~(CONFIG_SYS_PB_ETH_RESET); /* PHY configuration includes MDDIS and CFG1 ... CFG3 */ #if !PCU_E_WITH_SWAPPED_CS -# ifdef CFG_ETH_MDDIS_VALUE - value |= CFG_PB_ETH_MDDIS; +# ifdef CONFIG_SYS_ETH_MDDIS_VALUE + value |= CONFIG_SYS_PB_ETH_MDDIS; # else - value &= ~(CFG_PB_ETH_MDDIS); + value &= ~(CONFIG_SYS_PB_ETH_MDDIS); # endif #endif -#ifdef CFG_ETH_CFG1_VALUE - value |= CFG_PB_ETH_CFG1; +#ifdef CONFIG_SYS_ETH_CFG1_VALUE + value |= CONFIG_SYS_PB_ETH_CFG1; #else - value &= ~(CFG_PB_ETH_CFG1); + value &= ~(CONFIG_SYS_PB_ETH_CFG1); #endif -#ifdef CFG_ETH_CFG2_VALUE - value |= CFG_PB_ETH_CFG2; +#ifdef CONFIG_SYS_ETH_CFG2_VALUE + value |= CONFIG_SYS_PB_ETH_CFG2; #else - value &= ~(CFG_PB_ETH_CFG2); + value &= ~(CONFIG_SYS_PB_ETH_CFG2); #endif -#ifdef CFG_ETH_CFG3_VALUE - value |= CFG_PB_ETH_CFG3; +#ifdef CONFIG_SYS_ETH_CFG3_VALUE + value |= CONFIG_SYS_PB_ETH_CFG3; #else - value &= ~(CFG_PB_ETH_CFG3); + value &= ~(CONFIG_SYS_PB_ETH_CFG3); #endif /* Drive output signals to initial state */ @@ -357,11 +357,11 @@ void reset_phy (void) udelay (10000); /* De-assert Ethernet Powerdown */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */ udelay (10000); /* de-assert RESET signal of PHY */ - immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET; + immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET; udelay (1000); } @@ -414,7 +414,7 @@ U_BOOT_CMD (puma, 4, 1, do_puma, static void puma_set_mode (int mode) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; /* disable PUMA in memory controller */ @@ -452,7 +452,7 @@ static void puma_set_mode (int mode) static void puma_load (ulong addr, ulong len) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */ uchar *data = (uchar *) addr; int i; @@ -462,33 +462,33 @@ static void puma_load (ulong addr, ulong len) ++len; /* Reset FPGA */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */ - immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT); - immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT); + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */ + immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT); + immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT); #if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */ - immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */ - immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */ - immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */ + immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */ + immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */ + immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */ + immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */ #else - immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */ - immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */ - immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */ - immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */ + immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */ + immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */ + immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */ + immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */ #endif /* XXX */ udelay (100); #if PCU_E_WITH_SWAPPED_CS /* XXX */ - immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */ + immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */ #else - immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */ + immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */ #endif /* XXX */ /* wait until INIT indicates completion of reset */ for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) { udelay (1000); - if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT) + if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT) break; } if (i == PUMA_INIT_TIMEOUT) { @@ -519,14 +519,14 @@ static void puma_status (void) static int puma_init_done (void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* make sure pin is GPIO input */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE); - immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE); - immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE); + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE); + immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE); + immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE); - return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0; + return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0; } /* ------------------------------------------------------------------------- */ diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds index bc1ea7372..319cc7bd0 100644 --- a/board/siemens/pcu_e/u-boot.lds +++ b/board/siemens/pcu_e/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug index 2ee823745..bd9d76ce2 100644 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ b/board/siemens/pcu_e/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c index 61d758085..a8dfca824 100644 --- a/board/sixnet/flash.c +++ b/board/sixnet/flash.c @@ -23,12 +23,12 @@ #include <common.h> #include <mpc8xx.h> -/* environment.h defines the various CFG_ENV_... values in terms +/* environment.h defines the various CONFIG_ENV_... values in terms * of whichever ones are given in the configuration file. */ #include <environment.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -56,7 +56,7 @@ static void flash_reset(flash_info_t *info); static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); static void flash_get_offsets(ulong base, flash_info_t *info); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION static void flash_sync_real_protect(flash_info_t *info); #endif @@ -67,17 +67,17 @@ static void flash_sync_real_protect(flash_info_t *info); */ unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b; int i; /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } - size_b = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); + size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b; @@ -91,33 +91,33 @@ unsigned long flash_init (void) /* Do this again (was done already in flast_get_size), just * in case we move it when remap the FLASH. */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /* read the hardware protection status (if any) into the * protection array in flash_info. */ flash_sync_real_protect(&flash_info[0]); #endif -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_ADDR +#ifdef CONFIG_ENV_ADDR flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -405,7 +405,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info) return (info->size); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ @@ -544,7 +544,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) udelay (1000); while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { @@ -663,7 +663,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) /* data polling for D7 */ while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00F000F0; /* reset bank */ res = 1; } @@ -709,7 +709,7 @@ static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) start = get_timer (0); while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *dest = (FPW)0x00B000B0; /* Suspend program */ res = 1; } @@ -724,7 +724,7 @@ static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) return (res); } -#ifdef CFG_FLASH_PROTECTION +#ifdef CONFIG_SYS_FLASH_PROTECTION /*----------------------------------------------------------------------- */ int flash_real_protect (flash_info_t * info, long sector, int prot) diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c index dcd34726b..3ed581ec0 100644 --- a/board/sixnet/sixnet.c +++ b/board/sixnet/sixnet.c @@ -35,7 +35,7 @@ #if defined(CONFIG_CMD_NAND) #include <linux/mtd/nand_legacy.h> -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; #endif DECLARE_GLOBAL_DATA_PTR; @@ -133,7 +133,7 @@ const uint duart_table[] = #define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */ #define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */ #define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */ -#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */ +#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG)) /* FPGA port */ int board_postclk_init (void) { @@ -143,7 +143,7 @@ int board_postclk_init (void) # include "fpgadata.c" }; - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; #define porta (immap->im_ioport.iop_padat) const unsigned char* pdata; @@ -247,10 +247,10 @@ int board_postclk_init (void) /* ------------------------------------------------------------------------- */ /* base address for SRAM, assume 32-bit port, valid */ -#define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V) +#define NVRAM_BR_VALUE (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V) /* up to 64MB - will be adjusted for actual size */ -#define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \ +#define NVRAM_OR_PRELIM (ORMASK(CONFIG_SYS_SRAM_SIZE) \ | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR) /* * Miscellaneous platform dependent initializations after running in RAM. @@ -258,7 +258,7 @@ int board_postclk_init (void) int misc_init_r (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; char* s; char* e; @@ -271,7 +271,7 @@ int misc_init_r (void) /* Is there any SRAM? Is it 16 or 32 bits wide? */ /* First look for 32-bit SRAM */ - bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); + bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); if (bd->bi_sramsize == 0) { /* no 32-bit SRAM, but there could be 16-bit SRAM since @@ -279,7 +279,7 @@ int misc_init_r (void) * Try again with a 16-bit bus. */ memctl->memc_br2 |= BR_PS_16; - bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE); + bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE); } if (bd->bi_sramsize == 0) { @@ -288,7 +288,7 @@ int misc_init_r (void) else { /* adjust or2 for actual size of SRAM */ memctl->memc_or2 |= ORMASK(bd->bi_sramsize); - bd->bi_sramstart = CFG_SRAM_BASE; + bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10); } @@ -330,7 +330,7 @@ int misc_init_r (void) #if defined(CONFIG_CMD_NAND) void nand_init(void) { - unsigned long totlen = nand_probe(CFG_DFLASH_BASE); + unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE); printf ("%4lu MB\n", totlen >> 20); } @@ -498,7 +498,7 @@ const uint sdram_table[] = phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; uint size_sdram = 0; uint size_sdram9 = 0; diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index b91c44a57..efa42445e 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/sl8245/flash.c b/board/sl8245/flash.c index 553dc9822..4455b6387 100644 --- a/board/sl8245/flash.c +++ b/board/sl8245/flash.c @@ -25,15 +25,15 @@ #include <mpc824x.h> #include <asm/processor.h> -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -43,7 +43,7 @@ #define PARAM_SECT23_SIZE 0x8000 #define PARAM_SECT4_SIZE 0x10000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static int write_data (flash_info_t *info, ulong dest, ulong *data); static void write_via_fpu(vu_long *addr, ulong *data); @@ -79,8 +79,8 @@ unsigned long flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); write_via_fpu (&addr[0xaaa], precmd0); write_via_fpu (&addr[0x554], precmd1); @@ -108,10 +108,10 @@ unsigned long flash_init (void) write_via_fpu (addr, cmdres); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); for (j = 0; j < 32; j++) { - flash_info[i].start[j] = CFG_FLASH_BASE + + flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE; } flash_info[i].start[32] = @@ -125,29 +125,29 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE flash_protect ( FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]); #else flash_protect ( FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -#if CFG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) +#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]); #else flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif #endif @@ -267,7 +267,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) while (((addr[0] & 0x00800080) != 0x00800080) || ((addr[1] & 0x00800080) != 0x00800080)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); write_via_fpu (addr, cmdersusp); write_via_fpu (addr, cmdres); @@ -452,7 +452,7 @@ static int write_data (flash_info_t * info, ulong dest, ulong * data) while (((addr[0] & 0x00800080) != (data[0] & 0x00800080)) || ((addr[1] & 0x00800080) != (data[1] & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { write_via_fpu (chip, cmdres); return (1); } diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c index c853755a1..e849e013d 100644 --- a/board/sl8245/sl8245.c +++ b/board/sl8245/sl8245.c @@ -24,6 +24,7 @@ #include <common.h> #include <mpc824x.h> #include <pci.h> +#include <netdev.h> int checkboard (void) { @@ -36,13 +37,13 @@ int checkboard (void) phys_size_t initdram (int board_type) { -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size; long new_bank0_end; long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size - 1; mear1 = mpc824x_mpc107_getreg(MEAR1); @@ -56,7 +57,7 @@ phys_size_t initdram (int board_type) return (size); #else - return CFG_MAX_RAM_SIZE; + return CONFIG_SYS_MAX_RAM_SIZE; #endif } @@ -67,8 +68,6 @@ void pci_init_board(void) pci_mpc824x_init(&hose); } -extern int skge_initialize(bd_t *bis); - int board_eth_init(bd_t *bis) { int rc = 0; @@ -78,4 +77,3 @@ int board_eth_init(bd_t *bis) #endif return rc; } - diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c index fd9992d36..9eee60d0d 100644 --- a/board/smdk2400/flash.c +++ b/board/smdk2400/flash.c @@ -33,7 +33,7 @@ #define FLASH_BANK_SIZE 0x1000000 /* 2 x 8 MB */ #define MAIN_SECT_SIZE 0x40000 /* 2 x 128 kB */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x00FF00FF @@ -66,17 +66,17 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) | (INTEL_ID_28F640J3A & FLASH_TYPEMASK); flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) - flashbase = CFG_FLASH_BASE; + flashbase = CONFIG_SYS_FLASH_BASE; else panic ("configured too many flash banks!\n"); for (j = 0; j < flash_info[i].sector_count; j++) { @@ -92,18 +92,18 @@ ulong flash_init (void) * Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -299,7 +299,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_STATUS_RESET; result = BIT_TIMEOUT; break; @@ -394,7 +394,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) /* wait until flash is ready */ do { /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { *addr = CMD_SUSPEND; result = BIT_TIMEOUT; break; diff --git a/board/smdk2400/u-boot.lds b/board/smdk2400/u-boot.lds index 14cd22800..987b07d94 100644 --- a/board/smdk2400/u-boot.lds +++ b/board/smdk2400/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/smdk2410/flash.c b/board/smdk2410/flash.c index 376930bd3..132d752e8 100644 --- a/board/smdk2410/flash.c +++ b/board/smdk2410/flash.c @@ -30,7 +30,7 @@ ulong myflush (void); #define FLASH_BANK_SIZE PHYS_FLASH_SIZE #define MAIN_SECT_SIZE 0x10000 /* 64 KB */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x000000F0 @@ -41,8 +41,8 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define CMD_PROGRAM 0x000000A0 #define CMD_UNLOCK_BYPASS 0x00000020 -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1))) +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) #define BIT_ERASE_DONE 0x00000080 #define BIT_RDY_MASK 0x00000080 @@ -61,7 +61,7 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { ulong flashbase = 0; flash_info[i].flash_id = @@ -75,8 +75,8 @@ ulong flash_init (void) #error "Unknown flash configured" #endif flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); if (i == 0) flashbase = PHYS_FLASH_1; else @@ -111,13 +111,13 @@ ulong flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return size; } @@ -236,7 +236,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* check timeout */ if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip = TMO; break; @@ -332,7 +332,7 @@ static int write_hword (flash_info_t * info, ulong dest, ushort data) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { chip = ERR | TMO; break; } diff --git a/board/smdk2410/u-boot.lds b/board/smdk2410/u-boot.lds index 14cd22800..987b07d94 100644 --- a/board/smdk2410/u-boot.lds +++ b/board/smdk2410/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c index d2f169b88..9e276a104 100644 --- a/board/snmc/qs850/flash.c +++ b/board/snmc/qs850/flash.c @@ -29,7 +29,7 @@ #include <asm/u-boot.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ #define FLASH_WORD_SIZE unsigned long @@ -57,7 +57,7 @@ unsigned long flash_init (void) volatile FLASH_WORD_SIZE* flash_base; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -87,13 +87,13 @@ unsigned long flash_init (void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { + if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { /* Setup offsets */ flash_get_offsets ((ulong)flash_base, &flash_info[0]); /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); size_b1 = 0 ; flash_info[0].size = size_b0; return(size_b0); @@ -125,8 +125,8 @@ unsigned long flash_init (void) flash_get_offsets (base_b0, &flash_info[0]); /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); if (size_b1) { /* Re-do sizing to get full correct info */ @@ -134,11 +134,11 @@ unsigned long flash_init (void) flash_get_offsets (base_b1, &flash_info[1]); /* monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CFG_MONITOR_LEN, + (void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CONFIG_SYS_MONITOR_LEN, base_b1+size_b1-1, &flash_info[1]); /* monitor protection OFF by default (one is enough) */ - (void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CFG_MONITOR_LEN, + (void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CONFIG_SYS_MONITOR_LEN, base_b0+size_b0-1, &flash_info[0]); } else { flash_info[1].flash_id = FLASH_UNKNOWN; @@ -480,7 +480,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) while ((addr[0] & (0x00800080&FLASH_ID_MASK)) != (0x00800080&FLASH_ID_MASK) ) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -607,7 +607,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer(0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c index 2fbe8aeb5..cc8eaad88 100644 --- a/board/snmc/qs850/qs850.c +++ b/board/snmc/qs850/qs850.c @@ -146,7 +146,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -155,17 +155,17 @@ phys_size_t initdram (int board_type) /* * Prescaler for refresh */ - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* * Map controller bank 1 to the SDRAM address */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; + memctl->memc_or1 = CONFIG_SYS_OR1; + memctl->memc_br1 = CONFIG_SYS_BR1; udelay(1000); /* perform SDRAM initialization sequence */ - memctl->memc_mamr = CFG_16M_MAMR; + memctl->memc_mamr = CONFIG_SYS_16M_MAMR; udelay(100); /* Program the SDRAM's Mode Register */ @@ -192,7 +192,7 @@ phys_size_t initdram (int board_type) /* * Check for 32M SDRAM Memory Size */ - size = dram_size(CFG_32M_MAMR|MAMR_PTAE, + size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE, (long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE); udelay (1000); @@ -200,7 +200,7 @@ phys_size_t initdram (int board_type) * Check for 16M SDRAM Memory Size */ if (size != SDRAM_32M_MAX_SIZE) { - size = dram_size(CFG_16M_MAMR|MAMR_PTAE, + size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); udelay (1000); } @@ -221,7 +221,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 2410d5f2c..6fa9b8129 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c index aa2e85605..2cb8dcb9d 100644 --- a/board/snmc/qs860t/flash.c +++ b/board/snmc/qs860t/flash.c @@ -29,10 +29,10 @@ #include <asm/u-boot.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#ifdef CFG_FLASH_16BIT +#ifdef CONFIG_SYS_FLASH_16BIT #define FLASH_WORD_SIZE unsigned short #define FLASH_ID_MASK 0xFFFF #else @@ -46,7 +46,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* stolen from esteem192e/flash.c */ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info); -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT static int write_word (flash_info_t *info, ulong dest, ulong data); #else static int write_short (flash_info_t *info, ulong dest, ushort data); @@ -65,7 +65,7 @@ unsigned long flash_init (void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -79,20 +79,20 @@ unsigned long flash_init (void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { + if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { /* Setup offsets */ flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]); /* Monitor protection ON by default */ #if 0 /* sand: */ (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0, + FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0, FLASH_BASE1_PRELIM-1+size_b0, &flash_info[0]); #else (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); #endif size_b1 = 0 ; @@ -126,13 +126,13 @@ unsigned long flash_init (void) /* monitor protection ON by default */ #if 0 /* sand: */ (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0, + FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0, FLASH_BASE1_PRELIM-1+size_b0, &flash_info[0]); #else (void)flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]); #endif @@ -144,12 +144,12 @@ unsigned long flash_init (void) /* monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - base_b1+size_b1-CFG_MONITOR_LEN, + base_b1+size_b1-CONFIG_SYS_MONITOR_LEN, base_b1+size_b1-1, &flash_info[1]); /* monitor protection OFF by default (one is enough) */ (void)flash_protect(FLAG_PROTECT_CLEAR, - base_b0+size_b0-CFG_MONITOR_LEN, + base_b0+size_b0-CONFIG_SYS_MONITOR_LEN, base_b0+size_b0-1, &flash_info[0]); } else { @@ -182,7 +182,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info) else if (info->flash_id & FLASH_BTYPE) { if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; @@ -234,7 +234,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info) i = info->sector_count - 1; if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00008000; info->start[i--] = base + info->size - 0x0000C000; @@ -393,7 +393,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info) /* Write auto select command: read Manufacturer ID */ -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT /* * Note: if it is an AMD flash and the word at addr[0000] @@ -650,7 +650,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); if (info->flash_id < FLASH_AMD_COMP) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT addr[0x0555] = 0x00AA00AA; addr[0x02AA] = 0x00550055; addr[0x0555] = 0x00800080; @@ -690,7 +690,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -711,7 +711,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ barf = 0; -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT addr = (vu_long *) (info->start[sect]); addr[0] = 0x00200020; addr[0] = 0x00D000D0; @@ -766,7 +766,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_info_t *info; int i; - for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) { + for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) { if ((addr >= info->start[0]) && (addr < (info->start[0] + info->size)) ) { return (info); @@ -843,7 +843,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT ulong cp, wp, data; int l; #else @@ -852,7 +852,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) #endif int i, rc; -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT wp = (addr & ~3); /* get lower word aligned address */ @@ -979,7 +979,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT static int write_word (flash_info_t *info, ulong dest, ulong data) { vu_long *addr = (vu_long*)(info->start[0]); @@ -1015,13 +1015,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) if(info->flash_id > FLASH_AMD_COMP) { while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } } else { while(!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } @@ -1081,7 +1081,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) if(info->flash_id < FLASH_AMD_COMP) { /* AMD stuff */ while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -1089,7 +1089,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) } else { /* intel stuff */ while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } if( addr[0] & 0x003A) { /* check for error */ @@ -1103,7 +1103,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data) *addr = 0x00B0; *addr = 0x0070; while(!(addr[0] & 0x0080)){ /* wait for error or finish */ - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1); + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } *addr = 0x00FF; } diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c index 17c935621..b272d80d9 100644 --- a/board/snmc/qs860t/qs860t.c +++ b/board/snmc/qs860t/qs860t.c @@ -117,7 +117,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; @@ -131,12 +131,12 @@ phys_size_t initdram (int board_type) /* * Map controller bank 2 to the SDRAM address */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + memctl->memc_or2 = CONFIG_SYS_OR2; + memctl->memc_br2 = CONFIG_SYS_BR2; udelay(200); /* perform SDRAM initialization sequence */ - memctl->memc_mbmr = CFG_16M_MBMR; + memctl->memc_mbmr = CONFIG_SYS_16M_MBMR; udelay(100); memctl->memc_mar = 0x00000088; @@ -155,7 +155,7 @@ phys_size_t initdram (int board_type) /* * Check for 64M SDRAM Memory Size */ - size = dram_size (CFG_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); + size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE); udelay (1000); /* @@ -163,7 +163,7 @@ phys_size_t initdram (int board_type) */ if (size != SDRAM_64M_MAX_SIZE) { #endif - size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); + size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE); udelay (1000); #if 0 } @@ -184,31 +184,31 @@ phys_size_t initdram (int board_type) /* * Map the 8M Intel Flash device to chip select 1 */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; + memctl->memc_or1 = CONFIG_SYS_OR1; + memctl->memc_br1 = CONFIG_SYS_BR1; /* * Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg * to chip select 3 */ - memctl->memc_or3 = CFG_OR3; - memctl->memc_br3 = CFG_BR3; + memctl->memc_or3 = CONFIG_SYS_OR3; + memctl->memc_br3 = CONFIG_SYS_BR3; /* * Map chip selects 4, 5, 6, & 7 for external expansion connector */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; + memctl->memc_or5 = CONFIG_SYS_OR5; + memctl->memc_br5 = CONFIG_SYS_BR5; - memctl->memc_or6 = CFG_OR6; - memctl->memc_br6 = CFG_BR6; + memctl->memc_or6 = CONFIG_SYS_OR6; + memctl->memc_br6 = CONFIG_SYS_BR6; - memctl->memc_or7 = CFG_OR7; - memctl->memc_br7 = CFG_BR7; + memctl->memc_or7 = CONFIG_SYS_OR7; + memctl->memc_br7 = CONFIG_SYS_BR7; #endif @@ -227,7 +227,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mbmr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mbmr = mbmr_value; diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index 2410d5f2c..6fa9b8129 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index bbb5ee2c4..2b62b8470 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) @@ -37,7 +38,9 @@ void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for clock adjust: @@ -57,7 +60,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) * - frequency * - ddr1 vs. ddr2 */ - popts->cpo_override = 10; + popts->cpo_override = 0; /* * Factors to consider for write data delay: diff --git a/board/socrates/law.c b/board/socrates/law.c index 35c4a900a..71cff8cf0 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -36,6 +36,7 @@ * 0x0000_0000 0x2fff_ffff DDR 512M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xc000_0000 0xc00f_ffff FPGA 1M + * 0xc800_0000 0xcbff_ffff LIME 64M * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xfc00_0000 0xffff_ffff FLASH 64M @@ -46,13 +47,14 @@ */ struct law_entry law_table[] = { - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), -#if defined(CFG_FPGA_BASE) - SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), +#if defined(CONFIG_SYS_FPGA_BASE) + SET_LAW(CONFIG_SYS_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), #endif + SET_LAW(CONFIG_SYS_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 6ec53f872..7d76f4222 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -23,7 +23,7 @@ #include <common.h> -#if defined(CFG_NAND_BASE) +#if defined(CONFIG_SYS_NAND_BASE) #include <nand.h> #include <asm/errno.h> #include <asm/io.h> diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 12d1b8a73..029ba0298 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -41,7 +41,7 @@ */ long int sdram_setup(int casl) { - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); /* * Disable memory controller. @@ -49,28 +49,28 @@ long int sdram_setup(int casl) ddr->cs0_config = 0; ddr->sdram_cfg = 0; - ddr->cs0_bnds = CFG_DDR_CS0_BNDS; - ddr->cs0_config = CFG_DDR_CS0_CONFIG; - ddr->timing_cfg_0 = CFG_DDR_TIMING_0; - ddr->timing_cfg_1 = CFG_DDR_TIMING_1; - ddr->timing_cfg_2 = CFG_DDR_TIMING_2; - ddr->sdram_mode = CFG_DDR_MODE; - ddr->sdram_interval = CFG_DDR_INTERVAL; - ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2; - ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL; + ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; + ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; + ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE; + ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; + ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; + ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL; asm ("sync;isync;msync"); udelay(1000); - ddr->sdram_cfg = CFG_DDR_CONFIG; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG; asm ("sync; isync; msync"); udelay(1000); - if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) { + if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) { /* * OK, size detected -> all done */ - return CFG_SDRAM_SIZE<<20; + return CONFIG_SYS_SDRAM_SIZE<<20; } return 0; /* nothing found ! */ @@ -90,11 +90,11 @@ phys_size_t initdram (int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf ("SDRAM test phase 1:\n"); diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index d791f1135..d83dc7d6a 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -36,20 +36,23 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/io.h> - -#if defined(CFG_FPGA_BASE) +#include <i2c.h> +#include <mb862xx.h> +#include <video_fb.h> #include "upm_table.h" -#endif + DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ +extern GraphicDevice mb862xx; void local_bus_init (void); ulong flash_get_size (ulong base, int banknum); int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + char *src; int f; char *s = getenv("serial#"); @@ -79,16 +82,12 @@ int checkboard (void) * Initialize local bus. */ local_bus_init (); -#if defined(CFG_FPGA_BASE) - /* Init UPMA for FPGA access */ - upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); -#endif return 0; } int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -99,20 +98,20 @@ int misc_init_r (void) /* * Check if boot FLASH isn't max size */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); + if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { + memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff); + memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff); /* * Re-check to get correct base address */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); } /* * Check if only one FLASH bank is available */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { + if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { memctl->or1 = 0; memctl->br1 = 0; @@ -121,24 +120,24 @@ int misc_init_r (void) */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); } return 0; @@ -149,15 +148,38 @@ int misc_init_r (void) */ void local_bus_init (void) { + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + sys_info_t sysinfo; + uint clkdiv; + uint lbc_mhz; + uint lcrr = CONFIG_SYS_LBC_LCRR; + + get_sys_info (&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ + if (lbc_mhz >= 66) + lcrr &= ~LCRR_DBYP; /* DLL Enabled */ + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + + out_be32 (&lbc->lcrr, lcrr); + asm ("sync;isync;msync"); + + out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ + out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ + out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ + out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); - - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ - ecm->eedr = 0xffffffff; /* Clear ecm errors */ - ecm->eeer = 0xffffffff; /* Enable ecm errors */ + /* Init UPMA for FPGA access */ + out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ + upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); + /* Init UPMB for Lime controller access */ + out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ + upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); } #if defined(CONFIG_PCI) @@ -197,9 +219,14 @@ void pci_init_board (void) #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* set and reset the GPIO pin 2 which will reset the W83782G chip */ + out_8((unsigned char*)&gur->gpoutdr, 0x3F ); + out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ + udelay(200); + out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); + return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ @@ -208,31 +235,246 @@ int board_early_init_r (void) void ft_board_setup(void *blob, bd_t *bd) { - u32 val[4]; - int rc; + u32 val[12]; + int rc, i = 0; ft_cpu_setup(blob, bd); - /* Fixup NOR mapping */ - val[0] = 0; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize; + /* Fixup NOR FLASH mapping */ + val[i++] = 0; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = gd->bd->bi_flashstart; + val[i++] = gd->bd->bi_flashsize; + + if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { + /* Fixup LIME mapping */ + val[i++] = 2; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = CONFIG_SYS_LIME_BASE; + val[i++] = CONFIG_SYS_LIME_SIZE; + } + + /* Fixup FPGA mapping */ + val[i++] = 3; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = CONFIG_SYS_FPGA_BASE; + val[i++] = CONFIG_SYS_FPGA_SIZE; rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, sizeof(val), 1); - if (rc) - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); - -#if defined (CFG_FPGA_BASE) - memset(val, 0, sizeof(val)); - val[0] = CFG_FPGA_BASE; - rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg", - val, sizeof(val), 1); + val, i * sizeof(u32), 1); if (rc) - printf("Unable to update property \"fpga\", err=%s\n", + printf("Unable to update localbus ranges, err=%s\n", fdt_strerror(rc)); -#endif } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C) +#define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038) +#define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC) +/* Lime clock frequency */ +#define CONFIG_SYS_LIME_CLK_100MHZ 0x00000 +#define CONFIG_SYS_LIME_CLK_133MHZ 0x10000 +/* SDRAM parameter */ +#define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63 + +#define DISPLAY_WIDTH 800 +#define DISPLAY_HEIGHT 480 +#define DEFAULT_BRIGHTNESS 25 +#define BACKLIGHT_ENABLE (1 << 31) + +static const gdc_regs init_regs [] = +{ + {0x0100, 0x00010f00}, + {0x0020, 0x801901df}, + {0x0024, 0x00000000}, + {0x0028, 0x00000000}, + {0x002c, 0x00000000}, + {0x0110, 0x00000000}, + {0x0114, 0x00000000}, + {0x0118, 0x01df0320}, + {0x0004, 0x041f0000}, + {0x0008, 0x031f031f}, + {0x000c, 0x017f0349}, + {0x0010, 0x020c0000}, + {0x0014, 0x01df01e9}, + {0x0018, 0x00000000}, + {0x001c, 0x01e00320}, + {0x0100, 0x80010f00}, + {0x0, 0x0} +}; + +const gdc_regs *board_get_regs (void) +{ + return init_regs; +} + +#define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0) +#define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084) +int lime_probe(void) +{ + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + uint cfg_br2; + uint cfg_or2; + uint reg; + + cfg_br2 = memctl->br2; + cfg_or2 = memctl->or2; + + /* Configure GPCM for CS2 */ + memctl->br2 = 0; + memctl->or2 = 0xfc000410; + memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; + + /* Try to access GDC ID/Revision registers */ + reg = in_be32((void *)CONFIG_SYS_LIME_CID); + reg = in_be32((void *)CONFIG_SYS_LIME_CID); + if (reg == 0x303) { + reg = in_be32((void *)CONFIG_SYS_LIME_REV); + reg = in_be32((void *)CONFIG_SYS_LIME_REV); + reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0; + } else + reg = 0; + + /* Restore previous CS2 configuration */ + memctl->br2 = 0; + memctl->or2 = cfg_or2; + memctl->br2 = cfg_br2; + return reg; +} + +/* Returns Lime base address */ +unsigned int board_video_init (void) +{ + if (!lime_probe()) + return 0; + + /* + * Reset Lime controller + */ + out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1); + udelay(200); + + /* Set Lime clock to 133MHz */ + out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ); + /* Delay required */ + udelay(300); + /* Set memory parameters */ + out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); + + mb862xx.winSizeX = DISPLAY_WIDTH; + mb862xx.winSizeY = DISPLAY_HEIGHT; + mb862xx.gdfIndex = GDF_15BIT_555RGB; + mb862xx.gdfBytesPP = 2; + + return CONFIG_SYS_LIME_BASE; +} + +#define W83782D_REG_CFG 0x40 +#define W83782D_REG_BANK_SEL 0x4e +#define W83782D_REG_ADCCLK 0x4b +#define W83782D_REG_BEEP_CTRL 0x4d +#define W83782D_REG_BEEP_CTRL2 0x57 +#define W83782D_REG_PWMOUT1 0x5b +#define W83782D_REG_VBAT 0x5d + +static int w83782d_hwmon_init(void) +{ + u8 buf; + + if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) + return -1; + + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); + + buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, + buf | 0x80); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); + + buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); + i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, + (buf & 0xf4) | 0x01); + return 0; +} + +static void board_backlight_brightness(int br) +{ + u32 reg; + u8 buf; + u8 old_buf; + + /* Select bank 0 */ + if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + goto err; + else + buf = old_buf & 0xf8; + + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) + goto err; + + if (br > 0) { + /* PWMOUT1 duty cycle ctrl */ + buf = 255 / (100 / br); + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + goto err; + + /* LEDs on */ + reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); + if (!(reg & BACKLIGHT_ENABLE)); + out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), + reg | BACKLIGHT_ENABLE); + } else { + buf = 0; + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + goto err; + + /* LEDs off */ + reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); + reg &= ~BACKLIGHT_ENABLE; + out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); + } + /* Restore previous bank setting */ + if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + goto err; + + return; +err: + printf("W83782G I2C access failed\n"); +} + +void board_backlight_switch (int flag) +{ + char * param; + int rc; + + if (w83782d_hwmon_init()) + printf ("hwmon IC init failed\n"); + + if (flag) { + param = getenv("brightness"); + rc = param ? simple_strtol(param, NULL, 10) : -1; + if (rc < 0) + rc = DEFAULT_BRIGHTNESS; + } else { + rc = 0; + } + board_backlight_brightness(rc); +} + +#if defined(CONFIG_CONSOLE_EXTRA_INFO) +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { + strcpy (info, " Board: Socrates"); + } else { + info [0] = '\0'; + } +} +#endif diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index aea99ada2..4591e466b 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -31,26 +31,26 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* - * TLB 0: 64M Non-cacheable, guarded + * TLB 1: 64M Non-cacheable, guarded * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), @@ -58,7 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -66,29 +66,41 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), -#if defined(CFG_FPGA_BASE) +#if defined(CONFIG_SYS_FPGA_BASE) /* * TLB 4: 1M Non-cacheable, guarded * 0xc0000000 1M FPGA and NAND */ - SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_1M, 1), #endif /* + * TLB 5: 64M Non-cacheable, guarded + * 0xc8000000 16M LIME GDC framebuffer + * 0xc9fc0000 256K LIME GDC MMIO + * (0xcbfc0000 256K LIME GDC MMIO) + * MMIO is relocatable and could be at 0xcbfc0000 + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + + /* * TLB 6: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), +#if !defined(CONFIG_SPD_EEPROM) /* * TLB 7+8: 512M DDR, cache disabled (needed for memory test) * 0x00000000 512M DDR System memory @@ -96,13 +108,14 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/socrates/u-boot.lds b/board/socrates/u-boot.lds index 8d2f65ccc..499f531eb 100644 --- a/board/socrates/u-boot.lds +++ b/board/socrates/u-boot.lds @@ -144,6 +144,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h index ea64a59a0..2a89c963e 100644 --- a/board/socrates/upm_table.h +++ b/board/socrates/upm_table.h @@ -34,22 +34,42 @@ /* UPM Table Configuration Code for FPGA access */ static const unsigned int UPMTableA[] = { - 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, /* Words 0 to 3 */ - 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, /* Words 4 to 7 */ - 0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, /* Words 8 to 11 */ - 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, /* Words 12 to 15 */ - 0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, /* Words 16 to 19 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ - 0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, /* Words 24 to 27 */ - 0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, /* Words 28 to 31 */ - 0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 32 to 35 */ - 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 36 to 39 */ - 0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ - 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ + 0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */ + 0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */ + 0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */ + 0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */ + 0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */ + 0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */ + 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */ + 0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ }; +/* LIME UPM B Table Configuration Code */ +static unsigned int UPMTableB[] = +{ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffffc01, /* Words 4 to 7 */ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffffc00, 0xfffffc01, /* Words 20 to 23 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0ffffc01, /* Words 28 to 31 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39 */ + 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43 */ + 0x00fffc04, 0x00fffc04, 0x0ffffc00, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ +}; #endif diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c index 2b789d474..90d429802 100644 --- a/board/sorcery/sorcery.c +++ b/board/sorcery/sorcery.c @@ -26,6 +26,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <pci.h> +#include <netdev.h> phys_size_t initdram (int board_type) { @@ -33,7 +34,7 @@ phys_size_t initdram (int board_type) size = dramSetup (); - return get_ram_size(CFG_SDRAM_BASE, size); + return get_ram_size(CONFIG_SYS_SDRAM_BASE, size); } int checkboard (void) @@ -58,3 +59,10 @@ void pci_init_board (void) pci_mpc8220_init (&hose); #endif /* CONFIG_PCI */ } + +int board_eth_init(bd_t *bis) +{ + /* Initialize built-in FEC first */ + cpu_eth_init(bis); + return pci_eth_init(bis); +} diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c index cf21b215b..26d0f9c33 100644 --- a/board/spc1920/hpi.c +++ b/board/spc1920/hpi.c @@ -144,16 +144,16 @@ static int hpi_tiny_autoinc_test(void); /* init the host port interface on UPMA */ int hpi_init(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint)); udelay(100); - memctl->memc_mamr = CFG_MAMR; - memctl->memc_or3 = CFG_OR3; - memctl->memc_br3 = CFG_BR3; + memctl->memc_mamr = CONFIG_SYS_MAMR; + memctl->memc_or3 = CONFIG_SYS_OR3; + memctl->memc_br3 = CONFIG_SYS_BR3; /* reset dsp */ dsp_reset(); @@ -170,7 +170,7 @@ int hpi_init(void) /* activate the Host Port interface */ static int hpi_activate(void) { - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; /* turn on hpi */ pld->dsp_hpi_on = 0x1; @@ -193,7 +193,7 @@ static int hpi_activate(void) /* turn off the host port interface */ static void hpi_inactivate(void) { - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; /* deactivate hpi */ pld->dsp_hpi_on = 0x0; @@ -210,7 +210,7 @@ static void hpi_inactivate(void) /* reset the DSP */ static void dsp_reset(void) { - volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; + volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; pld->dsp_reset = 0x1; pld->dsp_hpi_on = 0x0; diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c index a32aad0ee..ee939bf24 100644 --- a/board/spc1920/spc1920.c +++ b/board/spc1920/spc1920.c @@ -84,9 +84,9 @@ const uint sdram_table[] = { phys_size_t initdram (int board_type) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immr->im_memctl; - /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */ + /* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */ long int size_b0; long int size8, size9; @@ -99,19 +99,19 @@ phys_size_t initdram (int board_type) udelay(100); - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; /* burst length=4, burst type=sequential, CAS latency=2 */ - memctl->memc_mar = CFG_MAR; + memctl->memc_mar = CONFIG_SYS_MAR; /* * Map controller bank 1 to the SDRAM bank at preliminary address. */ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; /* initialize memory address register */ - memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ /* mode initialization (offset 5) */ udelay (200); /* 0x80006105 */ @@ -132,7 +132,7 @@ phys_size_t initdram (int board_type) /* Need at least 10 DRAM accesses to stabilize */ for (i = 0; i < 10; ++i) { volatile unsigned long *addr = - (volatile unsigned long *) CFG_SDRAM_BASE; + (volatile unsigned long *) CONFIG_SYS_SDRAM_BASE; unsigned long val; val = *(addr + i); @@ -144,22 +144,22 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); udelay (1000); /* * try 9 column mode */ - size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE); if (size8 < size9) { /* leave configuration at 9 columns */ size_b0 = size9; - memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE; + memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE; udelay (500); } else { /* back to 8 columns */ size_b0 = size8; - memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; udelay (500); } @@ -169,15 +169,15 @@ phys_size_t initdram (int board_type) memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING; - memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; + memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V; udelay (1000); /* initalize the DSP Host Port Interface */ hpi_init(); /* FRAM Setup */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; udelay(1000); return (size_b0); @@ -193,7 +193,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mbmr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mbmr = mbmr_value; @@ -207,7 +207,7 @@ static long int dram_size (long int mbmr_value, long int *base, int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* Set Go/NoGo led (PA15) to color red */ immap->im_ioport.iop_papar &= ~0x1; @@ -240,7 +240,7 @@ int board_early_init_f(void) immap->im_ioport.iop_pddat |= 0x0020; -#ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */ +#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */ immap->im_cpm.cp_simode |= 0x7000; immap->im_cpm.cp_simode &= ~(0x8000); #endif diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index 8c46e4677..5af36c97a 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/spd8xx/flash.c b/board/spd8xx/flash.c index 8c0bb4f56..fb2fb6a7d 100644 --- a/board/spd8xx/flash.c +++ b/board/spd8xx/flash.c @@ -24,7 +24,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*----------------------------------------------------------------------- */ diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c index 6387f8a65..9e9678d62 100644 --- a/board/spd8xx/spd8xx.c +++ b/board/spd8xx/spd8xx.c @@ -145,7 +145,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0; @@ -153,23 +153,23 @@ phys_size_t initdram (int board_type) /* * Map controller bank 2 to the SRAM bank at preliminary address. */ - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + memctl->memc_or2 = CONFIG_SYS_OR2; + memctl->memc_br2 = CONFIG_SYS_BR2; #endif /* * Map controller bank 4 to the PER8 bank. */ - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; #if 0 /* Configure SHARC at UMA */ upmconfig (UPMA, (uint *) sharc_table, sizeof (sharc_table) / sizeof (uint)); /* Map controller bank 5 to the SHARC */ - memctl->memc_or5 = CFG_OR5; - memctl->memc_br5 = CFG_BR5; + memctl->memc_or5 = CONFIG_SYS_OR5; + memctl->memc_br5 = CONFIG_SYS_BR5; #endif memctl->memc_mamr = 0x00001000; @@ -178,17 +178,17 @@ phys_size_t initdram (int board_type) upmconfig (UPMB, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K; memctl->memc_mar = 0x00000088; /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; - memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */ + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */ udelay (200); memctl->memc_mcr = 0x80806105; @@ -205,10 +205,10 @@ phys_size_t initdram (int board_type) * Check Bank 0 Memory Size for re-configuration */ size_b0 = - dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM, + dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE); - memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE; + memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE; return (size_b0); } @@ -226,7 +226,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mbmr = mamr_value; @@ -238,7 +238,7 @@ static long int dram_size (long int mamr_value, long int *base, void reset_phy (void) { - immap_t *immr = (immap_t *) CFG_IMMR; + immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; ushort sreg; /* Configure extra port pins for NS DP83843 PHY */ @@ -274,21 +274,21 @@ void reset_phy (void) void ide_set_reset (int on) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; /* * Configure PC for IDE Reset Pin */ if (on) { /* assert RESET */ - immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET); + immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET); } else { /* release RESET */ - immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET; } /* program port pin as GPIO output */ - immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET); - immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET; + immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET); + immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET); + immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET; } /* ------------------------------------------------------------------------- */ diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index 13b29084f..7d94421dc 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -53,7 +53,7 @@ SECTIONS .text : { cpu/mpc8xx/start.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) *(.got1) @@ -123,6 +123,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index fd2245f57..67d37ae33 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c index 71de20899..9d3274149 100644 --- a/board/ssv/adnpesc1/adnpesc1.c +++ b/board/ssv/adnpesc1/adnpesc1.c @@ -76,14 +76,14 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { - nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; + nios_spi_t *spi = (nios_spi_t *)CONFIG_SYS_NIOS_SPIBASE; spi->slaveselect = SPI_RTC_CS_MASK; /* activate (1) */ } void spi_cs_deactivate(struct spi_slave *slave) { - nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; + nios_spi_t *spi = (nios_spi_t *)CONFIG_SYS_NIOS_SPIBASE; spi->slaveselect = 0; /* deactivate (0) */ } diff --git a/board/ssv/adnpesc1/config.mk b/board/ssv/adnpesc1/config.mk index 7d8eb03d8..cf0544572 100644 --- a/board/ssv/adnpesc1/config.mk +++ b/board/ssv/adnpesc1/config.mk @@ -22,7 +22,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x02fc0000 # ATTENTION: notice your CFG_MONITOR_LEN setting +TEXT_BASE = 0x02fc0000 # ATTENTION: notice your CONFIG_SYS_MONITOR_LEN setting ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG diff --git a/board/ssv/adnpesc1/flash.c b/board/ssv/adnpesc1/flash.c index fd8379b1b..882630c58 100644 --- a/board/ssv/adnpesc1/flash.c +++ b/board/ssv/adnpesc1/flash.c @@ -36,7 +36,7 @@ /*---------------------------------------------------------------------*/ #define BANKSZ (8 * 1024 * 1024) #define SECTSZ (64 * 1024) -#define UBOOTSECS ((CFG_MONITOR_LEN + CFG_ENV_SIZE) / SECTSZ) +#define UBOOTSECS ((CONFIG_SYS_MONITOR_LEN + CONFIG_ENV_SIZE) / SECTSZ) #define UBOOTAREA (UBOOTSECS * 64 * 1024) /* monitor / env area */ /*---------------------------------------------------------------------*/ @@ -47,16 +47,16 @@ unsigned long flash_init (void) flash_info_t *fli = &flash_info[0]; fli->size = BANKSZ; - fli->sector_count = CFG_MAX_FLASH_SECT; + fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT; fli->flash_id = FLASH_MAN_AMD + FLASH_AMLV640U; - addr = CFG_FLASH_BASE; + addr = CONFIG_SYS_FLASH_BASE; for (i = 0; i < fli->sector_count; ++i) { fli->start[i] = addr; addr += SECTSZ; /* Protect monitor / environment area */ - if (addr <= (CFG_FLASH_BASE + UBOOTAREA)) + if (addr <= (CONFIG_SYS_FLASH_BASE + UBOOTAREA)) fli->protect[i] = 1; else fli->protect[i] = 0; diff --git a/board/ssv/adnpesc1/vectors.S b/board/ssv/adnpesc1/vectors.S index fb7e17e43..8b2da2fed 100644 --- a/board/ssv/adnpesc1/vectors.S +++ b/board/ssv/adnpesc1/vectors.S @@ -57,12 +57,12 @@ .align 4 _vectors: -#if defined(CFG_NIOS_CPU_OCI_BASE) +#if defined(CONFIG_SYS_NIOS_CPU_OCI_BASE) /* OCI does the reset job */ .long _def_xhandler@h /* Vector 0 - NMI / Reset */ #else /* there is no OCI, so we have to do a direct reset jump here */ - .long CFG_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ + .long CONFIG_SYS_NIOS_CPU_RST_VECT /* Vector 0 - Reset to GERMS */ #endif .long _cwp_lolimit@h /* Vector 1 - underflow */ .long _cwp_hilimit@h /* Vector 2 - overflow */ @@ -80,7 +80,7 @@ _vectors: .long _def_xhandler@h /* Vector 13 - future reserved */ .long _def_xhandler@h /* Vector 14 - future reserved */ .long _def_xhandler@h /* Vector 15 - future reserved */ -#if (CFG_NIOS_TMRIRQ == 16) +#if (CONFIG_SYS_NIOS_TMRIRQ == 16) .long _timebase_int@h /* Vector 16 - lopri timer*/ #else .long _def_xhandler@h /* Vector 16 */ @@ -118,7 +118,7 @@ _vectors: .long _def_xhandler@h /* Vector 47 */ .long _def_xhandler@h /* Vector 48 */ .long _def_xhandler@h /* Vector 49 */ -#if (CFG_NIOS_TMRIRQ == 50) +#if (CONFIG_SYS_NIOS_TMRIRQ == 50) .long _timebase_int@h /* Vector 50 - lopri timer*/ #else .long _def_xhandler@h /* Vector 50 */ diff --git a/board/ssv/common/flash.c b/board/ssv/common/flash.c index 70cab7fa2..70bf9d678 100644 --- a/board/ssv/common/flash.c +++ b/board/ssv/common/flash.c @@ -29,7 +29,7 @@ #include <watchdog.h> #include <nios.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /*--------------------------------------------------------------------*/ void flash_print_info (flash_info_t * info) @@ -72,8 +72,8 @@ void flash_print_info (flash_info_t * info) int flash_erase (flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int prot, sect, wait; unsigned oldpri; ulong start; @@ -116,7 +116,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); *addr = 0xf0; *(addr+0xAAA/2) = 0xaa; *(addr+0x554/2) = 0x55; @@ -135,7 +135,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) udelay (125 * 1000); } putc ('.'); - if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("timeout\n"); return 1; } @@ -163,14 +163,14 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt) { - volatile CFG_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0]; - volatile CFG_FLASH_WORD_SIZE *dst = (vu_short *) addr; - CFG_FLASH_WORD_SIZE *src = (void *) srcbuffer; - CFG_FLASH_WORD_SIZE b; + volatile CONFIG_SYS_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0]; + volatile CONFIG_SYS_FLASH_WORD_SIZE *dst = (vu_short *) addr; + CONFIG_SYS_FLASH_WORD_SIZE *src = (void *) srcbuffer; + CONFIG_SYS_FLASH_WORD_SIZE b; unsigned oldpri; ulong start; - cnt /= sizeof(CFG_FLASH_WORD_SIZE); + cnt /= sizeof(CONFIG_SYS_FLASH_WORD_SIZE); while (cnt) { /* Check for sufficient erase */ b = *src; @@ -192,7 +192,7 @@ int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt) /* Verify write */ start = get_timer (0); while (*dst != b) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *cmd = 0xf0; return 1; } diff --git a/board/ssv/common/post.c b/board/ssv/common/post.c index a5f29c1a3..c7a9ccc89 100644 --- a/board/ssv/common/post.c +++ b/board/ssv/common/post.c @@ -25,19 +25,19 @@ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -#if !defined(CFG_NIOS_POST_WORD_ADDR) -#error "*** CFG_NIOS_POST_WORD_ADDR not defined ***" +#if !defined(CONFIG_SYS_NIOS_POST_WORD_ADDR) +#error "*** CONFIG_SYS_NIOS_POST_WORD_ADDR not defined ***" #endif void post_word_store (ulong a) { - volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR); + volatile void *save_addr = (void *)(CONFIG_SYS_NIOS_POST_WORD_ADDR); *(volatile ulong *) save_addr = a; } ulong post_word_load (void) { - volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR); + volatile void *save_addr = (void *)(CONFIG_SYS_NIOS_POST_WORD_ADDR); return *(volatile ulong *) save_addr; } diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c index 45372f427..7850794d6 100644 --- a/board/stxgp3/ddr.c +++ b/board/stxgp3/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/stxgp3/flash.c b/board/stxgp3/flash.c index 032989ba5..61c960247 100644 --- a/board/stxgp3/flash.c +++ b/board/stxgp3/flash.c @@ -37,19 +37,19 @@ #include <common.h> -#if !defined(CFG_NO_FLASH) +#if !defined(CONFIG_SYS_NO_FLASH) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -72,7 +72,7 @@ unsigned long flash_init (void) /* Init: enable write, * or we cannot even write flash commands */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; /* set the default sector offset */ @@ -80,7 +80,7 @@ unsigned long flash_init (void) /* Static FLASH Bank configuration here - FIXME XXX */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", @@ -88,22 +88,22 @@ unsigned long flash_init (void) } /* Re-do sizing to get full correct info */ - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif #endif @@ -329,7 +329,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) asm("sync"); return 1; } - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0xFFFFFFFF; /* reset bank */ asm("sync"); @@ -458,7 +458,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) flag = 0; while (((csr = *addr) & 0x00800080) != 0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { flag = 1; break; } @@ -502,7 +502,7 @@ static int clear_block_lock_bit(vu_long * addr) start = get_timer (0); while((*addr & 0x00800080) != 0x00800080){ - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout on clearing Block Lock Bit\n"); *addr = 0xFFFFFFFF; /* reset bank */ asm("sync"); @@ -512,4 +512,4 @@ static int clear_block_lock_bit(vu_long * addr) return 0; } -#endif /* !CFG_NO_FLASH */ +#endif /* !CONFIG_SYS_NO_FLASH */ diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c index a7e9ceb03..ba89f0edc 100644 --- a/board/stxgp3/law.c +++ b/board/stxgp3/law.c @@ -46,13 +46,13 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c index c80f1b381..3804fe080 100644 --- a/board/stxgp3/stxgp3.c +++ b/board/stxgp3/stxgp3.c @@ -203,7 +203,7 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); pci->peer &= 0xfffffffdf; /* disable master abort */ #endif @@ -215,7 +215,7 @@ reset_phy(void) { volatile uint *blatch; - blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; + blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; /* reset Giga bit Ethernet port if needed here */ @@ -267,7 +267,7 @@ show_activity(int flag) if (next_led_update > get_ticks()) return; - blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE; + blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE; led_bit >>= 1; if (led_bit == 0) @@ -284,7 +284,7 @@ initdram (int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ @@ -308,11 +308,11 @@ initdram (int board_type) } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c index d4104166a..aa11a5d39 100644 --- a/board/stxgp3/tlb.c +++ b/board/stxgp3/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xff000000 16M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_16M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -95,7 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Cacheable, non-guarded * 0xf000_0000 64M LBC SDRAM */ - SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -103,7 +103,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 7: 16K Non-cacheable, guarded * 0xfc000000 16K Configuration Latch register */ - SET_TLB_ENTRY(1, CFG_LBC_LCLDEVS_BASE, CFG_LBC_LCLDEVS_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), @@ -117,11 +117,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * Likely it needs to be increased by two for these entries. */ #error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 8, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000, + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 9, BOOKE_PAGESZ_64M, 1), #endif diff --git a/board/stxgp3/u-boot.lds b/board/stxgp3/u-boot.lds index d5363be5a..cdcb39a6b 100644 --- a/board/stxgp3/u-boot.lds +++ b/board/stxgp3/u-boot.lds @@ -148,6 +148,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/stxssa/ddr.c b/board/stxssa/ddr.c index 45372f427..7850794d6 100644 --- a/board/stxssa/ddr.c +++ b/board/stxssa/ddr.c @@ -10,6 +10,7 @@ #include <i2c.h> #include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> static void get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) @@ -40,7 +41,9 @@ fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, } } -void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) { /* * Factors to consider for CPO: diff --git a/board/stxssa/law.c b/board/stxssa/law.c index 8730cdfc4..55dde6675 100644 --- a/board/stxssa/law.c +++ b/board/stxssa/law.c @@ -47,14 +47,14 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), /* Map the whole localbus, including flash and reset latch. */ - SET_LAW(CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 124e1233b..73dddf3e0 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -39,6 +39,7 @@ #include <asm/io.h> #include <spd_sdram.h> #include <miiphy.h> +#include <netdev.h> long int fixed_sdram (void); @@ -206,7 +207,7 @@ reset_phy(void) #if 0 int i; #endif - blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE; + blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE; /* reset Giga bit Ethernet port if needed here */ @@ -252,7 +253,7 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR); + volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR); pci->peer &= 0xffffffdf; /* disable master abort */ #endif @@ -283,7 +284,7 @@ show_activity(int flag) if (next_led_update > get_ticks()) return; - blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE; + blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE; led_bit >>= 1; if (led_bit == 0) @@ -300,7 +301,7 @@ initdram (int board_type) #if defined(CONFIG_DDR_DLL) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint temp_ddrdll = 0; /* Work around to stabilize DDR DLL */ @@ -324,11 +325,11 @@ initdram (int board_type) } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("SDRAM test phase 1:\n"); @@ -400,3 +401,9 @@ pci_init_board(void) pci_mpc85xx_init(hose); #endif /* CONFIG_PCI */ } + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Initialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c index 86cbd1127..0386432b6 100644 --- a/board/stxssa/tlb.c +++ b/board/stxssa/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xfc000000 6M4 FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), @@ -54,7 +54,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 1: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), @@ -98,7 +98,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xfb000000 Configuration Latch register (one word) * 0xfc000000 Up to 64M flash */ - SET_TLB_ENTRY(1, CFG_LBC_OPTION_BASE, CFG_LBC_OPTION_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), }; diff --git a/board/stxssa/u-boot.lds b/board/stxssa/u-boot.lds index 93bedda66..6ee8d60ec 100644 --- a/board/stxssa/u-boot.lds +++ b/board/stxssa/u-boot.lds @@ -149,6 +149,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index a75037439..a1a36c493 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -349,7 +349,7 @@ static const uint nandcs_table[0x40] = { #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU) /* 9 */ -#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ +#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) @@ -401,7 +401,7 @@ void check_ram(unsigned int addr, unsigned int size) phys_size_t initdram(int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size; u32 d1, d2; @@ -418,10 +418,10 @@ phys_size_t initdram(int board_type) /* * Map controller bank 3 to the SDRAM bank at preliminary address. */ - memctl->memc_or4 = CFG_OR4_PRELIM; - memctl->memc_br4 = CFG_BR4_PRELIM; + memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM; + memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM; - memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */ udelay(200); @@ -529,7 +529,7 @@ void reset_phys(void) int board_early_init_f(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile iop8xx_t *ioport = &immap->im_ioport; volatile cpm8xx_t *cpm = &immap->im_cpm; volatile memctl8xx_t *memctl = &immap->im_memctl; @@ -579,13 +579,13 @@ int board_early_init_f(void) #include <linux/mtd/nand_legacy.h> extern ulong nand_probe(ulong physadr); -extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; +extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; void nand_init(void) { unsigned long totlen; - totlen = nand_probe(CFG_NAND_BASE); + totlen = nand_probe(CONFIG_SYS_NAND_BASE); printf ("%4lu MB\n", totlen >> 20); } #endif @@ -599,21 +599,7 @@ void hw_watchdog_reset(void) #endif -#ifdef CONFIG_SHOW_ACTIVITY - -/* called from timer interrupt every 1/CFG_HZ sec */ -void board_show_activity(ulong timestamp) -{ -} - -/* called when looping */ -void show_activity(int arg) -{ -} - -#endif - -#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) +#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) { /* printf("overwrite_console called\n"); */ diff --git a/board/stxxtc/u-boot.lds b/board/stxxtc/u-boot.lds index f560189c0..4966f4d4d 100644 --- a/board/stxxtc/u-boot.lds +++ b/board/stxxtc/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/stxxtc/u-boot.lds.debug b/board/stxxtc/u-boot.lds.debug index 5bf1a6628..d47c4082a 100644 --- a/board/stxxtc/u-boot.lds.debug +++ b/board/stxxtc/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c index 25e61dd5e..db1f21a58 100644 --- a/board/svm_sc8xx/flash.c +++ b/board/svm_sc8xx/flash.c @@ -23,11 +23,11 @@ #include <common.h> #include <mpc8xx.h> -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#ifndef CONFIG_ENV_ADDR +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -54,7 +54,7 @@ static void my_out_be32( unsigned *addr, int val); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; @@ -62,16 +62,16 @@ unsigned long flash_init (void) size_b0=0; size_b1=0; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } -#ifdef CFG_DOC_BASE +#ifdef CONFIG_SYS_DOC_BASE #ifndef CONFIG_FEL8xx_AT - memctl->memc_or5 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ - memctl->memc_br5 = CFG_DOC_BASE | 0x401; + memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */ + memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401; #else - memctl->memc_or3 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ - memctl->memc_br3 = CFG_DOC_BASE | 0x401; + memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */ + memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401; #endif #endif #if defined( CONFIG_BOOT_8B) @@ -136,54 +136,54 @@ unsigned long flash_init (void) } /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, &flash_info[1]); #endif } else { @@ -561,7 +561,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) # error CONFIG_BOOT_(size)B missing. #endif { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -710,7 +710,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); last = start; while( ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i] ) ) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { return 1; } } @@ -730,7 +730,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) start = get_timer (0); last = start; while( ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i] ) ) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) { return 1; } } @@ -749,7 +749,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c index 06fb18b34..4390e49dd 100644 --- a/board/svm_sc8xx/svm_sc8xx.c +++ b/board/svm_sc8xx/svm_sc8xx.c @@ -102,15 +102,15 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0 = 0; upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; #if defined (CONFIG_SDRAM_16M) - memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx; + memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx; memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ udelay(1); memctl->memc_mcr = 0x80002830; @@ -122,7 +122,7 @@ phys_size_t initdram (int board_type) memctl->memc_or1 = 0xff000a00; size_b0 = 0x01000000; #elif defined (CONFIG_SDRAM_32M) - memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx; + memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx; memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ udelay(1); memctl->memc_mcr = 0x80002830; @@ -134,7 +134,7 @@ phys_size_t initdram (int board_type) memctl->memc_or1 = 0xfe000a00; size_b0 = 0x02000000; #elif defined (CONFIG_SDRAM_64M) - memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx; + memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx; memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ udelay(1); memctl->memc_mcr = 0x80002830; @@ -154,9 +154,8 @@ phys_size_t initdram (int board_type) } #if defined(CONFIG_CMD_DOC) -extern void doc_probe (ulong physadr); void doc_init (void) { - doc_probe (CFG_DOC_BASE); + doc_probe (CONFIG_SYS_DOC_BASE); } #endif diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 14ff17987..ceab4d29d 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = env_offset; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -138,6 +138,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug index 0cd053a8b..016048dae 100644 --- a/board/svm_sc8xx/u-boot.lds.debug +++ b/board/svm_sc8xx/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/sx1/u-boot.lds b/board/sx1/u-boot.lds index b608223a7..9a9dd2106 100644 --- a/board/sx1/u-boot.lds +++ b/board/sx1/u-boot.lds @@ -52,6 +52,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c index e9f6418c4..933d5ecc8 100644 --- a/board/tb0229/flash.c +++ b/board/tb0229/flash.c @@ -27,10 +27,10 @@ #include <ppc4xx.h> #include <asm/processor.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#ifdef CFG_FLASH_16BIT +#ifdef CONFIG_SYS_FLASH_16BIT #define FLASH_WORD_SIZE unsigned short #define FLASH_ID_MASK 0xFFFF #else @@ -44,7 +44,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* stolen from esteem192e/flash.c */ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info); -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT static int write_word (flash_info_t * info, ulong dest, ulong data); #else static int write_short (flash_info_t * info, ulong dest, ushort data); @@ -63,14 +63,14 @@ unsigned long flash_init (void) unsigned long base_b0, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Static FLASH Bank configuration here - FIXME XXX */ size_b0 = - flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE, + flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE, &flash_info[0]); if (flash_info[0].flash_id == FLASH_UNKNOWN) { @@ -78,9 +78,9 @@ unsigned long flash_init (void) } /* Only one bank */ - if (CFG_MAX_FLASH_BANKS == 1) { + if (CONFIG_SYS_MAX_FLASH_BANKS == 1) { /* Setup offsets */ - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); /* Monitor protection ON by default */ #if 0 /* sand: */ @@ -91,19 +91,19 @@ unsigned long flash_init (void) &flash_info[0]); #else (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif size_b1 = 0; flash_info[0].size = size_b0; } -#ifdef CFG_FLASH_BASE_2 +#ifdef CONFIG_SYS_FLASH_BASE_2 /* 2 banks */ else { size_b1 = flash_get_size ((volatile FLASH_WORD_SIZE *) - CFG_FLASH_BASE_2, &flash_info[1]); + CONFIG_SYS_FLASH_BASE_2, &flash_info[1]); /* Re-do sizing to get full correct info */ @@ -144,8 +144,8 @@ unsigned long flash_init (void) &flash_info[0]); #else (void) flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif @@ -200,7 +200,7 @@ static void flash_get_offsets (ulong base, flash_info_t * info) } else if (info->flash_id & FLASH_BTYPE) { if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT /* set sector offsets for bottom boot block type */ info->start[0] = base + 0x00000000; info->start[1] = base + 0x00004000; @@ -256,7 +256,7 @@ static void flash_get_offsets (ulong base, flash_info_t * info) i = info->sector_count - 1; if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT info->start[i--] = base + info->size - 0x00004000; info->start[i--] = base + info->size - 0x00008000; info->start[i--] = base + info->size - 0x0000C000; @@ -448,7 +448,7 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info) /* Write auto select command: read Manufacturer ID */ -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT /* * Note: if it is an AMD flash and the word at addr[0000] @@ -699,7 +699,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts (); if (info->flash_id < FLASH_AMD_COMP) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT addr[0x0555] = 0x00AA00AA; addr[0x02AA] = 0x00550055; addr[0x0555] = 0x00800080; @@ -741,7 +741,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]); while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) != (0x00800080 & FLASH_ID_MASK)) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -762,7 +762,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ barf = 0; -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT addr = (vu_long *) (info->start[sect]); addr[0] = 0x00500050; addr[0] = 0x00200020; @@ -801,7 +801,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) l_sect = sect; } addr = (volatile FLASH_WORD_SIZE *) info->start[0]; -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */ #else addr[0] = (0x00FF & FLASH_ID_MASK); /* reset bank */ @@ -821,7 +821,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_info_t *info; int i; - for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) { + for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) { if ((addr >= info->start[0]) && (addr < (info->start[0] + info->size)) ) { return (info); @@ -898,7 +898,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) { -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT ulong cp, wp, data; int l; #else @@ -907,7 +907,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) #endif int i, rc; -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT wp = (addr & ~3); /* get lower word aligned address */ @@ -1034,7 +1034,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -#ifndef CFG_FLASH_16BIT +#ifndef CONFIG_SYS_FLASH_16BIT static int write_word (flash_info_t * info, ulong dest, ulong data) { vu_long *addr = (vu_long *) (info->start[0]); @@ -1076,7 +1076,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf ("timeout\n"); return (1); } @@ -1085,7 +1085,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) } else { while (!(addr[0] & 0x00800080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { printf ("timeout\n"); return (1); } @@ -1157,7 +1157,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) if (info->flash_id < FLASH_AMD_COMP) { /* AMD stuff */ while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -1165,7 +1165,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) } else { /* intel stuff */ while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } @@ -1184,7 +1184,7 @@ static int write_short (flash_info_t * info, ulong dest, ushort data) *addr = 0x00B0; *addr = 0x0070; while (!(addr[0] & 0x0080)) { /* wait for error or finish */ - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c index 921bd3adc..d3f05b273 100644 --- a/board/tb0229/tb0229.c +++ b/board/tb0229/tb0229.c @@ -34,7 +34,7 @@ void pci_init_board (void) phys_size_t initdram(int board_type) { - return get_ram_size (CFG_SDRAM_BASE, 0x8000000); + return get_ram_size (CONFIG_SYS_SDRAM_BASE, 0x8000000); } int checkboard (void) @@ -46,3 +46,8 @@ int checkboard (void) return 0; } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds index b18e6a6fc..086d74d32 100644 --- a/board/tb0229/u-boot.lds +++ b/board/tb0229/u-boot.lds @@ -65,6 +65,6 @@ SECTIONS . = ALIGN(4); .sbss (NOLOAD) : { *(.sbss) } - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } uboot_end = .; } diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c index a1601f274..dc4c6f18c 100644 --- a/board/total5200/sdram.c +++ b/board/total5200/sdram.c @@ -29,7 +29,7 @@ #include "sdram.h" -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -72,7 +72,7 @@ static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -81,7 +81,7 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) { ulong dramsize = 0; ulong dramsize2 = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -102,9 +102,9 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) /* find RAM size using SDRAM CS0 only */ mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { mpc5xxx_sdram_start(sdram_conf, 0); dramsize = test1; @@ -129,9 +129,9 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) /* find RAM size using SDRAM CS1 only */ mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (test1 > test2) { mpc5xxx_sdram_start(sdram_conf, 0); dramsize2 = test1; @@ -152,7 +152,7 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -170,7 +170,7 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize + dramsize2; } @@ -180,7 +180,7 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup and enable SDRAM chip selects */ @@ -199,9 +199,9 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) /* find RAM size */ mpc5xxx_sdram_start(sdram_conf, 0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); mpc5xxx_sdram_start(sdram_conf, 1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { mpc5xxx_sdram_start(sdram_conf, 0); dramsize = test1; @@ -212,12 +212,12 @@ long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf) /* set SDRAM end address according to size */ *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* Retrieve amount of SDRAM available */ dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ return dramsize; } diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c index 1ae24c4f3..c524d63f9 100644 --- a/board/total5200/total5200.c +++ b/board/total5200/total5200.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <netdev.h> #include "sdram.h" @@ -70,15 +71,15 @@ int checkboard (void) /* * Retrieve FPGA Revision. */ - printf ("(FPGA %08lX)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400)); + printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400)); /* * Take all peripherals in power-up mode. */ #if CONFIG_TOTAL5200_REV==2 - *(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70; + *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70; #else - *(vu_long *) (CFG_CPLD_BASE + 0x400) = 0x70; + *(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70; #endif return 0; @@ -283,7 +284,7 @@ void video_get_info_str (int line_number, char *info) /* Returns SED13806 base address. First thing called in the driver. */ unsigned int board_video_init (void) { - return CFG_LCD_BASE; + return CONFIG_SYS_LCD_BASE; } /* Called after initializing the SED13806 and before clearing the screen. */ @@ -308,3 +309,9 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SED13806 */ + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +} diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c index b3f095d80..124b47d22 100644 --- a/board/tqc/tqm5200/cam5200_flash.c +++ b/board/tqc/tqm5200/cam5200_flash.c @@ -35,7 +35,7 @@ #define swap16(x) __swab16(x) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* * CAM5200 is a TQM5200B based board. Additionally it also features @@ -51,15 +51,15 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ * 16 bit flash bank and two sets of routines *_32 and *_16 to handle * specifics of both flashes. */ -static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { - {CFG_BOOTCS_START, CFG_CS5_START | 1} +static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = { + {CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1} }; /*----------------------------------------------------------------------- * Functions */ static int write_word(flash_info_t * info, ulong dest, ulong data); -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word_32(flash_info_t * info, ulong dest, ulong data); static int write_word_16(flash_info_t * info, ulong dest, ulong data); static int flash_erase_32(flash_info_t * info, int s_first, int s_last); @@ -145,7 +145,7 @@ void flash_print_info(flash_info_t * info) /* * The following code cannot be run from FLASH! */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static ulong flash_get_size(vu_long * addr, flash_info_t * info) { @@ -164,23 +164,23 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) #endif { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr); /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090; udelay(1000); value = addr2[0]; DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; default: @@ -228,13 +228,13 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); info->protect[i] = addr2[2] & 1; } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; return (info->size); } @@ -242,14 +242,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_32(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (CFG_FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -262,7 +262,7 @@ static int wait_for_DQ7_32(flash_info_t * info, int sect) return 0; } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV int flash_erase(flash_info_t * info, int s_first, int s_last) { if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { @@ -277,8 +277,8 @@ static int flash_erase_32(flash_info_t * info, int s_first, int s_last) int flash_erase(flash_info_t * info, int s_first, int s_last) #endif { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; if ((s_first < 0) || (s_first > s_last)) { @@ -313,14 +313,14 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ l_sect = sect; /* @@ -342,8 +342,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); return 0; @@ -423,7 +423,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV static int write_word(flash_info_t * info, ulong dest, ulong data) { if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) { @@ -438,9 +438,9 @@ static int write_word_32(flash_info_t * info, ulong dest, ulong data) static int write_word(flash_info_t * info, ulong dest, ulong data) #endif { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i, flag; @@ -448,13 +448,13 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) if ((*((vu_long *)dest) & data) != data) return (2); - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0; dest2[i] = data2[i]; @@ -464,10 +464,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != - (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1); } } @@ -475,10 +475,10 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) return (0); } -#ifdef CFG_FLASH_2ND_16BIT_DEV +#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV -#undef CFG_FLASH_WORD_SIZE -#define CFG_FLASH_WORD_SIZE unsigned short +#undef CONFIG_SYS_FLASH_WORD_SIZE +#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* * The following code cannot be run from FLASH! @@ -486,29 +486,29 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) { short i; - CFG_FLASH_WORD_SIZE value; + CONFIG_SYS_FLASH_WORD_SIZE value; ulong base = (ulong) addr; - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr; DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr); /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* Write auto select command: read Manufacturer ID */ - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90009000; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000; udelay(1000); value = swap16(addr2[0]); DEBUGF("FLASH MANUFACT: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT: info->flash_id = FLASH_MAN_FUJ; break; default: @@ -522,12 +522,12 @@ static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) DEBUGF("\nFLASH DEVICEID: %x\n", value); switch (value) { - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B: info->flash_id += FLASH_AM320B; info->sector_count = 71; info->size = 0x00400000; break; /* => 4 MB */ - case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T: info->flash_id += FLASH_AM320T; info->sector_count = 71; info->size = 0x00400000; @@ -569,13 +569,13 @@ static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) for (i = 0; i < info->sector_count; i++) { /* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* D0 = 1 if protected */ - addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]); info->protect[i] = addr2[2] & 1; } /* issue bank reset to return to read mode */ - addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; return (info->size); } @@ -583,14 +583,14 @@ static ulong flash_get_size_16(vu_long * addr, flash_info_t * info) static int wait_for_DQ7_16(flash_info_t * info, int sect) { ulong start, now, last; - volatile CFG_FLASH_WORD_SIZE *addr = - (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = + (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); start = get_timer(0); last = start; - while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x80008000) != - (CFG_FLASH_WORD_SIZE) 0x80008000) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != + (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; } @@ -605,8 +605,8 @@ static int wait_for_DQ7_16(flash_info_t * info, int sect) static int flash_erase_16(flash_info_t * info, int s_first, int s_last) { - volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *addr2; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2; int flag, prot, sect, l_sect; if ((s_first < 0) || (s_first > s_last)) { @@ -641,14 +641,14 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) /* Start erase on unprotected sectors */ for (sect = s_first; sect <= s_last; sect++) { if (info->protect[sect] == 0) { /* not protected */ - addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]); - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80008000; - addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000; + addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */ l_sect = sect; /* @@ -670,8 +670,8 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) udelay(1000); /* reset to read mode */ - addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; - addr[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ + addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */ printf(" done\n"); return 0; @@ -679,27 +679,27 @@ static int flash_erase_16(flash_info_t * info, int s_first, int s_last) static int write_word_16(flash_info_t * info, ulong dest, ulong data) { - volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); - volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; - volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]); + volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest; + volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data; ulong start; int i; /* Check if Flash is (sufficiently) erased */ - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { if ((dest2[i] & swap16(data2[i])) != swap16(data2[i])) return (2); } - for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) { int flag; /* Disable interrupts which might cause a timeout here */ flag = disable_interrupts(); - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00; - addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500; - addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA000A000; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00; + addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500; + addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000; dest2[i] = swap16(data2[i]); @@ -709,10 +709,10 @@ static int write_word_16(flash_info_t * info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer(0); - while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80008000) != - (swap16(data2[i]) & (CFG_FLASH_WORD_SIZE) 0x80008000)) { + while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) != + (swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -720,7 +720,7 @@ static int write_word_16(flash_info_t * info, ulong dest, ulong data) return (0); } -#endif /* CFG_FLASH_2ND_16BIT_DEV */ +#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */ /*----------------------------------------------------------------------- * Functions @@ -734,7 +734,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data); unsigned long flash_init(void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; @@ -742,7 +742,7 @@ unsigned long flash_init(void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -765,16 +765,16 @@ unsigned long flash_init(void) } /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, &flash_info[i]); -#if defined(CFG_ENV_IS_IN_FLASH) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, +#if defined(CONFIG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); -#if defined(CFG_ENV_ADDR_REDUND) - (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, +#if defined(CONFIG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, &flash_info[i]); #endif #endif diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index fd1e68bbb..5483fcaf7 100644 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c @@ -165,9 +165,9 @@ static void i2s_init(void) psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE); psc->sicr = 0x22E00000; /* 16 bit data; I2S */ - *(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK + *(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK * 5.617 MHz */ - *(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable + *(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable * register */ psc->ccr = 0x1F03; /* 16 bit data width; 5.617MHz MCLK */ psc->ctur = 0x0F; /* 16 bit frame width */ @@ -751,9 +751,9 @@ int can_init(void) static int init_done = 0; int i; struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); /* GPIO configuration of the CAN pins is done in TQM5200.h */ @@ -896,9 +896,9 @@ int do_can(char *argv[]) { int i; struct mpc5xxx_mscan *can1 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900); struct mpc5xxx_mscan *can2 = - (struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980); + (struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980); /* send a message on CAN1 */ can1->cantbsel = 0x01; diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index 8b8e46137..faa2e0219 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -32,6 +32,7 @@ #include <pci.h> #include <asm/processor.h> #include <libfdt.h> +#include <netdev.h> #ifdef CONFIG_VIDEO_SM501 #include <sm501.h> @@ -53,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; void ps2mult_early_init(void); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -100,7 +101,7 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -110,7 +111,7 @@ phys_size_t initdram (int board_type) ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -131,9 +132,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -160,10 +161,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000); } if (test1 > test2) { sdram_start(0); @@ -185,7 +186,7 @@ phys_size_t initdram (int board_type) *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ } -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -202,7 +203,7 @@ phys_size_t initdram (int board_type) } else { dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the @@ -405,7 +406,7 @@ int board_early_init_r (void) ps2mult_early_init(); #endif /* CONFIG_PS2MULT */ -#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) /* Low level USB init, required for proper kernel operation */ usb_cpu_init(); #endif @@ -463,34 +464,34 @@ int last_stage_init (void) */ /* save original SRAM content */ - save = *(volatile u16 *)CFG_CS2_START; + save = *(volatile u16 *)CONFIG_SYS_CS2_START; restore = 1; /* write test pattern to SRAM */ - *(volatile u16 *)CFG_CS2_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in SRAM detection\n"); - if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) { /* no SRAM at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18); *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF; *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF; restore = 0; __asm__ volatile ("sync"); - } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) { + } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) { /* make sure that we access a mirrored address */ - *(volatile u16 *)CFG_CS2_START = 0x1111; + *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111; __asm__ volatile ("sync"); - if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) { + if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) { /* SRAM size = 512 kByte */ - *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START, + *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, 0x80000); __asm__ volatile ("sync"); puts ("SRAM: 512 kB\n"); @@ -502,7 +503,7 @@ int last_stage_init (void) } /* restore origianl SRAM content */ if (restore) { - *(volatile u16 *)CFG_CS2_START = save; + *(volatile u16 *)CONFIG_SYS_CS2_START = save; __asm__ volatile ("sync"); } @@ -512,21 +513,21 @@ int last_stage_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller at all, disable cs */ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17); *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF; @@ -538,7 +539,7 @@ int last_stage_init (void) } /* restore origianl FB content */ if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } @@ -678,21 +679,21 @@ unsigned int board_video_init (void) */ /* save origianl FB content */ - save = *(volatile u16 *)CFG_CS1_START; + save = *(volatile u16 *)CONFIG_SYS_CS1_START; restore = 1; /* write test pattern to FB memory */ - *(volatile u16 *)CFG_CS1_START = 0xA5A5; + *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5; __asm__ volatile ("sync"); /* * Put a different pattern on the data lines: otherwise they may float * long enough to read back what we wrote. */ - tmp = *(volatile u16 *)CFG_FLASH_BASE; + tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE; if (tmp == 0xA5A5) puts ("!! possible error in grafic controller detection\n"); - if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) { + if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) { /* no grafic controller found */ restore = 0; ret = 0; @@ -701,7 +702,7 @@ unsigned int board_video_init (void) } if (restore) { - *(volatile u16 *)CFG_CS1_START = save; + *(volatile u16 *)CONFIG_SYS_CS1_START = save; __asm__ volatile ("sync"); } return ret; @@ -749,3 +750,9 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Built in FEC comes first */ + return pci_eth_init(bis); +} diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile index 61221fdca..94ba1e94e 100644 --- a/board/tqc/tqm8260/Makefile +++ b/board/tqc/tqm8260/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o ../tqm8xx/load_sernum_ethaddr.o +COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqc/tqm8260/config.mk b/board/tqc/tqm8260/config.mk index 1fe99524c..3ecfc4876 100644 --- a/board/tqc/tqm8260/config.mk +++ b/board/tqc/tqm8260/config.mk @@ -25,7 +25,7 @@ # TQM8260 boards # -# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c deleted file mode 100644 index 056fe810b..000000000 --- a/board/tqc/tqm8260/flash.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * (C) Copyright 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Flash Routines for AMD devices on the TQM8260 board - * - *-------------------------------------------------------------------- - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <mpc8xx.h> - -#define V_ULONG(a) (*(volatile unsigned long *)( a )) -#define V_BYTE(a) (*(volatile unsigned char *)( a )) - - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; - - -/*----------------------------------------------------------------------- - */ -void flash_reset (void) -{ - if (flash_info[0].flash_id != FLASH_UNKNOWN) { - V_ULONG (flash_info[0].start[0]) = 0x00F000F0; - V_ULONG (flash_info[0].start[0] + 4) = 0x00F000F0; - } -} - -/*----------------------------------------------------------------------- - */ -ulong flash_get_size (ulong baseaddr, flash_info_t * info) -{ - short i; - unsigned long flashtest_h, flashtest_l; - - /* Write auto select command sequence and test FLASH answer */ - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + ((ulong) 0x0555 << 3)) = 0x00900090; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00AA00AA; - V_ULONG (baseaddr + 4 + ((ulong) 0x02AA << 3)) = 0x00550055; - V_ULONG (baseaddr + 4 + ((ulong) 0x0555 << 3)) = 0x00900090; - - flashtest_h = V_ULONG (baseaddr); /* manufacturer ID */ - flashtest_l = V_ULONG (baseaddr + 4); - - switch ((int) flashtest_h) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - flashtest_h = V_ULONG (baseaddr + 8); /* device ID */ - flashtest_l = V_ULONG (baseaddr + 12); - if (flashtest_h != flashtest_l) { - info->flash_id = FLASH_UNKNOWN; - } else { - switch (flashtest_h) { - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; - break; /* 4 * 1 MB = 4 MB */ - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00800000; - break; /* 4 * 2 MB = 8 MB */ - case AMD_ID_DL322T: - info->flash_id += FLASH_AMDL322T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL322B: - info->flash_id += FLASH_AMDL322B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323T: - info->flash_id += FLASH_AMDL323T; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_DL323B: - info->flash_id += FLASH_AMDL323B; - info->sector_count = 71; - info->size = 0x01000000; - break; /* 4 * 4 MB = 16 MB */ - case AMD_ID_LV640U: - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x02000000; - break; /* 4 * 8 MB = 32 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* no or unknown flash */ - } - } - - if (flashtest_h == AMD_ID_LV640U) { - - /* set up sector start adress table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = baseaddr + (i * 0x00040000); - - } else if (info->flash_id & FLASH_BTYPE) { - - /* set up sector start adress table (bottom sector type) */ - info->start[0] = baseaddr + 0x00000000; - info->start[1] = baseaddr + 0x00010000; - info->start[2] = baseaddr + 0x00018000; - info->start[3] = baseaddr + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = baseaddr + (i * 0x00040000) - 0x000C0000; - } - - } else { - - /* set up sector start adress table (top sector type) */ - i = info->sector_count - 1; - info->start[i--] = baseaddr + info->size - 0x00010000; - info->start[i--] = baseaddr + info->size - 0x00018000; - info->start[i--] = baseaddr + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = baseaddr + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - if ((V_ULONG (info->start[i] + 16) & 0x00010001) || - (V_ULONG (info->start[i] + 20) & 0x00010001)) { - info->protect[i] = 1; /* D0 = 1 if protected */ - } else { - info->protect[i] = 0; - } - } - - flash_reset (); - return (info->size); -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size_b0 = 0; - int i; - - /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here (only one bank) */ - - size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]); - if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0 >> 20); - } - - /* - * protect monitor and environment sectors - */ - -#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE -# endif - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); -#endif - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM800T: - printf ("29LV800T (8 M, top sector)\n"); - break; - case FLASH_AM800B: - printf ("29LV800T (8 M, bottom sector)\n"); - break; - case FLASH_AM160T: - printf ("29LV160T (16 M, top sector)\n"); - break; - case FLASH_AM160B: - printf ("29LV160B (16 M, bottom sector)\n"); - break; - case FLASH_AMDL322T: - printf ("29DL322T (32 M, top sector)\n"); - break; - case FLASH_AMDL322B: - printf ("29DL322B (32 M, bottom sector)\n"); - break; - case FLASH_AMDL323T: - printf ("29DL323T (32 M, top sector)\n"); - break; - case FLASH_AMDL323B: - printf ("29DL323B (32 M, bottom sector)\n"); - break; - case FLASH_AM640U: - printf ("29LV640D (64 M, uniform sector)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect]) - prot++; - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00800080; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - udelay (1000); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - V_ULONG (info->start[sect]) = 0x00300030; - V_ULONG (info->start[sect] + 4) = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 || - (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080) - { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - serial_putc ('.'); - last = now; - } - } - - DONE: - /* reset to read mode */ - flash_reset (); - - printf (" done\n"); - return 0; -} - -static int write_dword (flash_info_t *, ulong, unsigned char *); - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong dp; - static unsigned char bb[8]; - int i, l, rc, cc = cnt; - - dp = (addr & ~7); /* get lower dword aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - dp) != 0) { - for (i = 0; i < 8; i++) - bb[i] = (i < l || (i - l) >= cc) ? V_BYTE (dp + i) : *src++; - if ((rc = write_dword (info, dp, bb)) != 0) { - return (rc); - } - dp += 8; - cc -= 8 - l; - } - - /* - * handle word aligned part - */ - while (cc >= 8) { - if ((rc = write_dword (info, dp, src)) != 0) { - return (rc); - } - dp += 8; - src += 8; - cc -= 8; - } - - if (cc <= 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - for (i = 0; i < 8; i++) { - bb[i] = (i < cc) ? *src++ : V_BYTE (dp + i); - } - return (write_dword (info, dp, bb)); -} - -/*----------------------------------------------------------------------- - * Write a dword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_dword (flash_info_t * info, ulong dest, unsigned char *pdata) -{ - ulong start, cl, ch; - int flag, i; - - for (ch = 0, i = 0; i < 4; i++) - ch = (ch << 8) + *pdata++; /* high word */ - for (cl = 0, i = 0; i < 4; i++) - cl = (cl << 8) + *pdata++; /* low word */ - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *) dest) & ch) != ch - || (*((vu_long *) (dest + 4)) & cl) != cl) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest) = ch; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00AA00AA; - V_ULONG (info->start[0] + 4 + (0x02AA << 3)) = 0x00550055; - V_ULONG (info->start[0] + 4 + (0x0555 << 3)) = 0x00A000A0; - V_ULONG (dest + 4) = cl; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); - - /* data polling for D7 */ - start = get_timer (0); - while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) || - ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c index f201045d9..3039999f3 100644 --- a/board/tqc/tqm8260/tqm8260.c +++ b/board/tqc/tqm8260/tqm8260.c @@ -236,7 +236,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; @@ -261,7 +261,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -272,7 +272,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -285,10 +285,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif long psize, lsize; @@ -296,8 +296,8 @@ phys_size_t initdram (int board_type) psize = 16 * 1024 * 1024; lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; #if 0 /* Just for debugging */ #define prt_br_or(brX,orX) do { \ @@ -315,37 +315,37 @@ phys_size_t initdram (int board_type) prt_br_or (br3, or3); #endif -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); if (size8 < size9) { psize = size9; printf ("(60x:9COL - %ld MB, ", psize >> 20); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE); printf ("(60x:8COL - %ld MB, ", psize >> 20); } /* Local SDRAM setup: */ -#ifdef CFG_INIT_LOCAL_SDRAM - memctl->memc_lsrt = CFG_LSRT; - size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, +#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM + memctl->memc_lsrt = CONFIG_SYS_LSRT; + size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); - size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL, + size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL, (uchar *) SDRAM_BASE2_PRELIM); if (size8 < size9) { lsize = size9; printf ("Local:9COL - %ld MB) using ", lsize >> 20); } else { - lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL, + lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL, (uchar *) SDRAM_BASE2_PRELIM); printf ("Local:8COL - %ld MB) using ", lsize >> 20); } @@ -354,11 +354,11 @@ phys_size_t initdram (int board_type) /* Set up BR2 so that the local SDRAM goes * right after the 60x SDRAM */ - memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) | - (CFG_SDRAM_BASE + psize); + memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) | + (CONFIG_SYS_SDRAM_BASE + psize); #endif -#endif /* CFG_INIT_LOCAL_SDRAM */ -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile index 673026351..c97fe1496 100644 --- a/board/tqc/tqm8272/Makefile +++ b/board/tqc/tqm8272/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o +COBJS = $(BOARD).o ../tqm8xx/load_sernum_ethaddr.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqc/tqm8272/config.mk b/board/tqc/tqm8272/config.mk index af7a81e33..05c5f0cb8 100644 --- a/board/tqc/tqm8272/config.mk +++ b/board/tqc/tqm8272/config.mk @@ -25,7 +25,7 @@ # TQM8272 boards # -# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h +# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h # for the "final" configuration, with U-Boot in flash, or the address # in RAM where U-Boot is loaded at for debugging. # diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c new file mode 100644 index 000000000..8c8341b5a --- /dev/null +++ b/board/tqc/tqm8272/nand.c @@ -0,0 +1,276 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ioports.h> +#include <mpc8260.h> + +#include "tqm8272.h" + +/* UPM pattern for bus clock = 66.7 MHz */ +static const uint upmTable67[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 100 MHz */ +static const uint upmTable100[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, + /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 133.3 MHz */ +static const uint upmTable133[] = +{ + /* Offset UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> unused */ + /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ + /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, + /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +static int chipsel = 0; + +#if defined(CONFIG_CMD_NAND) + +#include <nand.h> +#include <linux/mtd/mtd.h> + +static u8 hwctl = 0; + +static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); + + if (hwctl & 0x1) { + WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS); + } else if (hwctl & 0x2) { + WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS); + } else { + WRITE_NAND(byte, base); + } +} + +static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + if ( ctrl & NAND_CLE ) + hwctl |= 0x1; + else + hwctl &= ~0x1; + if ( ctrl & NAND_ALE ) + hwctl |= 0x2; + else + hwctl &= ~0x2; + } + if (cmd != NAND_CMD_NONE) + upmnand_write_byte (mtd, cmd); +} + +static u_char upmnand_read_byte(struct mtd_info *mtdinfo) +{ + struct nand_chip *this = mtdinfo->priv; + ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); + + return READ_NAND(base); +} + +static int tqm8272_dev_ready(struct mtd_info *mtdinfo) +{ + /* constant delay (see also tR in the datasheet) */ + udelay(12); \ + return 1; +} + +#ifndef CONFIG_NAND_SPL +static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); + int i; + + for (i = 0; i< len; i++) + buf[i] = *base; +} + +static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); + int i; + + for (i = 0; i< len; i++) + *base = buf[i]; +} + +static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) +{ + struct nand_chip *this = mtdinfo->priv; + unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST); + int i; + + for (i = 0; i < len; i++) + if (buf[i] != *base) + return -1; + return 0; +} +#endif /* #ifndef CONFIG_NAND_SPL */ + +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + chipsel = chip; +} + +int board_nand_init(struct nand_chip *nand) +{ + static int UpmInit = 0; + volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; + volatile memctl8260_t *memctl = &immr->im_memctl; + + if (hwinf.nand == 0) return -1; + + /* Setup the UPM */ + if (UpmInit == 0) { + switch (hwinf.busclk_real) { + case 100000000: + upmconfig (UPMB, (uint *) upmTable100, + sizeof (upmTable100) / sizeof (uint)); + break; + case 133333333: + upmconfig (UPMB, (uint *) upmTable133, + sizeof (upmTable133) / sizeof (uint)); + break; + default: + upmconfig (UPMB, (uint *) upmTable67, + sizeof (upmTable67) / sizeof (uint)); + break; + } + UpmInit = 1; + } + + /* Setup the memctrl */ + memctl->memc_or3 = CONFIG_SYS_NAND_OR; + memctl->memc_br3 = CONFIG_SYS_NAND_BR; + memctl->memc_mbmr = (MxMR_OP_NORM); + + nand->ecc.mode = NAND_ECC_SOFT; + + nand->cmd_ctrl = upmnand_hwcontrol; + nand->read_byte = upmnand_read_byte; + nand->dev_ready = tqm8272_dev_ready; + +#ifndef CONFIG_NAND_SPL + nand->write_buf = tqm8272_write_buf; + nand->read_buf = tqm8272_read_buf; + nand->verify_buf = tqm8272_verify_buf; +#endif + + /* + * Select required NAND chip + */ + board_nand_select_device(nand, 0); + return 0; +} + +#endif diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index a0ec254ce..5d0741d80 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -26,10 +26,12 @@ #include <mpc8260.h> #include <command.h> +#include <netdev.h> #ifdef CONFIG_PCI #include <pci.h> #include <asm/m8260_pci.h> #endif +#include "tqm8272.h" #if 0 #define deb_printf(fmt,arg...) \ @@ -207,112 +209,6 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -#define _NOT_USED_ 0xFFFFFFFF - -/* UPM pattern for bus clock = 66.7 MHz */ -static const uint upmTable67[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f100, 0x0fa3b000, 0x0fa33100, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, 0x00a3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 100 MHz */ -static const uint upmTable100[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f200, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33000, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fc00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fc00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -/* UPM pattern for bus clock = 133.3 MHz */ -static const uint upmTable133[] = -{ - /* Offset UPM Read Single RAM array entry -> NAND Read Data */ - /* 0x00 */ 0x0fa3f300, 0x0fa3b000, 0x0fa33300, 0x0fa33000, - /* 0x04 */ 0x0fa33200, 0x0fa33004, 0xfffffc01, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x08 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Read Burst RAM array entry -> unused */ - /* 0x10 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - - /* UPM Write Single RAM array entry -> NAND Write Data, ADDR and CMD */ - /* 0x18 */ 0x00a3ff00, 0x00a3fc00, 0x00a3fd00, 0x0fa3fc00, - /* 0x1C */ 0x0fa3fd00, 0x0fa3fc04, 0xfffffc01, 0xfffffc00, - - /* UPM Write Burst RAM array entry -> unused */ - /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Refresh Timer RAM array entry -> unused */ - /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, - /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, - - /* UPM Exception RAM array entry -> unsused */ - /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, -}; - -static int chipsel = 0; - /* UPM pattern for slow init */ static const uint upmTableSlow[] = { @@ -391,7 +287,7 @@ int checkboard (void) char *p = (char *) HWIB_INFO_START_ADDR; puts ("Board: "); - if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { puts (p); } else { puts ("No HWIB assuming TQM8272"); @@ -431,7 +327,7 @@ static ulong set_sdram_timing (volatile uint *sdmr_ptr, ulong sdmr, int col) { #if defined(CONFIG_BOARD_GET_CPU_CLK_F) int clk = board_get_cpu_clk_f (); - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; int busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0); int cas; @@ -508,7 +404,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, */ maxsize = (1 + (~orx | 0x7fff)) / 2; - /* Since CFG_SDRAM_BASE is always 0 (??), we assume that + /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that * we are configuring CS1 if base != 0 */ sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr; @@ -533,7 +429,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, * accessing the SDRAM with a single-byte transaction." * * The appropriate BRx/ORx registers have already been set when we - * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. */ *sdmr_ptr = sdmr | PSDMR_OP_PREA; @@ -544,7 +440,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, *base = c; *sdmr_ptr = sdmr | PSDMR_OP_MRW; - *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; *base = c; @@ -557,10 +453,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT long size8, size9; #endif long psize, lsize; @@ -568,27 +464,27 @@ phys_size_t initdram (int board_type) psize = 16 * 1024 * 1024; lsize = 0; - memctl->memc_psrt = CFG_PSRT; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT /* 60x SDRAM setup: */ - size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE, 8); - size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL, - (uchar *) CFG_SDRAM_BASE, 9); + size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE, 8); + size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL, + (uchar *) CONFIG_SYS_SDRAM_BASE, 9); if (size8 < size9) { psize = size9; printf ("(60x:9COL - %ld MB, ", psize >> 20); } else { - psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL, - (uchar *) CFG_SDRAM_BASE, 8); + psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL, + (uchar *) CONFIG_SYS_SDRAM_BASE, 8); printf ("(60x:8COL - %ld MB, ", psize >> 20); } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ icache_enable (); @@ -615,35 +511,10 @@ static inline int scanChar (char *p, int len, unsigned long *number) return akt; } -typedef struct{ - int Bus; - int flash; - int flash_nr; - int ram; - int ram_cs; - int nand; - int nand_cs; - int eeprom; - int can; - unsigned long cpunr; - unsigned long option; - int SecEng; - int cpucl; - int cpmcl; - int buscl; - int busclk_real_ok; - int busclk_real; - unsigned char OK; - unsigned char ethaddr[20]; -} HWIB_INFO; - -HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, - 0, 0, 0, 0, 0, 0}; - static int dump_hwib(void) { HWIB_INFO *hw = &hwinf; - volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; char *s = getenv("serial#"); if (hw->OK) { @@ -736,7 +607,7 @@ int analyse_hwib (void) deb_printf(" %s pointer: %p\n", __FUNCTION__, p); /* Head = TQM */ - if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { deb_printf("No HWIB\n"); return -1; } @@ -833,7 +704,7 @@ int analyse_hwib (void) hw->OK = 1; /* search MAC Address */ - while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) { + while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) { if (*p < ' ' || *p > '~') { /* ASCII strings! */ return 0; } @@ -873,7 +744,7 @@ char get_cpu_str_f (char *buf) buf[i++] = 'M'; buf[i++] = 'P'; buf[i++] = 'C'; - if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { buf[i++] = *&p[3]; buf[i++] = *&p[4]; buf[i++] = *&p[5]; @@ -896,7 +767,7 @@ unsigned long board_get_cpu_clk_f (void) char *p = (char *) HWIB_INFO_START_ADDR; int i = 0; - if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { if (search_real_busclk (&i)) return i; } @@ -908,7 +779,7 @@ unsigned long board_get_cpu_clk_f (void) static int can_test (unsigned long off) { - volatile unsigned char *base = (unsigned char *) (CFG_CAN_BASE + off); + volatile unsigned char *base = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); *(base + 0x17) = 'T'; *(base + 0x18) = 'Q'; @@ -923,9 +794,9 @@ static int can_test (unsigned long off) static int can_config_one (unsigned long off) { - volatile unsigned char *ctrl = (unsigned char *) (CFG_CAN_BASE + off); - volatile unsigned char *cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02); - volatile unsigned char *clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f); + volatile unsigned char *ctrl = (unsigned char *) (CONFIG_SYS_CAN_BASE + off); + volatile unsigned char *cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02); + volatile unsigned char *clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f); unsigned char temp; *cpu_if = 0x45; @@ -954,13 +825,13 @@ static int can_config (void) static int init_can (void) { - volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; int count = 0; if ((hwinf.OK) && (hwinf.can)) { - memctl->memc_or4 = CFG_CAN_OR; - memctl->memc_br4 = CFG_CAN_BR; + memctl->memc_or4 = CONFIG_SYS_CAN_OR; + memctl->memc_br4 = CONFIG_SYS_CAN_BR; /* upm Init */ upmconfig (UPMC, (uint *) upmTableFast, sizeof (upmTableFast) / sizeof (uint)); @@ -971,7 +842,7 @@ static int init_can (void) MxMR_OP_NORM); /* can configure */ count = can_config (); - printf ("CAN: %d @ %x\n", count, CFG_CAN_BASE); + printf ("CAN: %d @ %x\n", count, CONFIG_SYS_CAN_BASE); if (hwinf.can != count) printf("!!! difference to HWIB\n"); } else { printf ("CAN: No\n"); @@ -999,7 +870,7 @@ U_BOOT_CMD( "\n" ); -#ifdef CFG_UPDATE_FLASH_SIZE +#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE static int get_flash_timing (void) { /* get it from the option -tf in CIB */ @@ -1044,7 +915,7 @@ static int get_flash_timing (void) /* Update the Flash_Size and the Flash Timing */ int update_flash_size (int flash_size) { - volatile immap_t * immr = (immap_t *)CFG_IMMR; + volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immr->im_memctl; unsigned long reg; unsigned long tim; @@ -1061,159 +932,12 @@ int update_flash_size (int flash_size) } #endif -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> -#include <linux/mtd/mtd.h> - -static u8 hwctl = 0; - -static void upmnand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - - if (hwctl & 0x1) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS); - } else if (hwctl & 0x2) { - WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS); - } else { - WRITE_NAND(byte, base); - } -} - -static u_char upmnand_read_byte(struct mtd_info *mtdinfo) -{ - struct nand_chip *this = mtdinfo->priv; - ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - - return READ_NAND(base); -} - -static int tqm8272_dev_ready(struct mtd_info *mtdinfo) -{ - /* constant delay (see also tR in the datasheet) */ - udelay(12); \ - return 1; -} - -#ifndef CONFIG_NAND_SPL -static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - buf[i] = *base; -} - -static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - int i; - - for (i = 0; i< len; i++) - *base = buf[i]; -} - -static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) -{ - struct nand_chip *this = mtdinfo->priv; - unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST); - int i; - - for (i = 0; i < len; i++) - if (buf[i] != *base) - return -1; - return 0; -} -#endif /* #ifndef CONFIG_NAND_SPL */ - -void board_nand_select_device(struct nand_chip *nand, int chip) -{ - chipsel = chip; -} - -int board_nand_init(struct nand_chip *nand) -{ - static int UpmInit = 0; - volatile immap_t * immr = (immap_t *)CFG_IMMR; - volatile memctl8260_t *memctl = &immr->im_memctl; - - if (hwinf.nand == 0) return -1; - - /* Setup the UPM */ - if (UpmInit == 0) { - switch (hwinf.busclk_real) { - case 100000000: - upmconfig (UPMB, (uint *) upmTable100, - sizeof (upmTable100) / sizeof (uint)); - break; - case 133333333: - upmconfig (UPMB, (uint *) upmTable133, - sizeof (upmTable133) / sizeof (uint)); - break; - default: - upmconfig (UPMB, (uint *) upmTable67, - sizeof (upmTable67) / sizeof (uint)); - break; - } - UpmInit = 1; - } - - /* Setup the memctrl */ - memctl->memc_or3 = CFG_NAND_OR; - memctl->memc_br3 = CFG_NAND_BR; - memctl->memc_mbmr = (MxMR_OP_NORM); - - nand->ecc.mode = NAND_ECC_SOFT; - - nand->cmd_ctrl = upmnand_hwcontrol; - nand->read_byte = upmnand_read_byte; - nand->write_byte = upmnand_write_byte; - nand->dev_ready = tqm8272_dev_ready; - -#ifndef CONFIG_NAND_SPL - nand->write_buf = tqm8272_write_buf; - nand->read_buf = tqm8272_read_buf; - nand->verify_buf = tqm8272_verify_buf; -#endif - - /* - * Select required NAND chip - */ - board_nand_select_device(nand, 0); - return 0; -} - -#endif - #ifdef CONFIG_PCI struct pci_controller hose; int board_early_init_f (void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN; return 0; @@ -1226,3 +950,8 @@ void pci_init_board(void) pci_mpc8250_init(&hose); } #endif + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/freescale/common/cds_eeprom.c b/board/tqc/tqm8272/tqm8272.h index 5034e0ca2..6d558ec59 100644 --- a/board/freescale/common/cds_eeprom.c +++ b/board/tqc/tqm8272/tqm8272.h @@ -1,5 +1,6 @@ /* - * Copyright 2004 Freescale Semiconductor. + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -20,41 +21,33 @@ * MA 02111-1307 USA */ - -#include <common.h> -#include <i2c.h> - -#include "eeprom.h" - - -typedef struct { - char idee_pcbid[4]; /* "CCID" for CDC v1.X */ - u8 idee_major; - u8 idee_minor; - char idee_serial[10]; - char idee_errata[2]; - char idee_date[8]; /* yyyymmdd */ - /* The rest of the EEPROM space is reserved */ -} id_eeprom_t; - - -unsigned int -get_cpu_board_revision(void) -{ - uint major = 0; - uint minor = 0; - - id_eeprom_t id_eeprom; - - i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, - (uchar *) &id_eeprom, sizeof(id_eeprom)); - - major = id_eeprom.idee_major; - minor = id_eeprom.idee_minor; - - if (major == 0xff && minor == 0xff) { - major = minor = 0; - } - - return MPC85XX_CPU_BOARD_REV(major,minor); -} +#ifndef _TQM8272_HEADER_H +#define _TQM8272_HEADER_H + +#define _NOT_USED_ 0xFFFFFFFF + +typedef struct{ + int Bus; + int flash; + int flash_nr; + int ram; + int ram_cs; + int nand; + int nand_cs; + int eeprom; + int can; + unsigned long cpunr; + unsigned long option; + int SecEng; + int cpucl; + int cpmcl; + int buscl; + int busclk_real_ok; + int busclk_real; + unsigned char OK; + unsigned char ethaddr[20]; +} HWIB_INFO; + +static HWIB_INFO hwinf = {0, 0, 1, 0, 1, 0, 0, 0, 0, 8272, 0 ,0, + 0, 0, 0, 0, 0, 0}; +#endif diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index e3d0309d9..0eedf4ae4 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -29,8 +29,8 @@ #ifdef CONFIG_PCI /* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) #ifndef CONFIG_PCI_PNP @@ -78,7 +78,7 @@ pci_init_board(void) u32 reg32; struct pci_controller * hose; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -128,10 +128,10 @@ pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; /* @@ -139,13 +139,13 @@ pci_init_board(void) */ /* PCI1 mem space */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); /* @@ -164,16 +164,16 @@ pci_init_board(void) /* PCI memory space */ pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 1, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ @@ -186,8 +186,8 @@ pci_init_board(void) hose->region_count = 3; pci_setup_indirect(hose, - (CFG_IMMR+0x8300), - (CFG_IMMR+0x8304)); + (CONFIG_SYS_IMMR+0x8300), + (CONFIG_SYS_IMMR+0x8304)); pci_register_hose(hose); diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 278780dde..106cac244 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -67,7 +67,7 @@ static void set_cs_config(short cs, long config); static void set_ddr_config(void); /* Local variable */ -static volatile immap_t *im = (immap_t *)CFG_IMMR; +static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; /************************************************************************** * Board initialzation after relocation to RAM. Used to detect the number @@ -92,13 +92,13 @@ phys_size_t initdram (int board_type) int cs; /* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); /* set CS bounds to maximum size */ for(cs = 0; cs < 4; ++cs) { set_cs_bounds(cs, - CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), DDR_MAX_SIZE_PER_CS); set_cs_config(cs, INITIAL_CS_CONFIG); @@ -122,7 +122,7 @@ phys_size_t initdram (int board_type) debug("\nDetecting Bank%d\n", cs); bank_size = get_ddr_bank_size(cs, - (volatile long*)(CFG_DDR_BASE + size)); + (volatile long*)(CONFIG_SYS_DDR_BASE + size)); size += bank_size; debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20); @@ -145,7 +145,7 @@ int checkboard (void) volatile immap_t * immr; u32 w, f; - immr = (immap_t *)CFG_IMMR; + immr = (immap_t *)CONFIG_SYS_IMMR; if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { printf("PCI: NOT in host mode..?!\n"); return 0; @@ -193,9 +193,9 @@ static int detect_num_flash_banks(void) tqm834x_num_flash_banks = 2; /* assume two banks */ /* Get bank 1 and 2 information */ - bank1_size = flash_get_size(CFG_FLASH_BASE, 0); + bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0); debug("Bank1 size: %lu\n", bank1_size); - bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1); + bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1); debug("Bank2 size: %lu\n", bank2_size); total_size = bank1_size + bank2_size; @@ -203,8 +203,8 @@ static int detect_num_flash_banks(void) /* Seems like we've got bank 2, but maybe it's mirrored 1 */ /* Set the base addresses */ - bank1_base = (FPWV *) (CFG_FLASH_BASE); - bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size); + bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE); + bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size); /* Put bank 2 into CFI command mode and read */ bank2_base[0x55] = 0x00980098; @@ -253,9 +253,9 @@ static int detect_num_flash_banks(void) debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); /* set OR0 and BR0 */ - im->lbus.bank[0].or = CFG_OR_TIMING_FLASH | + im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH | (-(total_size) & OR_GPCM_AM); - im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) | + im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) | (BR_MS_GPCM | BR_PS_32 | BR_V); return (0); diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index de3ea00e3..fc92cd8b3 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -66,20 +66,20 @@ #endif struct law_entry law_table[] = { - SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), - SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #ifdef CONFIG_PCIE1 - SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), #else /* !CONFIG_PCIE1 */ - SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), #endif /* CONFIG_PCIE1 */ #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) - SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ #ifdef CONFIG_PCIE1 - SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), #endif /* CONFIG_PCIE */ }; diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c index 9c5c12c84..dea652dfd 100644 --- a/board/tqc/tqm85xx/nand.c +++ b/board/tqc/tqm85xx/nand.c @@ -41,10 +41,10 @@ DECLARE_GLOBAL_DATA_PTR; extern uint get_lbc_clock (void); /* index of UPM RAM array run pattern for NAND command cycle */ -#define CFG_NAN_UPM_WRITE_CMD_OFS 0x08 +#define CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS 0x08 /* index of UPM RAM array run pattern for NAND address cycle */ -#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x10 +#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x10 /* Structure for table with supported UPM timings */ struct upm_freq { @@ -377,7 +377,7 @@ volatile const u32 *nand_upm_patt; */ static void upmb_write (u_char addr, ulong val) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); out_be32 (&lbc->mdr, val); @@ -385,7 +385,7 @@ static void upmb_write (u_char addr, ulong val) MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); /* dummy access to perform write */ - out_8 ((void __iomem *)CFG_NAND0_BASE, 0); + out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0); clrbits_be32(&lbc->mbmr, MxMR_OP_WARR); } @@ -396,11 +396,11 @@ static void upmb_write (u_char addr, ulong val) static void nand_upm_setup (volatile ccsr_lbc_t *lbc) { uint i; - uint or3 = CFG_OR3_PRELIM; + uint or3 = CONFIG_SYS_OR3_PRELIM; uint clock = get_lbc_clock (); out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */ - out_be32 (&lbc->br3, CFG_BR3_PRELIM); + out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM); /* * Search appropriate UPM table for bus clock. @@ -455,7 +455,7 @@ void board_nand_select_device (struct nand_chip *nand, int chip) int board_nand_init (struct nand_chip *nand) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); if (!nand_upm_patt) nand_upm_setup (lbc); diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 33bc4077e..783b2809e 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -66,9 +66,9 @@ int cas_latency (void); long int sdram_setup (int casl) { int i; - volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); #ifdef CONFIG_TQM8548 - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #else /* !CONFIG_TQM8548 */ unsigned long cfg_ddr_timing1; unsigned long cfg_ddr_mode; @@ -296,7 +296,7 @@ phys_size_t initdram (int board_type) * This DLL-Override only used on TQM8540 and TQM8560 */ { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int i, x; x = 10; @@ -336,11 +336,11 @@ phys_size_t initdram (int board_type) return dram_size; } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf ("SDRAM test phase 1:\n"); diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 380448a4f..16b102d1e 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -28,19 +28,19 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024, - CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024, - CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024, - CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -50,11 +50,11 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xf8000000 128M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000, - CFG_FLASH_BASE + 0x4000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000, + CONFIG_SYS_FLASH_BASE + 0x4000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 0, BOOKE_PAGESZ_64M, 1), @@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), @@ -70,8 +70,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, - CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), @@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M PCI express MEM First half */ - SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 256M Non-cacheable, guarded * 0xd0000000 256M PCI express MEM Second half */ - SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000, - CFG_PCIE1_MEM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000, + CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), #else /* !CONFIG_PCIE */ @@ -97,7 +97,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -105,8 +105,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000, - CFG_RIO_MEM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, + CONFIG_SYS_RIO_MEM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), #endif /* CONFIG_PCIE */ @@ -117,7 +117,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe2000000 16M PCI1 IO * 0xe3000000 16M CAN and NAND Flash */ - SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), @@ -128,12 +128,12 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, - CFG_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), @@ -142,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 9: 16M Non-cacheable, guarded * 0xef000000 16M PCI express IO */ - SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_16M, 1), #endif /* CONFIG_PCIE */ @@ -154,19 +154,19 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xc0000000 1G FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000, - CFG_FLASH_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000, + CONFIG_SYS_FLASH_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000, - CFG_FLASH_BASE + 0x20000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000, + CONFIG_SYS_FLASH_BASE + 0x20000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000, - CFG_FLASH_BASE + 0x30000000, + SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000, + CONFIG_SYS_FLASH_BASE + 0x30000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 0, BOOKE_PAGESZ_256M, 1), @@ -174,7 +174,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 4: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), @@ -182,8 +182,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 5: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, - CFG_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), @@ -192,7 +192,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 256M Non-cacheable, guarded * 0xc0000000 256M PCI express MEM First half */ - SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), #else /* !CONFIG_PCIE */ @@ -200,7 +200,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 256M Non-cacheable, guarded * 0xb0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_256M, 1), @@ -212,7 +212,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xa2000000 16M PCI1 IO * 0xa3000000 16M CAN and NAND Flash */ - SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1), @@ -223,12 +223,12 @@ struct fsl_e_tlb_entry tlb_table[] = { * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, - CFG_DDR_SDRAM_BASE + 0x10000000, + SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 9, BOOKE_PAGESZ_256M, 1), @@ -237,7 +237,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 10: 16M Non-cacheable, guarded * 0xaf000000 16M PCI express IO */ - SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 10, BOOKE_PAGESZ_16M, 1), #endif /* CONFIG_PCIE */ diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index ae3c2456f..73f1d01bd 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -23,7 +23,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -42,6 +42,7 @@ #include <flash.h> #include <libfdt.h> #include <fdt_support.h> +#include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -268,7 +269,7 @@ int checkboard (void) int misc_init_r (void) { - volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); /* * Adjust flash start and offset to detected values @@ -281,9 +282,9 @@ int misc_init_r (void) */ if (flash_info[0].size > 0) { memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | - (CFG_OR1_PRELIM & 0x00007fff); + (CONFIG_SYS_OR1_PRELIM & 0x00007fff); memctl->br1 = gd->bd->bi_flashstart | - (CFG_BR1_PRELIM & 0x00007fff); + (CONFIG_SYS_BR1_PRELIM & 0x00007fff); /* * Re-check to get correct base address for bank 1 */ @@ -297,9 +298,9 @@ int misc_init_r (void) * If bank 1 is equipped, bank 0 is mapped after bank 1 */ memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | - (CFG_OR0_PRELIM & 0x00007fff); + (CONFIG_SYS_OR0_PRELIM & 0x00007fff); memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | - (CFG_BR0_PRELIM & 0x00007fff); + (CONFIG_SYS_BR0_PRELIM & 0x00007fff); /* * Re-check to get correct base address for bank 0 */ @@ -310,26 +311,26 @@ int misc_init_r (void) */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); /* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND /* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, + &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); #endif return 0; @@ -341,7 +342,7 @@ int misc_init_r (void) */ static void upmc_write (u_char addr, uint val) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); out_be32 (&lbc->mdr, val); @@ -349,7 +350,7 @@ static void upmc_write (u_char addr, uint val) MxMR_OP_WARR | (addr & MxMR_MAD_MSK)); /* dummy access to perform write */ - out_8 ((void __iomem *)CFG_CAN_BASE, 0); + out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0); /* normal operation */ clrbits_be32(&lbc->mcmr, MxMR_OP_WARR); @@ -358,7 +359,7 @@ static void upmc_write (u_char addr, uint val) uint get_lbc_clock (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); sys_info_t sys_info; ulong clkdiv = lbc->lcrr & 0x0f; @@ -375,7 +376,7 @@ uint get_lbc_clock (void) return sys_info.freqSystemBus / clkdiv; } - puts("Invalid clock divider value in CFG_LBC_LCRR\n"); + puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n"); return 0; } @@ -385,8 +386,8 @@ uint get_lbc_clock (void) */ void local_bus_init (void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint lbc_mhz = get_lbc_clock () / 1000000; #ifdef CONFIG_MPC8548 @@ -417,7 +418,7 @@ void local_bus_init (void) gur->lbiuiplldcr1 = dummy; } - lcrr = CFG_LBC_LCRR; + lcrr = CONFIG_SYS_LBC_LCRR; /* * Local Bus Clock > 83.3 MHz. According to timing @@ -457,18 +458,18 @@ void local_bus_init (void) * Errata LBC11. * Fix Local Bus clock glitch when DLL is enabled. * - * If localbus freq is < 66Mhz, DLL bypass mode must be used. - * If localbus freq is > 133Mhz, DLL can be safely enabled. + * If localbus freq is < 66MHz, DLL bypass mode must be used. + * If localbus freq is > 133MHz, DLL can be safely enabled. * Between 66 and 133, the DLL is enabled with an override workaround. */ if (lbc_mhz < 66) { - lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA | LTEDR_RAWA | LTEDR_CSD; /* Disable all error checking */ } else if (lbc_mhz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ } else { /* @@ -483,7 +484,7 @@ void local_bus_init (void) lbc->lcrr = 0x10000004; } - lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ + lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ udelay (200); /* @@ -502,10 +503,10 @@ void local_bus_init (void) * set if Local Bus Clock is > 83 MHz. */ if (lbc_mhz > 83) - out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD); + out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD); else - out_be32 (&lbc->or2, CFG_OR2_CAN); - out_be32 (&lbc->br2, CFG_BR2_CAN); + out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN); + out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN); /* LGPL4 is UPWAIT */ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X); @@ -537,6 +538,9 @@ void local_bus_init (void) */ static int first_free_busno; +extern int fsl_pci_setup_inbound_windows(struct pci_region *r); +extern void fsl_pci_init(struct pci_controller *hose); + #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) static struct pci_controller pci1_hose; #endif /* CONFIG_PCI || CONFIG_PCI1 */ @@ -547,12 +551,12 @@ static struct pci_controller pcie1_hose; static inline void init_pci1(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; + struct pci_region *r = hose->regions; /* PORDEVSR[15] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; @@ -577,28 +581,23 @@ static inline void init_pci1(void) /* inbound */ - pci_set_region (hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region (hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_PHYS, + CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region (hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_PHYS, + CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect (hose, (int)&pci->cfg_addr, @@ -611,7 +610,7 @@ static inline void init_pci1(void) first_free_busno = hose->last_busno + 1; #ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & PORDEVSR_PCI)) { + if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { ushort reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; @@ -635,15 +634,15 @@ static inline void init_pci1(void) static inline void init_pcie1(void) { - volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCIE1 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR; - extern void fsl_pci_init(struct pci_controller *hose); + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; @@ -659,27 +658,23 @@ static inline void init_pcie1(void) puts ("\n"); /* inbound */ - pci_set_region (hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); + r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ - pci_set_region (hose->regions + 1, - CFG_PCIE1_MEM_BASE, - CFG_PCIE1_MEM_PHYS, - CFG_PCIE1_MEM_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_PHYS, + CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ - pci_set_region (hose->regions + 2, - CFG_PCIE1_IO_BASE, - CFG_PCIE1_IO_PHYS, - CFG_PCIE1_IO_SIZE, + pci_set_region (r++, + CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_PHYS, + CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); - hose->region_count = 3; + hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int)&pci->cfg_addr, @@ -706,31 +701,19 @@ void pci_init_board (void) } #ifdef CONFIG_OF_BOARD_SETUP +extern void ft_fsl_pci_setup(void *blob, const char *pci_alias, + struct pci_controller *hose); + void ft_board_setup (void *blob, bd_t *bd) { - int node, tmp[2]; - const char *path; - ft_cpu_setup (blob, bd); - node = fdt_path_offset (blob, "/aliases"); - tmp[0] = 0; - if (node >= 0) { #if defined(CONFIG_PCI) || defined(CONFIG_PCI1) - path = fdt_getprop (blob, node, "pci0", NULL); - if (path) { - tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; - do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); - } -#endif /* CONFIG_PCI || CONFIG_PCI1 */ + ft_fsl_pci_setup(blob, "pci0", &pci1_hose); +#endif #ifdef CONFIG_PCIE1 - path = fdt_getprop (blob, node, "pci1", NULL); - if (path) { - tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; - do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); - } -#endif /* CONFIG_PCIE1 */ - } + ft_fsl_pci_setup(blob, "pci1", &pcie1_hose); +#endif } #endif /* CONFIG_OF_BOARD_SETUP */ @@ -743,3 +726,9 @@ int board_early_init_r (void) return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ + +int board_eth_init(bd_t *bis) +{ + cpu_eth_init(bis); /* Intialize TSECs first */ + return pci_eth_init(bis); +} diff --git a/board/tqc/tqm85xx/u-boot.lds b/board/tqc/tqm85xx/u-boot.lds index 8cb551ae4..b1637a516 100644 --- a/board/tqc/tqm85xx/u-boot.lds +++ b/board/tqc/tqm85xx/u-boot.lds @@ -141,6 +141,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/tqc/tqm8xx/Makefile b/board/tqc/tqm8xx/Makefile index b48934b42..280982dd4 100644 --- a/board/tqc/tqm8xx/Makefile +++ b/board/tqc/tqm8xx/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o flash.o load_sernum_ethaddr.o +COBJS = $(BOARD).o load_sernum_ethaddr.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/tqc/tqm8xx/flash.c b/board/tqc/tqm8xx/flash.c deleted file mode 100644 index 1231c7c6f..000000000 --- a/board/tqc/tqm8xx/flash.c +++ /dev/null @@ -1,834 +0,0 @@ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#if 0 -#define DEBUG -#endif - -#include <common.h> -#include <mpc8xx.h> -#include <environment.h> - -#include <asm/processor.h> - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */ - -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ - && !defined(CONFIG_TQM885D) -# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ -# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) -# endif -#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */ - -#ifndef CFG_ENV_ADDR -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - unsigned long size_b0, size_b1; - int i; - -#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ - int scy, trlx, flash_or_timing, clk_diff; - - scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; - if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { - trlx = OR_TRLX; - scy *= 2; - } else - trlx = 0; - - /* We assume that each 10MHz of bus clock require 1-clk SCY - * adjustment. - */ - clk_diff = (gd->bus_clk / 1000000) - 50; - - /* We need proper rounding here. This is what the "+5" and "-5" - * are here for. - */ - if (clk_diff >= 0) - scy += (clk_diff + 5) / 10; - else - scy += (clk_diff - 5) / 10; - - /* For bus frequencies above 50MHz, we want to use relaxed timing - * (OR_TRLX). - */ - if (gd->bus_clk >= 50000000) - trlx = OR_TRLX; - else - trlx = 0; - - if (trlx) - scy /= 2; - - if (scy > 0xf) - scy = 0xf; - if (scy < 1) - scy = 1; - - flash_or_timing = (scy << 4) | trlx | - (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); -#endif - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM); - - size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); - - debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - if (size_b1 > size_b0) { - printf ("## ERROR: " - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", - size_b1, size_b1<<20, - size_b0, size_b0<<20 - ); - flash_info[0].flash_id = FLASH_UNKNOWN; - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[0].sector_count = -1; - flash_info[1].sector_count = -1; - flash_info[0].size = 0; - flash_info[1].size = 0; - return (0); - } - - debug ("## Before remap: " - "BR0: 0x%08x OR0: 0x%08x " - "BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0, - memctl->memc_br1, memctl->memc_or1); - - /* Remap FLASH according to real size */ -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); -#else - memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK); -#endif - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; - - debug ("## BR0: 0x%08x OR0: 0x%08x\n", - memctl->memc_br0, memctl->memc_or0); - - /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - debug ("Protect monitor: %08lx ... %08lx\n", - (ulong)CFG_MONITOR_BASE, - (ulong)CFG_MONITOR_BASE + monitor_flash_len - 1); - - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ -# ifdef CFG_ENV_ADDR_REDUND - debug ("Protect primary environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR, - (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); -# else - debug ("Protect environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR, - (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1); -# endif - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - -#ifdef CFG_ENV_ADDR_REDUND - debug ("Protect redundand environment: %08lx ... %08lx\n", - (ulong)CFG_ENV_ADDR_REDUND, - (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1); - - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - if (size_b1) { -#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); -#else - memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000); -#endif - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | - BR_MS_GPCM | BR_V; - - debug ("## BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - - /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), - &flash_info[1]); - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, - &flash_info[1]); -#endif - -#ifdef CFG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - &flash_info[1]); -#endif - } else { - memctl->memc_br1 = 0; /* invalidate bank */ - - flash_info[1].flash_id = FLASH_UNKNOWN; - flash_info[1].sector_count = -1; - flash_info[1].size = 0; - - debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", - memctl->memc_br1, memctl->memc_or1); - } - - debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1); - - flash_info[0].size = size_b0; - flash_info[1].size = size_b1; - - return (size_b0 + size_b1); -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n"); - break; - case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n"); - break; -# else /* ! TQM8xxM */ - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; -#endif /* TQM8xxM */ - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00900090; - - value = addr[0]; - - debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); - - switch (value) { - case AMD_MANUFACT: - debug ("Manufacturer: AMD\n"); - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - debug ("Manufacturer: FUJITSU\n"); - info->flash_id = FLASH_MAN_FUJ; - break; - default: - debug ("Manufacturer: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[1]; /* device ID */ - - debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); - - switch (value) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case AMD_ID_MIRROR: - debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n", - addr[14], addr[15]); - /* Special case for AMLV320MH/L */ - if ((addr[14] & 0x00ff00ff) == 0x001d001d && - (addr[15] & 0x00ff00ff) == 0x00000000) { - debug ("Chip: AMLV320MH/L\n"); - info->flash_id += FLASH_AMLV320U; - info->sector_count = 64; - info->size = 0x00800000; /* => 8 MB */ - break; - } - switch(addr[14]) { - case AMD_ID_LV128U_2: - if (addr[15] != AMD_ID_LV128U_3) { - debug ("Chip: AMLV128U -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV128U\n"); - info->flash_id += FLASH_AMLV128U; - info->sector_count = 256; - info->size = 0x02000000; - } - break; /* => 32 MB */ - case AMD_ID_LV640U_2: - if (addr[15] != AMD_ID_LV640U_3) { - debug ("Chip: AMLV640U -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV640U\n"); - info->flash_id += FLASH_AMLV640U; - info->sector_count = 128; - info->size = 0x01000000; - } - break; /* => 16 MB */ - case AMD_ID_LV320B_2: - if (addr[15] != AMD_ID_LV320B_3) { - debug ("Chip: AMLV320B -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - } else { - debug ("Chip: AMLV320B\n"); - info->flash_id += FLASH_AMLV320B; - info->sector_count = 71; - info->size = 0x00800000; - } - break; /* => 8 MB */ - default: - debug ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - break; - } - break; -# else /* ! TQM8xxM */ - case AMD_ID_LV400T: - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 71; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif /* TQM8xxM */ - - case AMD_ID_LV160T: - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_DL163B: - info->flash_id += FLASH_AMDL163B; - info->sector_count = 39; - info->size = 0x00400000; - break; /* => 4 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - } - - /* set up sector start address table */ - switch (value) { -#ifdef CONFIG_TQM8xxM /* mirror bit flash */ - case AMD_ID_MIRROR: - switch (info->flash_id & FLASH_TYPEMASK) { - /* only known types here - no default */ - case FLASH_AMLV128U: - case FLASH_AMLV640U: - case FLASH_AMLV320U: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x20000; - } - break; - case FLASH_AMLV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - } - break; -# else /* ! TQM8xxM */ - case AMD_ID_LV400B: - case AMD_ID_LV800B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV400T: - case AMD_ID_LV800T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_LV320B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - case AMD_ID_LV320T: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The last 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < (info->sector_count - 8)) - ? 2 * (64 << 10) - : 2 * ( 8 << 10); - } - break; -#endif /* TQM8xxM */ - case AMD_ID_LV160B: - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00008000; - info->start[2] = base + 0x0000C000; - info->start[3] = base + 0x00010000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + (i * 0x00020000) - 0x00060000; - } - break; - case AMD_ID_LV160T: - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00008000; - info->start[i--] = base + info->size - 0x0000C000; - info->start[i--] = base + info->size - 0x00010000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00020000; - } - break; - case AMD_ID_DL163B: - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - /* - * The first 8 sectors are 8 kB, - * all the other ones are 64 kB - */ - base += (i < 8) - ? 2 * ( 8 << 10) - : 2 * (64 << 10); - } - break; - default: - return (0); - break; - } - -#if 0 - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[2] & 1; - } -#endif - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0x00F000F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00800080; - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long*)(info->start[sect]); - addr[0] = 0x00300030; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long*)(info->start[l_sect]); - while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (volatile unsigned long *)info->start[0]; - addr[0] = 0x00F000F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long*)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0x0555] = 0x00AA00AA; - addr[0x02AA] = 0x00550055; - addr[0x0555] = 0x00A000A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ - -#endif /* !defined(CONFIG_FLASH_CFI_DRIVER) */ diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c index 143f36801..d2699020d 100644 --- a/board/tqc/tqm8xx/load_sernum_ethaddr.c +++ b/board/tqc/tqm8xx/load_sernum_ethaddr.c @@ -52,21 +52,21 @@ void load_sernum_ethaddr (void) { unsigned char *hwi; - unsigned char serial [CFG_HWINFO_SIZE]; - unsigned char ethaddr[CFG_HWINFO_SIZE]; + unsigned char serial [CONFIG_SYS_HWINFO_SIZE]; + unsigned char ethaddr[CONFIG_SYS_HWINFO_SIZE]; unsigned short ih, is, ie, part; - hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET); + hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET); ih = is = ie = 0; - if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) { + if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) { return; } part = 1; /* copy serial # / MAC address */ - while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) { + while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) { if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */ return; } diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index 96b6103fc..e065d69dd 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -21,16 +21,14 @@ * MA 02111-1307 USA */ -#if 0 -#define DEBUG -#endif - #include <common.h> #include <mpc8xx.h> #ifdef CONFIG_PS2MULT #include <ps2mult.h> #endif +extern flash_info_t flash_info[]; /* FLASH chips info */ + DECLARE_GLOBAL_DATA_PTR; static long int dram_size (long int, long int *, long int); @@ -141,7 +139,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size8, size9, size10; long int size_b0 = 0; @@ -156,7 +154,7 @@ phys_size_t initdram (int board_type) * with two SDRAM banks or four cycles every 31.2 us with one * bank. It will be adjusted after memory sizing. */ - memctl->memc_mptpr = CFG_MPTPR_2BK_8K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; /* * The following value is used as an address (i.e. opcode) for @@ -178,19 +176,19 @@ phys_size_t initdram (int board_type) * preliminary addresses - these have to be modified after the * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; #ifndef CONFIG_CAN_DRIVER if ((board_type != 'L') && (board_type != 'M') && (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */ - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; } #endif /* CONFIG_CAN_DRIVER */ - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ udelay (200); @@ -221,7 +219,7 @@ phys_size_t initdram (int board_type) * * try 8 column mode */ - size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20); udelay (1000); @@ -229,30 +227,30 @@ phys_size_t initdram (int board_type) /* * try 9 column mode */ - size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20); udelay(1000); -#if defined(CFG_MAMR_10COL) +#if defined(CONFIG_SYS_MAMR_10COL) /* * try 10 column mode */ - size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); + size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE); debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20); #else size10 = 0; -#endif /* CFG_MAMR_10COL */ +#endif /* CONFIG_SYS_MAMR_10COL */ if ((size8 < size10) && (size9 < size10)) { size_b0 = size10; } else if ((size8 < size9) && (size10 < size9)) { size_b0 = size9; - memctl->memc_mamr = CFG_MAMR_9COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_9COL; udelay (500); } else { size_b0 = size8; - memctl->memc_mamr = CFG_MAMR_8COL; + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; udelay (500); } debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20); @@ -283,7 +281,7 @@ phys_size_t initdram (int board_type) */ if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) { /* reduce to 15.6 us (62.4 us / quad) */ - memctl->memc_mptpr = CFG_MPTPR_2BK_4K; + memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; udelay (1000); } @@ -292,15 +290,15 @@ phys_size_t initdram (int board_type) */ if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */ - memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b0 > 0) { /* * Position Bank 0 immediately above Bank 1 */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; - memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; + memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b1; } else { unsigned long reg; @@ -314,24 +312,24 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } else { /* SDRAM Bank 0 is bigger - map first */ - memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br2 = - (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; + (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; if (size_b1 > 0) { /* * Position Bank 1 immediately above Bank 0 */ memctl->memc_or3 = - ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM; + ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; memctl->memc_br3 = - ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V) + size_b0; } else { unsigned long reg; @@ -347,7 +345,7 @@ phys_size_t initdram (int board_type) /* adjust refresh rate depending on SDRAM type, one bank */ reg = memctl->memc_mptpr; - reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */ + reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ memctl->memc_mptpr = reg; } } @@ -358,8 +356,8 @@ phys_size_t initdram (int board_type) /* UPM initialization for CAN @ CLKOUT <= 66 MHz */ /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; /* Initialize MBMR */ memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */ @@ -399,11 +397,9 @@ phys_size_t initdram (int board_type) #ifdef CONFIG_ISP1362_USB /* Initialize OR5 / BR5 */ - memctl->memc_or5 = CFG_OR5_ISP1362; - memctl->memc_br5 = CFG_BR5_ISP1362; + memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362; + memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362; #endif /* CONFIG_ISP1362_USB */ - - return (size_b0 + size_b1); } @@ -419,7 +415,7 @@ phys_size_t initdram (int board_type) static long int dram_size (long int mamr_value, long int *base, long int maxsize) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; memctl->memc_mamr = mamr_value; @@ -451,29 +447,117 @@ int board_early_init_r (void) #endif /* CONFIG_PS2MULT */ -/* ---------------------------------------------------------------------------- */ -/* HMI10 specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_HMI10 +#ifdef CONFIG_MISC_INIT_R int misc_init_r (void) { -# ifdef CONFIG_IDE_LED - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + +#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ + int scy, trlx, flash_or_timing, clk_diff; + + scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4; + if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) { + trlx = OR_TRLX; + scy *= 2; + } else { + trlx = 0; + } + /* + * We assume that each 10MHz of bus clock require 1-clk SCY + * adjustment. + */ + clk_diff = (gd->bus_clk / 1000000) - 50; + + /* + * We need proper rounding here. This is what the "+5" and "-5" + * are here for. + */ + if (clk_diff >= 0) + scy += (clk_diff + 5) / 10; + else + scy += (clk_diff - 5) / 10; + + /* + * For bus frequencies above 50MHz, we want to use relaxed timing + * (OR_TRLX). + */ + if (gd->bus_clk >= 50000000) + trlx = OR_TRLX; + else + trlx = 0; + + if (trlx) + scy /= 2; + + if (scy > 0xf) + scy = 0xf; + if (scy < 1) + scy = 1; + + flash_or_timing = (scy << 4) | trlx | + (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK)); + + memctl->memc_or0 = + flash_or_timing | (-flash_info[0].size & OR_AM_MSK); +#else + memctl->memc_or0 = + CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK); +#endif + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + debug ("## BR0: 0x%08x OR0: 0x%08x\n", + memctl->memc_br0, memctl->memc_or0); + + if (flash_info[1].size) { +#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ + memctl->memc_or1 = flash_or_timing | + (-flash_info[1].size & 0xFFFF8000); +#else + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | + (-flash_info[1].size & 0xFFFF8000); +#endif + memctl->memc_br1 = + ((CONFIG_SYS_FLASH_BASE + + flash_info[0]. + size) & BR_BA_MSK) | BR_MS_GPCM | BR_V; + + debug ("## BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } else { + memctl->memc_br1 = 0; /* invalidate bank */ + + debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n", + memctl->memc_br1, memctl->memc_or1); + } + +# ifdef CONFIG_IDE_LED /* Configure PA15 as output port */ immap->im_ioport.iop_padir |= 0x0001; immap->im_ioport.iop_paodr |= 0x0001; immap->im_ioport.iop_papar &= ~0x0001; immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */ # endif + +#ifdef CONFIG_NSCU + /* wake up ethernet module */ + immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ + immap->im_ioport.iop_pcdir |= 0x0004; /* output */ + immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ + immap->im_ioport.iop_pcdat |= 0x0004; /* enable */ +#endif /* CONFIG_NSCU */ + return (0); } +#endif /* CONFIG_MISC_INIT_R */ + # ifdef CONFIG_IDE_LED void ide_led (uchar led, uchar status) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* We have one led for both pcmcia slots */ if (status) { /* led on */ @@ -483,26 +567,34 @@ void ide_led (uchar led, uchar status) } } # endif -#endif /* CONFIG_HMI10 */ -/* ---------------------------------------------------------------------------- */ -/* NSCU specific stuff */ -/* ---------------------------------------------------------------------------- */ -#ifdef CONFIG_NSCU +#ifdef CONFIG_LCD_INFO +#include <lcd.h> +#include <version.h> +#include <timestamp.h> -int misc_init_r (void) +void lcd_show_board_info(void) { - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - /* wake up ethernet module */ - immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */ - immr->im_ioport.iop_pcdir |= 0x0004; /* output */ - immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */ - immr->im_ioport.iop_pcdat |= 0x0004; /* enable */ - - return (0); + char temp[32]; + + lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME); + lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n"); + lcd_printf (" Wolfgang DENK, wd@denx.de\n"); +#ifdef CONFIG_LCD_INFO_BELOW_LOGO + lcd_printf ("MPC823 CPU at %s MHz\n", + strmhz(temp, gd->cpu_clk)); + lcd_printf (" %ld MB RAM, %ld MB Flash\n", + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#else + /* leave one blank line */ + lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n", + strmhz(temp, gd->cpu_clk), + gd->ram_size >> 20, + gd->bd->bi_flashsize >> 20 ); +#endif /* CONFIG_LCD_INFO_BELOW_LOGO */ } -#endif /* CONFIG_NSCU */ +#endif /* CONFIG_LCD_INFO */ /* ---------------------------------------------------------------------------- */ /* TK885D specific initializaion */ @@ -548,7 +640,4 @@ int last_stage_init(void) return 0; } - #endif - -/* ------------------------------------------------------------------------- */ diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 8c46e4677..5af36c97a 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS lib_ppc/time.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -137,6 +137,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/tqc/tqm8xx/u-boot.lds.debug b/board/tqc/tqm8xx/u-boot.lds.debug index c33581d25..ea8538900 100644 --- a/board/tqc/tqm8xx/u-boot.lds.debug +++ b/board/tqc/tqm8xx/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/trab/Makefile b/board/trab/Makefile index 2402577a5..30e5fbbb3 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -50,7 +50,9 @@ $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB) $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \ -L$(obj)../../examples -lstubs \ - -L$(gcclibdir) -lgcc + -L$(obj)../../lib_generic -lgeneric \ + $(obj)../../lib_arm/div0.o \ + $(obj)../../lib_arm/_*.o $(OBJCOPY) -O srec $(<:.o=) $@ $(obj)trab_fkt.bin: $(obj)trab_fkt.srec diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c index 46110cc76..99327906b 100644 --- a/board/trab/auto_update.c +++ b/board/trab/auto_update.c @@ -28,7 +28,7 @@ #include <asm/byteorder.h> #include <usb.h> -#ifdef CFG_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER #include <hush.h> #endif @@ -42,8 +42,8 @@ #error "must define CONFIG_USB_STORAGE" #endif -#ifndef CFG_HUSH_PARSER -#error "must define CFG_HUSH_PARSER" +#ifndef CONFIG_SYS_HUSH_PARSER +#error "must define CONFIG_SYS_HUSH_PARSER" #endif #if !defined(CONFIG_CMD_FAT) diff --git a/board/trab/flash.c b/board/trab/flash.c index 3e8f105a0..317b61d87 100644 --- a/board/trab/flash.c +++ b/board/trab/flash.c @@ -28,7 +28,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info); -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; #define CMD_READ_ARRAY 0x00F000F0 @@ -42,9 +42,9 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; #define CMD_UNLOCK_BYPASS_RES1 0x00900090 #define CMD_UNLOCK_BYPASS_RES2 0x00000000 -#define MEM_FLASH_ADDR (*(volatile u32 *)CFG_FLASH_BASE) -#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2))) -#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2))) +#define MEM_FLASH_ADDR (*(volatile u32 *)CONFIG_SYS_FLASH_BASE) +#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2))) +#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2))) #define BIT_ERASE_DONE 0x00800080 #define BIT_RDY_MASK 0x00800080 @@ -63,17 +63,17 @@ ulong flash_init (void) int i, j; ulong size = 0; - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { ulong flashbase = 0; flash_info_t *info = &flash_info[i]; /* Init: no FLASHes known */ info->flash_id = FLASH_UNKNOWN; - size += flash_get_size (CFG_FLASH_BASE, info); + size += flash_get_size (CONFIG_SYS_FLASH_BASE, info); if (i == 0) - flashbase = CFG_FLASH_BASE; + flashbase = CONFIG_SYS_FLASH_BASE; else panic ("configured too many flash banks!\n"); for (j = 0; j < info->sector_count; j++) { @@ -102,18 +102,18 @@ ulong flash_init (void) * Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); -#ifdef CFG_ENV_ADDR_REDUND +#ifdef CONFIG_ENV_ADDR_REDUND flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1, &flash_info[0]); #endif @@ -257,7 +257,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { MEM_FLASH_ADDR1 = CMD_READ_ARRAY; chip1 = TMO; break; @@ -356,7 +356,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) result = *addr; /* check timeout */ - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { chip1 = ERR | TMO; break; } @@ -559,10 +559,10 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } return (info->size); diff --git a/board/trab/memory.c b/board/trab/memory.c index 052432e9d..895b68ef7 100644 --- a/board/trab/memory.c +++ b/board/trab/memory.c @@ -155,7 +155,7 @@ #include <post.h> #include <watchdog.h> -/* #if CONFIG_POST & CFG_POST_MEMORY */ +/* #if CONFIG_POST & CONFIG_SYS_POST_MEMORY */ /* * Define INJECT_*_ERRORS for testing error detection in the presence of @@ -184,7 +184,7 @@ * * For other processors, let the compiler generate the best code it can. */ -static void move64(unsigned long long *src, unsigned long long *dest) +static void move64(const unsigned long long *src, unsigned long long *dest) { #if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ @@ -231,12 +231,12 @@ static int memory_post_dataline(unsigned long long * pmem) int ret = 0; for ( i = 0; i < num_patterns; i++) { - move64((unsigned long long *)&(pattern[i]), pmem++); + move64(&(pattern[i]), pmem++); /* * Put a different pattern on the data lines: otherwise they * may float long enough to read back what we wrote. */ - move64((unsigned long long *)&otherpattern, pmem--); + move64(&otherpattern, pmem--); move64(pmem, &temp64); #ifdef INJECT_DATA_ERRORS @@ -465,7 +465,7 @@ int memory_post_test (int flags) if (flags & POST_SLOWTEST) { - ret = memory_post_tests (CFG_SDRAM_BASE, memsize); + ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize); } else { /* POST_NORMAL */ unsigned long i; @@ -482,5 +482,5 @@ int memory_post_test (int flags) } #endif /* 0 */ -/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */ +/* #endif */ /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */ /* #endif */ /* CONFIG_POST */ diff --git a/board/trab/trab.c b/board/trab/trab.c index b869023ea..57ff71878 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CFG_BRIGHTNESS +#ifdef CONFIG_SYS_BRIGHTNESS static void spi_init(void); static void wait_transmit_done(void); static void tsc2000_write(unsigned int page, unsigned int reg, @@ -199,7 +199,7 @@ int misc_init_r (void) free (str); } -#ifdef CFG_BRIGHTNESS +#ifdef CONFIG_SYS_BRIGHTNESS tsc2000_set_brightness(); #endif return (0); @@ -333,7 +333,7 @@ static int key_pressed(void) } #endif /* CONFIG_MODEM_SUPPORT */ -#ifdef CFG_BRIGHTNESS +#ifdef CONFIG_SYS_BRIGHTNESS static inline void SET_CS_TOUCH(void) { @@ -415,7 +415,7 @@ static void tsc2000_set_brightness(void) i = getenv_r("brightness", tmp, sizeof(tmp)); br = (i > 0) ? (int) simple_strtoul (tmp, NULL, 10) - : CFG_BRIGHTNESS; + : CONFIG_SYS_BRIGHTNESS; tsc2000_write(0, 0xb, br & 0xff); } diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index 7273ef97b..53cdb5a31 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -25,6 +25,7 @@ #include <common.h> #include <exports.h> +#include <timestamp.h> #include <s3c2400.h> #include "tsc2000.h" #include "rs485.h" @@ -293,10 +294,16 @@ int trab_fkt (int argc, char *argv[]) return 1; } +void hang (void) +{ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;); +} + int do_info (void) { printf ("Stand-alone application for TRAB board function test\n"); - printf ("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf ("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); return 0; } diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index 382a85b35..f13a5a9dc 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -27,6 +27,7 @@ #include <common.h> #include <s3c2400.h> +#include <div64.h> #include "tsc2000.h" #include "Pt1000_temp_data.h" @@ -332,6 +333,7 @@ void tsc2000_reg_init (void) int tsc2000_interpolate(long value, long data[][2], long *result) { int i; + unsigned long long val; /* the data is sorted and the first element is upper * limit so we can easily check for out-of-band values @@ -347,10 +349,10 @@ int tsc2000_interpolate(long value, long data[][2], long *result) result in 'long long'. */ - *result = data[i-1][1] + - ((unsigned long long)(data[i][1] - data[i-1][1]) - * (unsigned long long)(value - data[i-1][0])) - / (data[i][0] - data[i-1][0]); + val = ((unsigned long long)(data[i][1] - data[i-1][1]) + * (unsigned long long)(value - data[i-1][0])); + do_div(val, (data[i][0] - data[i-1][0])); + *result = data[i-1][1] + val; return 0; } diff --git a/board/trab/u-boot.lds b/board/trab/u-boot.lds index 043e01c9b..bd13d13a1 100644 --- a/board/trab/u-boot.lds +++ b/board/trab/u-boot.lds @@ -39,7 +39,7 @@ SECTIONS lib_generic/string.o (.text) . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) } @@ -60,6 +60,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S index d8869381a..128d55407 100644 --- a/board/trizepsiv/lowlevel_init.S +++ b/board/trizepsiv/lowlevel_init.S @@ -49,119 +49,119 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPSR3 - ldr r1, =CFG_GPSR3_VAL + ldr r1, =CONFIG_SYS_GPSR3_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GPCR3 - ldr r1, =CFG_GPCR3_VAL + ldr r1, =CONFIG_SYS_GPCR3_VAL str r1, [r0] ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL + ldr r1, =CONFIG_SYS_GRER0_VAL str r1, [r0] ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL + ldr r1, =CONFIG_SYS_GRER1_VAL str r1, [r0] ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL + ldr r1, =CONFIG_SYS_GRER2_VAL str r1, [r0] ldr r0, =GRER3 - ldr r1, =CFG_GRER3_VAL + ldr r1, =CONFIG_SYS_GRER3_VAL str r1, [r0] ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL + ldr r1, =CONFIG_SYS_GFER0_VAL str r1, [r0] ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL + ldr r1, =CONFIG_SYS_GFER1_VAL str r1, [r0] ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL + ldr r1, =CONFIG_SYS_GFER2_VAL str r1, [r0] ldr r0, =GFER3 - ldr r1, =CFG_GFER3_VAL + ldr r1, =CONFIG_SYS_GFER3_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GPDR3 - ldr r1, =CFG_GPDR3_VAL + ldr r1, =CONFIG_SYS_GPDR3_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] ldr r0, =GAFR3_L - ldr r1, =CFG_GAFR3_L_VAL + ldr r1, =CONFIG_SYS_GAFR3_L_VAL str r1, [r0] ldr r0, =GAFR3_U - ldr r1, =CFG_GAFR3_U_VAL + ldr r1, =CONFIG_SYS_GAFR3_U_VAL str r1, [r0] ldr r0, =PSSR /* enable GPIO pins */ - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ---------------------------------------------------------------- */ @@ -199,17 +199,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ /* that data latches */ /* MSC1: nCS(2,3) */ - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @@ -218,44 +218,44 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] ldr r2, [r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] ldr r2, [r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] ldr r2, [r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] ldr r2, [r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] ldr r2, [r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] ldr r2, [r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] ldr r2, [r1, #MCIO1_OFFSET] /* ---------------------------------------------------------------- */ /* Step 2c: Write FLYCNFG FIXME: what's that??? */ /* ---------------------------------------------------------------- */ - ldr r2, =CFG_FLYCNFG_VAL + ldr r2, =CONFIG_SYS_FLYCNFG_VAL str r2, [r1, #FLYCNFG_OFFSET] str r2, [r1, #FLYCNFG_OFFSET] @@ -270,7 +270,7 @@ mem_init: ldr r2, =0xFFF bic r4, r4, r2 - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL and r3, r3, r2 orr r4, r4, r3 @@ -300,7 +300,7 @@ mem_init: /* synchronous static memory. Note that SXLCR need not be written */ /* at this time. */ - ldr r2, =CFG_SXCNFG_VAL + ldr r2, =CONFIG_SYS_SXCNFG_VAL str r2, [r1, #SXCNFG_OFFSET] /* ---------------------------------------------------------------- */ @@ -329,7 +329,7 @@ mem_init: /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ /* configure but not enable each SDRAM partition pair. */ - ldr r4, =CFG_MDCNFG_VAL + ldr r4, =CONFIG_SYS_MDCNFG_VAL bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) @@ -357,7 +357,7 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -379,7 +379,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] /* enable APD */ @@ -443,11 +443,11 @@ initclks: /* Turn Off on-chip peripheral clocks (except for memory) */ /* for re-configuration. */ ldr r1, =CKEN - ldr r2, =CFG_CKEN + ldr r2, =CONFIG_SYS_CKEN str r2, [r1] /* ... and write the core clock config register */ - ldr r2, =CFG_CCCR + ldr r2, =CONFIG_SYS_CCCR ldr r1, =CCCR str r2, [r1] diff --git a/board/trizepsiv/u-boot.lds b/board/trizepsiv/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/trizepsiv/u-boot.lds +++ b/board/trizepsiv/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/uc100/pcmcia.c b/board/uc100/pcmcia.c index 407bdb73c..ad256783c 100644 --- a/board/uc100/pcmcia.c +++ b/board/uc100/pcmcia.c @@ -24,7 +24,7 @@ static void cfg_ports (void) { volatile immap_t *immap; - immap = (immap_t *)CFG_IMMR; + immap = (immap_t *)CONFIG_SYS_IMMR; /* * Configure Port A for MAX1602 PC-Card Power-Interface Switch @@ -49,10 +49,10 @@ int pcmcia_hardware_enable(int slot) udelay(10000); - immap = (immap_t *)CFG_IMMR; - sysp = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf)); - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); - cp = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm)); + immap = (immap_t *)CONFIG_SYS_IMMR; + sysp = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); + cp = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm)); /* Configure Ports for TPS2211A PC-Card Power-Interface Switch */ cfg_ports (); @@ -133,8 +133,8 @@ int pcmcia_hardware_disable(int slot) debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* switch VCC off */ immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */ @@ -163,8 +163,8 @@ int pcmcia_voltage_set(int slot, int vcc, int vpp) " Slot %c, Vcc=%d.%d, Vpp=%d.%d\n", 'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10); - immap = (immap_t *)CFG_IMMR; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + immap = (immap_t *)CONFIG_SYS_IMMR; + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); /* * Disable PCMCIA buffers (isolate the interface) * and assert RESET signal diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds index db2934249..66a57e6fb 100644 --- a/board/uc100/u-boot.lds +++ b/board/uc100/u-boot.lds @@ -65,7 +65,7 @@ SECTIONS lib_ppc/cache.o (.text) lib_ppc/time.o (.text) - common/environment.o (.text) + common/env_embedded.o (.text) *(.text) *(.fixup) @@ -136,6 +136,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug index 25702a543..575065711 100644 --- a/board/uc100/u-boot.lds.debug +++ b/board/uc100/u-boot.lds.debug @@ -60,7 +60,7 @@ SECTIONS lib_generic/vsprintf.o (.text) lib_generic/crc32.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c index 896f9693e..38c7be6ba 100644 --- a/board/uc100/uc100.c +++ b/board/uc100/uc100.c @@ -138,7 +138,7 @@ int board_switch(void) { volatile pcmconf8xx_t *pcmp; - pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia)); + pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); return ((pcmp->pcmc_pipr >> 24) & 0xf); } @@ -171,7 +171,7 @@ int checkboard (void) */ phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /*---------------------------------------------------------------------*/ @@ -187,8 +187,8 @@ phys_size_t initdram (int board_type) /*---------------------------------------------------------------------*/ memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */ - memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */ - memctl->memc_mbmr = CFG_MBMR_VAL; + memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */ + memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL; /*---------------------------------------------------------------------*/ /* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */ @@ -198,8 +198,8 @@ phys_size_t initdram (int board_type) /* clock rate (16.67MHz) to allow proper operation for all ADS */ /* clock frequencies. */ /*---------------------------------------------------------------------*/ - memctl->memc_or1 = CFG_OR1_PRELIM; - memctl->memc_br1 = CFG_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; /*-------------------------------------------------------------------*/ /* Wait at least 200 usec for DRAM to stabilize, this magic number */ @@ -209,8 +209,8 @@ phys_size_t initdram (int board_type) memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08; - memctl->memc_br1 = CFG_BR1_PRELIM; - memctl->memc_or1 = CFG_OR1_PRELIM; + memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; + memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; /*---------------------------------------------------------------------*/ /* run MRS command in location 5-8 of UPMB. */ @@ -236,7 +236,7 @@ phys_size_t initdram (int board_type) /*---------------------------------------------------------------------*/ /* rerstore MBMR value (4-beat refresh burst.) */ /*---------------------------------------------------------------------*/ - memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */ + memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */ udelay(200); @@ -251,9 +251,9 @@ int misc_init_r (void) /* * Make sure that RTC has clock output enabled (triggers watchdog!) */ - val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D); + val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D); val |= 0x80; - i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val); + i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val); /* * Configure PHY to setup LED's correctly and use 100MBit, FD diff --git a/board/uc101/uc101.c b/board/uc101/uc101.c index 69ba5078d..7df349f3e 100644 --- a/board/uc101/uc101.c +++ b/board/uc101/uc101.c @@ -99,7 +99,7 @@ #define GP_TIMER_GET_I(n, v) ( \ (((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8) -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start (int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -142,14 +142,14 @@ static void sdram_start (int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ phys_size_t initdram (int board_type) { ulong dramsize = 0; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -170,9 +170,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -194,7 +194,7 @@ phys_size_t initdram (int board_type) } *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -212,7 +212,7 @@ phys_size_t initdram (int board_type) dramsize2 = 0; } -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* return dramsize + dramsize2; */ return dramsize; @@ -222,7 +222,7 @@ int checkboard (void) { puts ("Board: MAN UC101\n"); /* clear the Display */ - *(char *)(CFG_DISP_CWORD) = 0x80; + *(char *)(CONFIG_SYS_DISP_CWORD) = 0x80; return 0; } @@ -345,9 +345,9 @@ int board_early_init_r (void) { *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ *(vu_long *)MPC5XXX_BOOTCS_START = - *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE); + *(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE); *(vu_long *)MPC5XXX_BOOTCS_STOP = - *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE); + *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE); /* Interbus enable it here ?? */ *(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1; return 0; diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c index 199f619a8..aac81167d 100644 --- a/board/utx8245/flash.c +++ b/board/utx8245/flash.c @@ -33,15 +33,15 @@ #define ROM_CS0_START 0xFF800000 #define ROM_CS1_START 0xFF000000 -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -50,7 +50,7 @@ #define SECT_SIZE_32KB 0x8000 #define SECT_SIZE_8KB 0x2000 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static int write_word (flash_info_t * info, ulong dest, ulong data); #if 0 @@ -80,8 +80,8 @@ unsigned long flash_init (void) ulong total_size = 0, device_size = 1; unsigned char manuf_id, device_id; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - vu_char *addr = (vu_char *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE); + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { + vu_char *addr = (vu_char *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE); addr[0x555] = 0xAA; /* get manuf/device info command */ addr[0x2AA] = 0x55; /* 3-cycle command */ @@ -97,7 +97,7 @@ unsigned long flash_init (void) device_size *= 2; flash_info[i].size = device_size; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; #if defined DEBUG_FLASH printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id); @@ -112,7 +112,7 @@ unsigned long flash_init (void) /* set individual sector start addresses */ for (j = 0; j < flash_info[i].sector_count; j++) { flash_info[i].start[j] = - (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE); } } @@ -126,14 +126,14 @@ unsigned long flash_init (void) /* set individual sector start addresses */ for (j = 0; j < flash_info[i].sector_count; j++) { flash_info[i].start[j] = - (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE); - if (j < (CFG_MAX_FLASH_SECT - 3)) { + if (j < (CONFIG_SYS_MAX_FLASH_SECT - 3)) { flash_info[i].start[j] = - (CFG_FLASH_BASE + i * FLASH_BANK_SIZE + + (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE); - } else if (j == (CFG_MAX_FLASH_SECT - 3)) { + } else if (j == (CONFIG_SYS_MAX_FLASH_SECT - 3)) { flash_info[i].start[j] = (flash_info[i].start[j - 1] + SECT_SIZE_32KB); @@ -156,22 +156,22 @@ unsigned long flash_init (void) addr[0] = 0xFF; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); total_size += flash_info[i].size; } /* Protect monitor and environment sectors */ -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE - flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); #endif -#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR) - flash_protect (FLAG_PROTECT_SET, CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); +#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) + flash_protect (FLAG_PROTECT_SET, CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); #endif Done: @@ -383,7 +383,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) start[0]) << sh8b)); while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != (FLASH_WORD_SIZE) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -524,7 +524,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) start = get_timer (0); while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c index e2a961a3a..840268915 100644 --- a/board/utx8245/utx8245.c +++ b/board/utx8245/utx8245.c @@ -32,6 +32,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <pci.h> +#include <netdev.h> #define SAVE_SZ 32 @@ -54,7 +55,7 @@ phys_size_t initdram(int board_type) long mear1; long emear1; - size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE); + size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); new_bank0_end = size/2 - 1; new_bank1_end = size - 1; @@ -127,3 +128,8 @@ void pci_init_board (void) icache_enable(); } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/v37/flash.c b/board/v37/flash.c index d845f652f..9b817ec14 100644 --- a/board/v37/flash.c +++ b/board/v37/flash.c @@ -38,7 +38,7 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -54,42 +54,42 @@ static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; short manu, dev_id; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } /* Do sizing to get full correct info */ - flash_get_id_word((void*)CFG_FLASH_BASE0,&manu,&dev_id); + flash_get_id_word((void*)CONFIG_SYS_FLASH_BASE0,&manu,&dev_id); size_b0 = flash_get_size(manu, dev_id, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE0, &flash_info[0],0); + flash_get_offsets (CONFIG_SYS_FLASH_BASE0, &flash_info[0],0); - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (0 - size_b0); + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0); -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE0 +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0 /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif - flash_get_id_long((void*)CFG_FLASH_BASE1,&manu,&dev_id); + flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id); size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]); - flash_get_offsets(CFG_FLASH_BASE1, &flash_info[1],1); + flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1); - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (0 - size_b1); + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1); flash_info[0].size = size_b0; flash_info[1].size = size_b1; @@ -395,7 +395,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_short *)(info->start[l_sect]); while ((addr[0] & 0x8080) != 0x8080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -524,7 +524,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } @@ -548,7 +548,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index 7bcf06155..bf78a3225 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -68,7 +68,7 @@ SECTIONS /* . = env_offset; */ - common/environment.o (.ppcenv) + common/env_embedded.o (.ppcenv) *(.text) *(.fixup) @@ -139,6 +139,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/v37/v37.c b/board/v37/v37.c index 2067fedfc..9c7bad52f 100644 --- a/board/v37/v37.c +++ b/board/v37/v37.c @@ -92,7 +92,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long temp; volatile int delay_cnt; @@ -136,8 +136,8 @@ phys_size_t initdram (int board_type) #ifdef CONFIG_CAN_DRIVER /* Initialize OR3 / BR3 */ - memctl->memc_or3 = CFG_OR3_CAN; - memctl->memc_br3 = CFG_BR3_CAN; + memctl->memc_or3 = CONFIG_SYS_OR3_CAN; + memctl->memc_br3 = CONFIG_SYS_BR3_CAN; /* Initialize MBMR */ memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */ @@ -191,7 +191,7 @@ phys_size_t initdram (int board_type) static long int dram_size () { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile sysconf8xx_t *siu = &immap->im_siu_conf; volatile pcmconf8xx_t *pcm = &immap->im_pcmcia; long int i, memory=1; diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c index 8815a0cb4..d77429549 100644 --- a/board/v38b/v38b.c +++ b/board/v38b/v38b.c @@ -29,7 +29,7 @@ #include <asm/processor.h> -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT static void sdram_start(int hi_addr) { long hi_addr_bit = hi_addr ? 0x01000000 : 0; @@ -68,7 +68,7 @@ static void sdram_start(int hi_addr) *(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; __asm__ volatile ("sync"); } -#endif /* !CFG_RAMBOOT */ +#endif /* !CONFIG_SYS_RAMBOOT */ phys_size_t initdram(int board_type) @@ -77,7 +77,7 @@ phys_size_t initdram(int board_type) ulong dramsize2 = 0; uint svr, pvr; -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT ulong test1, test2; /* setup SDRAM chip selects */ @@ -98,9 +98,9 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -123,10 +123,10 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); @@ -145,7 +145,7 @@ phys_size_t initdram(int board_type) else *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ -#else /* CFG_RAMBOOT */ +#else /* CONFIG_SYS_RAMBOOT */ /* retrieve size of memory connected to SDRAM CS0 */ dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF; @@ -161,7 +161,7 @@ phys_size_t initdram(int board_type) else dramsize2 = 0; -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* * On MPC5200B we need to set the special configuration delay in the diff --git a/board/versatile/flash.c b/board/versatile/flash.c index bbe5df724..3bdc895ec 100644 --- a/board/versatile/flash.c +++ b/board/versatile/flash.c @@ -32,7 +32,7 @@ #include <linux/byteorder/swab.h> #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -101,7 +101,7 @@ unsigned long flash_init (void) { int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_vpp(1); @@ -119,8 +119,8 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); return size; } @@ -246,10 +246,10 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -342,7 +342,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { if (get_timer_masked () > - CFG_FLASH_ERASE_TOUT) { + CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); /* suspend erase */ *addr = (FPW) 0x00B000B0; @@ -493,7 +493,7 @@ static int write_data (flash_info_t * info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ flash_vpp(0); return (1); diff --git a/board/versatile/u-boot.lds b/board/versatile/u-boot.lds index 82cb8e311..6e6e29bb6 100644 --- a/board/versatile/u-boot.lds +++ b/board/versatile/u-boot.lds @@ -46,6 +46,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/versatile/versatile.c b/board/versatile/versatile.c index 3b9b0207a..0f35caa9b 100644 --- a/board/versatile/versatile.c +++ b/board/versatile/versatile.c @@ -37,10 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -void flash__init (void); -void ether__init (void); -void peripheral_power_enable (void); - #if defined(CONFIG_SHOW_BOOT_PROGRESS) void show_boot_progress(int progress) { @@ -82,8 +78,6 @@ int board_init (void) icache_enable (); - flash__init (); - ether__init (); return 0; } @@ -98,22 +92,6 @@ int misc_init_r (void) Routine: Description: ******************************/ -void flash__init (void) -{ -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -} - -/****************************** - Routine: - Description: -******************************/ int dram_init (void) { return 0; diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c index d8ea6e573..f01597ad1 100644 --- a/board/voiceblue/eeprom.c +++ b/board/voiceblue/eeprom.c @@ -26,6 +26,7 @@ #include <common.h> #include <exports.h> +#include <timestamp.h> #include "../drivers/net/smc91111.h" #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE @@ -169,7 +170,7 @@ int eeprom(int argc, char *argv[]) /* Print help message */ if (argv[1][1] == 'h') { printf("VoiceBlue EEPROM writer\n"); - printf("Built: %s at %s\n", __DATE__ , __TIME__ ); + printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME); printf("Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); return 0; } diff --git a/board/voiceblue/eeprom.lds b/board/voiceblue/eeprom.lds index 89b0a8209..f3be320df 100644 --- a/board/voiceblue/eeprom.lds +++ b/board/voiceblue/eeprom.lds @@ -46,6 +46,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/voiceblue/u-boot.lds b/board/voiceblue/u-boot.lds index bce925bbf..8bf199079 100644 --- a/board/voiceblue/u-boot.lds +++ b/board/voiceblue/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c index fdd6ceb8b..310fde052 100644 --- a/board/w7o/cmd_vpd.c +++ b/board/w7o/cmd_vpd.c @@ -35,7 +35,7 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { VPD vpd; /* Board specific data struct */ - uchar dev_addr = CFG_DEF_EEPROM_ADDR; + uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR; /* Validate usage */ if (argc > 2) { diff --git a/board/w7o/flash.c b/board/w7o/flash.c index 32815fb63..677494977 100644 --- a/board/w7o/flash.c +++ b/board/w7o/flash.c @@ -29,7 +29,7 @@ #include <watchdog.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /*----------------------------------------------------------------------- * Functions @@ -49,7 +49,7 @@ unsigned long flash_init (void) unsigned long size_b1, base_b1; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -90,13 +90,13 @@ unsigned long flash_init (void) /* Protect the FPGA image */ (void)flash_protect(FLAG_PROTECT_SET, FLASH_BASE1_PRELIM, - FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN - 1, + FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN - 1, &flash_info[1]); /* Protect the default boot image */ (void)flash_protect(FLAG_PROTECT_SET, - FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN, - FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN + 0x600000 - 1, + FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN, + FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN + 0x600000 - 1, &flash_info[1]); /* Setup offsets for Main Flash */ @@ -294,11 +294,11 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) } } - /* Make sure we don't exceed CFG_MAX_FLASH_SECT */ - if (info->sector_count > CFG_MAX_FLASH_SECT) { + /* Make sure we don't exceed CONFIG_SYS_MAX_FLASH_SECT */ + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } /* set up sector start address table */ @@ -520,7 +520,7 @@ static int flash_erase32(flash_info_t *info, int s_first, int s_last) udelay (1000); while (((status = *addr) & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = 0x00B000B0; /* suspend erase */ *addr = 0x00FF00FF; /* reset to read mode */ @@ -787,7 +787,7 @@ static int write_word32(flash_info_t *info, ulong dest, ulong data) while (((status = *addr) & 0x00800080) != 0x00800080) { WATCHDOG_RESET(); - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/w7o/init.S b/board/w7o/init.S index 35d7dbceb..2fd84ba00 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -64,11 +64,11 @@ ext_bus_cntlr_init: mflr r3 /* get address of ..getAddr */ /* Calculate number of cache lines for this function */ - addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2) + addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) mtctr r4 ..ebcloop: icbt r0, r3 /* prefetch cache line for addr in r3*/ - addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */ + addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ bdnz ..ebcloop /* continue for $CTR cache lines */ /******************************************************************** @@ -103,14 +103,14 @@ ext_bus_cntlr_init: *******************************************************************/ addi r3, 0, pb0ap mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB0AP@h - ori r4, r4, CFG_W7O_EBC_PB0AP@l + addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h + ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l mtdcr ebccfgd, r4 addi r3, 0, pb0cr mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB0CR@h - ori r4, r4, CFG_W7O_EBC_PB0CR@l + addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h + ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l mtdcr ebccfgd, r4 /******************************************************************** @@ -118,14 +118,14 @@ ext_bus_cntlr_init: *******************************************************************/ addi r3, 0, pb7ap mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB7AP@h - ori r4, r4, CFG_W7O_EBC_PB7AP@l + addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h + ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l mtdcr ebccfgd, r4 addi r3, 0, pb7cr mtdcr ebccfga, r3 - addis r4, 0, CFG_W7O_EBC_PB7CR@h - ori r4, r4, CFG_W7O_EBC_PB7CR@l + addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h + ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l mtdcr ebccfgd, r4 /* We are all done */ diff --git a/board/w7o/post2.c b/board/w7o/post2.c index 6ee33eba3..1dfaa2f97 100644 --- a/board/w7o/post2.c +++ b/board/w7o/post2.c @@ -38,7 +38,7 @@ #if defined(CONFIG_RTC_M48T35A) void rtctest(void) { - volatile uchar *tchar = (uchar*)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9); + volatile uchar *tchar = (uchar*)(CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 9); struct rtc_time tmp; /* set up led code for RTC tests */ @@ -89,9 +89,9 @@ int dtt_test(int sensor) hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256; /* check values */ - if ((hyst != (CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS)) || - (trip != CFG_DTT_MAX_TEMP) || - (temp < CFG_DTT_LOW_TEMP) || (temp > CFG_DTT_MAX_TEMP)) + if ((hyst != (CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS)) || + (trip != CONFIG_SYS_DTT_MAX_TEMP) || + (temp < CONFIG_SYS_DTT_LOW_TEMP) || (temp > CONFIG_SYS_DTT_MAX_TEMP)) return 1; return 0; diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds index 3373793c6..80e960b9d 100644 --- a/board/w7o/u-boot.lds +++ b/board/w7o/u-boot.lds @@ -128,6 +128,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index d3ffed300..d2089de9d 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c index 2ce15680e..57558e88f 100644 --- a/board/w7o/vpd.c +++ b/board/w7o/vpd.c @@ -24,7 +24,7 @@ #if defined(VXWORKS) # include <stdio.h> # include <string.h> -# define CFG_DEF_EEPROM_ADDR 0xa0 +# define CONFIG_SYS_DEF_EEPROM_ADDR 0xa0 extern char iicReadByte( char, char ); extern ulong_t crc32( unsigned char *, unsigned long ); #else @@ -47,7 +47,7 @@ vpd_reader(unsigned char *buf, unsigned dev_addr, unsigned off, unsigned count) * SDRAM SPD in the first 128 bytes, * so skew the offset. */ - if (dev_addr == CFG_DEF_EEPROM_ADDR) + if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR) offset += SDRAM_SPD_DATA_SIZE; /* Try to read the I2C EEPROM */ @@ -127,7 +127,7 @@ static int vpd_is_valid(unsigned dev_addr, unsigned char *buf) /* Check Eyecatcher */ if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) { unsigned offset = 0; - if (dev_addr == CFG_DEF_EEPROM_ADDR) + if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR) offset += SDRAM_SPD_DATA_SIZE; printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr, offset); diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 0e3b84c61..22cdfcd7d 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -132,7 +132,7 @@ int checkboard (void) puts ("Board: "); /* VPD data present in I2C EEPROM */ - if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) { + if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) { /* * Known board type. */ @@ -204,7 +204,7 @@ static void w7o_env_init (VPD * vpd) /* * Read VPD */ - if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0) + if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0) return; /* diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c index 4bbd94f60..131399c9e 100644 --- a/board/w7o/watchdog.c +++ b/board/w7o/watchdog.c @@ -32,7 +32,7 @@ void hw_watchdog_reset(void) { - volatile ushort *hwd = (ushort *)(CFG_W7O_EBC_PB7CR & 0xfff00000); + volatile ushort *hwd = (ushort *)(CONFIG_SYS_W7O_EBC_PB7CR & 0xfff00000); /* * Read the LMG's hwd register and toggle the diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c index e2e08f742..c6e917167 100644 --- a/board/wepep250/flash.c +++ b/board/wepep250/flash.c @@ -82,7 +82,7 @@ #endif -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; static FLASH_BUS_RET flash_status_reg (void) { @@ -109,7 +109,7 @@ static int flash_ready (ulong timeout) return ok; } -#if ( CFG_MAX_FLASH_BANKS != 1 ) +#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 ) # error "WEP platform has only one flash bank!" #endif @@ -120,11 +120,11 @@ ulong flash_init (void) FLASH_BUS address = WEP_FLASH_BASE; flash_info[0].size = WEP_FLASH_BANK_SIZE; - flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; flash_info[0].flash_id = INTEL_MANUFACT; - memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) { flash_info[0].start[i] = address; #ifdef WEP_FLASH_UNLOCK /* Some devices are hw locked after start. */ @@ -137,13 +137,13 @@ ulong flash_init (void) } flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); return WEP_FLASH_BANK_SIZE; } @@ -209,7 +209,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); - if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) { *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); printf ("ok.\n"); } else { @@ -257,7 +257,7 @@ static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); *address = data; - if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) { *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); rc = ERR_TIMOUT; printf ("timeout! Aborting...\n"); diff --git a/board/wepep250/u-boot.lds b/board/wepep250/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/wepep250/u-boot.lds +++ b/board/wepep250/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c index 4742aafc5..91dcc0dcb 100644 --- a/board/westel/amx860/amx860.c +++ b/board/westel/amx860/amx860.c @@ -64,7 +64,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; /* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */ diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c index 12a1335b7..fe8bce412 100644 --- a/board/westel/amx860/flash.c +++ b/board/westel/amx860/flash.c @@ -24,17 +24,17 @@ #include <common.h> #include <mpc8xx.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -#if defined(CFG_ENV_IS_IN_FLASH) -# ifndef CFG_ENV_ADDR -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#if defined(CONFIG_ENV_IS_IN_FLASH) +# ifndef CONFIG_ENV_ADDR +# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) # endif -# ifndef CFG_ENV_SIZE -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +# ifndef CONFIG_ENV_SIZE +# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE # endif -# ifndef CFG_ENV_SECT_SIZE -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE +# ifndef CONFIG_ENV_SECT_SIZE +# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE # endif #endif @@ -60,13 +60,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info); unsigned long flash_init (void) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; unsigned long size_b0, size_b1; int i; /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; } @@ -113,64 +113,64 @@ unsigned long flash_init (void) memctl->memc_br1, memctl->memc_or1); /* Remap FLASH according to real size */ - memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); - memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; + memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); + memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0); /* Re-do sizing to get full correct info */ - size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); + size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); flash_info[0].size = size_b0; -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE +#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[0]); #endif -#ifdef CFG_ENV_IS_IN_FLASH +#ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[0]); #endif if (size_b1) { - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK); - memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | + memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK); + memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) | BR_MS_GPCM | BR_V; DEBUGF("## BR1: 0x%08x OR1: 0x%08x\n", memctl->memc_br1, memctl->memc_or1); /* Re-do sizing to get full correct info */ - size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), + size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0), &flash_info[1]); flash_info[1].size = size_b1; - flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); + flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]); -# if CFG_MONITOR_BASE >= CFG_FLASH_BASE +# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE /* monitor protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+monitor_flash_len-1, + CONFIG_SYS_MONITOR_BASE, + CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, &flash_info[1]); # endif -# ifdef CFG_ENV_IS_IN_FLASH +# ifdef CONFIG_ENV_IS_IN_FLASH /* ENV protection ON by default */ flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1, &flash_info[1]); #endif } else { @@ -503,7 +503,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -626,7 +626,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds index 10b38ec35..ef9a2515c 100644 --- a/board/westel/amx860/u-boot.lds +++ b/board/westel/amx860/u-boot.lds @@ -63,7 +63,7 @@ SECTIONS lib_generic/zlib.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) @@ -134,6 +134,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug index 7a7a40c23..dbd1f9d10 100644 --- a/board/westel/amx860/u-boot.lds.debug +++ b/board/westel/amx860/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS lib_ppc/extable.o (.text) . = env_offset; - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c index 9874a14fb..b051c8984 100644 --- a/board/xaeniax/flash.c +++ b/board/xaeniax/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -65,7 +65,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -85,13 +85,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0] ); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); return size; } @@ -203,10 +203,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -276,7 +276,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -410,7 +410,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S index fe3e7128a..57e162005 100644 --- a/board/xaeniax/lowlevel_init.S +++ b/board/xaeniax/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -47,67 +47,67 @@ lowlevel_init: /* Set up GPIO pins first ----------------------------------------- */ ldr r0,=GPSR0 - ldr r1,=CFG_GPSR0_VAL + ldr r1,=CONFIG_SYS_GPSR0_VAL str r1,[r0] ldr r0,=GPSR1 - ldr r1,=CFG_GPSR1_VAL + ldr r1,=CONFIG_SYS_GPSR1_VAL str r1,[r0] ldr r0,=GPSR2 - ldr r1,=CFG_GPSR2_VAL + ldr r1,=CONFIG_SYS_GPSR2_VAL str r1,[r0] ldr r0,=GPCR0 - ldr r1,=CFG_GPCR0_VAL + ldr r1,=CONFIG_SYS_GPCR0_VAL str r1,[r0] ldr r0,=GPCR1 - ldr r1,=CFG_GPCR1_VAL + ldr r1,=CONFIG_SYS_GPCR1_VAL str r1,[r0] ldr r0,=GPCR2 - ldr r1,=CFG_GPCR2_VAL + ldr r1,=CONFIG_SYS_GPCR2_VAL str r1,[r0] ldr r0,=GPDR0 - ldr r1,=CFG_GPDR0_VAL + ldr r1,=CONFIG_SYS_GPDR0_VAL str r1,[r0] ldr r0,=GPDR1 - ldr r1,=CFG_GPDR1_VAL + ldr r1,=CONFIG_SYS_GPDR1_VAL str r1,[r0] ldr r0,=GPDR2 - ldr r1,=CFG_GPDR2_VAL + ldr r1,=CONFIG_SYS_GPDR2_VAL str r1,[r0] ldr r0,=GAFR0_L - ldr r1,=CFG_GAFR0_L_VAL + ldr r1,=CONFIG_SYS_GAFR0_L_VAL str r1,[r0] ldr r0,=GAFR0_U - ldr r1,=CFG_GAFR0_U_VAL + ldr r1,=CONFIG_SYS_GAFR0_U_VAL str r1,[r0] ldr r0,=GAFR1_L - ldr r1,=CFG_GAFR1_L_VAL + ldr r1,=CONFIG_SYS_GAFR1_L_VAL str r1,[r0] ldr r0,=GAFR1_U - ldr r1,=CFG_GAFR1_U_VAL + ldr r1,=CONFIG_SYS_GAFR1_U_VAL str r1,[r0] ldr r0,=GAFR2_L - ldr r1,=CFG_GAFR2_L_VAL + ldr r1,=CONFIG_SYS_GAFR2_L_VAL str r1,[r0] ldr r0,=GAFR2_U - ldr r1,=CFG_GAFR2_U_VAL + ldr r1,=CONFIG_SYS_GAFR2_U_VAL str r1,[r0] ldr r0,=PSSR /* enable GPIO pins */ - ldr r1,=CFG_PSSR_VAL + ldr r1,=CONFIG_SYS_PSSR_VAL str r1,[r0] /* ---------------------------------------------------------------- */ @@ -145,17 +145,17 @@ mem_init: /* MSC registers: timing, bus width, mem type */ /* MSC0: nCS(0,1) */ - ldr r2,=CFG_MSC0_VAL + ldr r2,=CONFIG_SYS_MSC0_VAL str r2,[r1, #MSC0_OFFSET] ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */ /* MSC1: nCS(2,3) */ - ldr r2,=CFG_MSC1_VAL + ldr r2,=CONFIG_SYS_MSC1_VAL str r2,[r1, #MSC1_OFFSET] ldr r2,[r1, #MSC1_OFFSET] /* MSC2: nCS(4,5) */ - ldr r2,=CFG_MSC2_VAL + ldr r2,=CONFIG_SYS_MSC2_VAL str r2,[r1, #MSC2_OFFSET] ldr r2,[r1, #MSC2_OFFSET] @@ -164,37 +164,37 @@ mem_init: /* ---------------------------------------------------------------- */ /* MECR: Memory Expansion Card Register */ - ldr r2,=CFG_MECR_VAL + ldr r2,=CONFIG_SYS_MECR_VAL str r2,[r1, #MECR_OFFSET] ldr r2,[r1, #MECR_OFFSET] /* MCMEM0: Card Interface slot 0 timing */ - ldr r2,=CFG_MCMEM0_VAL + ldr r2,=CONFIG_SYS_MCMEM0_VAL str r2,[r1, #MCMEM0_OFFSET] ldr r2,[r1, #MCMEM0_OFFSET] /* MCMEM1: Card Interface slot 1 timing */ - ldr r2,=CFG_MCMEM1_VAL + ldr r2,=CONFIG_SYS_MCMEM1_VAL str r2,[r1, #MCMEM1_OFFSET] ldr r2,[r1, #MCMEM1_OFFSET] /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2,=CFG_MCATT0_VAL + ldr r2,=CONFIG_SYS_MCATT0_VAL str r2,[r1, #MCATT0_OFFSET] ldr r2,[r1, #MCATT0_OFFSET] /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2,=CFG_MCATT1_VAL + ldr r2,=CONFIG_SYS_MCATT1_VAL str r2,[r1, #MCATT1_OFFSET] ldr r2,[r1, #MCATT1_OFFSET] /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2,=CFG_MCIO0_VAL + ldr r2,=CONFIG_SYS_MCIO0_VAL str r2,[r1, #MCIO0_OFFSET] ldr r2,[r1, #MCIO0_OFFSET] /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2,=CFG_MCIO1_VAL + ldr r2,=CONFIG_SYS_MCIO1_VAL str r2,[r1, #MCIO1_OFFSET] ldr r2,[r1, #MCIO1_OFFSET] @@ -207,7 +207,7 @@ mem_init: /* ---------------------------------------------------------------- */ @ get the mdrefr settings - ldr r4,=CFG_MDREFR_VAL + ldr r4,=CONFIG_SYS_MDREFR_VAL @ write back mdrefr str r4,[r1, #MDREFR_OFFSET] @@ -261,7 +261,7 @@ mem_init: /* Step 4d: */ /* fetch platform value of mdcnfg */ @ - ldr r2, =CFG_MDCNFG_VAL + ldr r2, =CONFIG_SYS_MDCNFG_VAL @ disable all sdram banks @ @@ -296,7 +296,7 @@ mem_init: /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ - ldr r3, =CFG_DRAM_BASE + ldr r3, =CONFIG_SYS_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] @@ -326,7 +326,7 @@ mem_init: /* Step 4h: Write MDMRS. */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] @@ -342,7 +342,7 @@ initirqs: ldr r2, =ICLR str r1, [r2] - ldr r1, =CFG_ICMR_VAL /* mask all interrupts at the controller */ + ldr r1, =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */ ldr r2, =ICMR str r1, [r2] @@ -388,7 +388,7 @@ initclks: @ test: ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL + ldr r2, =CONFIG_SYS_CKEN_VAL str r2, [r1] /* ---------------------------------------------------------------- */ diff --git a/board/xaeniax/u-boot.lds b/board/xaeniax/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/xaeniax/u-boot.lds +++ b/board/xaeniax/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c index 5d493eeb7..e64beccc1 100644 --- a/board/xilinx/ml300/ml300.c +++ b/board/xilinx/ml300/ml300.c @@ -42,7 +42,7 @@ #include <common.h> #include <asm/processor.h> -#ifdef CFG_ENV_IS_IN_EEPROM +#ifdef CONFIG_ENV_IS_IN_EEPROM extern void convert_env(void); #endif diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c index 993dfa30f..421551337 100644 --- a/board/xilinx/ml300/serial.c +++ b/board/xilinx/ml300/serial.c @@ -45,9 +45,9 @@ DECLARE_GLOBAL_DATA_PTR; #define USE_CHAN1 \ - ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1)) + ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN1)) #define USE_CHAN2 \ - ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CFG_INIT_CHAN2)) + ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN2)) #if USE_CHAN1 #include <ns16550.h> @@ -82,21 +82,21 @@ void serial_putc(const char c) { if (c == '\n') - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); + NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r'); - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); + NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c); } int serial_getc(void) { - return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); + return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); } int serial_tstc(void) { - return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); + return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]); } void diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes deleted file mode 100644 index 9daf14709..000000000 --- a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/Ltypes +++ /dev/null @@ -1,55 +0,0 @@ -#!/bin/bash - -if [ $# -ne 1 ] -then - echo "usage: Ltypes filename" >&2 - exit 2 -fi - -FILE="$1" -#TMPFILE='mktemp "${FILE}.XXXXXX"' || exit 1 -TMPFILE=${FILE}.`date "+%s"` -touch $TMPFILE || exit 1 - -# Change all the Xilinx types to Linux types and put the result into a temp file -sed \ - -e 's/\bXTRUE\b/TRUE/g' \ - -e 's/\bXFALSE\b/FALSE/g' \ - -e 's/\bXNULL\b/NULL/g' \ - -e 's/"xenv.h"/<asm\/delay.h>/g' \ - -e 's/\bXENV_USLEEP\b/udelay/g' \ - -e 's/\bXuint8\b/u8/g' \ - -e 's/\bXuint16\b/u16/g' \ - -e 's/\bXuint32\b/u32/g' \ - -e 's/\bXint8\b/s8/g' \ - -e 's/\bXint16\b/s16/g' \ - -e 's/\bXint32\b/s32/g' \ - -e 's/\bXboolean\b/u32/g' \ - "${FILE}" > "${TMPFILE}" - -# Overlay the original file with the temp file -mv "${TMPFILE}" "${FILE}" - -# Are we doing xbasic_types.h? -if [ "${FILE##*/}" = xbasic_types.h ] -then - # Remember as you're reading this that we've already gone through the prior - # sed script. We need to do some other things to xbasic_types.h: - # 1) Add ifndefs around TRUE and FALSE defines - # 2) Remove definition of NULL as NULL - # 3) Replace most of the primitive types section with a #include - sed \ - -e '/u32 true/,/#define false/Ic\ -#ifndef TRUE\ -#define TRUE 1\ -#endif\ -#ifndef FALSE\ -#define FALSE 0\ -#endif' \ - -e '/#define[[:space:]][[:space:]]*NULL[[:space:]][[:space:]]*NULL/d' \ - -e '/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*char[[:space:]][[:space:]]*u8/,/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*long[[:space:]][[:space:]]*u32.*boolean/c\ -#include <linux/types.h>' \ - "${FILE}" > "${TMPFILE}" - - mv "${TMPFILE}" "${FILE}" -fi diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld deleted file mode 100644 index 516924126..000000000 --- a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.mld +++ /dev/null @@ -1,52 +0,0 @@ -# (c) Copyright 2004 Xilinx Inc. -# Author: Xilinx, Inc. -# -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by the -# Free Software Foundation; either version 2 of the License, or (at your -# option) any later version. -# -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -# FITNESS FOR A PARTICULAR PURPOSE. -# -# -# Xilinx hardware products are not intended for use in life support -# appliances, devices, or systems. Use in such applications is -# expressly prohibited. -# -# -# (c) Copyright 2002-2004 Xilinx Inc. -# All rights reserved. -# -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 675 Mass Ave, Cambridge, MA 02139, USA. - -OPTION psf_version = 2.1; - -BEGIN LIBRARY uboot OPTION DRC = uboot_drc; - -BEGIN ARRAY connected_periphs PROPERTY desc = "Peripherals connected to U-Boot"; -PROPERTY size = 0; -PARAM name = periph_name, desc = "Name of Peripheral connected", type = string; -END ARRAY - PARAMETER name = TARGET_DIR, desc = "Target Directory for U-Boot BSP", type = string; - -# location of persistent storage in the IIC EEPROM (defaults are set for ML300) -PARAMETER name = IIC_PERSISTENT_BASEADDR, desc = "Start of persistent storage block in the EEPROM address space", type = int, default = 1024; -PARAMETER name = IIC_PERSISTENT_HIGHADDR, desc = "End of persistent storage block in the EEPROM address space", type = int, default = 2047; -PARAMETER name = IIC_PERSISTENT_EEPROMADDR, desc = "Address of the EEPROM on the IIC bus", type = int, default = 0xA0; - -END LIBRARY diff --git a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl b/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl deleted file mode 100644 index 9d44f4493..000000000 --- a/board/xilinx/ml300/sw_services/uboot_v1_00_a/data/uboot_v2_1_0.tcl +++ /dev/null @@ -1,325 +0,0 @@ -# -# Author: Xilinx, Inc. -# -# -# This program is free software; you can redistribute it and/or modify it -# under the terms of the GNU General Public License as published by the -# Free Software Foundation; either version 2 of the License, or (at your -# option) any later version. -# -# -# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A -# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS -# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, -# XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE -# FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING -# ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. -# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO -# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY -# WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM -# CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND -# FITNESS FOR A PARTICULAR PURPOSE. -# -# -# Xilinx hardware products are not intended for use in life support -# appliances, devices, or systems. Use in such applications is -# expressly prohibited. -# -# -# (c) Copyright 2002-2004 Xilinx Inc. -# All rights reserved. -# -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Globals -lappend drvlist -set ltypes "../../../sw_services/uboot_v1_00_a/data/Ltypes" - -proc uboot_drc {lib_handle} { - puts "U-Boot DRC..." -} - -proc generate {libname} { - - global drvlist - - # Get list of peripherals connected to uboot - set conn_periphs [xget_handle $libname "ARRAY" "connected_periphs"] - #lappend drvlist - if {[string compare -nocase $conn_periphs ""] != 0} { - set conn_periphs_elems [xget_handle $conn_periphs "ELEMENTS" "*"] - # For each periph - foreach periph_elem $conn_periphs_elems { - set periph [xget_value $periph_elem "PARAMETER" "periph_name"] - # 1. Get driver - set drv [xget_swhandle $periph] - set posn [lsearch -exact $drvlist $drv] - if {$posn == -1} { - lappend drvlist $drv - } - } - - set file_handle [xopen_include_file "xparameters.h"] - puts $file_handle "\n/******************************************************************/\n" - puts $file_handle "/* U-Boot Redefines */" - puts $file_handle "\n/******************************************************************/\n" - close $file_handle - - foreach drv $drvlist { - set drvname [xget_value $drv "NAME"] - - #Redefines xparameters.h - if {[string compare -nocase $drvname "uartns550"] == 0} { - xredefine_uartns550 $drv "xparameters.h" - } elseif {[string compare -nocase $drvname "emac"] == 0} { - xredefine_emac $drv "xparameters.h" - } elseif {[string compare -nocase $drvname "iic"] == 0} { - xredefine_iic $drv "xparameters.h" - } - } - } - - # define core_clock - xredefine_params $libname "xparameters.h" "CORE_CLOCK_FREQ_HZ" - - # define the values for the persistent storage in IIC - xredefine_params $libname "xparameters.h" "IIC_PERSISTENT_BASEADDR" "IIC_PERSISTENT_HIGHADDR" "IIC_PERSISTENT_EEPROMADDR" - -} - -proc xget_corefreq {} { - set processor [xget_processor] - set name [xget_value $processor "NAME"] - puts "procname : $name" - set processor_driver [xget_swhandle [xget_value $processor "NAME"]] - puts "procdrv : $processor_driver" - if {[string compare -nocase $processor_driver ""] != 0} { - set arg "CORE_CLOCK_FREQ_HZ" - #set retval [xget_value $processor_driver "PARAMETER" $arg] - set retval [xget_dname [xget_value $processor_driver "NAME"] $arg] - return $retval - } -} - -# procedure that adds # defines to xparameters.h as XPAR_argument -proc xredefine_params {handle file_name args} { - - puts "xredfine ..." - # Open include file - set file_handle [xopen_include_file $file_name] - puts "args : $args" - - foreach arg $args { - if {[string compare -nocase $arg "CORE_CLOCK_FREQ_HZ"] == 0} { - set value [xget_corefreq] - puts "corefreq : $value" - } else { - set value [xget_value $handle "PARAMETER" $arg] - puts "value : $value" - } - - if {$value != ""} { - set value [xformat_addr_string $value $arg] - - if {[string compare -nocase $arg "IIC_PERSISTENT_BASEADDR"] == 0} { - set name "PERSISTENT_0_IIC_0_BASEADDR" - } elseif {[string compare -nocase $arg "IIC_PERSISTENT_HIGHADDR"] == 0} { - set name "PERSISTENT_0_IIC_0_HIGHADDR" - } elseif {[string compare -nocase $arg "IIC_PERSISTENT_EEPROMADDR"] == 0} { - set name "PERSISTENT_0_IIC_0_EEPROMADDR" - } else { - set name [string toupper $arg] - } - set name [format "XPAR_%s" $name] - puts $file_handle "#define $name $value" - } - } - - puts $file_handle "\n/******************************************************************/\n" - close $file_handle -} - -# uart redefines... -proc xredefine_uartns550 {drvhandle file_name} { - - xredefine_include_file $drvhandle $file_name "uartns550" "C_BASEADDR" "C_HIGHADDR" "CLOCK_HZ" "DEVICE_ID" - -} - -proc xredefine_emac {drvhandle file_name} { - - xredefine_include_file $drvhandle $file_name "emac" "C_BASEADDR" "C_HIGHADDR" "C_DMA_PRESENT" "C_MII_EXIST" "C_ERR_COUNT_EXIST" "DEVICE_ID" - -} - -proc xredefine_iic {drvhandle file_name} { - xredefine_include_file $drvhandle $file_name "iic" "C_BASEADDR" "C_HIGHADDR" "C_TEN_BIT_ADR" "DEVICE_ID" - -} - -####################### - -proc xredefine_include_file {drv_handle file_name drv_string args} { - - # Open include file - set file_handle [xopen_include_file $file_name] - - # Get all peripherals connected to this driver - set periphs [xget_periphs $drv_handle] - - set pname [format "XPAR_%s_" [string toupper $drv_string]] - - # Print all parameters for all peripherals - set device_id 0 - set sub_periphs 1 - foreach periph $periphs { - puts "$periph : $drv_string : $sub_periphs" - - for {set i 0} {$i < $sub_periphs} {incr i} { - foreach arg $args { - set name "${pname}${device_id}_" - - if {[string compare -nocase "CLOCK_HZ" $arg] == 0} { - set xdrv_string [format "%s%s" "X" $drv_string] - set value [xget_dname $xdrv_string $arg] - set name "${name}CLOCK_FREQ_HZ" - } else { - if {[string match C_* $arg]} { - set name [format "%s%s" $name [string range $arg 2 end]] - } else { - set name "${name}${arg}" - } - set value [xget_name $periph $arg] - } - - if {[string compare -nocase "uartns550" $drv_string] == 0} { - if {[string compare -nocase "C_BASEADDR" $arg] == 0} { - set value [format "(%s%s%s)" $value "+" "0x1000"] - } - } - - puts $file_handle "#define $name $value" - if {[string compare -nocase "DEVICE_ID" $arg] == 0} { - incr device_id - } - } - } - } - puts $file_handle "\n/******************************************************************/\n" - close $file_handle -} - -################################################## -# procedure post_generate -# This generates the drivers directory for uboot -# and runs the ltypes script -################################################## - -proc post_generate {lib_handle} { - - global drvlist - - # Create U-Boot tree structure - set pwd [pwd] - set common_dir "uboot/board/xilinx/common" - set xilinx_enet_dir "uboot/board/xilinx/xilinx_enet" - set ml300_dir "uboot/board/xilinx/ml300" - - exec bash -c "mkdir -p $common_dir $xilinx_enet_dir $ml300_dir" - - # Copy files for xilinx_ocp - xcopy_commonfiles - - foreach drv $drvlist { - set drvname [xget_value $drv "NAME"] - set ver [xget_value $drv "PARAMETER" "DRIVER_VER"] - set ver [string map {. _} $ver] - set dirname [format "%s_v%s" $drvname $ver] - - if {[string compare -nocase $drvname "emac"] == 0} { - xcopy_emac $drv $dirname - } elseif {[string compare -nocase $drvname "iic"] == 0} { - xcopy_iic $drv $dirname - } - } - - # Call Ltypes Script here - set uboot "uboot" - xltype_file $uboot - - # Move xparameters.h around - exec bash -c "cp ../../include/xparameters.h $ml300_dir" - - # copy the whole U-Boot BSP to its final destination - set value [xget_value $lib_handle "PARAMETER" TARGET_DIR] - puts "TARGET_DIR : $value" - - if {$value != ""} { - if {[file isdirectory $value] == 0} { - exec bash -c "mkdir -p $value" - } - exec bash -c "cp -Rp uboot/* $value" - } -} - -proc xcopy_commonfiles {} { - - global drvlist - - set common_dir "uboot/board/xilinx/common" - - foreach drv $drvlist { - set depends [xget_value $drv "OPTION" "DEPENDS"] - foreach dep $depends { - puts "dep : $dep" - if {[file isdirectory "../$dep"] == 1} { - exec bash -c "cp -f ../$dep/src/*.c $common_dir" - exec bash -c "cp -f ../$dep/src/*.h $common_dir" - } - } - } - -} - -proc xcopy_emac {drv_handle dirname} { - set emac "board/xilinx/xilinx_enet" - xcopy_dir $dirname $emac -} - -proc xcopy_iic {drv_handle dirname} { - set iic "board/xilinx/xilinx_iic" - xcopy_dir $dirname $iic -} - -proc xcopy_dir {srcdir dstdir} { - - set dstdirname [format "%s%s" "uboot/" $dstdir] - if {[file isdirectory "../$srcdir"] == 1} { - # Copy files from src to dst - exec bash -c "mkdir -p $dstdirname" - exec bash -c "cp -f ../$srcdir/src/*.c $dstdirname" - exec bash -c "cp -f ../$srcdir/src/*.h $dstdirname" - } else { - puts "$srcdir does not exist ..." - } -} - - -proc xltype_file {filename} { - - global ltypes - - puts $filename - - if {[file isdirectory $filename]} { - foreach entry [glob -nocomplain [file join $filename *]] { - xltype_file $entry - } - } else { - exec bash -c "$ltypes $filename" - } - -} diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds index 2d32225d4..913ff6ee7 100644 --- a/board/xilinx/ml300/u-boot.lds +++ b/board/xilinx/ml300/u-boot.lds @@ -64,14 +64,14 @@ SECTIONS cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) - cpu/ppc4xx/4xx_enet.o (.text) + drivers/net/4xx_enet.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) */ /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -142,6 +142,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug index 0552994f4..338392a07 100644 --- a/board/xilinx/ml300/u-boot.lds.debug +++ b/board/xilinx/ml300/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) - common/environment.o(.text) + common/env_embedded.o(.text) *(.text) *(.fixup) diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c index 955936d90..f388b775c 100644 --- a/board/xilinx/ml401/ml401.c +++ b/board/xilinx/ml401/ml401.c @@ -32,11 +32,11 @@ void do_reset (void) { -#ifdef CFG_GPIO_0 - *((unsigned long *)(CFG_GPIO_0_ADDR)) = - ++(*((unsigned long *)(CFG_GPIO_0_ADDR))); +#ifdef CONFIG_SYS_GPIO_0 + *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = + ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR))); #endif -#ifdef CFG_RESET_ADDRESS +#ifdef CONFIG_SYS_RESET_ADDRESS puts ("Reseting board\n"); asm ("bra r0"); #endif @@ -44,17 +44,17 @@ void do_reset (void) int gpio_init (void) { -#ifdef CFG_GPIO_0 - *((unsigned long *)(CFG_GPIO_0_ADDR)) = 0xFFFFFFFF; +#ifdef CONFIG_SYS_GPIO_0 + *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF; #endif return 0; } -#ifdef CFG_FSL_2 +#ifdef CONFIG_SYS_FSL_2 void fsl_isr2 (void *arg) { volatile int num; - *((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)) = - ++(*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4))); + *((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) = + ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4))); GET (num, 2); NGET (num, 2); puts("*"); diff --git a/board/xilinx/ml401/u-boot.lds b/board/xilinx/ml401/u-boot.lds index cb90854a3..b38f64877 100644 --- a/board/xilinx/ml401/u-boot.lds +++ b/board/xilinx/ml401/u-boot.lds @@ -61,6 +61,7 @@ SECTIONS { __bss_start = .; *(.bss) + . = ALIGN(4); __bss_end = .; } __end = . ; diff --git a/board/xilinx/ml507/.gitignore b/board/xilinx/ml507/.gitignore new file mode 100644 index 000000000..f6418a0c5 --- /dev/null +++ b/board/xilinx/ml507/.gitignore @@ -0,0 +1 @@ +/config.tmp diff --git a/board/xilinx/ml507/Makefile b/board/xilinx/ml507/Makefile index 72837048a..de23f296c 100644 --- a/board/xilinx/ml507/Makefile +++ b/board/xilinx/ml507/Makefile @@ -1,6 +1,7 @@ # -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2008 +# Ricardo Ribalda,Universidad Autonoma de Madrid, ricardo.ribalda@uam.es +# This work has been supported by: Qtechnology http://qtec.com/ # # See file CREDITS for list of people who contributed to this # project. @@ -21,38 +22,6 @@ # MA 02111-1307 USA # -include $(TOPDIR)/config.mk -ifneq ($(OBJTREE),$(SRCTREE)) -endif +COBJS += $(BOARD).o -INCS := -CFLAGS += $(INCS) -HOST_CFLAGS += $(INCS) - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o - -SOBJS = init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $^ - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### +include $(SRCTREE)/board/xilinx/ppc440-generic/Makefile diff --git a/board/xilinx/ml507/config.mk b/board/xilinx/ml507/config.mk index e827e8a93..51448ce7f 100644 --- a/board/xilinx/ml507/config.mk +++ b/board/xilinx/ml507/config.mk @@ -1,6 +1,7 @@ # -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com # # See file CREDITS for list of people who contributed to this # project. @@ -20,8 +21,6 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +# -ifndef TEXT_BASE -TEXT_BASE = 0x04000000 -endif +sinclude $(SRCTREE)/board/xilinx/ppc440-generic/config.mk diff --git a/board/xilinx/ml507/init.S b/board/xilinx/ml507/init.S deleted file mode 100644 index 3228a65e5..000000000 --- a/board/xilinx/ml507/init.S +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2008 - * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es - * This work has been supported by: QTechnology http://qtec.com/ - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. -*/ - -#include <ppc_asm.tmpl> -#include <config.h> -#include <asm-ppc/mmu.h> - -.section .bootpg,"ax" -.globl tlbtab - -tlbtab: -tlbtab_start - /* SDRAM */ -tlbentry(XPAR_DDR2_SDRAM_MEM_BASEADDR, SZ_256M, CFG_SDRAM_BASE, 0, - AC_R | AC_W | AC_X | SA_G | SA_I) - /* UART */ -tlbentry(XPAR_UARTLITE_0_BASEADDR, SZ_64K, XPAR_UARTLITE_0_BASEADDR, 0, - AC_R | AC_W | SA_G | SA_I) - /* PIC */ -tlbentry(XPAR_INTC_0_BASEADDR, SZ_64K, XPAR_INTC_0_BASEADDR, 0, - AC_R | AC_W | SA_G | SA_I) -#ifdef XPAR_IIC_EEPROM_BASEADDR - /* I2C */ -tlbentry(XPAR_IIC_EEPROM_BASEADDR, SZ_64K, XPAR_IIC_EEPROM_BASEADDR, 0, - AC_R | AC_W | SA_G | SA_I) -#endif -#ifdef XPAR_LLTEMAC_0_BASEADDR - /* Net */ -tlbentry(XPAR_LLTEMAC_0_BASEADDR, SZ_64K, XPAR_LLTEMAC_0_BASEADDR, 0, - AC_R | AC_W | SA_G | SA_I) -#endif -#ifdef XPAR_FLASH_MEM0_BASEADDR - /*Flash*/ -tlbentry(XPAR_FLASH_MEM0_BASEADDR, SZ_256M, XPAR_FLASH_MEM0_BASEADDR, 0, - AC_R | AC_W | AC_X | SA_G | SA_I) -#endif -tlbtab_end diff --git a/board/xilinx/ml507/ml507.c b/board/xilinx/ml507/ml507.c index d4993039e..f9789cf0f 100644 --- a/board/xilinx/ml507/ml507.c +++ b/board/xilinx/ml507/ml507.c @@ -20,28 +20,9 @@ #include <common.h> #include <asm/processor.h> -int board_pre_init(void) -{ - return 0; -} int checkboard(void) { - puts("ML507 Board\n"); + puts("Xilinx ML507 Board\n"); return 0; } - -phys_size_t initdram(int board_type) -{ - return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, - CFG_SDRAM_SIZE_MB * 1024 * 1024); -} - -void get_sys_info(sys_info_t * sysInfo) -{ - sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; - sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; - sysInfo->freqPCI = 0; - - return; -} diff --git a/board/xilinx/ml507/xparameters.h b/board/xilinx/ml507/xparameters.h index 77d2ddf9b..1992fff22 100644 --- a/board/xilinx/ml507/xparameters.h +++ b/board/xilinx/ml507/xparameters.h @@ -21,15 +21,14 @@ #ifndef XPARAMETER_H #define XPARAMETER_H -#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 -#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 -#define XPAR_INTC_0_BASEADDR 0x81800000 -#define XPAR_LLTEMAC_0_BASEADDR 0x81C00000 -#define XPAR_UARTLITE_0_BASEADDR 0x84000000 -#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 -#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 -#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 #define XPAR_UARTLITE_0_BAUDRATE 9600 #endif diff --git a/board/xilinx/ppc405-generic/.gitignore b/board/xilinx/ppc405-generic/.gitignore new file mode 100644 index 000000000..b644f5994 --- /dev/null +++ b/board/xilinx/ppc405-generic/.gitignore @@ -0,0 +1 @@ +config.tmp diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile new file mode 100644 index 000000000..b56bb490a --- /dev/null +++ b/board/xilinx/ppc405-generic/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +endif + +INCS := +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/ppc405-generic/config.mk b/board/xilinx/ppc405-generic/config.mk new file mode 100644 index 000000000..6d767552d --- /dev/null +++ b/board/xilinx/ppc405-generic/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp diff --git a/board/xilinx/ml507/u-boot-ram.lds b/board/xilinx/ppc405-generic/u-boot-ram.lds index 2c98d2785..6bbd3bd47 100644 --- a/board/xilinx/ml507/u-boot-ram.lds +++ b/board/xilinx/ppc405-generic/u-boot-ram.lds @@ -22,7 +22,7 @@ */ OUTPUT_ARCH(powerpc) -ENTRY(_start_440) +ENTRY(_start) SECTIONS { @@ -127,7 +127,7 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/xilinx/ml507/u-boot-rom.lds b/board/xilinx/ppc405-generic/u-boot-rom.lds index d5da018ba..d09400655 100644 --- a/board/xilinx/ml507/u-boot-rom.lds +++ b/board/xilinx/ppc405-generic/u-boot-rom.lds @@ -22,7 +22,7 @@ */ OUTPUT_ARCH(powerpc) -ENTRY(_start_440) +ENTRY(_start) SECTIONS { @@ -137,7 +137,7 @@ SECTIONS *(COMMON) } - ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); _end = . ; PROVIDE (end = .); diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c new file mode 100644 index 000000000..9bd1770eb --- /dev/null +++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +ulong __get_PCI_freq(void) +{ + return 0; +} + +ulong get_PCI_freq(void) __attribute__((weak, alias("__get_PCI_freq"))); + +int __board_pre_init(void) +{ + return 0; +} +int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); + +int __checkboard(void) +{ + puts("Xilinx PPC405 Generic Board\n"); + return 0; +} +int checkboard(void) __attribute__((weak, alias("__checkboard"))); + +phys_size_t __initdram(int board_type) +{ + return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, + CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); +} +phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); + +void __get_sys_info(sys_info_t *sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0; + + return; +} +void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h new file mode 100644 index 000000000..e8e8ced09 --- /dev/null +++ b/board/xilinx/ppc405-generic/xparameters.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_SPI_0_BASEADDR 0x83400000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 +#define XPAR_SPI_0_NUM_TRANSFER_BITS 8 + +#endif diff --git a/board/xilinx/ppc440-generic/.gitignore b/board/xilinx/ppc440-generic/.gitignore new file mode 100644 index 000000000..f6418a0c5 --- /dev/null +++ b/board/xilinx/ppc440-generic/.gitignore @@ -0,0 +1 @@ +/config.tmp diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile new file mode 100644 index 000000000..bf0a6ba4f --- /dev/null +++ b/board/xilinx/ppc440-generic/Makefile @@ -0,0 +1,62 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +endif + +INCS := +CFLAGS += $(INCS) +HOST_CFLAGS += $(INCS) + +LIB = $(obj)lib$(BOARD).a + +COBJS += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o + +SOBJS += ../../xilinx/ppc440-generic/init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/xilinx/ppc440-generic/config.mk b/board/xilinx/ppc440-generic/config.mk new file mode 100644 index 000000000..6d767552d --- /dev/null +++ b/board/xilinx/ppc440-generic/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2008 +# Ricardo Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es +# Work supported by Qtechnology http://www.qtec.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp diff --git a/board/xilinx/ppc440-generic/init.S b/board/xilinx/ppc440-generic/init.S new file mode 100644 index 000000000..1409467ea --- /dev/null +++ b/board/xilinx/ppc440-generic/init.S @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <ppc_asm.tmpl> +#include <config.h> +#include <asm-ppc/mmu.h> + +.section .bootpg,"ax" +.globl tlbtab + +tlbtab: +tlbtab_start +tlbentry(0x00000000, SZ_256M, 0x00000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x10000000, SZ_256M, 0x10000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x20000000, SZ_256M, 0x20000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x30000000, SZ_256M, 0x30000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x40000000, SZ_256M, 0x40000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x50000000, SZ_256M, 0x50000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x60000000, SZ_256M, 0x60000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x70000000, SZ_256M, 0x70000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x80000000, SZ_256M, 0x80000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0x90000000, SZ_256M, 0x90000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xa0000000, SZ_256M, 0xa0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xb0000000, SZ_256M, 0xb0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xc0000000, SZ_256M, 0xc0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xd0000000, SZ_256M, 0xd0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xe0000000, SZ_256M, 0xe0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbentry(0xf0000000, SZ_256M, 0xf0000000, 0, AC_R | AC_W | AC_X | SA_G | SA_I) +tlbtab_end diff --git a/board/freescale/m5235evb/u-boot.lds b/board/xilinx/ppc440-generic/u-boot-ram.lds index 33133a0fc..d65f3de67 100644 --- a/board/freescale/m5235evb/u-boot.lds +++ b/board/xilinx/ppc440-generic/u-boot-ram.lds @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -21,9 +21,9 @@ * MA 02111-1307 USA */ -OUTPUT_ARCH(m68k) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ +OUTPUT_ARCH(powerpc) +ENTRY(_start_440) + SECTIONS { /* Read-only sections, merged into text segment: */ @@ -55,15 +55,6 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/mcf523x/start.o (.text) - cpu/mcf523x/cpu_init.o (.text) - lib_m68k/traps.o (.text) - lib_m68k/interrupts.o (.text) - common/dlmalloc.o (.text) - lib_generic/zlib.o (.text) - - . = DEFINED(env_offset) ? env_offset : .; - common/environment.o (.text) *(.text) *(.fixup) @@ -75,6 +66,8 @@ SECTIONS { *(.rodata) *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } @@ -84,12 +77,9 @@ SECTIONS . = (. + 0x00FF) & 0xFFFFFF00; _erotext = .; PROVIDE (erotext = .); - .reloc : { - __got_start = .; *(.got) - __got_end = .; _GOT2_TABLE_ = .; *(.got2) _FIXUP_TABLE_ = .; @@ -131,14 +121,15 @@ SECTIONS __bss_start = .; .bss (NOLOAD) : { - _sbss = .; *(.sbss) *(.scommon) *(.dynbss) *(.bss) *(COMMON) . = ALIGN(4); - _ebss = .; } + + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); + _end = . ; PROVIDE (end = .); } diff --git a/board/xilinx/ppc440-generic/u-boot-rom.lds b/board/xilinx/ppc440-generic/u-boot-rom.lds new file mode 100644 index 000000000..8b468eee7 --- /dev/null +++ b/board/xilinx/ppc440-generic/u-boot-rom.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +ENTRY(_start_440) + +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + + ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c new file mode 100644 index 000000000..0c3d667c5 --- /dev/null +++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#include <config.h> +#include <common.h> +#include <asm/processor.h> + +int __board_pre_init(void) +{ + return 0; +} +int board_pre_init(void) __attribute__((weak, alias("__board_pre_init"))); + +int __checkboard(void) +{ + puts("Xilinx PPC440 Generic Board\n"); + return 0; +} +int checkboard(void) __attribute__((weak, alias("__checkboard"))); + +phys_size_t __initdram(int board_type) +{ + return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR, + CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024); +} +phys_size_t initdram(int) __attribute__((weak, alias("__initdram"))); + +void __get_sys_info(sys_info_t *sysInfo) +{ + sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; + sysInfo->freqPLB = XPAR_PLB_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0; + + return; +} +void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info"))); diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h new file mode 100644 index 000000000..1992fff22 --- /dev/null +++ b/board/xilinx/ppc440-generic/xparameters.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * based on xparameters-ml507.h by Xilinx + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. +*/ + +#ifndef XPARAMETER_H +#define XPARAMETER_H + +#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 +#define XPAR_IIC_EEPROM_BASEADDR 0x81600000 +#define XPAR_INTC_0_BASEADDR 0x81800000 +#define XPAR_UARTLITE_0_BASEADDR 0x84000000 +#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 +#define XPAR_PLB_CLOCK_FREQ_HZ 100000000 +#define XPAR_CORE_CLOCK_FREQ_HZ 400000000 +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13 +#define XPAR_UARTLITE_0_BAUDRATE 9600 + +#endif diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c index d3403038e..0b100d215 100644 --- a/board/xilinx/xilinx_enet/emac_adapter.c +++ b/board/xilinx/xilinx_enet/emac_adapter.c @@ -56,7 +56,7 @@ static XEmac Emac; static char etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ /* hardcoded MAC address for the Xilinx EMAC Core when env is nowhere*/ -#ifdef CFG_ENV_IS_NOWHERE +#ifdef CONFIG_ENV_IS_NOWHERE static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; #endif @@ -87,7 +87,7 @@ eth_init(bd_t * bis) /* make sure the Emac is stopped before it is started */ (void) XEmac_Stop(&Emac); -#ifdef CFG_ENV_IS_NOWHERE +#ifdef CONFIG_ENV_IS_NOWHERE memcpy(bis->bi_enetaddr, EMACAddr, 6); #endif diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c index 37dce0391..58aaeb769 100644 --- a/board/xilinx/xilinx_iic/iic_adapter.c +++ b/board/xilinx/xilinx_iic/iic_adapter.c @@ -42,7 +42,7 @@ #include <environment.h> #include <net.h> -#ifdef CFG_ENV_IS_IN_EEPROM +#ifdef CONFIG_ENV_IS_IN_EEPROM #include <i2c.h> #include "xiic_l.h" @@ -72,7 +72,7 @@ send(u32 adr, u8 * data, u32 len) memcpy(&sendBuf[2], &data[pos], wlen); /* Send to EEPROM through iic bus */ - ret = XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, + ret = XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, sendBuf, wlen + 2); udelay(IIC_DELAY); @@ -93,11 +93,11 @@ receive(u32 adr, u8 * data, u32 len) /* Provide EEPROM address */ ret = - XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, address, + XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, address, 2); /* Receive data from EEPROM */ ret = - XIic_Recv(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, data, len); + XIic_Recv(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, data, len); } /************************************************************************ @@ -221,7 +221,7 @@ read_crc(uchar * buffer, int len) u8 pre; /* previous EEPROM data bit */ int i, loc; - addr = CFG_ENV_OFFSET; /* start from first env address */ + addr = CONFIG_ENV_OFFSET; /* start from first env address */ n = 0; pre = 1; stop = 1; @@ -229,7 +229,7 @@ read_crc(uchar * buffer, int len) /* calculate runtime CRC according to ML300 and read back old CRC stored in the EEPROM */ - while (n < CFG_ENV_SIZE) { + while (n < CONFIG_ENV_SIZE) { receive(addr, buffer, len); /* found two null chars, end of env */ @@ -270,7 +270,7 @@ read_crc(uchar * buffer, int len) crc = 0; n = 0; addr = - CFG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t, + CONFIG_ENV_OFFSET - offsetof(env_t, crc) + offsetof(env_t, data); /* calculate u-boot crc */ while (n < ENV_SIZE) { @@ -464,7 +464,7 @@ save_env(void) /* update EEPROM env values if there is enough space */ if (update_crc(len, (uchar *)eprom) == 0) - send(CFG_ENV_OFFSET, (uchar *)eprom, len + 6); + send(CONFIG_ENV_OFFSET, (uchar *)eprom, len + 6); } /************************************************************************ @@ -483,7 +483,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) /* then read out EEPROM content for runtime u-boot CRC calculation */ receive(addr, buffer, len); - if (addr + len - CFG_ENV_OFFSET == CFG_ENV_SIZE) + if (addr + len - CONFIG_ENV_OFFSET == CONFIG_ENV_SIZE) /* end of runtime crc read */ ++envStep; return 0; @@ -492,7 +492,7 @@ i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) if (len < 2) { /* when call getenv_r */ receive(addr, buffer, len); - } else if (addr + len < CFG_ENV_OFFSET + CFG_ENV_SIZE) { + } else if (addr + len < CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) { /* calling env_relocate(), but don't read out crc value from EEPROM */ receive(addr, buffer + 4, len); @@ -511,7 +511,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) { /* save env on last page write called by u-boot */ - if (addr + len >= CFG_ENV_OFFSET + CFG_ENV_SIZE) + if (addr + len >= CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) save_env(); return 0; diff --git a/board/xilinx/xupv2p/xparameters.h b/board/xilinx/xupv2p/xparameters.h deleted file mode 100644 index 9e5ebdabc..000000000 --- a/board/xilinx/xupv2p/xparameters.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2007 Michal Simek - * - * Michal SIMEK <monstr@monstr.eu> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4 - */ - -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 11 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 1 - -/* Uart pheriphery is RS232_Uart_1 */ -#define XILINX_UARTLITE_BASEADDR 0x40600000 -#define XILINX_UARTLITE_BAUDRATE 115200 - -/* GPIO is LEDs_4Bit*/ -#define XILINX_GPIO_BASEADDR 0x40000000 - -/* FLASH doesn't exist none */ - -/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */ -#define XILINX_RAM_START 0x30000000 -#define XILINX_RAM_SIZE 0x10000000 - -/* Sysace Controller is SysACE_CompactFlash */ -#define XILINX_SYSACE_BASEADDR 0x41800000 -#define XILINX_SYSACE_HIGHADDR 0x4180ffff -#define XILINX_SYSACE_MEM_WIDTH 16 - -/* Ethernet controller is Ethernet_MAC */ -#define XILINX_EMACLITE_BASEADDR 0x40C00000 diff --git a/board/xm250/flash.c b/board/xm250/flash.c index aab47a0a5..b02149cd6 100644 --- a/board/xm250/flash.c +++ b/board/xm250/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -84,7 +84,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -104,13 +104,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0] ); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); return size; } @@ -232,10 +232,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -305,7 +305,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -439,7 +439,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } @@ -484,7 +484,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) reset_timer_masked (); while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; break; @@ -516,7 +516,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot) *addr = INTEL_PROTECT; /* set */ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { - if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) + if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) { printf("Flash lock bit operation timed out\n"); rc = 1; diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S index 2ebd39554..8230550c6 100644 --- a/board/xm250/lowlevel_init.S +++ b/board/xm250/lowlevel_init.S @@ -24,7 +24,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -51,98 +51,98 @@ lowlevel_init: /* Set up GPIO pins first */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL + ldr r1, =CONFIG_SYS_GRER0_VAL str r1, [r0] ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL + ldr r1, =CONFIG_SYS_GRER1_VAL str r1, [r0] ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL + ldr r1, =CONFIG_SYS_GRER2_VAL str r1, [r0] ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL + ldr r1, =CONFIG_SYS_GFER0_VAL str r1, [r0] ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL + ldr r1, =CONFIG_SYS_GFER1_VAL str r1, [r0] ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL + ldr r1, =CONFIG_SYS_GFER2_VAL str r1, [r0] ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] ldr r0, =GAFR0_L - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] /* enable GPIO pins */ ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* SET_LED 1 */ ldr r3, =MSC1 /* low - bank 2 Lubbock Registers / SRAM */ - ldr r2, =CFG_MSC1_VAL /* high - bank 3 Ethernet Controller */ + ldr r2, =CONFIG_SYS_MSC1_VAL /* high - bank 3 Ethernet Controller */ str r2, [r3] /* need to set MSC1 before trying to write to the HEX LEDs */ ldr r2, [r3] /* need to read it back to make sure the value latches (see MSC section of manual) */ @@ -181,47 +181,47 @@ mem_init: @ Step 2a @ write msc0, read back to ensure data latches @ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] @ write msc1 - ldr r2, =CFG_MSC1_VAL + ldr r2, =CONFIG_SYS_MSC1_VAL str r2, [r1, #MSC1_OFFSET] ldr r2, [r1, #MSC1_OFFSET] @ write msc2 - ldr r2, =CFG_MSC2_VAL + ldr r2, =CONFIG_SYS_MSC2_VAL str r2, [r1, #MSC2_OFFSET] ldr r2, [r1, #MSC2_OFFSET] @ Step 2b @ write mecr - ldr r2, =CFG_MECR_VAL + ldr r2, =CONFIG_SYS_MECR_VAL str r2, [r1, #MECR_OFFSET] @ write mcmem0 - ldr r2, =CFG_MCMEM0_VAL + ldr r2, =CONFIG_SYS_MCMEM0_VAL str r2, [r1, #MCMEM0_OFFSET] @ write mcmem1 - ldr r2, =CFG_MCMEM1_VAL + ldr r2, =CONFIG_SYS_MCMEM1_VAL str r2, [r1, #MCMEM1_OFFSET] @ write mcatt0 - ldr r2, =CFG_MCATT0_VAL + ldr r2, =CONFIG_SYS_MCATT0_VAL str r2, [r1, #MCATT0_OFFSET] @ write mcatt1 - ldr r2, =CFG_MCATT1_VAL + ldr r2, =CONFIG_SYS_MCATT1_VAL str r2, [r1, #MCATT1_OFFSET] @ write mcio0 - ldr r2, =CFG_MCIO0_VAL + ldr r2, =CONFIG_SYS_MCIO0_VAL str r2, [r1, #MCIO0_OFFSET] @ write mcio1 - ldr r2, =CFG_MCIO1_VAL + ldr r2, =CONFIG_SYS_MCIO1_VAL str r2, [r1, #MCIO1_OFFSET] /*SET_LED 3 */ @@ -229,14 +229,14 @@ mem_init: @ Step 2c @ fly-by-dma is defeatured on this part @ write flycnfg - @ldr r2, =CFG_FLYCNFG_VAL + @ldr r2, =CONFIG_SYS_FLYCNFG_VAL @str r2, [r1, #FLYCNFG_OFFSET] /* FIXME Does this sequence really make sense */ #ifdef REDBOOT_WAY @ Step 2d @ get the mdrefr settings - ldr r3, =CFG_MDREFR_VAL + ldr r3, =CONFIG_SYS_MDREFR_VAL @ extract DRI field (we need a valid DRI field) @ @@ -319,7 +319,7 @@ mem_init: #else @ Step 2d @ get the mdrefr settings - ldr r4, =CFG_MDREFR_VAL + ldr r4, =CONFIG_SYS_MDREFR_VAL @ write back mdrefr @ @@ -367,7 +367,7 @@ mem_init: @ Step 4d @ fetch platform value of mdcnfg @ - ldr r2, =CFG_MDCNFG_VAL + ldr r2, =CONFIG_SYS_MDCNFG_VAL @ disable all sdram banks @ @@ -404,7 +404,7 @@ mem_init: @ Access memory *not yet enabled* for CBR refresh cycles (8) @ - CBR is generated for all banks - ldr r2, =CFG_DRAM_BASE + ldr r2, =CONFIG_SYS_DRAM_BASE str r2, [r2] str r2, [r2] str r2, [r2] @@ -434,7 +434,7 @@ mem_init: @ Step 4h @ write mdmrs @ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] @ Done Memory Init @@ -453,7 +453,7 @@ mem_init: @ Set interrupt mask register @ - ldr r1, =CFG_ICMR_VAL + ldr r1, =CONFIG_SYS_ICMR_VAL ldr r2, =ICMR str r1, [r2] @@ -469,7 +469,7 @@ mem_init: @ set core clocks @ - ldr r2, =CFG_CCCR_VAL + ldr r2, =CONFIG_SYS_CCCR_VAL ldr r1, =CCCR str r2, [r1] @@ -492,7 +492,7 @@ mem_init: @ Turn on needed clocks @ ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL + ldr r2, =CONFIG_SYS_CKEN_VAL str r2, [r1] /*SET_LED 7 */ diff --git a/board/xm250/u-boot.lds b/board/xm250/u-boot.lds index bf42e9f3d..1e88820bc 100644 --- a/board/xm250/u-boot.lds +++ b/board/xm250/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/xpedite1k/config.mk b/board/xpedite1k/config.mk index e42b273a4..33dfbf1c0 100644 --- a/board/xpedite1k/config.mk +++ b/board/xpedite1k/config.mk @@ -38,5 +38,5 @@ PLATFORM_CPPFLAGS += -DDEBUG endif ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 endif diff --git a/board/xpedite1k/flash.c b/board/xpedite1k/flash.c index ce5d4e180..0711931e6 100644 --- a/board/xpedite1k/flash.c +++ b/board/xpedite1k/flash.c @@ -57,9 +57,9 @@ #define FLASH_SRAM_SEL_VAL 1 -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ -static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = { +static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = { {0xfff80000}, /* 0:000: configuraton 3 */ {0xfff90000}, /* 1:001: configuraton 4 */ {0xfffa0000}, /* 2:010: configuraton 7 */ @@ -89,7 +89,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data); unsigned long flash_init (void) { unsigned long total_b = 0; - unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS]; unsigned short index = 0; int i; @@ -98,7 +98,7 @@ unsigned long flash_init (void) DEBUGF("FLASH: Index: %d\n", index); /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; flash_info[i].sector_count = -1; flash_info[i].size = 0; @@ -366,7 +366,7 @@ int wait_for_DQ7(flash_info_t *info, int sect) start = get_timer (0); last = start; while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return -1; } @@ -594,7 +594,7 @@ static int write_word (flash_info_t * info, ulong dest, ulong data) while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/xpedite1k/init.S b/board/xpedite1k/init.S index 6cb20e40f..8a04f4f06 100644 --- a/board/xpedite1k/init.S +++ b/board/xpedite1k/init.S @@ -87,10 +87,10 @@ tlbtab: tlbtab_start tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) - tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) - tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I ) tlbtab_end diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds index 70b1e38f3..13c52b9f6 100644 --- a/board/xpedite1k/u-boot.lds +++ b/board/xpedite1k/u-boot.lds @@ -79,7 +79,7 @@ SECTIONS lib_generic/zlib.o (.text) /* . = env_offset;*/ -/* common/environment.o(.text)*/ +/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -150,6 +150,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug index e0da854a4..116c2ba6a 100644 --- a/board/xpedite1k/u-boot.lds.debug +++ b/board/xpedite1k/u-boot.lds.debug @@ -68,7 +68,7 @@ SECTIONS lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) -/* common/environment.o(.text) */ +/* common/env_embedded.o(.text) */ *(.text) *(.fixup) diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index c94a345d9..58bcfaf7b 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -40,7 +40,7 @@ int board_early_init_f(void) /* TBS: Setup the GPIO access for the user LEDs */ mfsdr(sdr_pfc0, sdrreg); mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00); - out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); + out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); LED0_OFF(); LED1_OFF(); LED2_OFF(); @@ -129,7 +129,7 @@ phys_size_t initdram (int board_type) } -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { uint *pstart = (uint *) 0x00000000; @@ -231,7 +231,7 @@ int pci_pre_init(struct pci_controller * hose ) return (0); } -#if defined(CFG_PCI_FORCE_PCI_CONV) +#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) /* Setup System Device Register PCIX0_XCR */ mfsdr(sdr_xcr, strap); strap &= 0x0f000000; @@ -249,7 +249,7 @@ int pci_pre_init(struct pci_controller * hose ) * may not be sufficient for a given board. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) void pci_target_init(struct pci_controller * hose ) { /*--------------------------------------------------------------------------+ @@ -264,7 +264,7 @@ void pci_target_init(struct pci_controller * hose ) * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); + out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); out32r( PCIX0_PIM0LAH, 0 ); out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); @@ -273,12 +273,12 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); + out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ /************************************************************************* @@ -299,7 +299,7 @@ void pci_target_init(struct pci_controller * hose ) #if defined(CONFIG_PCI) int is_pci_host(struct pci_controller *hose) { - return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0); + return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); } #endif /* defined(CONFIG_PCI) */ @@ -317,7 +317,7 @@ int post_hotkeys_pressed(void) void post_word_store (ulong a) { volatile ulong *save_addr = - (volatile ulong *)(CFG_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); *save_addr = a; } @@ -325,7 +325,7 @@ void post_word_store (ulong a) ulong post_word_load (void) { volatile ulong *save_addr = - (volatile ulong *)(CFG_POST_WORD_ADDR); + (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); return *save_addr; } @@ -342,7 +342,7 @@ void board_get_enetaddr (uchar * enet) unsigned char buff[0x100], *cp; /* Initialize I2C */ - i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* Read 256 bytes in EEPROM */ i2c_read (0x50, 0, 1, buff, 0x100); diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c index a188e2440..736905ad7 100644 --- a/board/xsengine/flash.c +++ b/board/xsengine/flash.c @@ -29,7 +29,7 @@ #define SWAP(x) __swab32(x) -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Functions */ static ulong flash_get_size (vu_long *addr, flash_info_t *info); @@ -43,7 +43,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]); @@ -61,8 +61,8 @@ unsigned long flash_init (void) } /* Protect monitor and environment sectors */ - flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] ); - flash_protect ( FLAG_PROTECT_SET,CFG_ENV_ADDR,CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] ); + flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); return size; } @@ -338,7 +338,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) last = start; addr = (vu_long*)(info->start[l_sect]); while ((addr[0] & 0x00800080) != 0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); return 1; } @@ -462,7 +462,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong data) /* data polling for D7 */ start = get_timer (0); while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { return (1); } } diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S index b0b156124..0d94ab60a 100644 --- a/board/xsengine/lowlevel_init.S +++ b/board/xsengine/lowlevel_init.S @@ -2,7 +2,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE .globl lowlevel_init lowlevel_init: @@ -14,93 +14,93 @@ lowlevel_init: /* General purpose set registers */ ldr r0, =GPSR0 - ldr r1, =CFG_GPSR0_VAL + ldr r1, =CONFIG_SYS_GPSR0_VAL str r1, [r0] ldr r0, =GPSR1 - ldr r1, =CFG_GPSR1_VAL + ldr r1, =CONFIG_SYS_GPSR1_VAL str r1, [r0] ldr r0, =GPSR2 - ldr r1, =CFG_GPSR2_VAL + ldr r1, =CONFIG_SYS_GPSR2_VAL str r1, [r0] /* General purpose clear registers */ ldr r0, =GPCR0 - ldr r1, =CFG_GPCR0_VAL + ldr r1, =CONFIG_SYS_GPCR0_VAL str r1, [r0] ldr r0, =GPCR1 - ldr r1, =CFG_GPCR1_VAL + ldr r1, =CONFIG_SYS_GPCR1_VAL str r1, [r0] ldr r0, =GPCR2 - ldr r1, =CFG_GPCR2_VAL + ldr r1, =CONFIG_SYS_GPCR2_VAL str r1, [r0] /* General rising edge registers */ ldr r0, =GRER0 - ldr r1, =CFG_GRER0_VAL + ldr r1, =CONFIG_SYS_GRER0_VAL str r1, [r0] ldr r0, =GRER1 - ldr r1, =CFG_GRER1_VAL + ldr r1, =CONFIG_SYS_GRER1_VAL str r1, [r0] ldr r0, =GRER2 - ldr r1, =CFG_GRER2_VAL + ldr r1, =CONFIG_SYS_GRER2_VAL str r1, [r0] /* General falling edge registers */ ldr r0, =GFER0 - ldr r1, =CFG_GFER0_VAL + ldr r1, =CONFIG_SYS_GFER0_VAL str r1, [r0] ldr r0, =GFER1 - ldr r1, =CFG_GFER1_VAL + ldr r1, =CONFIG_SYS_GFER1_VAL str r1, [r0] ldr r0, =GFER2 - ldr r1, =CFG_GFER2_VAL + ldr r1, =CONFIG_SYS_GFER2_VAL str r1, [r0] /* General edge detect registers */ ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] /* General alternate function registers */ ldr r0, =GAFR0_L /* [0:15] */ - ldr r1, =CFG_GAFR0_L_VAL + ldr r1, =CONFIG_SYS_GAFR0_L_VAL str r1, [r0] ldr r0, =GAFR0_U /* [31:16] */ - ldr r1, =CFG_GAFR0_U_VAL + ldr r1, =CONFIG_SYS_GAFR0_U_VAL str r1, [r0] ldr r0, =GAFR1_L /* [47:32] */ - ldr r1, =CFG_GAFR1_L_VAL + ldr r1, =CONFIG_SYS_GAFR1_L_VAL str r1, [r0] ldr r0, =GAFR1_U /* [63:48] */ - ldr r1, =CFG_GAFR1_U_VAL + ldr r1, =CONFIG_SYS_GAFR1_U_VAL str r1, [r0] ldr r0, =GAFR2_L /* [79:64] */ - ldr r1, =CFG_GAFR2_L_VAL + ldr r1, =CONFIG_SYS_GAFR2_L_VAL str r1, [r0] ldr r0, =GAFR2_U /* [80] */ - ldr r1, =CFG_GAFR2_U_VAL + ldr r1, =CONFIG_SYS_GAFR2_U_VAL str r1, [r0] /* General purpose direction registers */ ldr r0, =GPDR0 - ldr r1, =CFG_GPDR0_VAL + ldr r1, =CONFIG_SYS_GPDR0_VAL str r1, [r0] ldr r0, =GPDR1 - ldr r1, =CFG_GPDR1_VAL + ldr r1, =CONFIG_SYS_GPDR1_VAL str r1, [r0] ldr r0, =GPDR2 - ldr r1, =CFG_GPDR2_VAL + ldr r1, =CONFIG_SYS_GPDR2_VAL str r1, [r0] /* Power manager sleep status */ ldr r0, =PSSR - ldr r1, =CFG_PSSR_VAL + ldr r1, =CONFIG_SYS_PSSR_VAL str r1, [r0] /* ---- MEMORY INITIALISATION ---- */ @@ -121,17 +121,17 @@ mem_init: /* ---- FLASH INITIALISATION ---- */ /* Write MSC0 and read back to ensure data change is accepted by cpu */ - ldr r2, =CFG_MSC0_VAL + ldr r2, =CONFIG_SYS_MSC0_VAL str r2, [r1, #MSC0_OFFSET] ldr r2, [r1, #MSC0_OFFSET] /* ---- SDRAM INITIALISATION ---- */ /* get the MDREFR settings */ - ldr r2, =CFG_MDREFR_VAL + ldr r2, =CONFIG_SYS_MDREFR_VAL str r2, [r1, #MDREFR_OFFSET] /* fetch platform value of MDCNFG */ - ldr r2, =CFG_MDCNFG_VAL + ldr r2, =CONFIG_SYS_MDCNFG_VAL /* disable all sdram banks */ bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1) @@ -153,7 +153,7 @@ mem_init: /* Access memory *not yet enabled* for CBR refresh cycles (8) */ /* CBR is generated for all banks */ - ldr r2, =CFG_DRAM_BASE + ldr r2, =CONFIG_SYS_DRAM_BASE str r2, [r2] str r2, [r2] str r2, [r2] @@ -172,7 +172,7 @@ mem_init: str r2, [r1, #MDCNFG_OFFSET] /* write MDMRS to trigger an MSR command to all enabled SDRAM banks */ - ldr r2, =CFG_MDMRS_VAL + ldr r2, =CONFIG_SYS_MDMRS_VAL str r2, [r1, #MDMRS_OFFSET] /* ---- INTERRUPT INITIALISATION ---- */ @@ -183,7 +183,7 @@ mem_init: str r1, [r2] /* Set interrupt mask register */ - ldr r1, =CFG_ICMR_VAL + ldr r1, =CONFIG_SYS_ICMR_VAL ldr r2, =ICMR str r1, [r2] @@ -196,7 +196,7 @@ mem_init: str r2, [r1] /* set core clocks */ - ldr r2, =CFG_CCCR_VAL + ldr r2, =CONFIG_SYS_CCCR_VAL ldr r1, =CCCR str r2, [r1] @@ -215,7 +215,7 @@ mem_init: /* Turn on needed clocks */ ldr r1, =CKEN - ldr r2, =CFG_CKEN_VAL + ldr r2, =CONFIG_SYS_CKEN_VAL str r2, [r1] mov pc, r10 diff --git a/board/xsengine/u-boot.lds b/board/xsengine/u-boot.lds index bf42e9f3d..1e88820bc 100644 --- a/board/xsengine/u-boot.lds +++ b/board/xsengine/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } diff --git a/board/zeus/u-boot.lds b/board/zeus/u-boot.lds index d803625b5..877573e0d 100644 --- a/board/zeus/u-boot.lds +++ b/board/zeus/u-boot.lds @@ -126,6 +126,7 @@ SECTIONS *(.dynbss) *(.bss) *(COMMON) + . = ALIGN(4); } _end = . ; PROVIDE (end = .); diff --git a/board/zeus/update.c b/board/zeus/update.c index c76519f09..2f2a127f7 100644 --- a/board/zeus/update.c +++ b/board/zeus/update.c @@ -67,12 +67,12 @@ u8 buf_zeus_pe[] = { static int update_boot_eeprom(void) { u32 len = 0x20; - u8 chip = CFG_I2C_EEPROM_ADDR; + u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR; u8 *pbuf; u8 base; int i; - if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) { + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) { pbuf = buf_zeus_pe; base = 0x40; } else { diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 33d971ab0..974bdf29c 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR; #define REBOOT_NOP 0x00000000 #define REBOOT_DO_POST 0x00000001 -extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ extern env_t *env_ptr; extern uchar default_environment[]; @@ -73,8 +73,8 @@ int misc_init_r(void) u32 post_magic; u32 post_val; - post_magic = in_be32((void *)CFG_POST_MAGIC); - post_val = in_be32((void *)CFG_POST_VAL); + post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC); + post_val = in_be32((void *)CONFIG_SYS_POST_VAL); if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) { /* * Set special bootline bootparameter to pass this POST boot @@ -87,7 +87,7 @@ int misc_init_r(void) * via the sw-reset button. So disable further tests * upon next bootup here. */ - out_be32((void *)CFG_POST_VAL, REBOOT_NOP); + out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP); } else { /* * Only run POST when initiated via the sw-reset button mechanism @@ -144,14 +144,14 @@ int misc_init_r(void) /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - -CFG_MONITOR_LEN, + -CONFIG_SYS_MONITOR_LEN, 0xffffffff, &flash_info[0]); /* Env protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); return 0; @@ -166,7 +166,7 @@ int checkboard(void) puts("Board: Zeus-"); - if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) + if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) puts("PE"); else puts("CE"); @@ -180,39 +180,16 @@ int checkboard(void) putc('\n'); /* both LED's off */ - gpio_write_bit(CFG_GPIO_LED_RED, 0); - gpio_write_bit(CFG_GPIO_LED_GREEN, 0); + gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0); + gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0); udelay(10000); /* and on again */ - gpio_write_bit(CFG_GPIO_LED_RED, 1); - gpio_write_bit(CFG_GPIO_LED_GREEN, 1); + gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 1); + gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 1); return (0); } -static u32 detect_sdram_size(void) -{ - u32 val; - u32 size; - - mfsdram(mem_mb0cf, val); - size = (4 << 20) << ((val & 0x000e0000) >> 17); - - /* - * Check if 2nd bank is enabled too - */ - mfsdram(mem_mb1cf, val); - if (val & 1) - size += (4 << 20) << ((val & 0x000e0000) >> 17); - - return size; -} - -phys_size_t initdram (int board_type) -{ - return detect_sdram_size(); -} - static int default_env_var(char *buf, char *var) { char *ptr; @@ -249,12 +226,12 @@ static int restore_default(void) * Unprotect and erase environment area */ flash_protect(FLAG_PROTECT_CLEAR, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - flash_sect_erase(CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1); + flash_sect_erase(CONFIG_ENV_ADDR_REDUND, + CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1); /* * Now restore default environment from U-Boot image @@ -262,7 +239,7 @@ static int restore_default(void) */ memset(env_ptr, 0, sizeof(env_t)); memcpy(env_ptr->data, default_environment, ENV_SIZE); -#ifdef CFG_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT env_ptr->flags = 0xFF; #endif env_crc_update(); @@ -356,7 +333,7 @@ U_BOOT_CMD( static inline int sw_reset_pressed(void) { - return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET)); + return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET)); } int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) @@ -379,16 +356,16 @@ int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) if (!sw_reset_pressed()) break; - if ((delta > CFG_TIME_POST) && !post) { + if ((delta > CONFIG_SYS_TIME_POST) && !post) { printf("\nWhen released now, POST tests will be started."); - gpio_write_bit(CFG_GPIO_LED_GREEN, 0); + gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0); post = 1; } - if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) { + if ((delta > CONFIG_SYS_TIME_FACTORY_RESET) && !factory_reset) { printf("\nWhen released now, factory default values" " will be restored."); - gpio_write_bit(CFG_GPIO_LED_RED, 0); + gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0); factory_reset = 1; } @@ -400,7 +377,7 @@ int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) printf("\nSW-Reset Button released after %d milli-seconds!\n", delta); - if (delta > CFG_TIME_FACTORY_RESET) { + if (delta > CONFIG_SYS_TIME_FACTORY_RESET) { printf("Starting factory reset value restoration...\n"); /* @@ -416,14 +393,14 @@ int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) return 0; } - if (delta > CFG_TIME_POST) { + if (delta > CONFIG_SYS_TIME_POST) { printf("Starting POST configuration...\n"); /* * Enable POST upon next bootup */ - out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC); - out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST); + out_be32((void *)CONFIG_SYS_POST_MAGIC, REBOOT_MAGIC); + out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_DO_POST); post_bootmode_init(); /* @@ -455,8 +432,8 @@ int post_hotkeys_pressed(void) u32 post_magic; u32 post_val; - post_magic = in_be32((void *)CFG_POST_MAGIC); - post_val = in_be32((void *)CFG_POST_VAL); + post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC); + post_val = in_be32((void *)CONFIG_SYS_POST_VAL); if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) return 1; diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c index 103ef714f..027d56662 100644 --- a/board/zpc1900/zpc1900.c +++ b/board/zpc1900/zpc1900.c @@ -183,7 +183,7 @@ const iop_conf_t iop_conf_tab[4][32] = { } }; -#ifdef CFG_NVRAM_ACCESS_ROUTINE +#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE void *nvram_read(void *dest, long src, size_t count) { return memcpy(dest, (const void *)src, count); @@ -191,8 +191,8 @@ void *nvram_read(void *dest, long src, size_t count) void nvram_write(long dest, const void *src, size_t count) { - vu_char *p1 = (vu_char *)(CFG_EEPROM + 0x1555); - vu_char *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA); + vu_char *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555); + vu_char *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA); vu_char *d = (vu_char *)dest; const uchar *s = (const uchar *)src; @@ -218,16 +218,16 @@ void nvram_write(long dest, const void *src, size_t count) *p1 = 0xA0; udelay(10000); } -#endif /* CFG_NVRAM_ACCESS_ROUTINE */ +#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */ phys_size_t initdram(int board_type) { - vu_char *bcsr = (vu_char *)CFG_BCSR; - volatile immap_t *immap = (immap_t *)CFG_IMMR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8260_t *memctl = &immap->im_memctl; vu_char *ramaddr; uchar c = 0xFF; - long int msize = CFG_SDRAM_SIZE; + long int msize = CONFIG_SYS_SDRAM_SIZE; int i; if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */ @@ -237,38 +237,38 @@ phys_size_t initdram(int board_type) | SIUMCR_LBPC01; } -#ifndef CFG_RAMBOOT +#ifndef CONFIG_SYS_RAMBOOT immap->im_siu_conf.sc_ppc_acr = 0x03; immap->im_siu_conf.sc_ppc_alrh = 0x30126745; immap->im_siu_conf.sc_tescr1 = 0x00004000; - memctl->memc_mptpr = CFG_MPTPR; + memctl->memc_mptpr = CONFIG_SYS_MPTPR; -#ifdef CFG_LSDRAM_BASE +#ifdef CONFIG_SYS_LSDRAM_BASE /* Initialise local bus SDRAM only if the pins are configured as local bus pins and not as PCI. */ if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) { - memctl->memc_lsrt = CFG_LSRT; - memctl->memc_or4 = CFG_LSDRAM_OR; - memctl->memc_br4 = CFG_LSDRAM_BR; - ramaddr = (vu_char *)CFG_LSDRAM_BASE; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA; + memctl->memc_lsrt = CONFIG_SYS_LSRT; + memctl->memc_or4 = CONFIG_SYS_LSDRAM_OR; + memctl->memc_br4 = CONFIG_SYS_LSDRAM_BR; + ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA; *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR; for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW; *ramaddr = c; - memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN; + memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN; } -#endif /* CFG_LSDRAM_BASE */ +#endif /* CONFIG_SYS_LSDRAM_BASE */ /* Initialise 60x bus SDRAM */ - memctl->memc_psrt = CFG_PSRT; - memctl->memc_or2 = CFG_PSDRAM_OR; - memctl->memc_br2 = CFG_PSDRAM_BR; + memctl->memc_psrt = CONFIG_SYS_PSRT; + memctl->memc_or2 = CONFIG_SYS_PSDRAM_OR; + memctl->memc_br2 = CONFIG_SYS_PSDRAM_BR; /* * The mode data for Mode Register Write command must appear on * the address lines during a mode-set cycle. It is driven by @@ -278,18 +278,18 @@ phys_size_t initdram(int board_type) * the address lines. BL=0 because for 64-bit port size burst * length must be 4. */ - ramaddr = (vu_char *)(CFG_SDRAM_BASE | - ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); - memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ + ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE | + ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); + memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ *ramaddr = c; - memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ + memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ for (i = 0; i < 8; i++) *ramaddr = c; - memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ + memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ *ramaddr = c; - memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */ + memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN; /* Refresh enable */ *ramaddr = c; -#endif /* CFG_RAMBOOT */ +#endif /* CONFIG_SYS_RAMBOOT */ /* Return total 60x bus SDRAM size */ return msize * 1024 * 1024; @@ -297,7 +297,7 @@ phys_size_t initdram(int board_type) int checkboard(void) { - vu_char *bcsr = (vu_char *)CFG_BCSR; + vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40); return 0; diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c index 883c1ba3b..5ba84c68e 100644 --- a/board/zylonite/flash.c +++ b/board/zylonite/flash.c @@ -28,7 +28,7 @@ #include <linux/byteorder/swab.h> -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* Board support for 1 or 2 flash devices */ #define FLASH_PORT_WIDTH32 @@ -66,7 +66,7 @@ unsigned long flash_init (void) int i; ulong size = 0; - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { switch (i) { case 0: flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); @@ -86,13 +86,13 @@ unsigned long flash_init (void) /* Protect monitor and environment sectors */ flash_protect ( FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + monitor_flash_len - 1, + CONFIG_SYS_FLASH_BASE, + CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0] ); flash_protect ( FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0] ); + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] ); return size; #endif @@ -206,10 +206,10 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info) break; } - if (info->sector_count > CFG_MAX_FLASH_SECT) { + if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CFG_MAX_FLASH_SECT); - info->sector_count = CFG_MAX_FLASH_SECT; + info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); + info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; } addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ @@ -279,7 +279,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) *addr = (FPW) 0x00D000D0; /* erase confirm */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { printf ("Timeout\n"); *addr = (FPW) 0x00B000B0; /* suspend erase */ *addr = (FPW) 0x00FF00FF; /* reset to read mode */ @@ -413,7 +413,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { + if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S index da0176564..ff17c7e7b 100644 --- a/board/zylonite/lowlevel_init.S +++ b/board/zylonite/lowlevel_init.S @@ -29,7 +29,7 @@ #include <version.h> #include <asm/arch/pxa-regs.h> -DRAM_SIZE: .long CFG_DRAM_SIZE +DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE /* wait for coprocessor write complete */ .macro CPWAIT reg @@ -235,13 +235,13 @@ mem_init: orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access str r1, [r0] -#ifndef CFG_SKIP_DRAM_SCRUB +#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB /* scrub/init SDRAM if enabled/present */ -/* ldr r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */ -/* ldr r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */ +/* ldr r11, =0xa0000000 /\* base address of SDRAM (CONFIG_SYS_DRAM_BASE) *\/ */ +/* ldr r12, =0x04000000 /\* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) *\/ */ /* mov r8,r12 /\* save DRAM size (mk: why???) *\/ */ - ldr r8, =0xa0000000 /* base address of SDRAM (CFG_DRAM_BASE) */ - ldr r9, =0x04000000 /* size of memory to scrub (CFG_DRAM_SIZE) */ + ldr r8, =0xa0000000 /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */ + ldr r9, =0x04000000 /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */ mov r0, #0 /* scrub with 0x0000:0000 */ mov r1, #0 mov r2, #0 @@ -255,7 +255,7 @@ mem_init: stmia r8!, {r0-r7} beq 15f b 10b -#endif /* CFG_SKIP_DRAM_SCRUB */ +#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */ 15: /* Mask all interrupts */ diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c index 09bcbb233..899445ee6 100644 --- a/board/zylonite/nand.c +++ b/board/zylonite/nand.c @@ -28,26 +28,24 @@ #include <nand.h> #include <asm/arch/pxa-regs.h> -#ifdef CFG_DFC_DEBUG1 +#ifdef CONFIG_SYS_DFC_DEBUG1 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG1(fmt, args...) #endif -#ifdef CFG_DFC_DEBUG2 +#ifdef CONFIG_SYS_DFC_DEBUG2 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG2(fmt, args...) #endif -#ifdef CFG_DFC_DEBUG3 +#ifdef CONFIG_SYS_DFC_DEBUG3 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG3(fmt, args...) #endif -#define MIN(x, y) ((x < y) ? x : y) - /* These really don't belong here, as they are specific to the NAND Model */ static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; @@ -58,14 +56,12 @@ static struct nand_bbt_descr delta_bbt_descr = { .pattern = scan_ff_pattern }; -static struct nand_oobinfo delta_oob = { - .useecc = MTD_NANDECC_AUTOPL_USR, /* MTD_NANDECC_PLACEONLY, */ +static struct nand_ecclayout delta_oob = { .eccbytes = 6, .eccpos = {2, 3, 4, 5, 6, 7}, .oobfree = { {8, 2}, {12, 4} } }; - /* * not required for Monahans DFC */ @@ -213,7 +209,7 @@ static void wait_us(unsigned long us) static void dfc_clear_nddb(void) { NDCR &= ~NDCR_ND_RUN; - wait_us(CFG_NAND_OTHER_TO); + wait_us(CONFIG_SYS_NAND_OTHER_TO); } /* wait_event with timeout */ @@ -224,9 +220,9 @@ static unsigned long dfc_wait_event(unsigned long event) if(!event) return 0xff000000; else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) - timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; else - timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ; while(1) { ndsr = NDSR; @@ -249,7 +245,7 @@ static void dfc_new_cmd(void) int retry = 0; unsigned long status; - while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) { /* Clear NDSR */ NDSR = 0xFFF; @@ -440,8 +436,8 @@ int board_nand_init(struct nand_chip *nand) /* turn on the NAND Controller Clock (104 MHz @ D0) */ CKENA |= (CKENA_4_NAND | CKENA_9_SMC); -#undef CFG_TIMING_TIGHT -#ifndef CFG_TIMING_TIGHT +#undef CONFIG_SYS_TIMING_TIGHT +#ifndef CONFIG_SYS_TIMING_TIGHT tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), DFC_MAX_tCH); tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), @@ -480,7 +476,7 @@ int board_nand_init(struct nand_chip *nand) DFC_MAX_tWHR); tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), DFC_MAX_tAR); -#endif /* CFG_TIMING_TIGHT */ +#endif /* CONFIG_SYS_TIMING_TIGHT */ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); @@ -545,6 +541,7 @@ int board_nand_init(struct nand_chip *nand) nand->cmd_ctrl = dfc_hwcontrol; /* nand->dev_ready = dfc_device_ready; */ nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = &delta_oob; nand->options = NAND_BUSWIDTH_16; nand->waitfunc = dfc_wait; nand->read_byte = dfc_read_byte; @@ -553,7 +550,6 @@ int board_nand_init(struct nand_chip *nand) nand->write_buf = dfc_write_buf; nand->cmdfunc = dfc_cmdfunc; -/* nand->autooob = &delta_oob; */ nand->badblock_pattern = &delta_bbt_descr; return 0; } diff --git a/board/zylonite/u-boot.lds b/board/zylonite/u-boot.lds index 14d264a68..7cf9fdf63 100644 --- a/board/zylonite/u-boot.lds +++ b/board/zylonite/u-boot.lds @@ -51,6 +51,6 @@ SECTIONS . = ALIGN(4); __bss_start = .; - .bss (NOLOAD) : { *(.bss) } + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; } |