Coldfire MCF5249 support added

1 files changed, 110 insertions, 2 deletions

diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 8aff8f1ae..350c431db 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -34,7 +34,11 @@
 #include <asm/immap_5282.h>
 #endif
 
-#ifdef	CONFIG_M5272
+#ifdef	CONFIG_M5249
+#include <asm/m5249.h>
+#endif
+
+#if defined(CONFIG_M5272)
 /*
  * Breath some life into the CPU...
  *
@@ -118,7 +122,7 @@ int cpu_init_r  (void)
 {
 	return (0);
 }
-#endif /* #ifdef CONFIG_M5272 */
+#endif /* #if defined(CONFIG_M5272) */
 
 
 #ifdef	CONFIG_M5282
@@ -142,3 +146,107 @@ int cpu_init_r  (void)
 	return (0);
 }
 #endif
+
+#if defined(CONFIG_M5249)
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f (void)
+{
+#ifndef CFG_PLL_BYPASS
+	/*
+	 *  Setup the PLL to run at the specified speed
+	 *
+	 */
+	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
+	unsigned long pllcr;
+#ifdef CFG_FAST_CLK
+  	pllcr = 0x925a3100;                       /* ~140MHz clock (PLL bypass = 0) */
+#else
+	pllcr = 0x135a4140;                       /* ~72MHz clock (PLL bypass = 0) */
+#endif
+	cpll = cpll & 0xfffffffe; 		  /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
+	mbar2_writeLong(MCFSIM_PLLCR, cpll); 	  /* Set the PLL to bypass mode (PSTCLK = crystal) */
+	mbar2_writeLong(MCFSIM_PLLCR, pllcr);  	  /* set the clock speed */
+	pllcr ^= 0x00000001; 		      	  /* Set pll bypass to 1 */
+	mbar2_writeLong(MCFSIM_PLLCR, pllcr);  	  /* Start locking (pll bypass = 1) */
+	udelay(0x20);                             /* Wait for a lock ... */
+#endif /* #ifndef CFG_PLL_BYPASS */
+
+	/*
+	 *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
+	 *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
+	 *        which is their primary function.
+	 *        ~Jeremy
+	 */
+	mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
+	mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
+	mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
+	mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
+	mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
+
+	/*
+	 *  dBug Compliance:
+	 *    You can verify these values by using dBug's 'ird'
+	 *    (Internal Register Display) command
+	 *    ~Jeremy
+	 *
+ 	 */
+	mbar_writeByte(MCFSIM_MPARK, 0x30);    /* 5249 Internal Core takes priority over DMA */
+	mbar_writeByte(MCFSIM_SYPCR, 0x00);
+	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
+	mbar_writeByte(MCFSIM_SWSR, 0x00);
+	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
+	mbar_writeByte(MCFSIM_SWDICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
+	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
+	mbar_writeByte(MCFSIM_I2CICR, 0x00);
+	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
+	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
+	mbar_writeByte(MCFSIM_ICR6, 0x00);
+	mbar_writeByte(MCFSIM_ICR7, 0x00);
+	mbar_writeByte(MCFSIM_ICR8, 0x00);
+	mbar_writeByte(MCFSIM_ICR9, 0x00);
+	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
+
+	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
+	mbar2_writeByte(MCFSIM_INTBASE, 0x40);  /* Base interrupts at 64 */
+	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
+	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);  /* Enable a 1 cycle pre-drive cycle on CS1 */
+
+	/* Setup interrupt priorities for gpio7 */
+	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
+
+	/* IDE Config registers */
+	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
+	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
+
+	/*
+	 *  Setup chip selects...
+	 */
+
+	mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
+	mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
+	mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
+
+	mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
+	mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
+	mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
+
+	/* enable instruction cache now */
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r  (void)
+{
+	return (0);
+}
+#endif /* #if defined(CONFIG_M5249) */