diff options
| author | wdenk <wdenk> | 2005-04-05 23:32:21 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2005-04-05 23:32:21 +0000 |
| commit | 3c2b3d454daa6024cc20d166b2f50efde169c7fe (patch) | |
| tree | f66cfb007a5dec1d47a19b2cab8a9dc127468347 /cpu/mpc8220 | |
| parent | b304c96871c92d1ec8fa57dda36cc198660fd10e (diff) | |
* Patch by Ladislav Michl, 05 Apr 2005:
Add support for VoiceBlue board.
* Patch by Ladislav Michl, 05 Apr 2005:
Fix netboot_common() prototypes.
* Cleanup.
Diffstat (limited to 'cpu/mpc8220')
| -rw-r--r-- | cpu/mpc8220/speed.c | 2 | ||||
| -rw-r--r-- | cpu/mpc8220/start.S | 2 | ||||
| -rw-r--r-- | cpu/mpc8220/uart.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/cpu/mpc8220/speed.c b/cpu/mpc8220/speed.c index 0c3df7c99..8346efe12 100644 --- a/cpu/mpc8220/speed.c +++ b/cpu/mpc8220/speed.c @@ -74,7 +74,7 @@ int get_clocks (void) gd->inp_clk = CFG_MPC8220_CLKIN; /* Read XLB to PCI(INP) clock multiplier */ - pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & + pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) & PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT; /* XLB bus clock */ diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index c5d2388ca..52332023e 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -111,7 +111,7 @@ boot_warm: /* MBAR is mirrored into the MBAR SPR */ mtspr MBAR,r3 - mtspr SPRN_SPRG7W,r3 + mtspr SPRN_SPRG7W,r3 lis r4, CFG_DEFAULT_MBAR@h stw r3, 0(r4) #endif /* CFG_DEFAULT_MBAR */ diff --git a/cpu/mpc8220/uart.c b/cpu/mpc8220/uart.c index 4ff8ccbf3..42ae3250a 100644 --- a/cpu/mpc8220/uart.c +++ b/cpu/mpc8220/uart.c @@ -47,7 +47,7 @@ int psc_serial_init (void) /* write to CSR: RX/TX baud rate from timers */ psc->sr_csr = 0xdd000000; - psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; + psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1; /* Setting up BaudRate */ counter = ((gd->bus_clk / gd->baudrate)) >> 5; |