diff options
| author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:50 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:39 +0200 |
| commit | 8ed44d91c8122d00368523b0b746691c895d3b3c (patch) | |
| tree | 7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /cpu/mpc83xx | |
| parent | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff) | |
Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/mpc83xx')
| -rw-r--r-- | cpu/mpc83xx/spd_sdram.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 359a91558..42a4e675d 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -314,7 +314,7 @@ long int spd_sdram() + (spd.clk_cycle & 0x0f)); max_data_rate = max_bus_clk * 2; - debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate); + debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate); ddrc_clk = gd->mem_clk / 1000000; effective_data_rate = 0; @@ -401,7 +401,7 @@ long int spd_sdram() } } - debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate); + debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate); debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat); /* |