diff options
| author | Michael Brandt <michael.brandt@stericsson.com> | 2010-11-22 16:30:05 +0100 |
|---|---|---|
| committer | Michael BRANDT <michael.brandt@stericsson.com> | 2010-11-23 09:20:10 +0100 |
| commit | 8a81734f8320002a727c5c3280e8159aa3c51c04 (patch) | |
| tree | 8ad606b16c32045d4e469307e65db79989c4dfa8 /include | |
| parent | 4fb4da50ecea90b14994272b6d78cffe003a3a87 (diff) | |
U8500: config: removed non-applicable and unused defines
Some defines were inherited from the old U-Boot 1.3.1 and are not used
anywhere. This patch removes them.
As a side-effect the flash.c dummy was also removed.
Change-Id: Iecddb2f8bb59d909b936254085c358a1d246d205
Signed-off-by: Michael Brandt <michael.brandt@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9203
Reviewed-by: Sebastian RASMUSSEN <sebastian.rasmussen@stericsson.com>
Reviewed-by: Robert ROSENGREN <robert.rosengren@stericsson.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/u8500.h | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/include/configs/u8500.h b/include/configs/u8500.h index a8d205c53..f23d70f1f 100644 --- a/include/configs/u8500.h +++ b/include/configs/u8500.h @@ -28,19 +28,12 @@ * (easy to change) */ #define CONFIG_U8500 1 -#define CONFIG_U8500_ED 1 #define CONFIG_L2_OFF 1 #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF #define CONFIG_SYS_HZ 1000 /* must be 1000 */ -#ifndef CONFIG_U8500_V1 -#define CONFIG_SYS_TIMERBASE 0xA03DA000 /* MTU0 timer */ -#else -#define CONFIG_SYS_TIMERBASE 0xA03C6000 /* MTU0 timer */ -#endif - #define CONFIG_BOOTTIME #define BOARD_LATE_INIT 1 @@ -280,8 +273,7 @@ * FLASH and environment organization */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_NO_FLASH /*----------------------------------------------------------------------- * Video Logo Related configs @@ -308,8 +300,6 @@ * base register values for U8500 */ #define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock Management Unit */ -#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */ -#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ /* * U8500 GPIO register base for 9 banks |