diff options
70 files changed, 5843 insertions, 4635 deletions
@@ -1,3 +1,653 @@ +commit 92bad20ad74b70adf3839df9a0a47cce000ac3d7 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Apr 8 14:00:57 2008 -0400 + + Add support for u-boot in svn and localversion-* files + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit d23ff6827decf121461fbc5622612fd7effe207e +Author: Guennadi Liakhovetski <lg@denx.de> +Date: Thu Apr 3 17:04:22 2008 +0200 + + MX31ADS network and flash updates + + This patch allows U-Boot to use buffered writes to the Spansion NOR + flash installed on this board, and eliminates long delays in network + transfers after the board startup. + + Also modify flash layout to embed main and redundant environment + blocks in the U-Boot image. + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + +commit b5dc9b304d289831f291843ff88a45cbdf1a6290 +Author: Guennadi Liakhovetski <lg@denx.de> +Date: Mon Apr 14 10:53:12 2008 +0200 + + Support for the MX31ADS evaluation board from Freescale + + This patch adds support for the MX31ADS evaluation board from Freescale, + initialization code is copied from RedBoot sources, also provided by + Freescale. + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + +commit 5e3dca577b7c1bf58bd2b48449b18b7e7dcd8e04 +Author: Anatolij Gustschin <agust@denx.de> +Date: Thu Apr 17 18:18:00 2008 +0200 + + Fix crash on sequoia in ppc_4xx_eth_init + + Currently U-Boot crashes in ppc_4xx_eth_init on sequoia + with cache enabled (TLB Parity exeption). This patch + fixes the problem. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit accf7355767dc7f6b85d88bb1c75c9d95e84ba5b +Author: Anatolij Gustschin <agust@denx.de> +Date: Thu Apr 17 18:15:27 2008 +0200 + + ppc4xx: Fix crash on sequoia with cache enabled + + Currently U-Boot crashes on sequoia board in CPU POST if + cache is enabled (CONFIG_4xx_DCACHE defined). The cache + won't be disabled by change_tlb before CPU POST because + there is an insufficient adress range check since + CFG_MEM_TOP_HIDE was introduced. This patch tries to fix + this problem. + + Signed-off-by: Anatolij Gustschin <agust@denx.de> + +commit 43c509254fab375c49936498da944658117ed07c +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Thu Apr 17 23:35:13 2008 +0900 + + Use jr as register jump instruction + + Current assembler codes are inconsistent in the way of register jump + instruction usage; some use jr, some use j. Of course GNU as allows both + usages, but as can be expected from `Jump Register' the mnemonic `jr' is + more intuitive than `j'. For example, Linux doesn't have `j <reg>' usage + at all. + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit 7ce63709828d37b08866e537339a169bd0db2bd3 +Author: Guennadi Liakhovetski <lg@denx.de> +Date: Tue Apr 15 14:15:30 2008 +0200 + + RTC driver for MC13783 + + MC13783 is a multifunction IS with an SPI interface to the host. This + driver handles the RTC controller in this chip. + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + +commit 38254f45b0b412332726c90d3184ad47479fcffb +Author: Guennadi Liakhovetski <lg@denx.de> +Date: Tue Apr 15 14:14:25 2008 +0200 + + New i.MX31 SPI driver + + This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far + only implemented and tested on i.MX31, can with a modified register layout + and definitions be used for i.MX27, I think, MXC CPUs have similar SPI + controllers too. + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + +commit 7064122c2eef92f02a03ef37a1a1c07e70cd4e38 +Author: Magnus Lilja <lilja.magnus@gmail.com> +Date: Tue Apr 15 19:09:10 2008 +0200 + + Fix name of i.MX31 boards in config file header + + Correct the name of the i.MX31 Litekit and phyCORE boards in config files. + + Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com> + +commit a49864593e083a5d0779fb9ca98e5a0f2053183d +Author: Mike Frysinger <vapier@gentoo.org> +Date: Sun Apr 13 19:42:19 2008 -0400 + + allow ports to override go behavior + + Split the arch-specific logic out of the common go code and into a dedicated + weak function called do_go_exec() that lives in cpu directories. This will + need review from i386/nios people to make sure I didn't break them. + +commit 017e9b7925f74878d0e9475388cca9bda5ef9482 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Sun Apr 13 19:42:18 2008 -0400 + + allow ports to override bootelf behavior + + Change the bootelf setup function into a dedicated weak function called + do_bootelf_exec. This way ports can control the behavior however they + like before/after calling the ELF entry point. + +commit a4b46ed6b3502335c3f3a5d672abe0bcb44f20b7 +Author: Ulf Samuelsson <ulf@atmel.com> +Date: Sat Apr 12 20:56:03 2008 +0200 + + Reorder ARM boards in Makefile + + Rearrange ARM boards in Makefile so that ARM926EJ-S boards + are no longer under ARM92xT header. + + Signed-off-by: Ulf Samuelsson <ulf@atmel.com> + Ack-By Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit c3a60cb3bd67e120fc99b6ba88d9295c3c07f688 +Author: Ulf Samuelsson <ulf@atmel.com> +Date: Sat Apr 12 20:29:44 2008 +0200 + + Clean up dataflash partitioning + + This patch removes the board dependent parts from + "drivers/mtd/dataflash.c". + Each board relying on this, will have the appropriate + code in a new file, "partition.c" in the board directory. + board Makefiles updated to use the file. + + The dataflash partitions are aligned on sector/page boundaries. + + The CONFIG_NEW_DF_PARTITION was used to create named partitions + This is now the default operation, and the CONFIG variable is removed. + + Signed-off-by: Ulf Samuelsson <ulf@atmel.com> + +commit 51ecde946fec511a16346e498204ca10ad71080d +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Sat Apr 12 14:08:45 2008 +0200 + + gitignore: udpate stgit generated and .patch file + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 66e39818e95f51ee1c1dd2094407a8929543fa6d +Author: Wolfgang Denk <wd@denx.de> +Date: Fri Apr 18 00:15:36 2008 -0700 + + Get rid of redundant copy of renamed header file. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit c3aafd8cf814e33a77de81c2f22b8c772216a3cc +Author: Vlad Lungu <vlad@comsys.ro> +Date: Fri Apr 11 21:20:14 2008 +0300 + + Fix dependency generation for older gcc versions + + With gcc 3.3.3 at least, compilation fails with + + Generating include/autoconf.mk + gcc: compilation of header file requested + make: *** [include/autoconf.mk] Error 1 + + since commit 16fe77752eee099b9fb61ed73460e51cc94b37ba. + + Signed-off-by: Vlad Lungu <vlad@comsys.ro> + +commit cb1c4896905ab22fcd982e6a8a539f0031942e71 +Author: Marian Balakowicz <m8@semihalf.com> +Date: Fri Apr 11 11:07:49 2008 +0200 + + Restore the ability to continue booting after legacy image overwrite + + Before new uImage code was merged, bootm code allowed for the kernel image to + get overwritten during decompresion. new uImage introduced a check for image + overwrites and refused to boot the image that got overwritten. This patch + restores the old behavior. It also adds a warning when the image overwriten is + a multi-image file, because in such case accessing componentes other than the + first one will fail. + + Signed-off-by: Marian Balakowicz <m8@semihalf.com> + +commit de2b3216e6b4f3b2fe93759c05b17504f9dfe036 +Author: Marian Balakowicz <m8@semihalf.com> +Date: Fri Apr 11 11:07:43 2008 +0200 + + ppc: Fix ftd_blob variable init when processing raw blob + + Set fdt_blob variable before its value is printed out. + + Signed-off-by: Marian Balakowicz <m8@semihalf.com> + +commit 3d36be030043cd841a2551d00a395135e363a64b +Author: Jason Wessel <jason.wessel@windriver.com> +Date: Thu Apr 10 14:30:16 2008 -0500 + + Remove all the search paths from the .lds files. + + The cross compiler is responsible for providing the correct libraries + and the logic to find the linking libraries. + + Signed-off-by: Jason Wessel <jason.wessel@windriver.com> + +commit 7d721e34ae6be7d7db63e8d060a246278bb7ae58 +Author: Bartlomiej Sieka <tur@semihalf.com> +Date: Mon Apr 14 15:44:16 2008 +0200 + + Boot-related documentation update + + - document 'bootm_low' and 'bootm_size' environment variables + - update inaccurate CFG_BOOTMAPSZ entry + + Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> + +commit a6f0bd9f2b1971e2a61ac0fd1fc2c96cb7a4b67a +Author: Guennadi Liakhovetski <lg@denx.de> +Date: Wed Apr 9 17:34:08 2008 +0200 + + Fix regression introduced by a typo in "Tidied other cpu/arm920t/start.S code" + + Restore logic reverted by commit + + commit 80767a6cead9990d9e77e62be947843c2c72f469 + Author: Peter Pearse <peter.pearse@arm.com> + Date: Wed Sep 5 16:04:41 2007 +0100 + + Changed API name to coloured_led.h + Removed code using deprecated ifdef CONFIG_BOOTBINFUNC + Tidied other cpu/arm920t/start.S code + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + +commit e25cb8d3f4fcc265a9cdf8e9d577b59bdb64bbaf +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Apr 8 10:24:24 2008 -0400 + + Remove conflicting NAND ID + + There are two NAND entries with ID 0xDC and this obviously causes problems. + In the kernel, they punted the first entry, so we should do the same. + + See this upstream e-mail for more info: + http://lists.infradead.org/pipermail/linux-mtd/2007-July/018795.html + + Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 188e94c370621708d13547d58dbc6ed3c5602aa8 +Author: Shinya Kuribayashi <shinya.kuribayashi@necel.com> +Date: Tue Apr 8 16:20:35 2008 +0900 + + cpu/mips/cpu.c: Fix flush_cache bug + + Cache operations have to take line address (addr), not start_addr. + I noticed this bug when debugging ping failure. + + Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> + +commit 8f2a68a07c058fca1d413e54f71c2e7e78a74ed4 +Author: Martin Krause <martin.krause@tqs.de> +Date: Thu Apr 3 14:29:01 2008 +0200 + + TQM5200: fix default IDE reset level + + Before the first call of ide_reset(), the level of the IDE reset + signal on the TQM5200 is low (reset asserted). This patch sets the + default value to high (reset not asserted). + + Currently this patch fixes no real problem, but it is cleaner to + assert the reset signal only on demand, and not permanently. + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + +commit c61e033d6e8abb7b4060ee36060961e1399f6079 +Author: Detlev Zundel <dzu@denx.de> +Date: Thu Apr 3 14:18:48 2008 +0200 + + mgcoge, mgsuv: realign CONFIG_EXTRA_ENV_SETTING + + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit f308572e19eb7fe63aa3d41f214cde4c23c9800f +Author: Detlev Zundel <dzu@denx.de> +Date: Thu Apr 3 14:18:47 2008 +0200 + + mgcoge, mgsuv: rename 'addcon' to 'addcons' + + The latter name with 13 users is already established, so we will use + that. + + Signed-off-by: Detlev Zundel <dzu@denx.de> + +commit e175eacc87c3a9e4dad0799fee0e95732520afc7 +Author: Martin Krause <martin.krause@tqs.de> +Date: Thu Apr 3 13:37:56 2008 +0200 + + IDE: fix bug in reset sequence + + According to the ata (ata5) specification the RESET- signal + shall be asserted for at least 25 us. Without this patch, + the RESET- signal is asserted on some boards for only < 1 us + (e. g. on the TQM5200). This patch adds a general delay of + 25 us to the RESET- signal. + + Without this patch a Platinum 4 GiB CF card is not recognised + properly on boards with a TQM5200 (STK52xx, TB5200). + + Signed-off-by: Martin Krause <martin.krause@tqs.de> + +commit 813bea96a960916c72b4a3a7df840151529c26ce +Author: Sascha Laue <Sascha.Laue@gmx.biz> +Date: Thu Apr 3 14:43:11 2008 +0200 + + lwmon5: disable CONFIG_ZERO_BOOTDELAY + + Signed-off-by: Sascha Laue <sascha.laue@liebherr.com> + +commit 53eec6f1d25932e76d63ccb14082792b0b96bf41 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Wed Apr 2 08:03:58 2008 +0200 + + ds174x: Fix warning on return in rtc_get and rtc_set functions + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit a253b38bf50c85227c33ca0febc870ee49d1588e +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Wed Apr 2 08:03:57 2008 +0200 + + cmd_log.c: Fix assignment differ in signedness + + In function 'logbuff_init_ptrs': + cmd_log.c:79: warning: pointer targets in assignment differ in signedness + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit 6c0e9a8f1cc090fbfbc6f86b6b4fd17a1628f3df +Author: Gururaja Hebbar K R <gururajakr@sanyo.co.in> +Date: Wed Apr 2 11:04:43 2008 +0530 + + Remove duplicate #undef SHOW_INFO in drivers/usb/usb_ohci.c + + Signed-off-by: gururaja hebbar <gururajakr@sanyo.co.in> + +commit 478d5ec9ae3cbcc6040241d2d73dbbc61fe9b49d +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> +Date: Tue Apr 1 14:07:10 2008 +0200 + + s3c4510b_eth: fix 'packed' attribute ignored for fields of MACFrame + + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + +commit c08fb3ea36d19b1640b7906264581e9105534399 +Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Tue Apr 15 10:24:14 2008 +0200 + + Additional PCI IDs for IDE and network controllers + + These PCI IDs are required by the Linkstation platforms. + + Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> + +commit c0559be371b2a64b1a817088c3308688e2182f93 +Author: Joakim Tjernlund <joakim.tjernlund@transmode.se> +Date: Mon Apr 14 23:01:50 2008 +0200 + + Change env_get_char from a global function ptr to a function. + + This avoids an early global data reference. + + Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> + +commit 3e0f331c05d72f140715c1e9fca991927e44d422 +Author: Guennadi Liakhovetski <lg@denx.de> +Date: Tue Apr 29 12:35:08 2008 +0000 + + Clean up smsc911x driver + + Replace direct register address derefencing with accessor functions. + Restrict explicitly 32-bit bus-width, extend affected configurations + respectively. + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit de1b686b763aa8b87a86f6748ce9169e7fc0e4cd +Author: Sascha Hauer <s.hauer@pengutronix.de> +Date: Tue Apr 15 00:08:20 2008 -0400 + + This patch adds a driver for the following smsc network controllers: + LAN9115 + LAN9116 + LAN9117 + LAN9215 + LAN9216 + LAN9217 + + Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> + Signed-off-by: Guennadi Liakhovetski<lg@denx.de> + Signed-off-by: Ben Warren <biggerbadderben@gmail.com> + +commit 3dfd4aab929cccddb63d9ea509967861e1333b52 +Author: Sascha Laue <Sascha.Laue@gmx.biz> +Date: Tue Apr 1 15:13:03 2008 +0200 + + Fix watchdog POST for lwmon5 + + If the hardware watchdog detects a voltage error, the watchdog sets + GPIO62 to low. The watchdog POST has to detect this low level. + + Signed-off-by: Sascha Laue <leglas0@legpc180.leg.liebherr.i> + +commit 24b448448a917e52806f82660a5c9d47608894fb +Author: Dave Liu <r63238@freescale.com> +Date: Tue Apr 1 15:22:11 2008 +0800 + + ata: update the libata.h from ata.h of linux kernel + + Current libata.h of u-boot is out of sync from linux kernel, + this patch make it be consistent with linux kernel. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Tor Krill <tor@excito.com> + +commit f8f9dc98883f66f59eb0601da65808e6b139c87c +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Mon Mar 31 11:59:27 2008 -0500 + + Allow use of ARCH=powerpc when building + + The linux kernel is now mostly ARCH=powerpc, so to make life easier + allow use to use ARCH=powerpc and convert it to ARCH=ppc. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 8af657d2c6d1ca4f2f76973531394d4578ba2ef0 +Author: Kyungmin Park <kmpark@infradead.org> +Date: Mon Mar 31 10:40:54 2008 +0900 + + Add apollon board MAINTAINERS entry + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit 77e475cc0ed1832160017d364be32a0be9ff02a9 +Author: Kyungmin Park <kmpark@infradead.org> +Date: Mon Mar 31 10:40:36 2008 +0900 + + Fix OneNAND read + + It should access with 16-bit instead of 8-bit + + Now it uses the generic memcpy with 8-bit access. It means it reads wrong data from OneNAND. + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit a9da2b41079d230db3a5641625311983f85ce1fb +Author: Kyungmin Park <kmpark@infradead.org> +Date: Mon Mar 31 10:40:19 2008 +0900 + + Fix OneNAND erase command + + It mis-calculates the block address. + Also fix DECLARE_GLOBAL_DATA_PTR in env_onenand. + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit 61525f2ffa156665a66908fda47dbf29d65ea579 +Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de> +Date: Mon Mar 31 01:32:15 2008 +0200 + + Support for LinkStation / KuroBox HD and HG PPC models + + This patch is based on the port by Mihai Georgian (see linkstation.c for + Copyright information) and implements support for LinkStation / KuroBox HD + and HG PPC models from Buffalo Technology, whereby HD is deactivated at + the moment, pending network driver fixing. + + Notice to users: this is pretty much a barebone port. Support for network + on HG models is already in the U-Boot mainline, but you might also want + patches to switch fan / phy modes depending on the negotiated ethernet + parameters. This patch also doesn't support console switching, booting EM + mode, Buffalo specific ext2 magic number. So, if you want to use any of + those, you need additional patches. Otherwise this patche provides a fully + functional u-boot with a network console on your system. + + Signed-off-by: Guennadi Liakhovetski <lg@denx.de> + +commit 0f3ba7e9783f352318f197a3148f6d5cc3d75bea +Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com> +Date: Sun Mar 30 01:22:13 2008 -0500 + + Add CONFIG_MII_INIT support to related boards + + Replace CONFIG_8xx and CONFIG_MCF532x to CONFIG_MII_INIT in + cmd_init.c. Add CONFIG_MII_INIT to board configuration files + that use mii_init() in cmd_init.c. + + Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> + Acked-by: Ben Warren <biggerbadderben@gmail.com> + +commit f33fca22e76f20e4e4793810ca7a06a4805a6cf4 +Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com> +Date: Sun Mar 30 01:19:06 2008 -0500 + + Update CONFIG_PCIAUTO_SKIP_HOST_BRIDGE to related boards + + Remove test for CONFIG_MPC5200 in drivers/pci/pci_auto.c and define + CONFIG_PCIAUTO_SKIP_HOST_BRIDGE in related board configuration files. + + Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com> + +commit e99ccb488181d012248c6be30b2093e950319fc5 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Thu Mar 27 11:46:38 2008 -0500 + + Introduce phys_size_t and move phys_addr_t into asm/types.h + + Also add CONFIG_PHYS_64BIT on powerpc to deal with 32-bit ppc's + that have larger physical addresses like 44x, 85xx, and 86xx. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 20a14a42a25f72e379f38460b8a8484667536795 +Author: Andy Fleming <afleming@freescale.com> +Date: Wed Apr 2 16:19:07 2008 -0500 + + Rename include/md5.h to include/u-boot/md5.h + + Some systems have md5.h installed in /usr/include/. This isn't the + desired file (we want the one in include/md5.h). This will avoid the + conflict. This fixes the host tools building problem by creating a new + directory for U-Boot specific header files. + + [Patch by Andy Fleming, modified to use separate directory by Wolfgang + Denk] + + Signed-off-by: Wolfgang Denk <wd@denx.de> + Signed-off-by: Andy Fleming <afleming@freescale.com> + Acked-by: Timur Tabi <timur@freescale.com> + +commit f297b7a1ec87433f66320d89d993e1bc738c66b8 +Author: Dave Liu <r63238@freescale.com> +Date: Thu Mar 27 18:51:17 2008 +0800 + + drivers: code clean up + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit 0ff7cba4a2e51c90827f6d21a0b28b4d67109597 +Author: Dave Liu <r63238@freescale.com> +Date: Thu Mar 27 18:50:41 2008 +0800 + + drivers: clean up the ata_piix.h + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit e8f7ba404f1409606962815ecc955a06984b08b3 +Author: Dave Liu <r63238@freescale.com> +Date: Thu Mar 27 18:49:56 2008 +0800 + + doc: english polishing for README.sata + + according to gvb's suggestion, polishing for the doc. + + Signed-off-by: Jerry Van Baren <gerald.vanbaren@ge.com> + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit 3e3f766a5274d204780460e1879723b565296d34 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Wed Mar 26 18:53:28 2008 -0500 + + Fix warnings introduced by I2C bus speed setting patch + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 3c735e7437150e8615f26930c7819db85634276d +Author: eran liberty <eran.liberty@gmail.com> +Date: Thu Mar 27 00:50:49 2008 +0100 + + Altera Stratix II support + + Adds Support for Altera's Stratix II. + + Within your board specific init file you will have to call + + 1. fpga_init (/* relocated code offset. usually => */ gd->reloc_off); + 2. fpga_add (fpga_altera, (Altera_desc*)&altera_desc); + + Altera_desc* contines (for example): + { + Altera_StratixII, /* part type */ + passive_serial, /* interface type */ + 1, /* bytes of data part can accept */ + (void *)(&funcs), /* interface function table */ + 0L, /* base interface address */ + 0 /* implementation specific cookie */ + } + + funcs is the interface. It is of type altera_board_specific_func. + It looks like this: + altera_board_specific_func func = { + pre_fn, + config_fn, + status_fn, + done_fn, + clk_fn, + data_fn, + abort_fn, + post_fn, + }; + + you will have to implement these functions, which is usually bit + banging some gpio. + + Signed-off-by: Eran Liberty <liberty@extricom.com> + +commit 5ece9ec9f6cd52950ab848e2fe422dacf1d3a335 +Author: Wolfgang Denk <wd@denx.de> +Date: Sun Apr 13 14:32:54 2008 -0700 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 5ad862166aa24d62a69aa9c708f6b2f5c0d28fb7 Author: Sascha Hauer <s.hauer@pengutronix.de> Date: Wed Mar 26 20:41:17 2008 +0100 @@ -386,12 +386,6 @@ LIST_74xx=" \ ZUMA \ " -LIST_TSEC=" \ - ${LIST_85xx} \ - ${LIST_86xx} \ - ${LIST_83xx} \ -" - LIST_7xx=" \ BAB7xx \ CPCI750 \ @@ -400,6 +394,16 @@ LIST_7xx=" \ ppmc7xx \ " +######################################################################### +## PowerPC groups +######################################################################### + +LIST_TSEC=" \ + ${LIST_83xx} \ + ${LIST_85xx} \ + ${LIST_86xx} \ +" + LIST_ppc=" \ ${LIST_5xx} \ ${LIST_512x} \ @@ -510,6 +514,7 @@ LIST_ARM11=" \ apollon \ imx31_litekit \ imx31_phycore \ + mx31ads \ " ######################################################################### @@ -544,6 +549,9 @@ LIST_ixp=" \ scpu \ " +######################################################################### +## ARM groups +######################################################################### LIST_arm=" \ ${LIST_SA} \ @@ -704,6 +712,11 @@ LIST_blackfin=" \ ## SH Systems ######################################################################### +LIST_sh3=" \ + mpr2 \ + ms7720se \ +" + LIST_sh4=" \ ms7750se \ ms7722se \ @@ -712,11 +725,6 @@ LIST_sh4=" \ r2dplus \ " -LIST_sh3=" \ - mpr2 \ - ms7720se \ -" - LIST_sh=" \ ${LIST_sh3} \ ${LIST_sh4} \ @@ -754,17 +762,17 @@ build_target() { for arg in $@ do case "$arg" in - arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa| \ - avr32| \ - sparc| \ - blackfin| \ - coldfire| \ - microblaze| \ - mips|mips_el| \ - nios|nios2| \ - ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ - x86|I486|TSEC| \ - sh|sh4|sh3 \ + arm|SA|ARM7|ARM9|ARM10|ARM11|ixp|pxa \ + |avr32 \ + |blackfin \ + |coldfire \ + |microblaze \ + |mips|mips_el \ + |nios|nios2 \ + |ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \ + |sh|sh3|sh4 \ + |sparc \ + |x86|I486 \ ) for target in `eval echo '$LIST_'${arg}` do @@ -1187,10 +1187,13 @@ glacier_config: unconfig tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc -canyonlands_nand_config: unconfig +canyonlands_nand_config \ +glacier_nand_config: unconfig @mkdir -p $(obj)include $(obj)board/amcc/canyonlands @mkdir -p $(obj)nand_spl/board/amcc/canyonlands @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @echo "#define CONFIG_$$(echo $(subst ,,$(@:_nand_config=)) | \ + tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/canyonlands/config.tmp @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk @@ -2636,6 +2639,9 @@ imx31_litekit_config : unconfig imx31_phycore_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 +mx31ads_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31 + #======================================================================== # i386 #======================================================================== @@ -2968,7 +2974,8 @@ clean: $(obj)board/{integratorap,integratorcp}/u-boot.lds \ $(obj)board/{bf533-ezkit,bf533-stamp,bf537-stamp,bf561-ezkit}/u-boot.lds \ $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] - @rm -f $(obj)include/bmp_logo.h $(obj)nand_spl/{u-boot-spl,u-boot-spl.map} + @rm -f $(obj)include/bmp_logo.h + @rm -f $(obj)nand_spl/{u-boot-spl,u-boot-spl.map,System.map} @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl-2k.bin,ipl-4k.bin,ipl.map} @rm -f $(obj)api_examples/demo $(VERSION_FILE) @find $(OBJTREE) -type f \ @@ -2985,7 +2992,7 @@ clobber: clean $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) @rm -f $(obj)tools/{crc32.c,environment.c,env/crc32.c,md5.c,sha1.c,inca-swap-bytes} - @rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c} + @rm -f $(obj)tools/{image.c,fdt.c,fdt_ro.c,fdt_rw.c,fdt_strerror.c,zlib.h} @rm -f $(obj)tools/{fdt_wip.c,libfdt_internal.h} @rm -f $(obj)cpu/mpc824x/bedbug_603e.c @rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c index 37fa1c926..1d125b6e6 100644 --- a/board/amcc/canyonlands/bootstrap.c +++ b/board/amcc/canyonlands/bootstrap.c @@ -63,9 +63,22 @@ static u8 boot_configs[][17] = { /* * Bytes 5,6,8,9,11 change for NAND boot */ +#if 0 +/* + * Values for 512 page size NAND chips, not used anymore, just + * keep them here for reference + */ static u8 nand_boot[] = { 0x90, 0x01, 0xa0, 0x68, 0x58 }; +#else +/* + * Values for 2k page size NAND chips + */ +static u8 nand_boot[] = { + 0x90, 0x01, 0xa0, 0xe8, 0x58 +}; +#endif static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S index bd4cab56d..258fb5de8 100644 --- a/board/amcc/canyonlands/init.S +++ b/board/amcc/canyonlands/init.S @@ -51,6 +51,7 @@ tlbtab: #else tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) + tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I) #endif /* diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index f0837d415..332e3aaf2 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -56,10 +56,10 @@ SECTIONS cpu/ppc4xx/start.o (.text) /* Align to next NAND block */ - . = ALIGN(0x4000); + . = ALIGN(0x20000); common/environment.o (.ppcenv) /* Keep some space here for redundant env and potential bad env blocks */ - . = ALIGN(0x10000); + . = ALIGN(0x80000); *(.text) *(.fixup) diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile index 024997e77..c57cd6bb5 100644 --- a/board/esd/apc405/Makefile +++ b/board/esd/apc405/Makefile @@ -28,7 +28,9 @@ endif LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o strataflash.o ../common/misc.o +COBJS = $(BOARD).o \ + ../common/misc.o \ + ../common/auto_update.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 078df001e..b663184b6 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2005-2008 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * * (C) Copyright 2001-2003 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * @@ -23,17 +26,22 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> +#include <flash.h> +#include <asm/4xx_pci.h> +#include <pci.h> DECLARE_GLOBAL_DATA_PTR; -#if 0 -#define FPGA_DEBUG -#endif +#undef FPGA_DEBUG extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); extern void lxt971_no_sleep(void); +extern ulong flash_get_size (ulong base, int banknum); + +int flash_banks = CFG_MAX_FLASH_BANKS_DETECT; /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -46,82 +54,94 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" - /* Prototypes */ int gunzip(void *, int, unsigned char *, unsigned long *); - #ifdef CONFIG_LCD_USED /* logo bitmap data - gzip compressed and generated by bin2c */ unsigned char logo_bmp[] = { -#include CFG_LCD_LOGO_NAME +#include "logo_640_480_24bpp.c" }; /* * include common lcd code (for esd boards) */ #include "../common/lcd.c" - -#include CFG_LCD_HEADER_NAME +#include "../common/s1d13505_640_480_16bpp.h" +#include "../common/s1d13806_640_480_16bpp.h" #endif /* CONFIG_LCD_USED */ +/* + * include common auto-update code (for esd boards) + */ +#include "../common/auto_update.h" + +au_image_t au_image[] = { + {"preinst.img", 0, -1, AU_SCRIPT}, + {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT}, + {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT}, + {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT}, + {"work.img", 0xfe500000, 0x01400000, AU_NOR}, + {"data.img", 0xff900000, 0x00580000, AU_NOR}, + {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT}, + {"postinst.img", 0, 0, AU_SCRIPT}, +}; + +int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); int board_revision(void) { unsigned long cntrl0Reg; - unsigned long value; + volatile unsigned long value; /* * Get version of APC405 board from GPIO's */ - /* - * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) - */ + /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + mtdcr(cntrl0, cntrl0Reg | 0x03800000); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); + + /* wait some time before reading input */ + udelay(1000); + /* get config bits */ + value = in_be32((void*)GPIO0_IR) & 0x001c0000; /* * Restore GPIO settings */ mtdcr(cntrl0, cntrl0Reg); switch (value) { - case 0x00180000: - /* CS2==1 && CS3==1 -> version <= 1.2 */ + case 0x001c0000: + /* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */ return 2; - case 0x00080000: - /* CS2==0 && CS3==1 -> version 1.3 */ + case 0x000c0000: + /* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */ return 3; -#if 0 /* not yet manufactured ! */ - case 0x00100000: - /* CS2==1 && CS3==0 -> version 1.4 */ - return 4; - case 0x00000000: - /* CS2==0 && CS3==0 -> version 1.5 */ - return 5; -#endif + case 0x00180000: + /* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */ + return 6; + case 0x00140000: + /* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */ + return 8; default: /* should not be reached! */ return 0; } } - int board_early_init_f (void) { /* - * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) + * First pull fpga-prg pin low, to disable fpga logic */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ - out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ + out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */ + out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out_be32((void*)GPIO0_OR, 0); /* pull prg low */ /* * IRQ 0-15 405GP internally generated; active high; level sensitive @@ -140,48 +160,61 @@ int board_early_init_f (void) mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicvcr, 0x00000001); /* set vect base=0 */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + * EBC Configuration Register: set ready timeout to 512 ebc-clks + */ + mtebc(epcr, 0xa8400000); /* ebc always driven */ + + /* + * New boards have a single 32MB flash connected to CS0 + * instead of two 16MB flashes on CS0+1. */ -#if 1 /* test-only */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ -#else - mtebc (epcr, 0x28400000); /* ebc in high-z */ -#endif + if (board_revision() >= 8) { + /* disable CS1 */ + mtebc(pb1ap, 0); + mtebc(pb1cr, 0); + + /* resize CS0 to 32MB */ + mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8); + mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8); + } return 0; } - -/* ------------------------------------------------------------------------- */ - -int misc_init_f (void) +int board_early_init_r(void) { - return 0; /* dummy implementation */ + if (gd->board_type >= 8) + flash_banks = 1; + + return 0; } +#define FUJI_BASE 0xf0100200 +#define LCDBL_PWM 0xa0 +#define LCDBL_PWMMIN 0xa4 +#define LCDBL_PWMMAX 0xa8 -int misc_init_r (void) +int misc_init_r(void) { - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - volatile unsigned short *fpga_ctrl2 = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); - volatile unsigned char *duart0_mcr = - (unsigned char *)((ulong)DUART0_BA + 4); - volatile unsigned char *duart1_mcr = - (unsigned char *)((ulong)DUART1_BA + 4); - volatile unsigned short *fuji_lcdbl_pwm = - (unsigned short *)((ulong)0xf0100200 + 0xa0); + u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2); + u8 *duart0_mcr = (u8 *)(DUART0_BA + 4); + u8 *duart1_mcr = (u8 *)(DUART1_BA + 4); unsigned char *dst; ulong len = sizeof(fpgadata); int status; int index; int i; unsigned long cntrl0Reg; + char *str; + uchar *logo_addr; + ulong logo_size; + ushort minb, maxb; + int result; /* * Setup GPIO pins (CS6+CS7 as GPIO) @@ -190,9 +223,9 @@ int misc_init_r (void) mtdcr(cntrl0, cntrl0Reg | 0x00300000); dst = malloc(CFG_FPGA_MAX_SIZE); - if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf ("GUNZIP ERROR - must RESET board to recover\n"); - do_reset (NULL, 0, 0, NULL); + if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { + printf("GUNZIP ERROR - must RESET board to recover\n"); + do_reset(NULL, 0, 0, NULL); } status = fpga_boot(dst, len); @@ -200,31 +233,34 @@ int misc_init_r (void) printf("\nFPGA: Booting failed "); switch (status) { case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); + printf("(Timeout: " + "INIT not low after asserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); + printf("(Timeout: " + "INIT not high after deasserting PROGRAM*)\n "); break; case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); + printf("(Timeout: " + "DONE not high after programming FPGA)\n "); break; } /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; + index += len + 3; } - putc ('\n'); + putc('\n'); /* delayed reboot */ - for (i=20; i>0; i--) { + for (i = 20; i > 0; i--) { printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) + for (index = 0; index < 1000; index++) udelay(1000); } - putc ('\n'); + putc('\n'); do_reset(NULL, 0, 0, NULL); } @@ -235,12 +271,12 @@ int misc_init_r (void) /* display infos on fpgaimage */ index = 15; - for (i=0; i<4; i++) { + for (i = 0; i < 4; i++) { len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; + printf("%s ", &(dst[index + 1])); + index += len + 3; } - putc ('\n'); + putc('\n'); free(dst); @@ -255,51 +291,117 @@ int misc_init_r (void) /* * Write board revision in FPGA */ - *fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f); + out_be16(fpga_ctrl2, + (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f)); /* * Enable power on PS/2 interface (with reset) */ - *fpga_mode |= CFG_FPGA_CTRL_PS2_RESET; + out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET); for (i=0;i<100;i++) udelay(1000); udelay(1000); - *fpga_mode &= ~CFG_FPGA_CTRL_PS2_RESET; + out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET); /* * Enable interrupts in exar duart mcr[3] */ - *duart0_mcr = 0x08; - *duart1_mcr = 0x08; + out_8(duart0_mcr, 0x08); + out_8(duart1_mcr, 0x08); /* * Init lcd interface and display logo */ - lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM, - regs_13806_640_480_16bpp, - sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]), - logo_bmp, sizeof(logo_bmp)); + str = getenv("splashimage"); + if (str) { + logo_addr = (uchar *)simple_strtoul(str, NULL, 16); + logo_size = CFG_VIDEO_LOGO_MAX_SIZE; + } else { + logo_addr = logo_bmp; + logo_size = sizeof(logo_bmp); + } + + if (gd->board_type >= 6) { + result = lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13505_640_480_16bpp, + sizeof(regs_13505_640_480_16bpp) / + sizeof(regs_13505_640_480_16bpp[0]), + logo_addr, logo_size); + if (result && str) { + /* retry with internal image */ + logo_addr = logo_bmp; + logo_size = sizeof(logo_bmp); + lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13505_640_480_16bpp, + sizeof(regs_13505_640_480_16bpp) / + sizeof(regs_13505_640_480_16bpp[0]), + logo_addr, logo_size); + } + } else { + result = lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp) / + sizeof(regs_13806_640_480_16bpp[0]), + logo_addr, logo_size); + if (result && str) { + /* retry with internal image */ + logo_addr = logo_bmp; + logo_size = sizeof(logo_bmp); + lcd_init((uchar *)CFG_LCD_BIG_REG, + (uchar *)CFG_LCD_BIG_MEM, + regs_13806_640_480_16bpp, + sizeof(regs_13806_640_480_16bpp) / + sizeof(regs_13806_640_480_16bpp[0]), + logo_addr, logo_size); + } + } /* * Reset microcontroller and setup backlight PWM controller */ - *fpga_mode |= 0x0014; + out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014); for (i=0;i<10;i++) udelay(1000); - *fpga_mode |= 0x001c; - *fuji_lcdbl_pwm = 0x00ff; + out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c); + + minb = 0; + maxb = 0xff; + str = getenv("lcdbl"); + if (str) { + minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff; + if (str && (*str=',')) { + str++; + maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff; + } else + minb = 0; + + out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb); + out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb); + + printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb); + } + out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff); + + if (getenv("usb_self") == NULL) { + setenv("usb_load", CFG_USB_LOAD_COMMAND); + setenv("usbargs", CFG_USB_ARGS); + setenv("bootcmd", CONFIG_BOOTCOMMAND); + setenv("usb_self", CFG_USB_SELF_COMMAND); + saveenv(); + } return (0); } - /* * Check Board Identity: */ - int checkboard (void) { - unsigned char str[64]; + char str[64]; int i = getenv_r ("serial#", str, sizeof(str)); puts ("Board: "); @@ -311,18 +413,11 @@ int checkboard (void) } gd->board_type = board_revision(); - printf(", Rev 1.%ld\n", gd->board_type); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); + printf(", Rev. 1.%ld\n", gd->board_type); return 0; } -/* ------------------------------------------------------------------------- */ - long int initdram (int board_type) { unsigned long val; @@ -330,43 +425,64 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ - -int testdram (void) +#ifdef CONFIG_IDE_RESET +void ide_set_reset(int on) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); + u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); - return (0); + /* + * Assert or deassert CompactFlash Reset Pin + */ + if (on) { + out_be16(fpga_mode, + in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET); + } else { + out_be16(fpga_mode, + in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET); + } } +#endif /* CONFIG_IDE_RESET */ -/* ------------------------------------------------------------------------- */ +void reset_phy(void) +{ + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +} -#ifdef CONFIG_IDE_RESET +#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT) +int usb_board_init(void) +{ + return 0; +} -void ide_set_reset(int on) +int usb_board_stop(void) { - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL); + unsigned short tmp; + int i; /* - * Assert or deassert CompactFlash Reset Pin + * reset PCI bus + * This is required to make some very old Linux OHCI driver + * work after U-Boot has used the OHCI controller. */ - if (on) { /* assert RESET */ - *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET); - } else { /* release RESET */ - *fpga_mode |= CFG_FPGA_CTRL_CF_RESET; - } -} + pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp); + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000)); -#endif /* CONFIG_IDE_RESET */ + for (i = 0; i < 100; i++) + udelay(1000); -/* ------------------------------------------------------------------------- */ + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp); + return 0; +} + +int usb_board_init_fail(void) +{ + usb_board_stop(); + return 0; +} +#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */ diff --git a/board/esd/apc405/fpgadata.c b/board/esd/apc405/fpgadata.c index c31625a99..0b4664e87 100644 --- a/board/esd/apc405/fpgadata.c +++ b/board/esd/apc405/fpgadata.c @@ -1,2280 +1,2004 @@ - 0x1f,0x8b,0x08,0x08,0x30,0x6a,0x41,0x42,0x00,0x03,0x61,0x62,0x67,0x34,0x30,0x35, - 0x5f,0x31,0x5f,0x30,0x32,0x2e,0x62,0x69,0x74,0x00,0xed,0xbd,0x0b,0x74,0x1c,0xd5, - 0x95,0x2e,0xbc,0xeb,0x54,0x49,0x2e,0x75,0xb7,0xd4,0xa5,0x87,0x89,0x00,0x63,0x4a, - 0x2d,0xd9,0xb4,0x3d,0x6d,0xb9,0x2d,0x1b,0x59,0x08,0x59,0x2a,0x3d,0x20,0x1d,0xec, - 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0xe0,0x4f,0xc5,0xff,0x02,0x04,0xc4,0x15,0x0c,0x36,0xb4, + 0x04,0x00, diff --git a/board/esd/apc405/strataflash.c b/board/esd/apc405/strataflash.c deleted file mode 100644 index ad7a71dc4..000000000 --- a/board/esd/apc405/strataflash.c +++ /dev/null @@ -1,789 +0,0 @@ -/* - * (C) Copyright 2002 - * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/processor.h> - -#undef DEBUG_FLASH -/* - * This file implements a Common Flash Interface (CFI) driver for ppcboot. - * The width of the port and the width of the chips are determined at initialization. - * These widths are used to calculate the address for access CFI data structures. - * It has been tested on an Intel Strataflash implementation. - * - * References - * JEDEC Standard JESD68 - Common Flash Interface (CFI) - * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes - * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets - * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet - * - * TODO - * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available - * Add support for other command sets Use the PRI and ALT to determine command set - * Verify erase and program timeouts. - */ - -#define FLASH_CMD_CFI 0x98 -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_CMD_RESET 0xff -#define FLASH_CMD_BLOCK_ERASE 0x20 -#define FLASH_CMD_ERASE_CONFIRM 0xD0 -#define FLASH_CMD_WRITE 0x40 -#define FLASH_CMD_PROTECT 0x60 -#define FLASH_CMD_PROTECT_SET 0x01 -#define FLASH_CMD_PROTECT_CLEAR 0xD0 -#define FLASH_CMD_CLEAR_STATUS 0x50 -#define FLASH_CMD_WRITE_TO_BUFFER 0xE8 -#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 - -#define FLASH_STATUS_DONE 0x80 -#define FLASH_STATUS_ESS 0x40 -#define FLASH_STATUS_ECLBS 0x20 -#define FLASH_STATUS_PSLBS 0x10 -#define FLASH_STATUS_VPENS 0x08 -#define FLASH_STATUS_PSS 0x04 -#define FLASH_STATUS_DPS 0x02 -#define FLASH_STATUS_R 0x01 -#define FLASH_STATUS_PROTECT 0x01 - -#define FLASH_OFFSET_CFI 0x55 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 -#define FLASH_OFFSET_USER_PROTECTION 0x85 -#define FLASH_OFFSET_INTEL_PROTECTION 0x81 - -#define FLASH_MAN_CFI 0x01000000 - -typedef union { - unsigned char c; - unsigned short w; - unsigned long l; -} cfiword_t; - -typedef union { - unsigned char * cp; - unsigned short *wp; - unsigned long *lp; -} cfiptr_t; - -#define NUM_ERASE_REGIONS 4 - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c); -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf); -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd); -static int flash_detect_cfi(flash_info_t * info); -static ulong flash_get_size (ulong base, int banknum); -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword); -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt); -#ifdef CFG_FLASH_USE_BUFFER_WRITE -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len); -#endif -/*----------------------------------------------------------------------- - * create an address based on the offset and the port width - */ -inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset) -{ - return ((uchar *)(info->start[sect] + (offset * info->portwidth))); -} -/*----------------------------------------------------------------------- - * read a character at a port width address - */ -inline uchar flash_read_uchar(flash_info_t * info, uchar offset) -{ - uchar *cp; - cp = flash_make_addr(info, 0, offset); - return (cp[info->portwidth - 1]); -} - -/*----------------------------------------------------------------------- - * read a short word by swapping for ppc format. - */ -ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]); - -} - -/*----------------------------------------------------------------------- - * read a long word by picking the least significant byte of each maiximum - * port size word. Swap for ppc format. - */ -ulong flash_read_long(flash_info_t * info, int sect, uchar offset) -{ - uchar * addr; - - addr = flash_make_addr(info, sect, offset); - return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | - (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]); - -} - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - unsigned long size; - int i; - unsigned long address; - - - /* The flash is positioned back to back, with the demultiplexing of the chip - * based on the A24 address line. - * - */ - - address = CFG_FLASH_BASE; - size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(address, i); - address += CFG_FLASH_INCREMENT; - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i, - flash_info[0].size, flash_info[i].size<<20); - } - } - -#if 0 /* test-only */ - /* Monitor protection ON by default */ -#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE) - for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++) - (void)flash_real_protect(&flash_info[0], i, 1); -#endif -#else - /* monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - - CFG_MONITOR_LEN, - - 1, &flash_info[1]); -#endif - - return (size); -} - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot; - int sect; - - if( info->flash_id != FLASH_MAN_CFI) { - printf ("Can't erase unknown flash type - aborted\n"); - return 1; - } - if ((s_first < 0) || (s_first > s_last)) { - printf ("- no sectors to erase\n"); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE); - flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM); - - if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) { - rcode = 1; - } else - printf("."); - } - } - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id != FLASH_MAN_CFI) { - printf ("missing or unknown FLASH type\n"); - return; - } - - printf("CFI conformant FLASH (%d x %d)", - (info->portwidth << 3 ), (info->chipwidth << 3 )); - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", - info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { -#ifdef CFG_FLASH_EMPTY_INFO - int k; - int size; - int erased; - volatile unsigned long *flash; - - /* - * Check if whole sector is erased - */ - if (i != (info->sector_count-1)) - size = info->start[i+1] - info->start[i]; - else - size = info->start[0] + info->size - info->start[i]; - erased = 1; - flash = (volatile unsigned long *)info->start[i]; - size = size >> 2; /* divide by 4 for longword access */ - for (k=0; k<size; k++) - { - if (*flash++ != 0xffffffff) - { - erased = 0; - break; - } - } - - if ((i % 5) == 0) - printf ("\n "); - /* print empty and read-only info */ - printf (" %08lX%s%s", - info->start[i], - erased ? " E" : " ", - info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); -#endif - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp; - ulong cp; - int aln; - cfiword_t cword; - int i, rc; - - /* get lower aligned address */ - wp = (addr & ~(info->portwidth - 1)); - - /* handle unaligned start */ - if((aln = addr - wp) != 0) { - cword.l = 0; - cp = wp; - for(i=0;i<aln; ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - - for(; (i< info->portwidth) && (cnt > 0) ; i++) { - flash_add_byte(info, &cword, *src++); - cnt--; - cp++; - } - for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp) - flash_add_byte(info, &cword, (*(uchar *)cp)); - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp = cp; - } - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - while(cnt >= info->portwidth) { - i = info->buffer_size > cnt? cnt: info->buffer_size; - if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK) - return rc; - wp += i; - src += i; - cnt -=i; - } -#else - /* handle the aligned part */ - while(cnt >= info->portwidth) { - cword.l = 0; - for(i = 0; i < info->portwidth; i++) { - flash_add_byte(info, &cword, *src++); - } - if((rc = flash_write_cfiword(info, wp, cword)) != 0) - return rc; - wp += info->portwidth; - cnt -= info->portwidth; - } -#endif /* CFG_FLASH_USE_BUFFER_WRITE */ - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - cword.l = 0; - for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) { - flash_add_byte(info, &cword, *src++); - --cnt; - } - for (; i<info->portwidth; ++i, ++cp) { - flash_add_byte(info, & cword, (*(uchar *)cp)); - } - - return flash_write_cfiword(info, wp, cword); -} - -/*----------------------------------------------------------------------- - */ -int flash_real_protect(flash_info_t *info, long sector, int prot) -{ - int retcode = 0; - - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); - if(prot) - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); - - if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout, - prot?"protect":"unprotect")) == 0) { - - info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if(prot == 0) { - int i; - for(i = 0 ; i<info->sector_count; i++) { - if(info->protect[i]) - flash_real_protect(info, i, 1); - } - } - } - - return retcode; -} -/*----------------------------------------------------------------------- - * wait for XSR.7 to be set. Time out with an error if it does not. - * This routine does not set the flash to read-array mode. - */ -static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - ulong start; - - /* Wait for command completion */ - start = get_timer (0); - while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { - if (get_timer(start) > info->erase_blk_tout) { - printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]); - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return ERR_TIMOUT; - } - } - return ERR_OK; -} -/*----------------------------------------------------------------------- - * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check. - * This routine sets the flash to read-array mode. - */ -static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt) -{ - int retcode; - retcode = flash_status_check(info, sector, tout, prompt); - if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) { - retcode = ERR_INVAL; - printf("Flash %s error at address %lx\n", prompt,info->start[sector]); - if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){ - printf("Command Sequence Error.\n"); - } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){ - printf("Block Erase Error.\n"); - retcode = ERR_NOT_ERASED; - } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) { - printf("Locking Error\n"); - } - if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){ - printf("Block locked.\n"); - retcode = ERR_PROTECTED; - } - if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) - printf("Vpp Low Error.\n"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_RESET); - return retcode; -} -/*----------------------------------------------------------------------- - */ -static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c) -{ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cword->c = c; - break; - case FLASH_CFI_16BIT: - cword->w = (cword->w << 8) | c; - break; - case FLASH_CFI_32BIT: - cword->l = (cword->l << 8) | c; - } -} - - -/*----------------------------------------------------------------------- - * make a proper sized command based on the port and chip widths - */ -static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf) -{ - int i; - uchar *cp = (uchar *)cmdbuf; - for(i=0; i< info->portwidth; i++) - *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; -} - -/* - * Write a proper sized command to the correct address - */ -static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - - volatile cfiptr_t addr; - cfiword_t cword; - addr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *addr.cp = cword.c; - break; - case FLASH_CFI_16BIT: - *addr.wp = cword.w; - break; - case FLASH_CFI_32BIT: - *addr.lp = cword.l; - break; - } -} - -/*----------------------------------------------------------------------- - */ -static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = (cptr.cp[0] == cword.c); - break; - case FLASH_CFI_16BIT: - retval = (cptr.wp[0] == cword.w); - break; - case FLASH_CFI_32BIT: - retval = (cptr.lp[0] == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} -/*----------------------------------------------------------------------- - */ -static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd) -{ - cfiptr_t cptr; - cfiword_t cword; - int retval; - cptr.cp = flash_make_addr(info, sect, offset); - flash_make_cmd(info, cmd, &cword); - switch(info->portwidth) { - case FLASH_CFI_8BIT: - retval = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - retval = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - retval = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - retval = 0; - break; - } - return retval; -} - -/*----------------------------------------------------------------------- - * detect if flash is compatible with the Common Flash Interface (CFI) - * http://www.jedec.org/download/search/jesd68.pdf - * -*/ -static int flash_detect_cfi(flash_info_t * info) -{ - - for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT; - info->portwidth <<= 1) { - for(info->chipwidth =FLASH_CFI_BY8; - info->chipwidth <= info->portwidth; - info->chipwidth <<= 1) { - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI); - if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && - flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) - return 1; - } - } - return 0; -} -/* - * The following code cannot be run from FLASH! - * - */ -static ulong flash_get_size (ulong base, int banknum) -{ - flash_info_t * info = &flash_info[banknum]; - int i, j; - int sect_cnt; - unsigned long sector; - unsigned long tmp; - int size_ratio; - uchar num_erase_regions; - int erase_region_size; - int erase_region_count; - - info->start[0] = base; - - if(flash_detect_cfi(info)){ -#ifdef DEBUG_FLASH - printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */ -#endif - size_ratio = info->portwidth / info->chipwidth; - num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS); -#ifdef DEBUG_FLASH - printf("found %d erase regions\n", num_erase_regions); -#endif - sect_cnt = 0; - sector = base; - for(i = 0 ; i < num_erase_regions; i++) { - if(i > NUM_ERASE_REGIONS) { - printf("%d erase regions found, only %d used\n", - num_erase_regions, NUM_ERASE_REGIONS); - break; - } - tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS); - erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128; - tmp >>= 16; - erase_region_count = (tmp & 0xffff) +1; - for(j = 0; j< erase_region_count; j++) { - info->start[sect_cnt] = sector; - sector += (erase_region_size * size_ratio); - info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT); - sect_cnt++; - } - } - - info->sector_count = sect_cnt; - /* multiply the size by the number of chips */ - info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio; - info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE)); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); - info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT))); - tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); - info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000; - info->flash_id = FLASH_MAN_CFI; - } - - flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); - return(info->size); -} - - -/*----------------------------------------------------------------------- - */ -static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword) -{ - - cfiptr_t ctladdr; - cfiptr_t cptr; - int flag; - - ctladdr.cp = flash_make_addr(info, 0, 0); - cptr.cp = (uchar *)dest; - - - /* Check if Flash is (sufficiently) erased */ - switch(info->portwidth) { - case FLASH_CFI_8BIT: - flag = ((cptr.cp[0] & cword.c) == cword.c); - break; - case FLASH_CFI_16BIT: - flag = ((cptr.wp[0] & cword.w) == cword.w); - break; - case FLASH_CFI_32BIT: - flag = ((cptr.lp[0] & cword.l) == cword.l); - break; - default: - return 2; - } - if(!flag) - return 2; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); - - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cptr.cp[0] = cword.c; - break; - case FLASH_CFI_16BIT: - cptr.wp[0] = cword.w; - break; - case FLASH_CFI_32BIT: - cptr.lp[0] = cword.l; - break; - } - - /* re-enable interrupts if necessary */ - if(flag) - enable_interrupts(); - - return flash_full_status_check(info, 0, info->write_tout, "write"); -} - -#ifdef CFG_FLASH_USE_BUFFER_WRITE - -/* loop through the sectors from the highest address - * when the passed address is greater or equal to the sector address - * we have a match - */ -static int find_sector(flash_info_t *info, ulong addr) -{ - int sector; - for(sector = info->sector_count - 1; sector >= 0; sector--) { - if(addr >= info->start[sector]) - break; - } - return sector; -} - -static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len) -{ - - int sector; - int cnt; - int retcode; - volatile cfiptr_t src; - volatile cfiptr_t dst; - - src.cp = cp; - dst.cp = (uchar *)dest; - sector = find_sector(info, dest); - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER); - if((retcode = flash_status_check(info, sector, info->buffer_write_tout, - "write to buffer")) == ERR_OK) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - cnt = len; - break; - case FLASH_CFI_16BIT: - cnt = len >> 1; - break; - case FLASH_CFI_32BIT: - cnt = len >> 2; - break; - default: - return ERR_INVAL; - break; - } - flash_write_cmd(info, sector, 0, (uchar)cnt-1); - while(cnt-- > 0) { - switch(info->portwidth) { - case FLASH_CFI_8BIT: - *dst.cp++ = *src.cp++; - break; - case FLASH_CFI_16BIT: - *dst.wp++ = *src.wp++; - break; - case FLASH_CFI_32BIT: - *dst.lp++ = *src.lp++; - break; - default: - return ERR_INVAL; - break; - } - } - flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM); - retcode = flash_full_status_check(info, sector, info->buffer_write_tout, - "buffer write"); - } - flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); - return retcode; -} -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 1bf81c699..7e6eea0f1 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -44,29 +44,16 @@ extern au_image_t au_image[]; extern int N_AU_IMAGES; -#define AU_DEBUG -#undef AU_DEBUG - -#undef debug -#ifdef AU_DEBUG -#define debug(fmt,args...) printf (fmt ,##args) -#else -#define debug(fmt,args...) -#endif /* AU_DEBUG */ - - -#define LOAD_ADDR ((unsigned char *)0x100000) /* where to load files into memory */ -#define MAX_LOADSZ 0x1e00000 +/* where to load files into memory */ +#define LOAD_ADDR ((unsigned char *)0x100000) +#define MAX_LOADSZ 0x1c00000 /* externals */ extern int fat_register_device(block_dev_desc_t *, int); extern int file_fat_detectfs(void); extern long file_fat_read(const char *, void *, unsigned long); -long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols); -#ifdef CONFIG_VFD -extern int trab_vfd (ulong); -extern int transfer_pic(unsigned char, unsigned char *, int, int); -#endif +long do_fat_read (const char *filename, void *buffer, + unsigned long maxsize, int dols); extern int flash_sect_erase(ulong, ulong); extern int flash_sect_protect (int, ulong, ulong); extern int flash_write (char *, ulong, ulong); @@ -78,14 +65,15 @@ extern int flash_write (char *, ulong, ulong); #define NANDRW_JFFS2 0x02 #define NANDRW_JFFS2_SKIP 0x04 extern struct nand_chip nand_dev_desc[]; -extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, - size_t * retlen, u_char * buf); -extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); +extern int nand_legacy_rw(struct nand_chip* nand, int cmd, + size_t start, size_t len, + size_t * retlen, u_char * buf); +extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, + size_t len, int clean); #endif extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; - int au_check_cksum_valid(int i, long nbytes) { image_header_t *hdr; @@ -117,7 +105,6 @@ int au_check_cksum_valid(int i, long nbytes) return 0; } - int au_check_header_valid(int i, long nbytes) { image_header_t *hdr; @@ -132,20 +119,11 @@ int au_check_header_valid(int i, long nbytes) #endif /* check the easy ones first */ -#undef CHECK_VALID_DEBUG -#ifdef CHECK_VALID_DEBUG - printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC); - printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_PPC); - printf("size %#x %#lx ", image_get_data_size (hdr), nbytes); - printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL); -#endif - if (nbytes < image_get_header_size ()) - { + if (nbytes < image_get_header_size ()) { printf ("Image %s bad header SIZE\n", au_image[i].name); return -1; } - if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) - { + if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) { printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); return -1; } @@ -155,11 +133,13 @@ int au_check_header_valid(int i, long nbytes) } /* check the type - could do this all in one gigantic if() */ - if ((au_image[i].type == AU_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) { + if (((au_image[i].type & AU_TYPEMASK) == AU_FIRMWARE) && + !image_check_type (hdr, IH_TYPE_FIRMWARE)) { printf ("Image %s wrong type\n", au_image[i].name); return -1; } - if ((au_image[i].type == AU_SCRIPT) && !image_check_type (hdr, IH_TYPE_SCRIPT)) { + if (((au_image[i].type & AU_TYPEMASK) == AU_SCRIPT) && + !image_check_type (hdr, IH_TYPE_SCRIPT)) { printf ("Image %s wrong type\n", au_image[i].name); return -1; } @@ -167,22 +147,9 @@ int au_check_header_valid(int i, long nbytes) /* recycle checksum */ checksum = image_get_data_size (hdr); -#if 0 /* test-only */ - /* for kernel and app the image header must also fit into flash */ - if (idx != IDX_DISK) - checksum += image_get_header_size (); - /* check the size does not exceed space in flash. HUSH scripts */ - /* all have ausize[] set to 0 */ - if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { - printf ("Image %s is bigger than FLASH\n", au_image[i].name); - return -1; - } -#endif - return 0; } - int au_do_update(int i, long sz) { image_header_t *hdr; @@ -203,7 +170,7 @@ int au_do_update(int i, long sz) } #endif - switch (au_image[i].type) { + switch (au_image[i].type & AU_TYPEMASK) { case AU_SCRIPT: printf("Executing script %s\n", au_image[i].name); @@ -243,38 +210,43 @@ int au_do_update(int i, long sz) */ if (au_image[i].type == AU_FIRMWARE) { char *orig = (char*)start; - char *new = (char *)((char *)hdr + image_get_header_size ()); + char *new = (char *)((char *)hdr + + image_get_header_size ()); nbytes = image_get_data_size (hdr); - while(--nbytes) { + while (--nbytes) { if (*orig++ != *new++) { break; } } if (!nbytes) { - printf("Skipping firmware update - images are identical\n"); + printf ("Skipping firmware update - " + "images are identical\n"); break; } } /* unprotect the address range */ - /* this assumes that ONLY the firmware is protected! */ - if (au_image[i].type == AU_FIRMWARE) { - flash_sect_protect(0, start, end); + if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || + (au_image[i].type == AU_FIRMWARE)) { + flash_sect_protect (0, start, end); } /* * erase the address range. */ if (au_image[i].type != AU_NAND) { - printf("Updating NOR FLASH with image %s\n", au_image[i].name); + printf ("Updating NOR FLASH with image %s\n", + au_image[i].name); debug ("flash_sect_erase(%lx, %lx);\n", start, end); - flash_sect_erase(start, end); + flash_sect_erase (start, end); } else { #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - printf("Updating NAND FLASH with image %s\n", au_image[i].name); + printf ("Updating NAND FLASH with image %s\n", + au_image[i].name); debug ("nand_legacy_erase(%lx, %lx);\n", start, end); - rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); + rc = nand_legacy_erase (nand_dev_desc, start, + end - start + 1, 0); debug ("nand_legacy_erase returned %x\n", rc); #endif } @@ -296,20 +268,26 @@ int au_do_update(int i, long sz) * copy the data from RAM to FLASH */ if (au_image[i].type != AU_NAND) { - debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); - rc = flash_write((char *)addr, start, nbytes); + debug ("flash_write(%p, %lx, %x)\n", + addr, start, nbytes); + rc = flash_write ((char *)addr, start, + (nbytes + 1) & ~1); } else { #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); - rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, - start, nbytes, (size_t *)&total, (uchar *)addr); - debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); + debug ("nand_legacy_rw(%p, %lx, %x)\n", + addr, start, nbytes); + rc = nand_legacy_rw (nand_dev_desc, + NANDRW_WRITE | NANDRW_JFFS2, + start, nbytes, (size_t *)&total, + (uchar *)addr); + debug ("nand_legacy_rw: ret=%x total=%d nbytes=%d\n", + rc, total, nbytes); #else rc = -1; #endif } if (rc != 0) { - printf("Flashing failed due to error %d\n", rc); + printf ("Flashing failed due to error %d\n", rc); return -1; } @@ -317,23 +295,30 @@ int au_do_update(int i, long sz) * check the dcrc of the copy */ if (au_image[i].type != AU_NAND) { - rc = crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)); + rc = crc32 (0, (uchar *)(start + off), + image_get_data_size (hdr)); } else { #if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY) - rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, - start, nbytes, (size_t *)&total, (uchar *)addr); - rc = crc32 (0, (uchar *)(addr + off), image_get_data_size (hdr)); + rc = nand_legacy_rw (nand_dev_desc, + NANDRW_READ | NANDRW_JFFS2 | + NANDRW_JFFS2_SKIP, + start, nbytes, (size_t *)&total, + (uchar *)addr); + rc = crc32 (0, (uchar *)(addr + off), + image_get_data_size (hdr)); #endif } if (rc != image_get_dcrc (hdr)) { - printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name); + printf ("Image %s Bad Data Checksum After COPY\n", + au_image[i].name); return -1; } /* protect the address range */ /* this assumes that ONLY the firmware is protected! */ - if (au_image[i].type == AU_FIRMWARE) { - flash_sect_protect(1, start, end); + if (((au_image[i].type & AU_FLAGMASK) == AU_PROTECT) || + (au_image[i].type == AU_FIRMWARE)) { + flash_sect_protect (1, start, end); } break; @@ -345,7 +330,6 @@ int au_do_update(int i, long sz) return 0; } - static void process_macros (const char *input, char *output) { char c, prev; @@ -359,16 +343,17 @@ static void process_macros (const char *input, char *output) #ifdef DEBUG_PARSER char *output_start = output; - printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input); + printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", + strlen(input), input); #endif - prev = '\0'; /* previous character */ + prev = '\0'; /* previous character */ while (inputcnt && outputcnt) { c = *input++; inputcnt--; - if (state!=3) { + if (state != 3) { /* remove one level of escape characters */ if ((c == '\\') && (prev != '\\')) { if (inputcnt-- == 0) @@ -379,7 +364,7 @@ static void process_macros (const char *input, char *output) } switch (state) { - case 0: /* Waiting for (unescaped) $ */ + case 0: /* Waiting for (unescaped) $ */ if ((c == '\'') && (prev != '\\')) { state = 3; break; @@ -391,7 +376,7 @@ static void process_macros (const char *input, char *output) outputcnt--; } break; - case 1: /* Waiting for ( */ + case 1: /* Waiting for ( */ if (c == '(' || c == '{') { state++; varname_start = input; @@ -410,7 +395,8 @@ static void process_macros (const char *input, char *output) if (c == ')' || c == '}') { int i; char envname[CFG_CBSIZE], *envval; - int envcnt = input-varname_start-1; /* Varname # of chars */ + /* Varname # of chars */ + int envcnt = input - varname_start - 1; /* Get the varname */ for (i = 0; i < envcnt; i++) { @@ -448,11 +434,10 @@ static void process_macros (const char *input, char *output) #ifdef DEBUG_PARSER printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", - strlen(output_start), output_start); + strlen (output_start), output_start); #endif } - /* * this is called from board_init() after the hardware has been set up * and is usable. That seems like a good time to do this. @@ -460,84 +445,84 @@ static void process_macros (const char *input, char *output) */ int do_auto_update(void) { - block_dev_desc_t *stor_dev; + block_dev_desc_t *stor_dev = NULL; long sz; int i, res, cnt, old_ctrlc, got_ctrlc; char buffer[32]; char str[80]; + int n; - /* - * Check whether a CompactFlash is inserted - */ - if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) { - return -1; /* no disk detected! */ + if (ide_dev_desc[0].type != DEV_TYPE_UNKNOWN) { + stor_dev = get_dev ("ide", 0); + if (stor_dev == NULL) { + debug ("ide: unknown device\n"); + return -1; + } } - /* check whether it has a partition table */ - stor_dev = get_dev("ide", 0); - if (stor_dev == NULL) { - debug ("Uknown device type\n"); - return -1; - } - if (fat_register_device(stor_dev, 1) != 0) { - debug ("Unable to register ide disk 0:1 for fatls\n"); + if (fat_register_device (stor_dev, 1) != 0) { + debug ("Unable to register ide disk 0:1\n"); return -1; } /* * Check if magic file is present */ - if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) { + if ((n = do_fat_read (AU_MAGIC_FILE, buffer, + sizeof(buffer), LS_NO)) <= 0) { + debug ("No auto_update magic file (n=%d)\n", n); return -1; } #ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show(1); + board_auto_update_show (1); #endif puts("\nAutoUpdate Disk detected! Trying to update system...\n"); /* make sure that we see CTRL-C and save the old state */ - old_ctrlc = disable_ctrlc(0); + old_ctrlc = disable_ctrlc (0); /* just loop thru all the possible files */ for (i = 0; i < N_AU_IMAGES; i++) { /* * Try to expand the environment var in the fname */ - process_macros(au_image[i].name, str); - strcpy(au_image[i].name, str); + process_macros (au_image[i].name, str); + strcpy (au_image[i].name, str); printf("Reading %s ...", au_image[i].name); /* just read the header */ - sz = do_fat_read(au_image[i].name, LOAD_ADDR, image_get_header_size (), LS_NO); + sz = do_fat_read (au_image[i].name, LOAD_ADDR, + image_get_header_size (), LS_NO); debug ("read %s sz %ld hdr %d\n", au_image[i].name, sz, image_get_header_size ()); if (sz <= 0 || sz < image_get_header_size ()) { puts(" not found\n"); continue; } - if (au_check_header_valid(i, sz) < 0) { + if (au_check_header_valid (i, sz) < 0) { puts(" header not valid\n"); continue; } - sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO); + sz = do_fat_read (au_image[i].name, LOAD_ADDR, + MAX_LOADSZ, LS_NO); debug ("read %s sz %ld hdr %d\n", au_image[i].name, sz, image_get_header_size ()); if (sz <= 0 || sz <= image_get_header_size ()) { puts(" not found\n"); continue; } - if (au_check_cksum_valid(i, sz) < 0) { + if (au_check_cksum_valid (i, sz) < 0) { puts(" checksum not valid\n"); continue; } puts(" done\n"); do { - res = au_do_update(i, sz); + res = au_do_update (i, sz); /* let the user break out of the loop */ - if (ctrlc() || had_ctrlc()) { - clear_ctrlc(); + if (ctrlc() || had_ctrlc ()) { + clear_ctrlc (); if (res < 0) got_ctrlc = 1; break; @@ -547,17 +532,16 @@ int do_auto_update(void) } /* restore the old state */ - disable_ctrlc(old_ctrlc); + disable_ctrlc (old_ctrlc); puts("AutoUpdate finished\n\n"); #ifdef CONFIG_AUTO_UPDATE_SHOW - board_auto_update_show(0); + board_auto_update_show (0); #endif return 0; } - int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { do_auto_update(); diff --git a/board/esd/common/auto_update.h b/board/esd/common/auto_update.h index e2af3c7b1..3ed0e1637 100644 --- a/board/esd/common/auto_update.h +++ b/board/esd/common/auto_update.h @@ -29,16 +29,21 @@ #define AU_MAGIC_FILE "__auto_update" -#define AU_SCRIPT 1 -#define AU_FIRMWARE 2 -#define AU_NOR 3 -#define AU_NAND 4 +#define AU_TYPEMASK 0x000000ff +#define AU_FLAGMASK 0xffff0000 + +#define AU_PROTECT 0x80000000 + +#define AU_SCRIPT 0x01 +#define AU_FIRMWARE (0x02 | AU_PROTECT) +#define AU_NOR 0x03 +#define AU_NAND 0x04 struct au_image_s { char name[80]; ulong start; ulong size; - int type; + ulong type; }; typedef struct au_image_s au_image_t; diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index ed50def48..c23dc81a2 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -44,37 +44,57 @@ void lcd_setup(int lcd, int config) /* * Set endianess and reset lcd controller 0 (small) */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ + + /* set reset to low */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST); udelay(10); /* wait 10us */ - if (config == 1) - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - else - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + if (config == 1) { + /* big-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + } else { + /* little-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + } udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ + /* set reset to high */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD0_RST); } else { /* * Set endianess and reset lcd controller 1 (big) */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ + + /* set reset to low */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST); udelay(10); /* wait 10us */ - if (config == 1) - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ - else - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ + if (config == 1) { + /* big-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); + } else { + /* little-endian */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN); + } udelay(10); /* wait 10us */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ + /* set reset to high */ + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CFG_LCD1_RST); } /* * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive */ - out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ + out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN); } #endif /* CFG_LCD_ENDIAN */ -void lcd_bmp(uchar *logo_bmp) +int lcd_bmp(uchar *logo_bmp) { int i; uchar *ptr; @@ -99,13 +119,18 @@ void lcd_bmp(uchar *logo_bmp) len = CFG_VIDEO_LOGO_MAX_SIZE; dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { - printf("Error: malloc in gunzip failed!\n"); - return; + printf("Error: malloc for gunzip failed!\n"); + return 1; + } + if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, + (uchar *)logo_bmp, &len) != 0) { + free(dst); + return 1; + } + if (len == CFG_VIDEO_LOGO_MAX_SIZE) { + printf("Image could be truncated" + " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); } - if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) - return; - if (len == CFG_VIDEO_LOGO_MAX_SIZE) - printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n"); /* * Check for bmp mark 'BM' @@ -113,7 +138,7 @@ void lcd_bmp(uchar *logo_bmp) if (*(ushort *)dst != 0x424d) { printf("LCD: Unknown image format!\n"); free(dst); - return; + return 1; } } else { /* @@ -150,7 +175,7 @@ void lcd_bmp(uchar *logo_bmp) printf("LCD: Unknown bpp (%d) im image!\n", bpp); if ((dst != NULL) && (dst != (uchar *)logo_bmp)) free(dst); - return; + return 1; } printf(" (%d*%d, %dbpp)\n", width, height, bpp); @@ -180,23 +205,28 @@ void lcd_bmp(uchar *logo_bmp) if (bpp == 24) { for (x = 0; x < width; x++) { /* - * Generate epson 16bpp fb-format from 24bpp image + * Generate epson 16bpp fb-format + * from 24bpp image */ b = *bmp++ >> 3; g = *bmp++ >> 2; r = *bmp++ >> 3; - val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); + val = ((r & 0x1f) << 11) | + ((g & 0x3f) << 5) | + (b & 0x1f); *ptr2++ = val; } } else if (bpp == 8) { for (x = 0; x < line_size; x++) { /* query rgb value from palette */ - ptr = (unsigned char *)(dst + 14 + 40) ; + ptr = (unsigned char *)(dst + 14 + 40); ptr += (*bmp++) << 2; b = *ptr++ >> 3; g = *ptr++ >> 2; r = *ptr++ >> 3; - val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); + val = ((r & 0x1f) << 11) | + ((g & 0x3f) << 5) | + (b & 0x1f); *ptr2++ = val; } } @@ -208,11 +238,12 @@ void lcd_bmp(uchar *logo_bmp) if ((dst != NULL) && (dst != (uchar *)logo_bmp)) free(dst); + return 0; } -void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, - uchar *logo_bmp, ulong len) +int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, + uchar *logo_bmp, ulong len) { int i; ushort s1dReg; @@ -263,8 +294,22 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, lcd_reg += 0x10000; /* add offset for 705 regs */ puts("LCD: S1D13705"); } else { - puts("LCD: No controller detected!\n"); - return; + out_8(&lcd_reg[0x1a], 0x00); + udelay(1000); + if (in_8(&lcd_reg[1]) == 0x0c) { + /* + * S1D13505 detected + */ + reg_byte_swap = TRUE; + palette_index = 0x25; + palette_value = 0x27; + lcd_depth = 16; + + puts("LCD: S1D13505"); + } else { + puts("LCD: No controller detected!\n"); + return 1; + } } /* @@ -279,7 +324,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, s1dReg &= ~0x0001; } s1dValue = regs[i].Value; - lcd_reg[s1dReg] = s1dValue; + out_8(&lcd_reg[s1dReg], s1dValue); } /* @@ -291,15 +336,15 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Display bmp image */ - lcd_bmp(logo_bmp); + return lcd_bmp(logo_bmp); } -#if defined(CONFIG_VIDEO_SM501) int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong addr; +#ifdef CONFIG_VIDEO_SM501 char *str; - +#endif if (argc != 2) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; @@ -307,19 +352,22 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[1], NULL, 16); +#ifdef CONFIG_VIDEO_SM501 str = getenv("bd_type"); if ((strcmp(str, "ppc221") == 0) || (strcmp(str, "ppc231") == 0)) { /* * SM501 available, use standard bmp command */ - return (video_display_bitmap(addr, 0, 0)); + return video_display_bitmap(addr, 0, 0); } else { /* * No SM501 available, use esd epson bmp command */ - lcd_bmp((uchar *)addr); - return 0; + return lcd_bmp((uchar *)addr); } +#else + return lcd_bmp((uchar *)addr); +#endif } U_BOOT_CMD( @@ -327,4 +375,3 @@ U_BOOT_CMD( "esdbmp - display BMP image\n", "<imageAddr> - display image\n" ); -#endif diff --git a/board/esd/common/s1d13505_640_480_16bpp.h b/board/esd/common/s1d13505_640_480_16bpp.h new file mode 100644 index 000000000..02b3b9291 --- /dev/null +++ b/board/esd/common/s1d13505_640_480_16bpp.h @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2008 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz) + * Memory: DRAM (MCLK=40.000 MHz) + */ +static S1D_REGS regs_13505_640_480_16bpp[] = +{ + {0x1B,0x00}, /* Miscellaneous Register */ + {0x23,0x20}, /* Performance Enhancement Register 1 */ + {0x01,0x30}, /* Memory Configuration Register */ + {0x22,0x24}, /* Performance Enhancement Register 0 */ + {0x02,0x25}, /* Panel Type Register */ + {0x03,0x00}, /* MOD Rate Register */ + {0x04,0x4F}, /* Horizontal Display Width Register */ + {0x05,0x0c}, /* Horizontal Non-Display Period Register */ + {0x06,0x00}, /* HRTC/FPLINE Start Position Register */ + {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */ + {0x08,0xDF}, /* Vertical Display Height Register 0 */ + {0x09,0x01}, /* Vertical Display Height Register 1 */ + {0x0A,0x3E}, /* Vertical Non-Display Period Register */ + {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */ + {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */ + {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */ + {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */ + {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */ + {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */ + {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */ + {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */ + {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */ + {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */ + {0x16,0x80}, /* Memory Address Offset Register 0 */ + {0x17,0x02}, /* Memory Address Offset Register 1 */ + {0x18,0x00}, /* Pixel Panning Register */ + {0x19,0x01}, /* Clock Configuration Register */ + {0x1A,0x00}, /* Power Save Configuration Register */ + {0x1C,0x00}, /* MD Configuration Readback Register 0 */ + {0x1E,0x06}, /* General IO Pins Configuration Register 0 */ + {0x1F,0x00}, /* General IO Pins Configuration Register 1 */ + {0x20,0x00}, /* General IO Pins Control Register 0 */ + {0x21,0x00}, /* General IO Pins Control Register 1 */ + {0x23,0x20}, /* Performance Enhancement Register 1 */ + {0x0D,0x15}, /* Display Mode Register */ +}; diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 90d930955..ca5c177e3 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -293,20 +293,9 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] sdsdp[2]=0x40082350; sdsdp[3]=0x0d050000; } else if (!strcmp(argv[1], "667")) { - /* PLB=133MHz, PLB/PCI=4 */ + /* PLB=133MHz, PLB/PCI=3 */ printf("Bootstrapping for 667MHz\n"); sdsdp[0]=0x8778a256; - sdsdp[1]=0x0947a030; - sdsdp[2]=0x40082350; - sdsdp[3]=0x0d050000; - } else if (!strcmp(argv[1], "test")) { - /* - * TODO: this will replace the 667 MHz config above. - * But it needs some more testing on a real 667 MHz CPU. - */ - printf("Bootstrapping for test" - " (667MHz PLB=133PLB PLB/PCI=3)\n"); - sdsdp[0]=0x8778a256; sdsdp[1]=0x095fa030; sdsdp[2]=0x40082350; sdsdp[3]=0x0d050000; diff --git a/board/imx31_litekit/imx31_litekit.c b/board/imx31_litekit/imx31_litekit.c index 5ba60e9f7..e0fbf25fc 100644 --- a/board/imx31_litekit/imx31_litekit.c +++ b/board/imx31_litekit/imx31_litekit.c @@ -52,7 +52,7 @@ int board_init (void) mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_RTS1__UART1_CTS_B); - gd->bd->bi_arch_number = 447; /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_MX31LITE; /* board id for linux */ gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ return 0; diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c index 37d9b57fa..02086a003 100644 --- a/board/linkstation/ide.c +++ b/board/linkstation/ide.c @@ -81,12 +81,12 @@ int ide_preinit (void) #endif pci_write_config_dword(devbusfn, IT8212_PCI_IdeBusSkewCONTROL, 0x02040204); /* __LS_COMMENT__ BUFFALO changed 2004.11.10 changed for EMI */ - pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */ -/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */ - pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00); + pci_write_config_byte(devbusfn, IT8212_PCI_IdeDrivingCURRENT, 0x36); /* 10mA */ +/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x09); */ /* 4mA */ +/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x12); */ /* 6mA */ +/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x24); */ /* 6mA,2mA */ +/* pci_write_config_byte(dev, IT8212_PCI_IdeDrivingCURRENT, 0x2D); */ /* 8mA,4mA */ + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x00); } return (status); diff --git a/board/mx31ads/Makefile b/board/mx31ads/Makefile new file mode 100644 index 000000000..dfadd9685 --- /dev/null +++ b/board/mx31ads/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx31ads.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mx31ads/config.mk b/board/mx31ads/config.mk new file mode 100644 index 000000000..d34dc02d9 --- /dev/null +++ b/board/mx31ads/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x87f00000 diff --git a/board/mx31ads/lowlevel_init.S b/board/mx31ads/lowlevel_init.S new file mode 100644 index 000000000..099a7ca81 --- /dev/null +++ b/board/mx31ads/lowlevel_init.S @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/mx31-regs.h> + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + +/* RedBoot: AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =0x43F00000 + ldr r1, =0x77777777 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =0x53F00000 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =0x43F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] + + ldr r0, =0x53F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] +.endm /* init_aips */ + +/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =0x43F04000 + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =0x00302154 + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =0x10 + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =0x0 + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm /* init_max */ + +/* RedBoot: M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =0xB8003000 + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =0x00000040 + str r0, [r1] /* M3IF control reg */ +.endm /* init_m3if */ + +/* RedBoot: To support 133MHz DDR */ +.macro init_drive_strength + /* + * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits + * in SW_PAD_CTL registers + */ + + /* SDCLK */ + ldr r1, =0x43FAC200 + ldr r0, [r1, #0x6C] + bic r0, r0, #(1 << 12) + str r0, [r1, #0x6C] + + /* CAS */ + ldr r0, [r1, #0x70] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x70] + + /* RAS */ + ldr r0, [r1, #0x74] + bic r0, r0, #(1 << 2) + str r0, [r1, #0x74] + + /* CS2 (CSD0) */ + ldr r0, [r1, #0x7C] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x7C] + + /* DQM3 */ + ldr r0, [r1, #0x84] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x84] + + /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ + ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ +pad_loop: + ldr r0, [r1, #0x88] + bic r0, r0, #(1 << 22) + bic r0, r0, #(1 << 12) + bic r0, r0, #(1 << 2) + str r0, [r1, #0x88] + add r1, r1, #4 + subs r2, r2, #0x1 + bne pad_loop +.endm /* init_drive_strength */ + +/* CPLD on CS4 setup */ +.macro init_cs4 + ldr r0, =WEIM_BASE + ldr r1, =0x0000D843 + str r1, [r0, #0x40] + ldr r1, =0x22252521 + str r1, [r0, #0x44] + ldr r1, =0x22220A00 + str r1, [r0, #0x48] +.endm /* init_cs4 */ + +.globl lowlevel_init +lowlevel_init: + + /* Redboot initializes very early AIPS, what for? + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF */ + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_drive_strength + + init_cs4 + + /* Image Processing Unit: */ + /* Too early to switch display on? */ + REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ + /* Clock Control Module: */ + REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ + + /* PBC CPLD on CS4 */ + mov r1, #CS4_BASE + ldrh r1, [r1, #0x2] + /* Is 27MHz switch set? */ + ands r1, r1, #0x16 + + /* 532-133-66.5 */ + ldr r0, =CCM_BASE + ldr r1, =0xFF871D58 + /* PDR0 */ + str r1, [r0, #0x4] + ldreq r1, MPCTL_PARAM_532 + ldrne r1, MPCTL_PARAM_532_27 + /* MPCTL */ + str r1, [r0, #0x10] + + /* Set UPLL=240MHz, USB=60MHz */ + ldr r1, =0x49FCFE7F + /* PDR1 */ + str r1, [r0, #0x8] + ldreq r1, UPCTL_PARAM_240 + ldrne r1, UPCTL_PARAM_240_27 + /* UPCTL */ + str r1, [r0, #0x14] + /* default CLKO to 1/8 of the ARM core */ + mov r1, #0x000002C0 + add r1, r1, #0x00000006 + /* COSR */ + str r1, [r0, #0x1c] + + /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */ +/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ + + /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ +/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ + /* Default: 1, 4, 12, 1 */ + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ + REG 0xB8001010, 0x00000004 + REG 0xB8001004, 0x006ac73a + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x80000033, 0xda + REG8 0x81000000, 0xff + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + + mov pc, lr + +MPCTL_PARAM_532: + .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) +MPCTL_PARAM_532_27: + .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) +UPCTL_PARAM_240: + .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) +UPCTL_PARAM_240_27: + .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/mx31ads/mx31ads.c b/board/mx31ads/mx31ads.c new file mode 100644 index 000000000..dd0e150e9 --- /dev/null +++ b/board/mx31ads/mx31ads.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init (void) +{ + int i; + + /* CS0: Nor Flash */ + /* + * CS0L and CS0A values are from the RedBoot sources by Freescale + * and are also equal to those used by Sascha Hauer for the Phytec + * i.MX31 board. CS0U is just a slightly optimized hardware default: + * the only non-zero field "Wait State Control" is set to half the + * default value. + */ + __REG(CSCR_U(0)) = 0x00000f00; + __REG(CSCR_L(0)) = 0x10000D03; + __REG(CSCR_A(0)) = 0x00720900; + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_RTS1__UART1_CTS_B); + + /* SPI2 */ + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SPI_RDY); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0); + mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS1); + + /* start SPI2 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); + + /* PBC setup */ + /* Enable UART transceivers also reset the Ethernet/external UART */ + readw(CS4_BASE + 4); + + writew(0x8023, CS4_BASE + 4); + + /* RedBoot also has an empty loop with 100000 iterations here - + * clock doesn't run yet */ + for (i = 0; i < 100000; i++) + ; + + /* Clear the reset, toggle the LEDs */ + writew(0xDF, CS4_BASE + 6); + + /* clock still doesn't run */ + for (i = 0; i < 100000; i++) + ; + + /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ + readb(CS4_BASE + 8); + readb(CS4_BASE + 7); + readb(CS4_BASE + 8); + readb(CS4_BASE + 7); + + gd->bd->bi_arch_number = MACH_TYPE_MX31ADS; /* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ + + return 0; +} + +int checkboard (void) +{ + printf("Board: MX31ADS\n"); + return 0; +} diff --git a/board/mx31ads/u-boot.lds b/board/mx31ads/u-boot.lds new file mode 100644 index 000000000..49713d454 --- /dev/null +++ b/board/mx31ads/u-boot.lds @@ -0,0 +1,70 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/arm1136/start.o (.text) + board/mx31ads/libmx31ads.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c index 48c185082..ac0022e7b 100644 --- a/board/siemens/common/fpga.c +++ b/board/siemens/common/fpga.c @@ -160,7 +160,7 @@ static int fpga_load (fpga_t* fpga, ulong addr, int checkall) data = (uchar*)image_get_data (hdr); len = image_get_data_size (hdr); - verify = getenv_verify (); + verify = getenv_yesno ("verify"); if (verify) { if (!image_check_dcrc (hdr)) { strcpy (msg, "Bad Image Data CRC"); diff --git a/common/cmd_autoscript.c b/common/cmd_autoscript.c index 1a37b90d7..932f6388f 100644 --- a/common/cmd_autoscript.c +++ b/common/cmd_autoscript.c @@ -65,7 +65,7 @@ autoscript (ulong addr, const char *fit_uname) size_t fit_len; #endif - verify = getenv_verify (); + verify = getenv_yesno ("verify"); switch (genimg_get_format ((void *)addr)) { case IMAGE_FORMAT_LEGACY: diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 3a0c83d2d..44f6b9f6e 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -100,7 +100,6 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #endif #if defined(CONFIG_ARTOS) && defined(CONFIG_PPC) -extern uchar (*env_get_char)(int); /* Returns a character from the environment */ static boot_os_fn do_bootm_artos; #endif @@ -133,8 +132,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) struct lmb lmb; memset ((void *)&images, 0, sizeof (images)); - images.verify = getenv_verify(); - images.autostart = getenv_autostart(); + images.verify = getenv_yesno ("verify"); + images.autostart = getenv_yesno ("autostart"); images.lmb = &lmb; lmb_init(&lmb); diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index 7916fc197..2753389ea 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -51,7 +51,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) size_t fit_len; #endif - verify = getenv_verify (); + verify = getenv_yesno ("verify"); if (argc > 1) { addr = simple_strtoul(argv[1], NULL, 16); diff --git a/common/image.c b/common/image.c index d218f2f88..83e359312 100644 --- a/common/image.c +++ b/common/image.c @@ -155,7 +155,7 @@ static table_entry_t uimage_comp[] = { { -1, "", "", }, }; -unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); +uint32_t crc32 (uint32_t, const unsigned char *, uint); static void genimg_print_size (uint32_t size); #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC) static void genimg_print_time (time_t timestamp); @@ -316,19 +316,27 @@ static void image_print_type (image_header_t *hdr) } /** - * __image_print_contents - prints out the contents of the legacy format image + * image_print_contents - prints out the contents of the legacy format image * @hdr: pointer to the legacy format image header * @p: pointer to prefix string * - * __image_print_contents() formats a multi line legacy image contents description. + * image_print_contents() formats a multi line legacy image contents description. * The routine prints out all header fields followed by the size/offset data * for MULTI/SCRIPT images. * * returns: * no returned results */ -static void __image_print_contents (image_header_t *hdr, const char *p) +void image_print_contents (image_header_t *hdr) { + const char *p; + +#ifdef USE_HOSTCC + p = ""; +#else + p = " "; +#endif + printf ("%sImage Name: %.*s\n", p, IH_NMLEN, image_get_name (hdr)); #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC) printf ("%sCreated: ", p); @@ -366,15 +374,6 @@ static void __image_print_contents (image_header_t *hdr, const char *p) } } -inline void image_print_contents (image_header_t *hdr) -{ - __image_print_contents (hdr, " "); -} - -inline void image_print_contents_noindent (image_header_t *hdr) -{ - __image_print_contents (hdr, ""); -} #ifndef USE_HOSTCC /** @@ -444,15 +443,9 @@ static image_header_t* image_get_ramdisk (ulong rd_addr, uint8_t arch, /* Shared dual-format routines */ /*****************************************************************************/ #ifndef USE_HOSTCC -int getenv_verify (void) -{ - char *s = getenv ("verify"); - return (s && (*s == 'n')) ? 0 : 1; -} - -int getenv_autostart (void) +int getenv_yesno (char *var) { - char *s = getenv ("autostart"); + char *s = getenv (var); return (s && (*s == 'n')) ? 0 : 1; } @@ -1265,18 +1258,18 @@ static void fit_get_debug (const void *fit, int noffset, } /** - * __fit_print_contents - prints out the contents of the FIT format image + * fit_print_contents - prints out the contents of the FIT format image * @fit: pointer to the FIT format image header * @p: pointer to prefix string * - * __fit_print_contents() formats a multi line FIT image contents description. + * fit_print_contents() formats a multi line FIT image contents description. * The routine prints out FIT image properties (root node level) follwed by * the details of each component image. * * returns: * no returned results */ -static void __fit_print_contents (const void *fit, const char *p) +void fit_print_contents (const void *fit) { char *desc; char *uname; @@ -1286,10 +1279,17 @@ static void __fit_print_contents (const void *fit, const char *p) int ndepth; int count = 0; int ret; + const char *p; #if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC) time_t timestamp; #endif +#ifdef USE_HOSTCC + p = ""; +#else + p = " "; +#endif + /* Root node properties */ ret = fit_get_desc (fit, 0, &desc); printf ("%sFIT description: ", p); @@ -1361,16 +1361,6 @@ static void __fit_print_contents (const void *fit, const char *p) } } -inline void fit_print_contents (const void *fit) -{ - __fit_print_contents (fit, " "); -} - -inline void fit_print_contents_noindent (const void *fit) -{ - __fit_print_contents (fit, ""); -} - /** * fit_image_print - prints out the FIT component image details * @fit: pointer to the FIT format image header diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c index 8bb8b4571..6c670f0b7 100644 --- a/cpu/arm926ejs/davinci/timer.c +++ b/cpu/arm926ejs/davinci/timer.c @@ -42,9 +42,9 @@ typedef volatile struct { u_int32_t pid12; - u_int32_t emumgt_clksped; - u_int32_t gpint_en; - u_int32_t gpdir_dat; + u_int32_t emumgt; + u_int32_t na1; + u_int32_t na2; u_int32_t tim12; u_int32_t tim34; u_int32_t prd12; @@ -52,21 +52,12 @@ typedef volatile struct { u_int32_t tcr; u_int32_t tgcr; u_int32_t wdtcr; - u_int32_t tlgc; - u_int32_t tlmr; } davinci_timer; davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE; #define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ) -#define READ_TIMER timer->tim34 - -/* - * Timer runs with CFG_HZ_CLOCK, currently 27MHz. To avoid wrap - * around of timestamp already after min ~159s, divide it, e.g. by 16. - * timestamp will then wrap around all min ~42min - */ -#define DIV(x) ((x) >> 4) +#define TIM_CLK_DIV 16 static ulong timestamp; static ulong lastinc; @@ -76,63 +67,51 @@ int timer_init(void) /* We are using timer34 in unchained 32-bit mode, full speed */ timer->tcr = 0x0; timer->tgcr = 0x0; - timer->tgcr = 0x06; + timer->tgcr = 0x06 | ((TIM_CLK_DIV - 1) << 8); timer->tim34 = 0x0; timer->prd34 = TIMER_LOAD_VAL; lastinc = 0; - timer->tcr = 0x80 << 16; timestamp = 0; + timer->tcr = 2 << 22; return(0); } void reset_timer(void) { - reset_timer_masked(); -} - -ulong get_timer(ulong base) -{ - return(get_timer_masked() - base); -} - -void set_timer(ulong t) -{ - timestamp = t; -} - -void udelay(unsigned long usec) -{ - udelay_masked(usec); -} - -void reset_timer_masked(void) -{ - lastinc = DIV(READ_TIMER); + timer->tcr = 0x0; + timer->tim34 = 0; + lastinc = 0; timestamp = 0; + timer->tcr = 2 << 22; } -ulong get_timer_raw(void) +static ulong get_timer_raw(void) { - ulong now = DIV(READ_TIMER); + ulong now = timer->tim34; if (now >= lastinc) { /* normal mode */ timestamp += now - lastinc; } else { /* overflow ... */ - timestamp += now + DIV(TIMER_LOAD_VAL) - lastinc; + timestamp += now + TIMER_LOAD_VAL - lastinc; } lastinc = now; return timestamp; } -ulong get_timer_masked(void) +ulong get_timer(ulong base) +{ + return((get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base); +} + +void set_timer(ulong t) { - return(get_timer_raw() / DIV(TIMER_LOAD_VAL)); + timestamp = t; } -void udelay_masked(unsigned long usec) +void udelay(unsigned long usec) { ulong tmo; ulong endtime; @@ -140,7 +119,7 @@ void udelay_masked(unsigned long usec) tmo = CFG_HZ_CLOCK / 1000; tmo *= usec; - tmo /= 1000; + tmo /= (1000 * TIM_CLK_DIV); endtime = get_timer_raw() + tmo; @@ -165,8 +144,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - ulong tbclk; - - tbclk = CFG_HZ; - return(tbclk); + return CFG_HZ; } diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index fdf9d35e2..309eb30e8 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -172,11 +172,8 @@ boot_warm: /* time t 5 */ /* there and deflate the flash size back to minimal size */ /*------------------------------------------------------------*/ bl map_flash_by_law1 - - GET_GOT /* initialize GOT access */ - lwz r4, GOT(_start) - addi r4, r4, -EXC_OFF_SYS_RESET - + lis r4, (CFG_MONITOR_BASE)@h + ori r4, r4, (CFG_MONITOR_BASE)@l addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET mtlr r5 blr @@ -875,8 +872,8 @@ relocate_code: mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ - lwz r4, GOT(_start) - addi r4, r4, -EXC_OFF_SYS_RESET + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index dcd881737..74b210cd1 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -116,22 +116,21 @@ int checkcpu (void) get_sys_info(&sysinfo); puts("Clock Configuration:\n"); - printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000); - printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000); - + printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000)); + printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000)); ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9; switch (ddr_ratio) { case 0x0: printf(" DDR:%4lu MHz (%lu MT/s data rate), ", - sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000); + DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; case 0x7: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ", - sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000); + DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000)); break; default: printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ", - sysinfo.freqDDRBus / 2000000, sysinfo.freqDDRBus / 1000000); + DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000)); break; } @@ -154,7 +153,7 @@ int checkcpu (void) clkdiv *= 2; #endif printf("LBC:%4lu MHz\n", - sysinfo.freqSystemBus / 1000000 / clkdiv); + DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv); } else { printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bde6d1e96..bb87740ba 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -52,7 +52,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) if (*reg == id) { fdt_setprop_string(blob, off, "status", "okay"); } else { - u32 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; + u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; val = cpu_to_fdt32(val); fdt_setprop_string(blob, off, "status", "disabled"); diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index d90d39767..699441b46 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -65,6 +65,9 @@ void get_sys_info (sys_info_t * sysInfo) int get_clocks (void) { sys_info_t sys_info; +#ifdef CONFIG_MPC8544 + volatile ccsr_gur_t *gur = (void *) CFG_MPC85xx_GUTS_ADDR; +#endif #if defined(CONFIG_CPM2) volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CFG_MPC85xx_CPM_ADDR; uint sccr, dfbrg; @@ -78,8 +81,34 @@ int get_clocks (void) gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; gd->mem_clk = sys_info.freqDDRBus; + + /* + * The base clock for I2C depends on the actual SOC. Unfortunately, + * there is no pattern that can be used to determine the frequency, so + * the only choice is to look up the actual SOC number and use the value + * for that SOC. This information is taken from application note + * AN2919. + */ +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) gd->i2c1_clk = sys_info.freqSystemBus; - gd->i2c2_clk = sys_info.freqSystemBus; +#elif defined(CONFIG_MPC8544) + /* + * On the 8544, the I2C clock is the same as the SEC clock. This can be + * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See + * 4.4.3.3 of the 8544 RM. Note that this might actually work for all + * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the + * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. + */ + if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) + gd->i2c1_clk = sys_info.freqSystemBus / 3; + else + gd->i2c1_clk = sys_info.freqSystemBus / 2; +#else + /* Most 85xx SOCs use CCB/2, so this is the default behavior. */ + gd->i2c1_clk = sys_info.freqSystemBus / 2; +#endif + gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S index 5124dec77..ceb3ec0d3 100644 --- a/cpu/ppc4xx/cache.S +++ b/cpu/ppc4xx/cache.S @@ -166,9 +166,11 @@ _GLOBAL(invalidate_dcache) #ifdef CONFIG_440 .globl dcache_disable + .globl dcache_enable .globl icache_disable .globl icache_enable dcache_disable: +dcache_enable: icache_disable: icache_enable: blr diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index fa799529d..05b42fec9 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -165,6 +165,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) } } + sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; + sysInfo->freqUART = sysInfo->freqProcessor; } diff --git a/doc/README.mips b/doc/README.mips new file mode 100644 index 000000000..85dea400c --- /dev/null +++ b/doc/README.mips @@ -0,0 +1,57 @@ + +Notes for the MIPS architecture port of U-Boot + +Toolchains +---------- + + http://www.denx.de/wiki/DULG/ELDK + ELDK < DULG < DENX + + http://www.emdebian.org/crosstools.html + Embedded Debian -- Cross-development toolchains + + http://buildroot.uclibc.org/ + Buildroot + +Known Issues +------------ + + * Little endian build problem + + If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all + objects will be generated in big-endian format. + + * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c + + Cache will be disabled before entering the loaded ELF image without + writing back and invalidating cache lines. This leads to cache + incoherency in most cases, unless the code gets loaded after U-Boot + re-initializes the cache. The more common uImage 'bootm' command does + not suffer this problem. + + [workaround] To avoid this cache incoherency, + 1) insert flush_cache(all) before calling dcache_disable(), or + 2) fix dcache_disable() to do both flushing and disabling cache. + + * Note that Linux users need to kill dcache_disable() in do_bootelf_exec() + or override do_bootelf_exec() not to disable I-/D-caches, because most + Linux/MIPS ports don't re-enable caches after entering kernel_entry. + +TODOs +----- + + * Probe CPU types, I-/D-cache and TLB size etc. automatically + + * Secondary cache support missing + + * Centralize the link directive files + + * Initialize TLB entries redardless of their use + + * R2000/R3000 class parts are not supported + + * Limited testing across different MIPS variants + + * Due to cache initialization issues, the DRAM on board must be + initialized in board specific assembler language before the cache init + code is run -- that is, initialize the DRAM in lowlevel_init(). diff --git a/drivers/net/ax88796.h b/drivers/net/ax88796.h index 069ae80fa..0e6f8a201 100644 --- a/drivers/net/ax88796.h +++ b/drivers/net/ax88796.h @@ -23,24 +23,24 @@ #ifndef __DRIVERS_AX88796L_H__ #define __DRIVERS_AX88796L_H__ -#define DP_DATA (0x10 << 1) -#define START_PG 0x40 /* First page of TX buffer */ -#define START_PG2 0x48 -#define STOP_PG 0x80 /* Last page +1 of RX ring */ -#define TX_PAGES 12 -#define RX_START (START_PG+TX_PAGES) -#define RX_END STOP_PG +#define DP_DATA (0x10 << 1) +#define START_PG 0x40 /* First page of TX buffer */ +#define START_PG2 0x48 +#define STOP_PG 0x80 /* Last page +1 of RX ring */ +#define TX_PAGES 12 +#define RX_START (START_PG+TX_PAGES) +#define RX_END STOP_PG #define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE -#define AX88796L_BYTE_ACCESS 0x00001000 -#define AX88796L_OFFSET 0x00000400 -#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ +#define AX88796L_BYTE_ACCESS 0x00001000 +#define AX88796L_OFFSET 0x00000400 +#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ AX88796L_BYTE_ACCESS + AX88796L_OFFSET -#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) -#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) +#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) +#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) #define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) -#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) +#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) #define EECS_HIGH (AX88796L_MEMR |= 0x10) #define EECS_LOW (AX88796L_MEMR &= 0xef) @@ -53,7 +53,7 @@ #define PAGE0_SET (AX88796L_CR &= 0x3f) #define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) -#define BIT_DUMMY 0 +#define BIT_DUMMY 0 #define MAC_EEP_READ 1 #define MAC_EEP_WRITE 2 #define MAC_EEP_ERACE 3 @@ -62,20 +62,20 @@ /* R7780MP Specific code */ #if defined(CONFIG_R7780MP) -#define ISA_OFFSET 0x1400 -#define DP_IN(_b_, _o_, _d_) (_d_) = \ +#define ISA_OFFSET 0x1400 +#define DP_IN(_b_, _o_, _d_) (_d_) = \ *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) #define DP_OUT(_b_, _o_, _d_) \ *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) -#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) #else /* Please change for your target boards */ -#define ISA_OFFSET 0x0000 -#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) -#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) -#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) +#define ISA_OFFSET 0x0000 +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) +#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) +#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) #endif diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c index 99baeea3e..d09da7829 100644 --- a/drivers/net/ne2000.c +++ b/drivers/net/ne2000.c @@ -1,5 +1,5 @@ /* -Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> +Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world @@ -57,13 +57,13 @@ and are covered by the appropriate copyright disclaimers included herein. ========================================================================== #####DESCRIPTIONBEGIN#### -Author(s): gthomas -Contributors: gthomas, jskov, rsandifo -Date: 2001-06-13 +Author(s): gthomas +Contributors: gthomas, jskov, rsandifo +Date: 2001-06-13 Purpose: Description: -FIXME: Will fail if pinged with large packets (1520 bytes) +FIXME: Will fail if pinged with large packets (1520 bytes) Add promisc config Add SNMP @@ -77,24 +77,26 @@ Add SNMP #include <net.h> #include <malloc.h> -#define mdelay(n) udelay((n)*1000) +#define mdelay(n) udelay((n)*1000) /* forward definition of function used for the uboot interface */ void uboot_push_packet_len(int len); void uboot_push_tx_done(int key, int val); /* - ------------------------------------------------------------------------ - Debugging details - - Set to perms of: - 0 disables all debug output - 1 for process debug output - 2 for added data IO output: get_reg, put_reg - 4 for packet allocation/free output - 8 for only startup status, so we can tell we're installed OK -*/ -/*#define DEBUG 0xf*/ + * Debugging details + * + * Set to perms of: + * 0 disables all debug output + * 1 for process debug output + * 2 for added data IO output: get_reg, put_reg + * 4 for packet allocation/free output + * 8 for only startup status, so we can tell we're installed OK + */ +#if 0 +#define DEBUG 0xf +#else #define DEBUG 0 +#endif #if DEBUG & 1 #define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) @@ -128,27 +130,28 @@ dp83902a_init(void) DEBUG_FUNCTION(); base = dp->base; - if (!base) return false; /* No device found */ + if (!base) + return false; /* No device found */ DEBUG_LINE(); #if defined(NE2000_BASIC_INIT) /* AX88796L doesn't need */ /* Prepare ESA */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ /* Use the address from the serial EEPROM */ for (i = 0; i < 6; i++) DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", - "eeprom", - dp->esa[0], - dp->esa[1], - dp->esa[2], - dp->esa[3], - dp->esa[4], - dp->esa[5] ); + "eeprom", + dp->esa[0], + dp->esa[1], + dp->esa[2], + dp->esa[3], + dp->esa[4], + dp->esa[5] ); #endif /* NE2000_BASIC_INIT */ return true; @@ -162,7 +165,7 @@ dp83902a_stop(void) DEBUG_FUNCTION(); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ @@ -170,11 +173,11 @@ dp83902a_stop(void) } /* - This function is called to "start up" the interface. It may be called - multiple times, even when the hardware is already running. It will be - called whenever something "hardware oriented" changes and should leave - the hardware ready to send/receive packets. -*/ + * This function is called to "start up" the interface. It may be called + * multiple times, even when the hardware is already running. It will be + * called whenever something "hardware oriented" changes and should leave + * the hardware ready to send/receive packets. + */ static void dp83902a_start(u8 * enaddr) { @@ -196,16 +199,16 @@ dp83902a_start(u8 * enaddr) dp->tx_started = false; dp->running = true; DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ - DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */ + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */ DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ - dp->rx_next = dp->rx_buf_start-1; + dp->rx_next = dp->rx_buf_start - 1; dp->running = true; DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ - DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ + DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ dp->running = true; - for (i = 0; i < ETHER_ADDR_LEN; i++) { + for (i = 0; i < ETHER_ADDR_LEN; i++) { /* FIXME */ /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + * 0x1400)) = enaddr[i];*/ @@ -214,15 +217,15 @@ dp83902a_start(u8 * enaddr) /* Enable and start device */ DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ - DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ + DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ dp->running = true; } /* - This routine is called to start the transmitter. It is split out from the - data handling routine so it may be called either when data becomes first - available or when an Tx interrupt occurs -*/ + * This routine is called to start the transmitter. It is split out from the + * data handling routine so it may be called either when data becomes first + * available or when an Tx interrupt occurs + */ static void dp83902a_start_xmit(int start_page, int len) @@ -249,9 +252,9 @@ dp83902a_start_xmit(int start_page, int len) } /* - This routine is called to send data to the hardware. It is known a-priori - that there is free buffer space (dp->tx_next). -*/ + * This routine is called to send data to the hardware. It is known a-priori + * that there is free buffer space (dp->tx_next). + */ static void dp83902a_send(u8 *data, int total_len, u32 key) { @@ -265,7 +268,8 @@ dp83902a_send(u8 *data, int total_len, u32 key) DEBUG_FUNCTION(); len = pkt_len = total_len; - if (pkt_len < IEEE_8023_MIN_FRAME) pkt_len = IEEE_8023_MIN_FRAME; + if (pkt_len < IEEE_8023_MIN_FRAME) + pkt_len = IEEE_8023_MIN_FRAME; start_page = dp->tx_next; if (dp->tx_next == dp->tx_buf1) { @@ -284,17 +288,19 @@ dp83902a_send(u8 *data, int total_len, u32 key) printf("TX prep page %d len %d\n", start_page, pkt_len); #endif - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ { - /* Dummy read. The manual sez something slightly different, */ - /* but the code is extended a bit to do what Hitachi's monitor */ - /* does (i.e., also read data). */ + /* + * Dummy read. The manual sez something slightly different, + * but the code is extended a bit to do what Hitachi's monitor + * does (i.e., also read data). + */ u16 tmp; int len = 1; - DP_OUT(base, DP_RSAL, 0x100-len); - DP_OUT(base, DP_RSAH, (start_page-1) & 0xff); + DP_OUT(base, DP_RSAL, 0x100 - len); + DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff); DP_OUT(base, DP_RBCL, len); DP_OUT(base, DP_RBCH, 0); DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); @@ -302,8 +308,10 @@ dp83902a_send(u8 *data, int total_len, u32 key) } #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA - /* Stall for a bit before continuing to work around random data */ - /* corruption problems on some platforms. */ + /* + * Stall for a bit before continuing to work around random data + * corruption problems on some platforms. + */ CYGACC_CALL_IF_DELAY_US(1); #endif @@ -336,16 +344,18 @@ dp83902a_send(u8 *data, int total_len, u32 key) printf(" + %d bytes of padding\n", pkt_len - total_len); #endif /* Padding to 802.3 length was required */ - for (i = total_len; i < pkt_len;) { + for (i = total_len; i < pkt_len;) { i++; DP_OUT_DATA(dp->data, 0); } } #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA - /* After last data write, delay for a bit before accessing the */ - /* device again, or we may get random data corruption in the last */ - /* datum (on some platforms). */ + /* + * After last data write, delay for a bit before accessing the + * device again, or we may get random data corruption in the last + * datum (on some platforms). + */ CYGACC_CALL_IF_DELAY_US(1); #endif @@ -360,21 +370,21 @@ dp83902a_send(u8 *data, int total_len, u32 key) /* Start transmit if not already going */ if (!dp->tx_started) { if (start_page == dp->tx1) { - dp->tx_int = 1; /* Expecting interrupt from BUF1 */ + dp->tx_int = 1; /* Expecting interrupt from BUF1 */ } else { - dp->tx_int = 2; /* Expecting interrupt from BUF2 */ + dp->tx_int = 2; /* Expecting interrupt from BUF2 */ } dp83902a_start_xmit(start_page, pkt_len); } } /* - This function is called when a packet has been received. It's job is - to prepare to unload the packet from the hardware. Once the length of - the packet is known, the upper layer of the driver can be told. When - the upper layer is ready to unload the packet, the internal function - 'dp83902a_recv' will be called to actually fetch it from the hardware. -*/ + * This function is called when a packet has been received. It's job is + * to prepare to unload the packet from the hardware. Once the length of + * the packet is known, the upper layer of the driver can be told. When + * the upper layer is ready to unload the packet, the internal function + * 'dp83902a_recv' will be called to actually fetch it from the hardware. + */ static void dp83902a_RxEvent(void) { @@ -407,9 +417,9 @@ dp83902a_RxEvent(void) DP_OUT(base, DP_RSAH, pkt); if (dp->rx_next == pkt) { if (cur == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); else - DP_OUT(base, DP_BNDRY, cur-1); /* Update pointer */ + DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */ return; } dp->rx_next = pkt; @@ -420,13 +430,13 @@ dp83902a_RxEvent(void) #endif /* read header (get data size)*/ - for (i = 0; i < sizeof(rcv_hdr);) { + for (i = 0; i < sizeof(rcv_hdr);) { DP_IN_DATA(dp->data, rcv_hdr[i++]); } #if DEBUG & 5 printf("rx hdr %02x %02x %02x %02x\n", - rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); + rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]); #endif len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); @@ -434,19 +444,19 @@ dp83902a_RxEvent(void) uboot_push_packet_len(len); if (rcv_hdr[1] == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); + DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); else - DP_OUT(base, DP_BNDRY, rcv_hdr[1]-1); /* Update pointer */ + DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */ } } /* - This function is called as a result of the "eth_drv_recv()" call above. - It's job is to actually fetch data for a packet from the hardware once - memory buffers have been allocated for the packet. Note that the buffers - may come in pieces, using a scatter-gather list. This allows for more - efficient processing in the upper layers of the stack. -*/ + * This function is called as a result of the "eth_drv_recv()" call above. + * It's job is to actually fetch data for a packet from the hardware once + * memory buffers have been allocated for the packet. Note that the buffers + * may come in pieces, using a scatter-gather list. This allows for more + * efficient processing in the upper layers of the stack. + */ static void dp83902a_recv(u8 *data, int len) { @@ -478,7 +488,7 @@ dp83902a_recv(u8 *data, int len) #endif saved = false; - for (i = 0; i < 1; i++) { + for (i = 0; i < 1; i++) { if (data) { mlen = len; #if DEBUG & 4 @@ -545,8 +555,10 @@ dp83902a_TxEvent(void) uboot_push_tx_done(key, 0); } -/* Read the tally counters to clear them. Called in response to a CNT */ -/* interrupt. */ +/* + * Read the tally counters to clear them. Called in response to a CNT + * interrupt. + */ static void dp83902a_ClearCounters(void) { @@ -560,8 +572,10 @@ dp83902a_ClearCounters(void) DP_OUT(base, DP_ISR, DP_ISR_CNT); } -/* Deal with an overflow condition. This code follows the procedure set */ -/* out in section 7.0 of the datasheet. */ +/* + * Deal with an overflow condition. This code follows the procedure set + * out in section 7.0 of the datasheet. + */ static void dp83902a_Overflow(void) { @@ -581,9 +595,11 @@ dp83902a_Overflow(void) DP_OUT(base, DP_TCR, DP_TCR_LOCAL); DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); - /* Read in as many packets as we can and acknowledge any and receive */ - /* interrupts. Since the buffer has overflowed, a receive event of */ - /* some kind will have occured. */ + /* + * Read in as many packets as we can and acknowledge any and receive + * interrupts. Since the buffer has overflowed, a receive event of + * some kind will have occured. + */ dp83902a_RxEvent(); DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); @@ -591,8 +607,10 @@ dp83902a_Overflow(void) DP_OUT(base, DP_ISR, DP_ISR_OFLW); DP_OUT(base, DP_TCR, DP_TCR_NORMAL); - /* If a transmit command was issued, but no transmit event has occured, */ - /* restart it here. */ + /* + * If a transmit command was issued, but no transmit event has occured, + * restart it here. + */ DP_IN(base, DP_ISR, isr); if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); @@ -609,25 +627,33 @@ dp83902a_poll(void) DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); DP_IN(base, DP_ISR, isr); while (0 != isr) { - /* The CNT interrupt triggers when the MSB of one of the error */ - /* counters is set. We don't much care about these counters, but */ - /* we should read their values to reset them. */ + /* + * The CNT interrupt triggers when the MSB of one of the error + * counters is set. We don't much care about these counters, but + * we should read their values to reset them. + */ if (isr & DP_ISR_CNT) { dp83902a_ClearCounters(); } - /* Check for overflow. It's a special case, since there's a */ - /* particular procedure that must be followed to get back into */ - /* a running state.a */ + /* + * Check for overflow. It's a special case, since there's a + * particular procedure that must be followed to get back into + * a running state.a + */ if (isr & DP_ISR_OFLW) { dp83902a_Overflow(); } else { - /* Other kinds of interrupts can be acknowledged simply by */ - /* clearing the relevant bits of the ISR. Do that now, then */ - /* handle the interrupts we care about. */ - DP_OUT(base, DP_ISR, isr); /* Clear set bits */ + /* + * Other kinds of interrupts can be acknowledged simply by + * clearing the relevant bits of the ISR. Do that now, then + * handle the interrupts we care about. + */ + DP_OUT(base, DP_ISR, isr); /* Clear set bits */ if (!dp->running) break; /* Is this necessary? */ - /* Check for tx_started on TX event since these may happen */ - /* spuriously it seems. */ + /* + * Check for tx_started on TX event since these may happen + * spuriously it seems. + */ if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { dp83902a_TxEvent(); } @@ -658,8 +684,8 @@ typedef struct hw_info_t { #define HAS_MII 0x40 #define USE_SHMEM 0x80 /* autodetected */ -#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ -#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ +#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */ +#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */ #define MII_PHYID_REV_MASK 0xfffffff0 #define MII_PHYID_REG1 0x02 #define MII_PHYID_REG2 0x03 @@ -669,7 +695,7 @@ static hw_info_t hw_info[] = { { /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 }, { /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 }, { /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94, - DELAY_OUTPUT | HAS_IBM_MISC }, + DELAY_OUTPUT | HAS_IBM_MISC }, { /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 }, { /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 }, { /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 }, @@ -677,48 +703,48 @@ static hw_info_t hw_info[] = { { /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 }, { /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 }, { /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 }, { /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 }, { /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* IBM FME */ 0x0374, 0x00, 0x04, 0xac, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 }, { /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 }, { /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 }, { /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 }, { /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 }, { /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 }, { /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45, - HAS_MISC_REG | HAS_IBM_MISC }, + HAS_MISC_REG | HAS_IBM_MISC }, { /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 }, { /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 }, { /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 }, { /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b, - DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, + DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF }, { /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 }, { /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 }, { /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 }, @@ -744,11 +770,11 @@ u32 nic_base; static u8 *pbuf = NULL; static int pkey = -1; -static int initialized=0; +static int initialized = 0; void uboot_push_packet_len(int len) { PRINTK("pushed len = %d\n", len); - if (len>=2000) { + if (len >= 2000) { printf("NE2000: packet too big\n"); return; } @@ -779,7 +805,7 @@ int eth_init(bd_t *bd) { #ifdef CONFIG_DRIVER_NE2000_CCR { - vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; + vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR; PRINTK("CCR before is %x\n", *p); *p = CONFIG_DRIVER_NE2000_VAL; @@ -811,7 +837,7 @@ int eth_init(bd_t *bd) { return -1; dp83902a_start(dev_addr); - initialized=1; + initialized = 1; return 0; } @@ -821,7 +847,7 @@ void eth_halt() { PRINTK("### eth_halt\n"); if(initialized) dp83902a_stop(); - initialized=0; + initialized = 0; } int eth_rx() { diff --git a/drivers/net/ne2000.h b/drivers/net/ne2000.h index d324a0008..604948286 100644 --- a/drivers/net/ne2000.h +++ b/drivers/net/ne2000.h @@ -1,5 +1,5 @@ /* -Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> +Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world @@ -7,9 +7,9 @@ are GPL, so this is, of course, GPL. ========================================================================== - dev/dp83902a.h + dev/dp83902a.h - National Semiconductor DP83902a ethernet chip + National Semiconductor DP83902a ethernet chip ========================================================================== ####ECOSGPLCOPYRIGHTBEGIN#### @@ -57,9 +57,9 @@ are GPL, so this is, of course, GPL. ========================================================================== #####DESCRIPTIONBEGIN#### - Author(s): gthomas - Contributors: gthomas, jskov - Date: 2001-06-13 + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 Purpose: Description: @@ -79,17 +79,17 @@ are GPL, so this is, of course, GPL. /* Enable NE2000 basic init function */ #define NE2000_BASIC_INIT -#define DP_DATA 0x10 -#define START_PG 0x50 /* First page of TX buffer */ -#define STOP_PG 0x80 /* Last page +1 of RX ring */ +#define DP_DATA 0x10 +#define START_PG 0x50 /* First page of TX buffer */ +#define STOP_PG 0x80 /* Last page +1 of RX ring */ -#define RX_START 0x50 -#define RX_END 0x80 +#define RX_START 0x50 +#define RX_END 0x80 -#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_))) -#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_) -#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_))) -#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_) +#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_))) +#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_) +#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_))) +#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_) static void pcnet_reset_8390(void) { diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h index 1badf62bf..990d7488c 100644 --- a/drivers/net/ne2000_base.h +++ b/drivers/net/ne2000_base.h @@ -1,5 +1,5 @@ /* -Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> +Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world @@ -8,9 +8,9 @@ are GPL, so this is, of course, GPL. ========================================================================== - dev/dp83902a.h + dev/dp83902a.h - National Semiconductor DP83902a ethernet chip + National Semiconductor DP83902a ethernet chip ========================================================================== ####ECOSGPLCOPYRIGHTBEGIN#### @@ -58,9 +58,9 @@ are GPL, so this is, of course, GPL. ========================================================================== #####DESCRIPTIONBEGIN#### - Author(s): gthomas - Contributors: gthomas, jskov - Date: 2001-06-13 + Author(s): gthomas + Contributors: gthomas, jskov + Date: 2001-06-13 Purpose: Description: @@ -76,6 +76,9 @@ are GPL, so this is, of course, GPL. These can be overridden by the platform header */ +#ifndef __NE2000_BASE_H__ +#define __NE2000_BASE_H__ + #define bool int #define false 0 @@ -92,191 +95,191 @@ are GPL, so this is, of course, GPL. /* H/W infomation struct */ typedef struct hw_info_t { - u32 offset; - u8 a0, a1, a2; - u32 flags; + u32 offset; + u8 a0, a1, a2; + u32 flags; } hw_info_t; typedef struct dp83902a_priv_data { - u8* base; - u8* data; - u8* reset; - int tx_next; /* First free Tx page */ - int tx_int; /* Expecting interrupt from this buffer */ - int rx_next; /* First free Rx page */ - int tx1, tx2; /* Page numbers for Tx buffers */ - u32 tx1_key, tx2_key; /* Used to ack when packet sent */ - int tx1_len, tx2_len; - bool tx_started, running, hardwired_esa; - u8 esa[6]; - void* plf_priv; - - /* Buffer allocation */ - int tx_buf1, tx_buf2; - int rx_buf_start, rx_buf_end; + u8* base; + u8* data; + u8* reset; + int tx_next; /* First free Tx page */ + int tx_int; /* Expecting interrupt from this buffer */ + int rx_next; /* First free Rx page */ + int tx1, tx2; /* Page numbers for Tx buffers */ + u32 tx1_key, tx2_key; /* Used to ack when packet sent */ + int tx1_len, tx2_len; + bool tx_started, running, hardwired_esa; + u8 esa[6]; + void* plf_priv; + + /* Buffer allocation */ + int tx_buf1, tx_buf2; + int rx_buf_start, rx_buf_end; } dp83902a_priv_data_t; /* - ------------------------------------------------------------------------ - Some forward declarations -*/ + * Some forward declarations + */ int get_prom( u8* mac_addr); static void dp83902a_poll(void); /* ------------------------------------------------------------------------ */ /* Register offsets */ -#define DP_CR 0x00 -#define DP_CLDA0 0x01 -#define DP_PSTART 0x01 /* write */ -#define DP_CLDA1 0x02 -#define DP_PSTOP 0x02 /* write */ -#define DP_BNDRY 0x03 -#define DP_TSR 0x04 -#define DP_TPSR 0x04 /* write */ -#define DP_NCR 0x05 -#define DP_TBCL 0x05 /* write */ -#define DP_FIFO 0x06 -#define DP_TBCH 0x06 /* write */ -#define DP_ISR 0x07 -#define DP_CRDA0 0x08 -#define DP_RSAL 0x08 /* write */ -#define DP_CRDA1 0x09 -#define DP_RSAH 0x09 /* write */ -#define DP_RBCL 0x0a /* write */ -#define DP_RBCH 0x0b /* write */ -#define DP_RSR 0x0c -#define DP_RCR 0x0c /* write */ -#define DP_FER 0x0d -#define DP_TCR 0x0d /* write */ -#define DP_CER 0x0e -#define DP_DCR 0x0e /* write */ -#define DP_MISSED 0x0f -#define DP_IMR 0x0f /* write */ -#define DP_DATAPORT 0x10 /* "eprom" data port */ - -#define DP_P1_CR 0x00 -#define DP_P1_PAR0 0x01 -#define DP_P1_PAR1 0x02 -#define DP_P1_PAR2 0x03 -#define DP_P1_PAR3 0x04 -#define DP_P1_PAR4 0x05 -#define DP_P1_PAR5 0x06 -#define DP_P1_CURP 0x07 -#define DP_P1_MAR0 0x08 -#define DP_P1_MAR1 0x09 -#define DP_P1_MAR2 0x0a -#define DP_P1_MAR3 0x0b -#define DP_P1_MAR4 0x0c -#define DP_P1_MAR5 0x0d -#define DP_P1_MAR6 0x0e -#define DP_P1_MAR7 0x0f - -#define DP_P2_CR 0x00 -#define DP_P2_PSTART 0x01 -#define DP_P2_CLDA0 0x01 /* write */ -#define DP_P2_PSTOP 0x02 -#define DP_P2_CLDA1 0x02 /* write */ -#define DP_P2_RNPP 0x03 -#define DP_P2_TPSR 0x04 -#define DP_P2_LNPP 0x05 -#define DP_P2_ACH 0x06 -#define DP_P2_ACL 0x07 -#define DP_P2_RCR 0x0c -#define DP_P2_TCR 0x0d -#define DP_P2_DCR 0x0e -#define DP_P2_IMR 0x0f +#define DP_CR 0x00 +#define DP_CLDA0 0x01 +#define DP_PSTART 0x01 /* write */ +#define DP_CLDA1 0x02 +#define DP_PSTOP 0x02 /* write */ +#define DP_BNDRY 0x03 +#define DP_TSR 0x04 +#define DP_TPSR 0x04 /* write */ +#define DP_NCR 0x05 +#define DP_TBCL 0x05 /* write */ +#define DP_FIFO 0x06 +#define DP_TBCH 0x06 /* write */ +#define DP_ISR 0x07 +#define DP_CRDA0 0x08 +#define DP_RSAL 0x08 /* write */ +#define DP_CRDA1 0x09 +#define DP_RSAH 0x09 /* write */ +#define DP_RBCL 0x0a /* write */ +#define DP_RBCH 0x0b /* write */ +#define DP_RSR 0x0c +#define DP_RCR 0x0c /* write */ +#define DP_FER 0x0d +#define DP_TCR 0x0d /* write */ +#define DP_CER 0x0e +#define DP_DCR 0x0e /* write */ +#define DP_MISSED 0x0f +#define DP_IMR 0x0f /* write */ +#define DP_DATAPORT 0x10 /* "eprom" data port */ + +#define DP_P1_CR 0x00 +#define DP_P1_PAR0 0x01 +#define DP_P1_PAR1 0x02 +#define DP_P1_PAR2 0x03 +#define DP_P1_PAR3 0x04 +#define DP_P1_PAR4 0x05 +#define DP_P1_PAR5 0x06 +#define DP_P1_CURP 0x07 +#define DP_P1_MAR0 0x08 +#define DP_P1_MAR1 0x09 +#define DP_P1_MAR2 0x0a +#define DP_P1_MAR3 0x0b +#define DP_P1_MAR4 0x0c +#define DP_P1_MAR5 0x0d +#define DP_P1_MAR6 0x0e +#define DP_P1_MAR7 0x0f + +#define DP_P2_CR 0x00 +#define DP_P2_PSTART 0x01 +#define DP_P2_CLDA0 0x01 /* write */ +#define DP_P2_PSTOP 0x02 +#define DP_P2_CLDA1 0x02 /* write */ +#define DP_P2_RNPP 0x03 +#define DP_P2_TPSR 0x04 +#define DP_P2_LNPP 0x05 +#define DP_P2_ACH 0x06 +#define DP_P2_ACL 0x07 +#define DP_P2_RCR 0x0c +#define DP_P2_TCR 0x0d +#define DP_P2_DCR 0x0e +#define DP_P2_IMR 0x0f /* Command register - common to all pages */ -#define DP_CR_STOP 0x01 /* Stop: software reset */ -#define DP_CR_START 0x02 /* Start: initialize device */ -#define DP_CR_TXPKT 0x04 /* Transmit packet */ -#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ -#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ -#define DP_CR_SEND 0x18 /* Send packet */ -#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ -#define DP_CR_PAGE0 0x00 /* Page select */ -#define DP_CR_PAGE1 0x40 -#define DP_CR_PAGE2 0x80 -#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ +#define DP_CR_STOP 0x01 /* Stop: software reset */ +#define DP_CR_START 0x02 /* Start: initialize device */ +#define DP_CR_TXPKT 0x04 /* Transmit packet */ +#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ +#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ +#define DP_CR_SEND 0x18 /* Send packet */ +#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ +#define DP_CR_PAGE0 0x00 /* Page select */ +#define DP_CR_PAGE1 0x40 +#define DP_CR_PAGE2 0x80 +#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ /* Data configuration register */ -#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ -#define DP_DCR_BOS 0x02 /* 1=Little Endian */ -#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ -#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ -#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ -#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ -#define DP_DCR_FIFO_2 0x20 -#define DP_DCR_FIFO_4 0x40 -#define DP_DCR_FIFO_6 0x60 +#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ +#define DP_DCR_BOS 0x02 /* 1=Little Endian */ +#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ +#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ +#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ +#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ +#define DP_DCR_FIFO_2 0x20 +#define DP_DCR_FIFO_4 0x40 +#define DP_DCR_FIFO_6 0x60 -#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) +#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) /* Interrupt status register */ -#define DP_ISR_RxP 0x01 /* Packet received */ -#define DP_ISR_TxP 0x02 /* Packet transmitted */ -#define DP_ISR_RxE 0x04 /* Receive error */ -#define DP_ISR_TxE 0x08 /* Transmit error */ -#define DP_ISR_OFLW 0x10 /* Receive overflow */ -#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ -#define DP_ISR_RDC 0x40 /* Remote DMA complete */ -#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ +#define DP_ISR_RxP 0x01 /* Packet received */ +#define DP_ISR_TxP 0x02 /* Packet transmitted */ +#define DP_ISR_RxE 0x04 /* Receive error */ +#define DP_ISR_TxE 0x08 /* Transmit error */ +#define DP_ISR_OFLW 0x10 /* Receive overflow */ +#define DP_ISR_CNT 0x20 /* Tally counters need emptying */ +#define DP_ISR_RDC 0x40 /* Remote DMA complete */ +#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ /* Interrupt mask register */ -#define DP_IMR_RxP 0x01 /* Packet received */ -#define DP_IMR_TxP 0x02 /* Packet transmitted */ -#define DP_IMR_RxE 0x04 /* Receive error */ -#define DP_IMR_TxE 0x08 /* Transmit error */ -#define DP_IMR_OFLW 0x10 /* Receive overflow */ -#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ -#define DP_IMR_RDC 0x40 /* Remote DMA complete */ +#define DP_IMR_RxP 0x01 /* Packet received */ +#define DP_IMR_TxP 0x02 /* Packet transmitted */ +#define DP_IMR_RxE 0x04 /* Receive error */ +#define DP_IMR_TxE 0x08 /* Transmit error */ +#define DP_IMR_OFLW 0x10 /* Receive overflow */ +#define DP_IMR_CNT 0x20 /* Tall counters need emptying */ +#define DP_IMR_RDC 0x40 /* Remote DMA complete */ -#define DP_IMR_All 0x3F /* Everything but remote DMA */ +#define DP_IMR_All 0x3F /* Everything but remote DMA */ /* Receiver control register */ -#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ -#define DP_RCR_AR 0x02 /* Accept runt packets */ -#define DP_RCR_AB 0x04 /* Accept broadcast packets */ -#define DP_RCR_AM 0x08 /* Accept multicast packets */ -#define DP_RCR_PROM 0x10 /* Promiscuous mode */ -#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ +#define DP_RCR_SEP 0x01 /* Save bad(error) packets */ +#define DP_RCR_AR 0x02 /* Accept runt packets */ +#define DP_RCR_AB 0x04 /* Accept broadcast packets */ +#define DP_RCR_AM 0x08 /* Accept multicast packets */ +#define DP_RCR_PROM 0x10 /* Promiscuous mode */ +#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ /* Receiver status register */ -#define DP_RSR_RxP 0x01 /* Packet received */ -#define DP_RSR_CRC 0x02 /* CRC error */ -#define DP_RSR_FRAME 0x04 /* Framing error */ -#define DP_RSR_FO 0x08 /* FIFO overrun */ -#define DP_RSR_MISS 0x10 /* Missed packet */ -#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ -#define DP_RSR_DIS 0x40 /* Receiver disabled */ -#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ +#define DP_RSR_RxP 0x01 /* Packet received */ +#define DP_RSR_CRC 0x02 /* CRC error */ +#define DP_RSR_FRAME 0x04 /* Framing error */ +#define DP_RSR_FO 0x08 /* FIFO overrun */ +#define DP_RSR_MISS 0x10 /* Missed packet */ +#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ +#define DP_RSR_DIS 0x40 /* Receiver disabled */ +#define DP_RSR_DFR 0x80 /* Receiver processing deferred */ /* Transmitter control register */ -#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ -#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ -#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ -#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ -#define DP_TCR_OUTLOOP 0x08 /* External loopback */ -#define DP_TCR_ATD 0x10 /* Auto transmit disable */ -#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ +#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ +#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ +#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ +#define DP_TCR_INLOOP 0x04 /* Full internal loopback */ +#define DP_TCR_OUTLOOP 0x08 /* External loopback */ +#define DP_TCR_ATD 0x10 /* Auto transmit disable */ +#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ /* Transmit status register */ -#define DP_TSR_TxP 0x01 /* Packet transmitted */ -#define DP_TSR_COL 0x04 /* Collision (at least one) */ -#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ -#define DP_TSR_CRS 0x10 /* Lost carrier */ -#define DP_TSR_FU 0x20 /* FIFO underrun */ -#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ -#define DP_TSR_OWC 0x80 /* Collision outside normal window */ - -#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ -#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ +#define DP_TSR_TxP 0x01 /* Packet transmitted */ +#define DP_TSR_COL 0x04 /* Collision (at least one) */ +#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ +#define DP_TSR_CRS 0x10 /* Lost carrier */ +#define DP_TSR_FU 0x20 /* FIFO underrun */ +#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ +#define DP_TSR_OWC 0x80 /* Collision outside normal window */ + +#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ +#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ +#endif /* __NE2000_BASE_H__ */ diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 4e270c9f7..386fa50bd 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -30,7 +30,7 @@ #include <pci.h> #if 0 -#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ +#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ #endif #if PCNET_DEBUG_LEVEL > 0 @@ -70,42 +70,42 @@ /* The PCNET Rx and Tx ring descriptors. */ struct pcnet_rx_head { - u32 base; - s16 buf_length; - s16 status; - u32 msg_length; - u32 reserved; + u32 base; + s16 buf_length; + s16 status; + u32 msg_length; + u32 reserved; }; struct pcnet_tx_head { - u32 base; - s16 length; - s16 status; - u32 misc; - u32 reserved; + u32 base; + s16 length; + s16 status; + u32 misc; + u32 reserved; }; /* The PCNET 32-Bit initialization block, described in databook. */ struct pcnet_init_block { - u16 mode; - u16 tlen_rlen; - u8 phys_addr[6]; - u16 reserved; - u32 filter[2]; - /* Receive and transmit ring base, along with extra bits. */ - u32 rx_ring; - u32 tx_ring; - u32 reserved2; + u16 mode; + u16 tlen_rlen; + u8 phys_addr[6]; + u16 reserved; + u32 filter[2]; + /* Receive and transmit ring base, along with extra bits. */ + u32 rx_ring; + u32 tx_ring; + u32 reserved2; }; typedef struct pcnet_priv { - struct pcnet_rx_head rx_ring[RX_RING_SIZE]; - struct pcnet_tx_head tx_ring[TX_RING_SIZE]; - struct pcnet_init_block init_block; - /* Receive Buffer space */ - unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; - int cur_rx; - int cur_tx; + struct pcnet_rx_head rx_ring[RX_RING_SIZE]; + struct pcnet_tx_head tx_ring[TX_RING_SIZE]; + struct pcnet_init_block init_block; + /* Receive Buffer space */ + unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; + int cur_rx; + int cur_tx; } pcnet_priv_t; static pcnet_priv_t *lp; @@ -118,57 +118,121 @@ static pcnet_priv_t *lp; static u16 pcnet_read_csr (struct eth_device *dev, int index) { - outw (index, dev->iobase+PCNET_RAP); - return inw (dev->iobase+PCNET_RDP); + outw (index, dev->iobase + PCNET_RAP); + return inw (dev->iobase + PCNET_RDP); } static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase+PCNET_RAP); - outw (val, dev->iobase+PCNET_RDP); + outw (index, dev->iobase + PCNET_RAP); + outw (val, dev->iobase + PCNET_RDP); } static u16 pcnet_read_bcr (struct eth_device *dev, int index) { - outw (index, dev->iobase+PCNET_RAP); - return inw (dev->iobase+PCNET_BDP); + outw (index, dev->iobase + PCNET_RAP); + return inw (dev->iobase + PCNET_BDP); } static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase+PCNET_RAP); - outw (val, dev->iobase+PCNET_BDP); + outw (index, dev->iobase + PCNET_RAP); + outw (val, dev->iobase + PCNET_BDP); } static void pcnet_reset (struct eth_device *dev) { - inw (dev->iobase+PCNET_RESET); + inw (dev->iobase + PCNET_RESET); } static int pcnet_check (struct eth_device *dev) { - outw (88, dev->iobase+PCNET_RAP); - return (inw (dev->iobase+PCNET_RAP) == 88); + outw (88, dev->iobase + PCNET_RAP); + return (inw (dev->iobase + PCNET_RAP) == 88); } -static int pcnet_init( struct eth_device* dev, bd_t *bis); -static int pcnet_send (struct eth_device* dev, volatile void *packet, - int length); -static int pcnet_recv (struct eth_device* dev); -static void pcnet_halt (struct eth_device* dev); -static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_num); +static int pcnet_init (struct eth_device *dev, bd_t * bis); +static int pcnet_send (struct eth_device *dev, volatile void *packet, + int length); +static int pcnet_recv (struct eth_device *dev); +static void pcnet_halt (struct eth_device *dev); +static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) static struct pci_device_id supported[] = { - { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, - { } + {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, + {} }; -int pcnet_initialize(bd_t *bis) +int pcnet_initialize (bd_t * bis) { +<<<<<<< HEAD:drivers/net/pcnet.c + pci_dev_t devbusfn; + struct eth_device *dev; + u16 command, status; + int dev_nr = 0; + + PCNET_DEBUG1 ("\npcnet_initialize...\n"); + + for (dev_nr = 0;; dev_nr++) { + + /* + * Find the PCnet PCI device(s). + */ + if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { + break; + } + + /* + * Allocate and pre-fill the device structure. + */ + dev = (struct eth_device *) malloc (sizeof *dev); + dev->priv = (void *) devbusfn; + sprintf (dev->name, "pcnet#%d", dev_nr); + + /* + * Setup the PCI device. + */ + pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, + (unsigned int *) &dev->iobase); + dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); + dev->iobase &= ~0xf; + + PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); + + command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + pci_write_config_word (devbusfn, PCI_COMMAND, command); + pci_read_config_word (devbusfn, PCI_COMMAND, &status); + if ((status & command) != command) { + printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); + free (dev); + continue; + } + + pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); + + /* + * Probe the PCnet chip. + */ + if (pcnet_probe (dev, bis, dev_nr) < 0) { + free (dev); + continue; + } + + /* + * Setup device structure and register the driver. + */ + dev->init = pcnet_init; + dev->halt = pcnet_halt; + dev->send = pcnet_send; + dev->recv = pcnet_recv; + + eth_register (dev); +======= pci_dev_t devbusfn; struct eth_device* dev; u16 command, status; @@ -196,6 +260,7 @@ int pcnet_initialize(bd_t *bis) * Setup the PCI device. */ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (unsigned int *)&dev->iobase); + dev->iobase=pci_io_to_phys(devbusfn,dev->iobase); dev->iobase &= ~0xf; PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", @@ -219,308 +284,311 @@ int pcnet_initialize(bd_t *bis) if (pcnet_probe(dev, bis, dev_nr) < 0) { free(dev); continue; +>>>>>>> Fixed pcnet io_base:drivers/net/pcnet.c } - /* - * Setup device structure and register the driver. - */ - dev->init = pcnet_init; - dev->halt = pcnet_halt; - dev->send = pcnet_send; - dev->recv = pcnet_recv; - - eth_register(dev); - } - - udelay(10 * 1000); + udelay (10 * 1000); - return dev_nr; + return dev_nr; } -static int pcnet_probe(struct eth_device* dev, bd_t *bis, int dev_nr) +static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) { - int chip_version; - char *chipname; + int chip_version; + char *chipname; + #ifdef PCNET_HAS_PROM - int i; + int i; #endif - /* Reset the PCnet controller */ - pcnet_reset(dev); - - /* Check if register access is working */ - if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { - printf("%s: CSR register access check failed\n", dev->name); - return -1; - } - - /* Identify the chip */ - chip_version = pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev,89) << 16); - if ((chip_version & 0xfff) != 0x003) - return -1; - chip_version = (chip_version >> 12) & 0xffff; - switch (chip_version) { + /* Reset the PCnet controller */ + pcnet_reset (dev); + + /* Check if register access is working */ + if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { + printf ("%s: CSR register access check failed\n", dev->name); + return -1; + } + + /* Identify the chip */ + chip_version = + pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); + if ((chip_version & 0xfff) != 0x003) + return -1; + chip_version = (chip_version >> 12) & 0xffff; + switch (chip_version) { + case 0x2621: + chipname = "PCnet/PCI II 79C970A"; /* PCI */ + break; #ifdef CONFIG_PCNET_79C973 - case 0x2625: - chipname = "PCnet/FAST III 79C973"; /* PCI */ - break; + case 0x2625: + chipname = "PCnet/FAST III 79C973"; /* PCI */ + break; #endif #ifdef CONFIG_PCNET_79C975 - case 0x2627: - chipname = "PCnet/FAST III 79C975"; /* PCI */ - break; + case 0x2627: + chipname = "PCnet/FAST III 79C975"; /* PCI */ + break; #endif - default: - printf("%s: PCnet version %#x not supported\n", - dev->name, chip_version); - return -1; - } + default: + printf ("%s: PCnet version %#x not supported\n", + dev->name, chip_version); + return -1; + } - PCNET_DEBUG1("AMD %s\n", chipname); + PCNET_DEBUG1 ("AMD %s\n", chipname); #ifdef PCNET_HAS_PROM - /* - * In most chips, after a chip reset, the ethernet address is read from - * the station address PROM at the base address and programmed into the - * "Physical Address Registers" CSR12-14. - */ - for (i = 0; i < 3; i++) { - unsigned int val; - val = pcnet_read_csr(dev, i+12) & 0x0ffff; - /* There may be endianness issues here. */ - dev->enetaddr[2*i ] = val & 0x0ff; - dev->enetaddr[2*i+1] = (val >> 8) & 0x0ff; - } + /* + * In most chips, after a chip reset, the ethernet address is read from + * the station address PROM at the base address and programmed into the + * "Physical Address Registers" CSR12-14. + */ + for (i = 0; i < 3; i++) { + unsigned int val; + + val = pcnet_read_csr (dev, i + 12) & 0x0ffff; + /* There may be endianness issues here. */ + dev->enetaddr[2 * i] = val & 0x0ff; + dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; + } #endif /* PCNET_HAS_PROM */ - return 0; + return 0; } -static int pcnet_init(struct eth_device* dev, bd_t *bis) +static int pcnet_init (struct eth_device *dev, bd_t * bis) { - int i, val; - u32 addr; + int i, val; + u32 addr; - PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); + PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); - /* Switch pcnet to 32bit mode */ - pcnet_write_bcr (dev, 20, 2); + /* Switch pcnet to 32bit mode */ + pcnet_write_bcr (dev, 20, 2); #ifdef CONFIG_PN62 - /* Setup LED registers */ - val = pcnet_read_bcr (dev, 2) | 0x1000; - pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ - pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ - pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ - pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ - pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ + /* Setup LED registers */ + val = pcnet_read_bcr (dev, 2) | 0x1000; + pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ + pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ + pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ + pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ + pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ #endif - /* Set/reset autoselect bit */ - val = pcnet_read_bcr (dev, 2) & ~2; - val |= 2; - pcnet_write_bcr (dev, 2, val); - - /* Enable auto negotiate, setup, disable fd */ - val = pcnet_read_bcr(dev, 32) & ~0x98; - val |= 0x20; - pcnet_write_bcr(dev, 32, val); - - /* - * We only maintain one structure because the drivers will never - * be used concurrently. In 32bit mode the RX and TX ring entries - * must be aligned on 16-byte boundaries. - */ - if (lp == NULL) { - addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); - addr = (addr + 0xf) & ~0xf; - lp = (pcnet_priv_t *)addr; - } - - lp->init_block.mode = cpu_to_le16(0x0000); - lp->init_block.filter[0] = 0x00000000; - lp->init_block.filter[1] = 0x00000000; - - /* - * Initialize the Rx ring. - */ - lp->cur_rx = 0; - for (i = 0; i < RX_RING_SIZE; i++) { - lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); - lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); - lp->rx_ring[i].status = cpu_to_le16(0x8000); - PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", - i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length, - lp->rx_ring[i].status); - } - - /* - * Initialize the Tx ring. The Tx buffer address is filled in as - * needed, but we do need to clear the upper ownership bit. - */ - lp->cur_tx = 0; - for (i = 0; i < TX_RING_SIZE; i++) { - lp->tx_ring[i].base = 0; - lp->tx_ring[i].status = 0; - } - - /* - * Setup Init Block. - */ - PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); - - for (i = 0; i < 6; i++) { - lp->init_block.phys_addr[i] = dev->enetaddr[i]; - PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); - } - - lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | - RX_RING_LEN_BITS); - lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); - lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); - - PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", - lp->init_block.tlen_rlen, - lp->init_block.rx_ring, lp->init_block.tx_ring); - - /* - * Tell the controller where the Init Block is located. - */ - addr = PCI_TO_MEM(dev, &lp->init_block); - pcnet_write_csr(dev, 1, addr & 0xffff); - pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); - - pcnet_write_csr (dev, 4, 0x0915); - pcnet_write_csr (dev, 0, 0x0001); /* start */ - - /* Wait for Init Done bit */ - for (i = 10000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x0100) - break; - udelay(10); - } - if (i <= 0) { - printf("%s: TIMEOUT: controller init failed\n", dev->name); - pcnet_reset (dev); - return -1; - } + /* Set/reset autoselect bit */ + val = pcnet_read_bcr (dev, 2) & ~2; + val |= 2; + pcnet_write_bcr (dev, 2, val); - /* - * Finally start network controller operation. - */ - pcnet_write_csr (dev, 0, 0x0002); + /* Enable auto negotiate, setup, disable fd */ + val = pcnet_read_bcr (dev, 32) & ~0x98; + val |= 0x20; + pcnet_write_bcr (dev, 32, val); - return 0; -} + /* + * We only maintain one structure because the drivers will never + * be used concurrently. In 32bit mode the RX and TX ring entries + * must be aligned on 16-byte boundaries. + */ + if (lp == NULL) { + addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); + addr = (addr + 0xf) & ~0xf; + lp = (pcnet_priv_t *) addr; + } -static int pcnet_send(struct eth_device* dev, volatile void *packet, int pkt_len) -{ - int i, status; - struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + lp->init_block.mode = cpu_to_le16 (0x0000); + lp->init_block.filter[0] = 0x00000000; + lp->init_block.filter[1] = 0x00000000; - PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); + /* + * Initialize the Rx ring. + */ + lp->cur_rx = 0; + for (i = 0; i < RX_RING_SIZE; i++) { + lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); + lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); + lp->rx_ring[i].status = cpu_to_le16 (0x8000); + PCNET_DEBUG1 + ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, + lp->rx_ring[i].base, lp->rx_ring[i].buf_length, + lp->rx_ring[i].status); + } - /* Wait for completion by testing the OWN bit */ - for (i = 1000; i > 0; i--) { - status = le16_to_cpu(entry->status); - if ((status & 0x8000) == 0) - break; - udelay(100); - PCNET_DEBUG2("."); - } - if (i <= 0) { - printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", - dev->name, lp->cur_tx, status); - pkt_len = 0; - goto failure; - } - - /* - * Setup Tx ring. Caution: the write order is important here, - * set the status with the "ownership" bits last. - */ - status = 0x8300; - entry->length = le16_to_cpu(-pkt_len); - entry->misc = 0x00000000; - entry->base = PCI_TO_MEM_LE(dev, packet); - entry->status = le16_to_cpu(status); - - /* Trigger an immediate send poll. */ - pcnet_write_csr (dev, 0, 0x0008); - - failure: - if (++lp->cur_tx >= TX_RING_SIZE) + /* + * Initialize the Tx ring. The Tx buffer address is filled in as + * needed, but we do need to clear the upper ownership bit. + */ lp->cur_tx = 0; + for (i = 0; i < TX_RING_SIZE; i++) { + lp->tx_ring[i].base = 0; + lp->tx_ring[i].status = 0; + } - PCNET_DEBUG2("done\n"); - return pkt_len; -} + /* + * Setup Init Block. + */ + PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); -static int pcnet_recv(struct eth_device* dev) -{ - struct pcnet_rx_head *entry; - int pkt_len = 0; - u16 status; + for (i = 0; i < 6; i++) { + lp->init_block.phys_addr[i] = dev->enetaddr[i]; + PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); + } + + lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | + RX_RING_LEN_BITS); + lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); + lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); + + PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", + lp->init_block.tlen_rlen, + lp->init_block.rx_ring, lp->init_block.tx_ring); - while (1) { - entry = &lp->rx_ring[lp->cur_rx]; /* - * If we own the next entry, it's a new packet. Send it up. + * Tell the controller where the Init Block is located. */ - if (((status = le16_to_cpu(entry->status)) & 0x8000) != 0) { - break; + addr = PCI_TO_MEM (dev, &lp->init_block); + pcnet_write_csr (dev, 1, addr & 0xffff); + pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); + + pcnet_write_csr (dev, 4, 0x0915); + pcnet_write_csr (dev, 0, 0x0001); /* start */ + + /* Wait for Init Done bit */ + for (i = 10000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x0100) + break; + udelay (10); } - status >>= 8; - - if (status != 0x03) { /* There was an error. */ - - printf("%s: Rx%d", dev->name, lp->cur_rx); - PCNET_DEBUG1(" (status=0x%x)", status); - if (status & 0x20) printf(" Frame"); - if (status & 0x10) printf(" Overflow"); - if (status & 0x08) printf(" CRC"); - if (status & 0x04) printf(" Fifo"); - printf(" Error\n"); - entry->status &= le16_to_cpu(0x03ff); - - } else { - - pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; - if (pkt_len < 60) { - printf("%s: Rx%d: invalid packet length %d\n", - dev->name, lp->cur_rx, pkt_len); - } else { - NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); - PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", - lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]); - } + if (i <= 0) { + printf ("%s: TIMEOUT: controller init failed\n", dev->name); + pcnet_reset (dev); + return -1; } - entry->status |= cpu_to_le16(0x8000); - if (++lp->cur_rx >= RX_RING_SIZE) - lp->cur_rx = 0; - } - return pkt_len; + /* + * Finally start network controller operation. + */ + pcnet_write_csr (dev, 0, 0x0002); + + return 0; } -static void pcnet_halt(struct eth_device* dev) +static int pcnet_send (struct eth_device *dev, volatile void *packet, + int pkt_len) { - int i; + int i, status; + struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; + + PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, + packet); + + /* Wait for completion by testing the OWN bit */ + for (i = 1000; i > 0; i--) { + status = le16_to_cpu (entry->status); + if ((status & 0x8000) == 0) + break; + udelay (100); + PCNET_DEBUG2 ("."); + } + if (i <= 0) { + printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", + dev->name, lp->cur_tx, status); + pkt_len = 0; + goto failure; + } + + /* + * Setup Tx ring. Caution: the write order is important here, + * set the status with the "ownership" bits last. + */ + status = 0x8300; + entry->length = le16_to_cpu (-pkt_len); + entry->misc = 0x00000000; + entry->base = PCI_TO_MEM_LE (dev, packet); + entry->status = le16_to_cpu (status); - PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); + /* Trigger an immediate send poll. */ + pcnet_write_csr (dev, 0, 0x0008); - /* Reset the PCnet controller */ - pcnet_reset (dev); + failure: + if (++lp->cur_tx >= TX_RING_SIZE) + lp->cur_tx = 0; - /* Wait for Stop bit */ - for (i = 1000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x4) - break; - udelay(10); - } - if (i <= 0) { - printf("%s: TIMEOUT: controller reset failed\n", dev->name); - } + PCNET_DEBUG2 ("done\n"); + return pkt_len; } +static int pcnet_recv (struct eth_device *dev) +{ + struct pcnet_rx_head *entry; + int pkt_len = 0; + u16 status; + + while (1) { + entry = &lp->rx_ring[lp->cur_rx]; + /* + * If we own the next entry, it's a new packet. Send it up. + */ + if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { + break; + } + status >>= 8; + + if (status != 0x03) { /* There was an error. */ + + printf ("%s: Rx%d", dev->name, lp->cur_rx); + PCNET_DEBUG1 (" (status=0x%x)", status); + if (status & 0x20) + printf (" Frame"); + if (status & 0x10) + printf (" Overflow"); + if (status & 0x08) + printf (" CRC"); + if (status & 0x04) + printf (" Fifo"); + printf (" Error\n"); + entry->status &= le16_to_cpu (0x03ff); + + } else { + + pkt_len = + (le32_to_cpu (entry->msg_length) & 0xfff) - 4; + if (pkt_len < 60) { + printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); + } else { + NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); + PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", + lp->cur_rx, pkt_len, + lp->rx_buf[lp->cur_rx]); + } + } + entry->status |= cpu_to_le16 (0x8000); + + if (++lp->cur_rx >= RX_RING_SIZE) + lp->cur_rx = 0; + } + return pkt_len; +} + +static void pcnet_halt (struct eth_device *dev) +{ + int i; + + PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); + + /* Reset the PCnet controller */ + pcnet_reset (dev); + + /* Wait for Stop bit */ + for (i = 1000; i > 0; i--) { + if (pcnet_read_csr (dev, 0) & 0x4) + break; + udelay (10); + } + if (i <= 0) { + printf ("%s: TIMEOUT: controller reset failed\n", dev->name); + } +} #endif diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 68e45e17b..7dc33be89 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -182,7 +182,8 @@ fsl_pci_init(struct pci_controller *hose) /* Clear all error indications */ - pci->pme_msg_det = 0xffffffff; + if (bridge) + pci->pme_msg_det = 0xffffffff; pci->pedr = 0xffffffff; pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); diff --git a/drivers/usb/usb_ohci.c b/drivers/usb/usb_ohci.c index 5c201b3b4..ee0f2e45b 100644 --- a/drivers/usb/usb_ohci.c +++ b/drivers/usb/usb_ohci.c @@ -86,11 +86,11 @@ * e.g. PCI controllers need this */ #ifdef CFG_OHCI_SWAP_REG_ACCESS -# define readl(a) __swap_32(*((vu_long *)(a))) -# define writel(a, b) (*((vu_long *)(b)) = __swap_32((vu_long)a)) +# define readl(a) __swap_32(*((volatile u32 *)(a))) +# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a)) #else -# define readl(a) (*((vu_long *)(a))) -# define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a)) +# define readl(a) (*((volatile u32 *)(a))) +# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a)) #endif /* CFG_OHCI_SWAP_REG_ACCESS */ #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) @@ -138,28 +138,14 @@ int got_rhsc; /* device which was disconnected */ struct usb_device *devgone; -/*-------------------------------------------------------------------------*/ - -/* AMD-756 (D2 rev) reports corrupt register contents in some cases. - * The erratum (#4) description is incorrect. AMD's workaround waits - * till some bits (mostly reserved) are clear; ok for all revs. - */ -#define OHCI_QUIRK_AMD756 0xabcd -#define read_roothub(hc, register, mask) ({ \ - u32 temp = readl (&hc->regs->roothub.register); \ - if (hc->flags & OHCI_QUIRK_AMD756) \ - while (temp & mask) \ - temp = readl (&hc->regs->roothub.register); \ - temp; }) - -static u32 roothub_a (struct ohci *hc) - { return read_roothub (hc, a, 0xfc0fe000); } +static inline u32 roothub_a (struct ohci *hc) + { return readl (&hc->regs->roothub.a); } static inline u32 roothub_b (struct ohci *hc) { return readl (&hc->regs->roothub.b); } static inline u32 roothub_status (struct ohci *hc) { return readl (&hc->regs->roothub.status); } -static u32 roothub_portstatus (struct ohci *hc, int i) - { return read_roothub (hc, portstatus [i], 0xffe0fce0); } +static inline u32 roothub_portstatus (struct ohci *hc, int i) + { return readl (&hc->regs->roothub.portstatus[i]); } /* forward declaration */ static int hc_interrupt (void); diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 4f7306725..68b9861d4 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -849,6 +849,7 @@ int video_display_bitmap (ulong bmp_image, int x, int y) if (!((bmp->header.signature[0] == 'B') && (bmp->header.signature[1] == 'M'))) { printf ("Error: no valid bmp.gz image at %lx\n", bmp_image); + free(dst); return 1; } #else @@ -869,6 +870,10 @@ int video_display_bitmap (ulong bmp_image, int x, int y) if (compression != BMP_BI_RGB) { printf ("Error: compression type %ld not supported\n", compression); +#ifdef CONFIG_VIDEO_BMP_GZIP + if (dst) + free(dst); +#endif return 1; } diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index d04072e67..02b7dcbcb 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -138,5 +138,19 @@ #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) #define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE 0x70000000 +#define CSD0_BASE 0x80000000 +#define CSD1_BASE 0x90000000 +#define CS0_BASE 0xA0000000 +#define CS1_BASE 0xA8000000 +#define CS2_BASE 0xB0000000 +#define CS3_BASE 0xB2000000 +#define CS4_BASE 0xB4000000 +#define CS4_PSRAM_BASE 0xB5000000 +#define CS5_BASE 0xB6000000 +#define PCMCIA_MEM_BASE 0xC0000000 #endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 01cb2d74f..dc6e278ff 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1570,7 +1570,9 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - char res1[12]; + uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ +#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020 + char res1[8]; uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ char res2[12]; uint gpiocr; /* 0xe0030 - GPIO control register */ diff --git a/include/common.h b/include/common.h index 8630780e9..0ac1f8017 100644 --- a/include/common.h +++ b/include/common.h @@ -604,8 +604,9 @@ int sprintf(char * buf, const char *fmt, ...); int vsprintf(char *buf, const char *fmt, va_list args); /* lib_generic/crc32.c */ -ulong crc32 (ulong, const unsigned char *, uint); -ulong crc32_no_comp (ulong, const unsigned char *, uint); +uint32_t crc32 (uint32_t, const unsigned char *, uint); +uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); +uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ @@ -661,7 +662,7 @@ int pcmcia_init (void); /* * Board-specific Platform code can reimplement show_boot_progress () if needed */ -void inline show_boot_progress (int val); +void __attribute__((weak)) show_boot_progress (int val); #ifdef CONFIG_INIT_CRITICAL #error CONFIG_INIT_CRITICAL is deprecated! @@ -670,6 +671,9 @@ void inline show_boot_progress (int val); #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) + /* Multicore arch functions */ #ifdef CONFIG_MP int cpu_status(int nr); diff --git a/include/configs/APC405.h b/include/configs/APC405.h index f6495e484..e2ab39dc8 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2005-2008 + * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com + * * (C) Copyright 2001-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * @@ -24,7 +27,6 @@ /* * board/config.h - configuration options, board specific */ - #ifndef __CONFIG_H #define __CONFIG_H @@ -32,42 +34,78 @@ * High Level Configuration Options * (easy to change) */ - #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_APCG405 1 /* ...on a APC405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_R 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */ #define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ - "bootm ffc00000" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#define CFG_USB_LOAD_COMMAND "fatload usb 0 200000 pImage;" \ + "fatload usb 0 300000 pImage.initrd" +#define CFG_USB_SELF_COMMAND "usb start;run usb_load;usb stop;" \ + "run ramargs addip addcon usbargs;" \ + "bootm 200000 300000" +#define CFG_USB_ARGS "setenv bootargs $(bootargs) usbboot=1" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=abg405\0" \ + "bd_type=abg405\0" \ + "serial#=AA0000\0" \ + "kernel_addr=fe000000\0" \ + "ramdisk_addr=fe100000\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname)::off panic=1\0" \ + "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)" \ + " $(optargs)\0" \ + "flash_self=run ramargs addip addcon;" \ + "bootm $(kernel_addr) $(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;" \ + "bootm\0" \ + "rootpath=/tftpboot/abg405/target_root\0" \ + "img=/tftpboot/abg405/pImage\0" \ + "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0" \ + "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ + "cp.b 100000 fff80000 80000\0" \ + "ipaddr=10.0.111.111\0" \ + "netmask=255.255.0.0\0" \ + "serverip=10.0.0.190\0" \ + "splashimage=ffe80000\0" \ + "usb_load="CFG_USB_LOAD_COMMAND"\0" \ + "usb_self="CFG_USB_SELF_COMMAND"\0" \ + "usbargs="CFG_USB_ARGS"\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self;run usb_self" + +#define CONFIG_ETHADDR 00:02:27:8e:00:00 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 + #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ - /* * BOOTP options */ @@ -76,7 +114,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -93,95 +130,86 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_USB +#define CONFIG_CMD_AUTOSCRIPT #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_AUTO_UPDATE 1 /* autoupdate via CF or USB */ -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ +#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ + +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#undef CFG_HUSH_PARSER /* use "hush" command parser */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#if 1 /* test-only */ #define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ -#else -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CFG_BASE_BAUD 691200 -#endif /* The following table includes the supported baudrates */ #define CFG_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } #define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ /* Only interrupt boot if space is pressed */ /* If a long serial cable is connected but */ /* other end is dead, garbage will be read */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" -#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR #define CONFIG_AUTOBOOT_STOP_STR " " -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ +#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ - +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI_SKIP_HOST_BRIDGE 1 #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ @@ -192,119 +220,123 @@ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -/*----------------------------------------------------------------------- +/* * IDE/ATA stuff - *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#define CONFIG_IDE_RESET 1 /* reset for ide supported */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#define CONFIG_IDE_RESET 1 /* reset for ide supported */ -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS) /* max. 1 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR 0xF0100000 -#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR 0xF0100000 +#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */ +#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ -/*----------------------------------------------------------------------- +/* * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_MONITOR_BASE 0xFFF80000 -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_BOOTMAPSZ (8 << 20) /* Init. Memory map for Linux */ -/*----------------------------------------------------------------------- +/* * FLASH organization */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#undef CFG_FLASH_PROTECTION /* don't use hardware protection */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/ -#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#ifndef __ASSEMBLY__ +extern int flash_banks; +#endif -#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */ +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CFG_MAX_FLASH_BANKS flash_banks /* max num of flash banks */ + /* updated in board_early_init_r */ +#define CFG_MAX_FLASH_BANKS_DETECT 2 +#define CFG_FLASH_QUIET_TEST 1 +#define CFG_FLASH_INCREMENT 0x01000000 +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_AUTOPROTECT_LIST { \ + {0xfe000000, 0x500000}, \ + {0xffe80000, 0x180000} \ + } +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_BANKS_LIST { \ + CFG_FLASH_BASE, \ + CFG_FLASH_BASE + CFG_FLASH_INCREMENT \ + } +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/*----------------------------------------------------------------------- +/* * Environment Variable setup */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x000 /* environment starts at the */ + /* beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ +#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting vendor vars */ -#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CFG_NVRAM_SIZE 242 /* NVRAM size */ +#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CFG_NVRAM_SIZE 242 /* NVRAM size */ -/*----------------------------------------------------------------------- +/* * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + /* last 4 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- +/* * External Bus Controller (EBC) Setup */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define DUART0_BA 0xF0000400 /* DUART Base Address */ -#define DUART1_BA 0xF0000408 /* DUART Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define PS2_BA 0xF0000600 /* PS/2 Base Address */ -#define CF_BA 0xF0100000 /* CompactFlash Base Address */ -#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ -#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ -#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ -#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ -#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ - -#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ - -/* Memory Bank 0 (Flash Bank 0) initialization */ +#define FLASH0_BA (CFG_FLASH_BASE + CFG_FLASH_INCREMENT) /* FLASH 0 BA */ +#define FLASH1_BA CFG_FLASH_BASE /* FLASH 1 Base Address */ +#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define DUART0_BA 0xF0000400 /* DUART Base Address */ +#define DUART1_BA 0xF0000408 /* DUART Base Address */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define PS2_BA 0xF0000600 /* PS/2 Base Address */ +#define CF_BA 0xF0100000 /* CompactFlash Base Address */ +#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */ +#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */ +#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */ +#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */ +#define VGA_BA 0xF1000000 /* Epson VGA Base Address */ + +#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */ + +/* Memory Bank 0 (Flash Bank 0) initialization */ #define CFG_EBC_PB0AP 0x92015480 #define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ +#define CFG_EBC_PB0AP_HWREV8 CFG_EBC_PB0AP +#define CFG_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */ -/* Memory Bank 1 (Flash Bank 1) initialization */ +/* Memory Bank 1 (Flash Bank 1) initialization */ #define CFG_EBC_PB1AP 0x92015480 #define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ @@ -328,7 +360,7 @@ #define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/ -/*----------------------------------------------------------------------- +/* * FPGA stuff */ @@ -351,48 +383,56 @@ #define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ #define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ -/*----------------------------------------------------------------------- +/* * LCD Setup */ +#define CFG_LCD_BIG_MEM (VGA_BA + 0x200000) /* S1D13806 Mem Base */ +#define CFG_LCD_BIG_REG VGA_BA /* S1D13806 Reg Base */ -#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */ -#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */ - -#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ +#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */ /* Image information... */ -#define CONFIG_LCD_USED CONFIG_LCD_BIG -#define CFG_LCD_HEADER_NAME "../common/s1d13806_640_480_16bpp.h" -#define CFG_LCD_LOGO_NAME "logo_640_480_24bpp.c" +#define CONFIG_LCD_USED CONFIG_LCD_BIG -#define CFG_LCD_MEM CFG_LCD_BIG_MEM -#define CFG_LCD_REG CFG_LCD_BIG_REG +#define CFG_LCD_MEM CFG_LCD_BIG_MEM +#define CFG_LCD_REG CFG_LCD_BIG_REG #define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20) -/*----------------------------------------------------------------------- +/* * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ -#define CFG_TEMP_STACK_OCM 1 +#define CFG_TEMP_STACK_OCM 1 /* On Chip Memory location */ #define CFG_OCM_DATA_ADDR 0xF8000000 #define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* reserved bytes for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /* * Internal Definitions * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ -#endif /* __CONFIG_H */ +/* + * PCI OHCI controller + */ +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_PCI_OHCI 1 +#define CFG_OHCI_SWAP_REG_ACCESS 1 +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 +#define CFG_USB_OHCI_SLOT_NAME "ohci_pci" +#define CONFIG_USB_STORAGE 1 +#define CFG_USB_OHCI_BOARD_INIT 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index c147424ad..81e7c1e4d 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 DENX Software Engineering + * (C) Copyright 2007, 2008 DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. @@ -413,7 +413,7 @@ "addtty=setenv bootargs ${bootargs} " \ "console=${consdev},${baudrate}\0" \ "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ "flash_self=run ramargs addip addtty;" \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ @@ -422,10 +422,10 @@ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ "net_self=tftp ${kernel_addr_r} ${bootfile};" \ "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ "run ramargs addip addtty;" \ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ "update=protect off ${u-boot_addr} +${filesize};" \ "era ${u-boot_addr} +${filesize};" \ "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index be9432b4c..3dd577aae 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -141,6 +141,9 @@ * On 440EPx the SPL is copied to SDRAM before the NAND controller is * set up. While still running from cache, I experienced problems accessing * the NAND controller. sr - 2006-08-25 + * + * This is the first official implementation of booting from 2k page sized + * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8) */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ @@ -153,24 +156,27 @@ /* * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) */ -#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ -#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ +#define CFG_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */ /* * Now the NAND chip has to be defined (no autodetection used!) */ -#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ -#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ -#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ -#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ -#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ +#define CFG_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT (CFG_NAND_BLOCK_SIZE / CFG_NAND_PAGE_SIZE) + /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/ +#define CFG_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */ #define CFG_NAND_ECCSIZE 256 #define CFG_NAND_ECCBYTES 3 #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) -#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_OOBSIZE 64 #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) -#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} +#define CFG_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63} #ifdef CFG_ENV_IS_IN_NAND /* @@ -231,7 +237,7 @@ #define CONFIG_DDR_ECC 1 /* with ECC support */ #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ #endif -#define CFG_MBYTES_SDRAM 256 /* 256MB */ +#define CFG_MBYTES_SDRAM 512 /* 512MB */ /*----------------------------------------------------------------------- * I2C @@ -313,15 +319,18 @@ #define CONFIG_HOSTNAME canyonlands #define CFG_BOOTFILE "bootfile=canyonlands/uImage\0" #define CFG_DTBFILE "fdt_file=canyonlands/canyonlands.dtb\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" #else #define CONFIG_HOSTNAME glacier #define CFG_BOOTFILE "bootfile=glacier/uImage\0" #define CFG_DTBFILE "fdt_file=glacier/glacier.dtb\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ CFG_BOOTFILE \ CFG_DTBFILE \ + CFG_ROOTPATH \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ @@ -330,18 +339,18 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "net_nfs=tftp 400000 ${bootfile};" \ - "tftp ${fdt_addr} ${fdt_file};" \ - "run nfsargs addip addtty;" \ - "bootm 400000 - ${fdt_addr}\0" \ - "net_nfs_fdt=net_nfs\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "rootpath=/opt/eldk/ppc_4xxFP\0" \ - "fdt_addr=800000\0" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=800000\0" \ "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ "ramdisk_addr=fc200000\0" \ "initrd_high=30000000\0" \ "load=tftp 200000 ${hostname}/u-boot.bin\0" \ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 605eb4058..5e97cfa72 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/mx31-regs.h> + /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ @@ -91,7 +93,7 @@ #define CONFIG_DRIVER_SMC911X 1 -#define CONFIG_DRIVER_SMC911X_BASE 0xb4020000 +#define CONFIG_DRIVER_SMC911X_BASE (CS4_BASE + 0x00020000) #define CONFIG_DRIVER_SMC911X_32_BIT 1 /* @@ -127,18 +129,18 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_FLASH_BASE 0xa0000000 +#define CFG_FLASH_BASE CS0_BASE #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ #define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ -#define CFG_ENV_ADDR 0xa01f0000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x001f0000) #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SECT_SIZE (64 * 1024) #define CFG_ENV_SIZE (64 * 1024) diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index a394b4b7c..a9c86f9e3 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2008 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -155,8 +155,8 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate} " \ - "ubootver=${ubootver} board=${board}\0" \ + "console=${console},${baudrate} " \ + "ubootver=${ubootver} board=${board}\0" \ "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addcons;" \ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h new file mode 100644 index 000000000..5286e1f53 --- /dev/null +++ b/include/configs/mx31ads.h @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> + * + * Configuration settings for the MX31ADS Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx31-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ +#define CONFIG_MX31_CLK32 32000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Disabled for now due to build problems under Debian and a significant increase + * in the final file size: 144260 vs. 109536 Bytes. + */ +#if 0 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#endif + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#define CONFIG_MX31_UART 1 +#define CFG_MX31_UART1 1 + +#define CONFIG_HARD_SPI 1 +#define CONFIG_MXC_SPI 1 +#define CONFIG_MXC_SPI_IFACE 1 /* Default SPI interface number */ + +#define CONFIG_RTC_MC13783 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DATE + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.23.168 +#define CONFIG_SERVERIP 192.168.23.2 +#define CONFIG_LOADADDR (CSD0_BASE + 0x800000) /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=mx31ads/u-boot.bin\0" \ + "kernel=mx31ads/uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa003ffff; " \ + "erase ${uboot_addr} 0xa003ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +#define CONFIG_DRIVER_CS8900 1 +#define CS8900_BASE 0xb4020300 +#define CS8900_BUS16 1 /* follow the Linux driver */ + +/* + * The MX31ADS board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs 4 network packets for that. Which means, at startup, you + * will not receive answers to the first 4 packest, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0 /* memtest works on */ +#define CFG_MEMTEST_END 0x10000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR CONFIG_LOADADDR + +#define CFG_HZ 32000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_FLASH_BASE CS0_BASE +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE (32 * 1024) +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + +/* S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the end. + * The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low 4 sectors, + * if we put environment next to it, we will have to occupy 128KiB for it. + * Putting it at the top of flash we use only 32KiB. */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index ed41b2f50..ac72f983e 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -173,7 +173,7 @@ "upd=run load update\0" \ "ipaddr=10.0.0.233\0" \ "serverip=10.0.0.152\0" \ - "netmask=255.255.0.0\0" \ + "netmask=255.255.0.0\0" \ "ethaddr=c6:6f:13:36:f3:81\0" \ "eth1addr=c6:6f:13:36:f3:82\0" \ "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index e1640195a..d6bcc8e3b 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -22,31 +22,31 @@ */ /* - * This file contains the configuration parameters for the dbau1x00 board. + * This file contains the configuration parameters for qemu-mips target. */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ -#define CONFIG_QEMU_MIPS 1 +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ +#define CONFIG_QEMU_MIPS 1 #define CONFIG_MISC_INIT_R /*IP address is default used by Qemu*/ -#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ -#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address*/ +#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */ +#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */ -#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */ #define CONFIG_BAUDRATE 115200 /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#undef CONFIG_BOOTARGS +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#undef CONFIG_BOOTARGS -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CONFIG_EXTRA_ENV_SETTINGS \ "addmisc=setenv bootargs ${bootargs} " \ "console=ttyS0,${baudrate} " \ "panic=1\0" \ @@ -56,7 +56,6 @@ #define CONFIG_BOOTCOMMAND "bootp;bootelf" - /* * BOOTP options */ @@ -65,7 +64,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -74,27 +72,24 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS #define CONFIG_CMD_DHCP #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_NE2000_BASE (0xb4000300) -#define CFG_NO_FLASH #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 -#define CFG_NS16550_CLK 115200 -#define CFG_NS16550_COM1 (0xb40003f8) +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK 115200 +#define CFG_NS16550_COM1 (0xb40003f8) #define CONFIG_CONS_INDEX 1 #define CONFIG_CMD_IDE #define CONFIG_DOS_PARTITION -#define CFG_IDE_MAXBUS 2 +#define CFG_IDE_MAXBUS 2 #define CFG_ATA_IDE0_OFFSET (0x1f0) #define CFG_ATA_IDE1_OFFSET (0x170) #define CFG_ATA_DATA_OFFSET (0) @@ -106,18 +101,18 @@ /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "qemu-mips # " /* Monitor Command Prompt */ +#define CFG_PROMPT "qemu-mips # " /* Monitor Command Prompt */ #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MALLOC_LEN 128*1024 @@ -125,11 +120,11 @@ #define CFG_MHZ 132 -#define CFG_HZ (CFG_MHZ * 1000000) +#define CFG_HZ (CFG_MHZ * 1000000) -#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ -#define CFG_LOAD_ADDR 0x81000000 /* default load address */ +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ #define CFG_MEMTEST_START 0x80100000 #define CFG_MEMTEST_END 0x80800000 @@ -139,21 +134,30 @@ */ /* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) #define CFG_INIT_SP_OFFSET 0x400000 /* We boot from this flash, selected with dip switch */ #define CFG_FLASH_BASE 0xbfc00000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 128 +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) + +/* Address and size of Primary Environment Sector */ +#define CFG_ENV_SIZE 0x8000 -#define CFG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_OVERWRITE 1 -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_SIZE 0x10000 #undef CONFIG_NET_MULTI -#define MEM_SIZE 128 +#define MEM_SIZE 128 #undef CONFIG_MEMSIZE_IN_BYTES @@ -164,4 +168,4 @@ #define CFG_ICACHE_SIZE 16384 #define CFG_CACHELINE_SIZE 32 -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d00c22f0d..133cbcf17 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -671,7 +671,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "hostname=sbc8349\0" \ + "hostname=sbc8349\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -690,7 +690,7 @@ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ "upd=run load update\0" \ "fdtaddr=400000\0" \ - "fdtfile=sbc8349.dtb\0" \ + "fdtfile=sbc8349.dtb\0" \ "" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/environment.h b/include/environment.h index af605ab7a..c4f7c33be 100644 --- a/include/environment.h +++ b/include/environment.h @@ -84,18 +84,23 @@ # endif #endif /* CFG_ENV_IS_IN_NAND */ +#ifdef USE_HOSTCC +# include <stdint.h> +#else +# include <linux/types.h> +#endif #ifdef CFG_REDUNDAND_ENVIRONMENT -# define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) +# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) #else -# define ENV_HEADER_SIZE (sizeof(unsigned long)) +# define ENV_HEADER_SIZE (sizeof(uint32_t)) #endif #define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE) typedef struct environment_s { - unsigned long crc; /* CRC32 over data bytes */ + uint32_t crc; /* CRC32 over data bytes */ #ifdef CFG_REDUNDAND_ENVIRONMENT unsigned char flags; /* active/obsolete flags */ #endif diff --git a/include/image.h b/include/image.h index 60fdb2bea..4076484a5 100644 --- a/include/image.h +++ b/include/image.h @@ -364,8 +364,7 @@ int image_check_hcrc (image_header_t *hdr); int image_check_dcrc (image_header_t *hdr); #ifndef USE_HOSTCC int image_check_dcrc_wd (image_header_t *hdr, ulong chunksize); -int getenv_verify (void); -int getenv_autostart (void); +int getenv_yesno (char *var); ulong getenv_bootm_low(void); ulong getenv_bootm_size(void); void memmove_wd (void *to, void *from, size_t len, ulong chunksz); @@ -392,8 +391,7 @@ ulong image_multi_count (image_header_t *hdr); void image_multi_getimg (image_header_t *hdr, ulong idx, ulong *data, ulong *len); -inline void image_print_contents (image_header_t *hdr); -inline void image_print_contents_noindent (image_header_t *hdr); +void image_print_contents (image_header_t *hdr); #ifndef USE_HOSTCC static inline int image_check_target_arch (image_header_t *hdr) @@ -469,8 +467,7 @@ inline int fit_parse_conf (const char *spec, ulong addr_curr, inline int fit_parse_subimage (const char *spec, ulong addr_curr, ulong *addr, const char **image_name); -inline void fit_print_contents (const void *fit); -inline void fit_print_contents_noindent (const void *fit); +void fit_print_contents (const void *fit); void fit_image_print (const void *fit, int noffset, const char *p); void fit_image_print_hash (const void *fit, int noffset, const char *p); diff --git a/include/sha1.h b/include/sha1.h index 15ea13cd3..734d1fb15 100644 --- a/include/sha1.h +++ b/include/sha1.h @@ -80,6 +80,17 @@ void sha1_csum( unsigned char *input, int ilen, unsigned char output[20] ); /** + * \brief Output = SHA-1( input buffer ), with watchdog triggering + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-1 checksum result + * \param chunk_sz watchdog triggering period (in bytes of input processed) + */ +void sha1_csum_wd (unsigned char *input, int ilen, + unsigned char output[20], unsigned int chunk_sz); + +/** * \brief Output = SHA-1( file contents ) * * \param path input file name diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h index 046d1eee7..8b44a7f84 100644 --- a/include/u-boot/md5.h +++ b/include/u-boot/md5.h @@ -20,4 +20,12 @@ struct MD5Context { */ void md5 (unsigned char *input, int len, unsigned char output[16]); +/* + * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'. + * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the + * watchdog every 'chunk_sz' bytes of input processed. + */ +void md5_wd (unsigned char *input, int len, unsigned char output[16], + unsigned int chunk_sz); + #endif /* _MD5_H */ diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c index df0dbca34..58cd22eb7 100644 --- a/lib_generic/crc32.c +++ b/lib_generic/crc32.c @@ -10,18 +10,19 @@ #ifndef USE_HOSTCC /* Shut down "ANSI does not permit..." warnings */ #include <common.h> +#else +#include <stdint.h> #endif #include "zlib.h" #define local static #define ZEXPORT /* empty */ -unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); #ifdef DYNAMIC_CRC_TABLE local int crc_table_empty = 1; -local uLongf crc_table[256]; +local uint32_t crc_table[256]; local void make_crc_table OF((void)); /* @@ -50,7 +51,7 @@ local void make_crc_table OF((void)); */ local void make_crc_table() { - uLong c; + uint32_t c; int n, k; uLong poly; /* polynomial exclusive-or pattern */ /* terms of polynomial defining this crc (except x^32): */ @@ -74,7 +75,7 @@ local void make_crc_table() /* ======================================================================== * Table of CRC-32's of all single-byte values (made by make_crc_table) */ -local const uLongf crc_table[256] = { +local const uint32_t crc_table[256] = { 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L, 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, @@ -134,12 +135,12 @@ local const uLongf crc_table[256] = { /* ========================================================================= * This function can be used by asm versions of crc32() */ -const uLongf * ZEXPORT get_crc_table() +const uint32_t * ZEXPORT get_crc_table() { #ifdef DYNAMIC_CRC_TABLE if (crc_table_empty) make_crc_table(); #endif - return (const uLongf *)crc_table; + return (const uint32_t *)crc_table; } #endif @@ -150,8 +151,8 @@ const uLongf * ZEXPORT get_crc_table() #define DO8(buf) DO4(buf); DO4(buf); /* ========================================================================= */ -uLong ZEXPORT crc32(crc, buf, len) - uLong crc; +uint32_t ZEXPORT crc32(crc, buf, len) + uint32_t crc; const Bytef *buf; uInt len; { @@ -178,7 +179,7 @@ uLong ZEXPORT crc32(crc, buf, len) /* No ones complement version. JFFS2 (and other things ?) * don't use ones compliment in their CRC calculations. */ -uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len) +uint32_t ZEXPORT crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len) { #ifdef DYNAMIC_CRC_TABLE if (crc_table_empty) @@ -197,3 +198,30 @@ uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len) } #endif + +/* + * Calculate the crc32 checksum triggering the watchdog every 'chunk_sz' bytes + * of input. + */ +ulong crc32_wd (ulong crc, const unsigned char *buf, uint len, uint chunk_sz) +{ +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + const unsigned char *end, *curr; + int chunk; + + curr = buf; + end = buf + len; + while (curr < end) { + chunk = end - curr; + if (chunk > chunk_sz) + chunk = chunk_sz; + crc = crc32 (crc, curr, chunk); + curr += chunk; + WATCHDOG_RESET (); + } +#else + crc = crc32 (crc, buf, len); +#endif + + return crc; +} diff --git a/lib_generic/md5.c b/lib_generic/md5.c index 3cee431c7..20178b8dc 100644 --- a/lib_generic/md5.c +++ b/lib_generic/md5.c @@ -272,3 +272,39 @@ md5 (unsigned char *input, int len, unsigned char output[16]) MD5Update(&context, input, len); MD5Final(output, &context); } + + +/* + * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'. + * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the + * watchdog every 'chunk_sz' bytes of input processed. + */ +void +md5_wd (unsigned char *input, int len, unsigned char output[16], + unsigned int chunk_sz) +{ + struct MD5Context context; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + unsigned char *end, *curr; + int chunk; +#endif + + MD5Init(&context); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + curr = input; + end = input + len; + while (curr < end) { + chunk = end - curr; + if (chunk > chunk_sz) + chunk = chunk_sz; + MD5Update(&context, curr, chunk); + curr += chunk; + WATCHDOG_RESET (); + } +#else + MD5Update(&context, input, len); +#endif + + MD5Final(output, &context); +} diff --git a/lib_generic/sha1.c b/lib_generic/sha1.c index 08ffa6b9b..69506592f 100644 --- a/lib_generic/sha1.c +++ b/lib_generic/sha1.c @@ -309,6 +309,39 @@ void sha1_csum (unsigned char *input, int ilen, unsigned char output[20]) } /* + * Output = SHA-1( input buffer ). Trigger the watchdog every 'chunk_sz' + * bytes of input processed. + */ +void sha1_csum_wd (unsigned char *input, int ilen, unsigned char output[20], + unsigned int chunk_sz) +{ + sha1_context ctx; +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + unsigned char *end, *curr; + int chunk; +#endif + + sha1_starts (&ctx); + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) + curr = input; + end = input + ilen; + while (curr < end) { + chunk = end - curr; + if (chunk > chunk_sz) + chunk = chunk_sz; + sha1_update (&ctx, curr, chunk); + curr += chunk; + WATCHDOG_RESET (); + } +#else + sha1_update (&ctx, input, ilen); +#endif + + sha1_finish (&ctx, output); +} + +/* * Output = HMAC-SHA-1( input buffer, hmac key ) */ void sha1_hmac (unsigned char *key, int keylen, diff --git a/lib_ppc/board.c b/lib_ppc/board.c index b2bc4ebc5..1b8a8721a 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -124,7 +124,6 @@ DECLARE_GLOBAL_DATA_PTR; #define CFG_MEM_TOP_HIDE 0 #endif -extern ulong _start; extern ulong __init_end; extern ulong _end; ulong monitor_flash_len; diff --git a/nand_spl/board/amcc/canyonlands/config.mk b/nand_spl/board/amcc/canyonlands/config.mk index 6dad876ae..c8d7c2352 100644 --- a/nand_spl/board/amcc/canyonlands/config.mk +++ b/nand_spl/board/amcc/canyonlands/config.mk @@ -34,9 +34,9 @@ # TEXT_BASE = 0xE3003000 -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = TEXT_BASE + 0x4000 -PAD_TO = 0xE3007000 +# PAD_TO used to generate a 128kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x20000 +PAD_TO = 0xE3023000 PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c index 48708a8ee..79f3b0f42 100644 --- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c +++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c @@ -49,11 +49,11 @@ long int initdram(int board_type) * enabled. This will only work for the same memory * configuration as used here: * - * Crucial CT3264AC53E.4FD - 256MB SO-DIMM + * Crucial CT6464AC53E.4FE - 512MB SO-DIMM * */ mtsdram(SDRAM_MCOPT2, 0x00000000); - mtsdram(SDRAM_MCOPT1, 0x05122000); + mtsdram(SDRAM_MCOPT1, 0x05322000); mtsdram(SDRAM_MODT0, 0x01000000); mtsdram(SDRAM_CODT, 0x00800021); mtsdram(SDRAM_WRDTR, 0x82000823); @@ -62,7 +62,7 @@ long int initdram(int board_type) mtsdram(SDRAM_RTR, 0x06180000); mtsdram(SDRAM_SDTR1, 0x80201000); mtsdram(SDRAM_SDTR2, 0x42103243); - mtsdram(SDRAM_SDTR3, 0x0A0D0D16); + mtsdram(SDRAM_SDTR3, 0x0A0D0D1A); mtsdram(SDRAM_MMODE, 0x00000632); mtsdram(SDRAM_MEMODE, 0x00000040); mtsdram(SDRAM_INITPLR0, 0xB5380000); @@ -86,7 +86,7 @@ long int initdram(int board_type) wait_init_complete(); - mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */ + mtdcr(SDRAM_R0BAS, 0x0000F000); /* MQ0_B0BAS */ mtsdram(SDRAM_RDCC, 0x40000000); mtsdram(SDRAM_RQDC, 0x80000038); diff --git a/tools/Makefile b/tools/Makefile index 8784a6d5c..b89792327 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -236,7 +236,11 @@ $(obj)environment.c: $(obj)environment.o: $(obj)environment.c $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c -o $@ $< -$(obj)crc32.c: +$(obj)zlib.h: + @rm -f $@ + ln -s $(src)../include/zlib.h $@ + +$(obj)crc32.c: $(obj)zlib.h @rm -f $(obj)crc32.c ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c diff --git a/tools/envcrc.c b/tools/envcrc.c index 7b7718324..550cf82d1 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -22,6 +22,7 @@ */ #include <stdio.h> +#include <stdint.h> #include <stdlib.h> #include <unistd.h> @@ -58,15 +59,15 @@ #endif /* CFG_ENV_IS_IN_FLASH */ #ifdef CFG_REDUNDAND_ENVIRONMENT -# define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) +# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) #else -# define ENV_HEADER_SIZE (sizeof(unsigned long)) +# define ENV_HEADER_SIZE (sizeof(uint32_t)) #endif #define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE) -extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); +extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int); #ifdef ENV_IS_EMBEDDED extern unsigned int env_size; @@ -76,7 +77,7 @@ extern unsigned char environment; int main (int argc, char **argv) { #ifdef ENV_IS_EMBEDDED - int crc; + uint32_t crc; unsigned char *envptr = &environment, *dataptr = envptr + ENV_HEADER_SIZE; unsigned int datasize = ENV_SIZE; diff --git a/tools/mkimage.c b/tools/mkimage.c index 6e1ff2b1e..ea7a826f8 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -229,10 +229,10 @@ NXTARG: ; if (fdt_check_header (ptr)) { /* old-style image */ image_verify_header ((char *)ptr, sbuf.st_size); - image_print_contents_noindent ((image_header_t *)ptr); + image_print_contents ((image_header_t *)ptr); } else { /* FIT image */ - fit_print_contents_noindent (ptr); + fit_print_contents (ptr); } (void) munmap((void *)ptr, sbuf.st_size); @@ -363,7 +363,7 @@ NXTARG: ; image_set_hcrc (hdr, checksum); - image_print_contents_noindent (hdr); + image_print_contents (hdr); (void) munmap((void *)ptr, sbuf.st_size); diff --git a/tools/setlocalversion b/tools/setlocalversion index 9bbdafdb6..bbb2ab2f7 100755 --- a/tools/setlocalversion +++ b/tools/setlocalversion @@ -22,4 +22,18 @@ if head=`git rev-parse --verify HEAD 2>/dev/null`; then | read dummy; then printf '%s' -dirty fi + + # Is this git on svn? + if git config --get svn-remote.svn.url >/dev/null; then + printf -- '-svn%s' "`git-svn find-rev $head`" + fi fi + +# Check for svn and a svn repo. +if rev=`svn info 2>/dev/null` ; then + rev=`echo "${rev}" | grep '^Revision' | awk '{print $NF}'` + printf -- '-svn%s' $rev +fi + +# Check for any localversion-* files +printf '%s' "`cat localversion-* 2>/dev/null`" |