diff options
336 files changed, 12505 insertions, 1840 deletions
@@ -1,3 +1,1173 @@ +commit cf7e399fb35b3aea90a27d1df72f45f5d6156204 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Jan 27 16:12:21 2009 -0500 + + SATA: do not auto-initialize during boot + + Rather than have the board code initialize SATA automatically during boot, + make the user manually run "sata init". This brings the SATA subsystem in + line with common U-Boot policy. + + Rather than having a dedicated weak function "is_sata_supported", people + can override sata_initialize() to do their weird board stuff. Then they + can call the actual __sata_initialize(). + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 50970839712dda35399e2fa83fe818df9354d618 +Author: Richard Retanubun <RichardRetanubun@RuggedCom.com> +Date: Mon Jan 26 08:45:14 2009 -0500 + + part_efi: Fix partition size calculation due to inclusive ending LBA. + + The ending LBA is inclusive. Hence, the partition size should be + ((ending-LBA + 1) - starting-LBA) to get the proper partition size. + + This is confirmed against the results from the parted tool. + (e.g. use parted /dev/sda -s unit S print) and observe the size. + + Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> + +commit b5b004ad8a0ac6f98bd5708ec8b22fbddd1c1042 +Author: Tomasz Figa <tomasz.figa@gmail.com> +Date: Tue Dec 30 18:35:57 2008 +0100 + + jffs2: Fix zero sector_size when not using CONFIG_JFFS2_CMDLINE + + This patch fixes a bug (?) introduced after inclusion of the new + JFFS2 code. + + When not using CONFIG_JFFS2_CMDLINE, the code in cmd_jffs2.c doesn't + fill in part->sector_size (keeping it as 0), but a correct value is + needed by the code in jffs2_1pass.c. This causes all JFFS2 accesses + to be in the same place of the memory, what obviously means + impossibility to use the JFFS2 partition. + + This problem is fixed in this patch by including sector size + calculation in non-CONFIG_JFFS2_CMDLINE mtdparts_init variant. + + Signed-off-by: Tomasz Figa <tomasz.figa_at_gmail.com> + +commit ba69dc26a5fd606da49573bb2f15e756a34f3f98 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Dec 30 02:59:25 2008 -0500 + + saveenv: standardize enablement + + Rather than special casing each environment type for enabling the saveenv + command, have them all behave the same. This avoids bitrot as new env + sources are added/removed. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 2ac6985a7466a1c8a7aa8b2fa24d360925a82764 +Author: Andrew Dyer <adyer@righthandtech.com> +Date: Mon Dec 29 17:36:01 2008 -0600 + + soft_i2c.c add option for repeated start in i2c_read() + + This patch adds a #define to optionally change the behaviour of + i2c_read() in soft_i2c.c to send an I2C repeated start instead of a + stop-start between sending the device address pointer write and + reading back the data. The current behaviour is retained as the + default. + + While most devices will work either way, I have a smart battery(*) + that requires repeated start, and someone at some point found a + device that required a stop-start. + + (*) http://www.inspired-energy.com/Standard_Products/NL2054/NL2054%20Rev1.0%20Data%20Sheet.pdf + + Signed-off-by: Andrew Dyer <adyer@righthandtech.com> + +commit 3429071700963ca2f944c51d695a7481af0cee33 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Jan 27 22:07:14 2009 +0100 + + {delta,zylonite}/lowlevel_init.S: fix typo + + Commit 9d803d8c mistakenly changed some constants + from 0x300 into 300 - this patch fixes it. + + Pointed out by Tom Evans <tom@ceos.com.au>, see + http://article.gmane.org/gmane.comp.boot-loaders.u-boot/51992 for + details. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 1bc434373013af241835c14011ac3f291dccbf53 +Author: Stefan Althoefer <stefan.althoefer@web.de> +Date: Sat Dec 20 19:40:41 2008 +0100 + + drivers/net/e1000.c: missing terminator for supported devices + + Signed-off-by: Stefan Althoefer <stefan.althoefer@web.de> + +commit 65f7d41031a70b1649b35020995c505edca91533 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Jan 27 21:36:28 2009 +0100 + + fat.c: fix warning: array subscript is above array bounds + + Fix based on suggestion by David Hawkins <dwh@ovro.caltech.edu>. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 107b801cf3fe39612d69d70581ebc3bf5e215554 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Fri Jan 2 15:11:41 2009 +0100 + + Fix gunzip in case of insufficient output buffer + + U-Boot's gunzip() function does not handle the return code + of zlib's inflate() function correctly. gunzip() is implemented + to uncompress all input data in one run. So the correct return + code for the good case is Z_STREAM_END. In case of insufficient + output buffer memory inflate returns Z_OK. For gunzip() this + is an error. + + It also makes sense to me to call inflateEnd() also in case + of an error. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit 2a61eff6a82f0d6e2335d968799b3fbeb3ff4d8e +Author: Stefan Roese <sr@denx.de> +Date: Wed Jan 21 17:25:01 2009 +0100 + + MIPS: Add VCT board series support (Part 3/3) + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit ae691e5719c48f1d2826cb72722497d1d162765b +Author: Stefan Roese <sr@denx.de> +Date: Wed Jan 21 17:24:49 2009 +0100 + + MIPS: Add VCT board series support (Part 2/3) + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 50752790bc9285c0c1c5235e88f3a4ef2eec1e72 +Author: Stefan Roese <sr@denx.de> +Date: Wed Jan 21 17:24:39 2009 +0100 + + MIPS: Add VCT board series support (Part 1/3) + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 03d3bfb00806b5441f1871c7408c1749863e0fdc +Author: Stefan Roese <sr@denx.de> +Date: Wed Jan 21 17:20:20 2009 +0100 + + MIPS: Add flush_dcache_range() and invalidate_dcache_range() + + This patch adds flush_/invalidate_dcache_range() to the MIPS architecture. + Those functions are needed for the upcoming dcache support for the USB + EHCI driver. I chose this API because those cache handling functions are + already present in the PPC architecture. + + Signed-off-by: Stefan Roese <sr@denx.de> + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit e8eac437189430d8e04a5d254ed92c58bc534a79 +Author: Richard Retanubun <RichardRetanubun@RuggedCom.com> +Date: Wed Jan 14 08:44:26 2009 -0500 + + CFI: Add geometry reversal for STMicro M29W320ET + + Added flash_fixup_stm to fix geometry reversal on STMicro M29W320ET flash chip. + + Modeled after flash_fixup_amd, this patch handles the geometry reversal + or erase sectors that exist for ST Micro (now Numonyx) M29W320ET flash. + Since I cannot test all STM's chips, the detection is implemented as + narrow as possible for now. + + Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 0f8e851e897b535959a0781171910cd97f33c30c +Author: Jens Gehrlein <sew_s@tqs.de> +Date: Tue Dec 16 17:25:55 2008 +0100 + + CFI: increase performance of function find_sector() + + Tested on TQM5200S-BD with Samsung K8P2815UQB + + Signed-off-by: Jens Gehrlein <sew_s@tqs.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit a7292871a79cc48d98e3a708dd3c3b81580db6ef +Author: Jens Gehrlein <sew_s@tqs.de> +Date: Tue Dec 16 17:25:54 2008 +0100 + + CFI: avoid redundant function call in single word programming mode + + The function find_sector() doesn't need to be called twice in + the case of AMD command set. + Tested on TQM5200S-BD with Samsung K8P2815UQB. + + Signed-off-by: Jens Gehrlein <sew_s@tqs.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit c8901f46a71ec16e084e604596a09e23bfb0f6ac +Author: Stefan Roese <sr@denx.de> +Date: Mon Jan 26 10:15:23 2009 +0100 + + ppc4xx: Remove compilation warning in gdppc440etc.c + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 91f33534728e6416d332ad2b53ad1d6fde57f7fc +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Fri Jan 2 12:19:47 2009 +0100 + + ppc4xx: Remove CONFIG_SYS_IGNORE_405_UART_ERRATA_59 from config files + + Lot's of 405 board config files use CONFIG_SYS_IGNORE_405_UART_ERRATA_59. + Either they define or undef it. Because it's not used in any source + files this patch removes any references to it. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 89b8619aaeafc922ca0c3bb249872591050c8dcc +Author: Dirk Eibach <eibach@gdsys.de> +Date: Tue Dec 9 13:12:40 2008 +0100 + + ppc4xx: Add GDsys PowerPC 440 ETX board support. + + Board support for the Guntermann & Drunck PowerPC 440 ETX module. + Based on the AMCC Yosemite board support by Stefan Roese. + + Signed-off-by: Dirk Eibach <eibach@gdsys.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 3943d2ff6cc40dd601a9feeb39eb6d3d5090ea6d +Author: Dirk Eibach <eibach@gdsys.de> +Date: Tue Dec 9 11:00:07 2008 +0100 + + ppc4xx: Improve DDR autodetect + + Added support for a second memory bank to DDR autodetection for 440 + platforms. + Made hardcoded values configurable. + + Signed-off-by: Dirk Eibach <eibach@gdsys.de> + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 24113a44ed5cd3257a0237c3961e121812fca6db +Author: Mike Frysinger <vapier@gentoo.org> +Date: Tue Dec 30 03:15:38 2008 -0500 + + easylogo: add optional gzip support + + Some images can be quite large, so add an option to compress the + image data with gzip in the U-Boot image. Then at runtime, the + board can decompress it with the normal zlib functions. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 7e4b9b4f6f43838fad3ad72c029a3d7fc7c7d48c +Author: Bryan Wu <bryan.wu@analog.com> +Date: Fri Jan 2 20:47:45 2009 -0500 + + fat: fix unaligned errors + + A couple of buffers in the fat code are declared as an array of bytes. + But it is then cast up to a structure with 16bit and 32bit members. + Since GCC assumes structure alignment here, we have to force the + buffers to be aligned according to the structure usage. + + Signed-off-by: Bryan Wu <bryan.wu@analog.com> + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 68f8718df2ed4c2f43031407ccf6cfa81125dddc +Author: Brad Bozarth <bflinux@yumbrad.com> +Date: Thu Jan 1 22:45:47 2009 -0500 + + spi flash: fix crash due to spi flash miscommunication + + Higher spi flash layers expect to be given back a pointer that was + malloced so that it can free the result, but the lower layers return + a pointer that is in the middle of the malloced memory. Reorder the + members of the lower spi structures so that things work out. + + Signed-off-by: Brad Bozarth <bflinux@yumbrad.com> + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + +commit ce82ff05388b5ddafdf6082ef0776cce72c40b1c +Author: Yuri Tikhonov <yur@emcraft.com> +Date: Sat Dec 20 14:54:21 2008 +0300 + + FPU POST: fix warnings when building with 2.18 binutils + + When compile u-boot with the 2.18 binutils the following + warning messages for each object file in post/lib_ppc/fpu/ is + produced at the linking stage: + + post/libpost.a(acc1.o) uses hard float, u-boot uses soft-float + ... + + This is because of the fact that, in general, the soft-float and + hard-float ABIs are incompatible; the 2.18 binutils do checking + of the Tag_GNU_Power_ABI_FP attribute of the files to be linked, and + produce the worning like above if these are not compatible. + + The incompatibility of ABIs is concerned only the float values: + e.g. the soft-float ABI assumes the float argument passing in the + pair of rX registers, and the hard-float ABI assumes passing of + the float argument in the fX register. When we don't pass the float + arguments between the functions compiled with different floatness, + then such an application will work correctly. + This is the case for the FPU POST: u-boot (compiled with soft-float) + doesn't pass to (and doesn't get from) the FPU POST functions any + floats; there are no functions exported from the post/lib_ppc/fpu/ + objects which would work with float parameters/returns too. So, we + can reassure the linker not to worry about the difference in ABI + attributes of linking files just by setting the 'soft-float' + attribute for the objects in post/lib_ppc/fpu. And this patch does + this. + + Also, to avoid passing both soft- and hard-float options in CFLAGS + when compiling the files from post/lib_ppc/fpu (which is OK, but + looks rather dirty) this patch removes the soft-float string from + CFLAGS in post/lib_ppc/fpu/Makefile. + + Signed-off-by: Yuri Tikhonov <yur@emcraft.com> + +commit a7c9310457e85b4598abe5b304108edf11332e2f +Author: Peter Tyser <ptyser@xes-inc.com> +Date: Wed Dec 17 16:36:22 2008 -0600 + + Add support for Maxim's DS4510 I2C device + + Initial support for the DS4510, a CPU supervisor with + integrated EEPROM, SRAM, and 4 programmable non-volatile + GPIO pins. The CONFIG_DS4510 define enables support + for the device while the CONFIG_CMD_DS4510 define + enables the ds4510 command. The additional + CONFIG_DS4510_INFO, CONFIG_DS4510_MEM, and + CONFIG_DS4510_RST defines add additional sub-commands + to the ds4510 command when defined. + + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> + +commit b6fc6fd49a84543e1324e1620b9f301ff7c1f27f +Author: Dirk Eibach <eibach@gdsys.de> +Date: Tue Dec 16 14:51:56 2008 +0100 + + common: Iteration limit for memory test. + + The iteration limit is passed to mtest as a fourth parameter: + [start [end [pattern [iterations]]]] + If no fourth parameter is supplied, there is no iteration limit and the + test will loop forever. + + Signed-off-by: Dirk Eibach <eibach@gdsys.de> + +commit 97cae3a4c68d856374ccc70fd2c5f8714cc94f7d +Author: Stefan Roese <sr@denx.de> +Date: Mon Dec 15 15:40:12 2008 +0100 + + serial: Rename driver vcth to vct to support other board variants + + Moved driver vcth.c to vct.c to better reflect the VCT board series. + This driver is now used by the VCT platforms: + + vct_premium + vct_platinum + vct_platinumsvc + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 36ede4d63e59c9277ec180b09c39b8bf46425ba2 +Author: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> +Date: Fri Dec 12 00:45:27 2008 +0900 + + nios: Move README.nios_CONFIG_SYS_NIOS_CPU to doc/ dir + + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> + +commit c3284b030b1cd492b4f46c576aea01bef258599d +Author: Peter Korsgaard <jacmet@sunsite.dk> +Date: Wed Dec 10 16:24:16 2008 +0100 + + common/main: support bootdelay=0 for CONFIG_AUTOBOOT_KEYED + + Support bootdelay=0 in abortboot for the CONFIG_AUTOBOOT_KEYED case + similar to the CONFIG_ZERO_BOOTDELAY_CHECK support for the + !CONFIG_AUTOBOOT_KEYED case. + + Do this by reversing the loop so we do at least one iteration before + checking for timeout. + + Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> + +commit 94f9279f7bbdc01bbc7cf85aedf9b545943b94c3 +Author: Niklaus Giger <niklaus.giger@netstal.com> +Date: Mon Dec 8 17:24:08 2008 +0100 + + Added legacy flash ST Micro M29W040B + +commit 626d07348e5f9f302f4ea182161a89f7362a0488 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Mon Dec 8 20:04:51 2008 +1100 + + Fixed off-by-one errors in lib_m68k/interrupts.c + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit a5989c42ae5e295f274a795c426c47819bbdbfda +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:29:05 2008 +1100 + + Removed all references to CONFIG_SYS_RESET_GENERIC + + Generic i386 reset - #define made redundant by weak function + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 2b5360eb2bc0b741ae5cb3c84d35ccdd17667c8a +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:29:04 2008 +1100 + + Remove #ifdef CONFIG_SC520 in source code + + CONFIG_SC520 is now used for conditional compile + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit ead056bc206f6b7ee6dc98766678b64635ea20b8 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:29:03 2008 +1100 + + Added MMCR reset functionality + + Reset function specific to AMD SC520 microcontroller - Is more of a + 'hard reset' that the triple fault. + + Requires CONFIG_SYS_RESET_SC520 to be defined in config + + I would have liked to add this to a new file (cpu/i386/sc520/reset.c) + but ld requires that a object file in a library arhive MUST contain + at least one function which does not override a weak function (and is + called from outside the object file) in order for that object file to + be extracted from the archive. This would be the only function on the + new file, and hence, will never get linked in. + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 3f5f18d12d32ee0661bf51dfc55752c005230d6e +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:29:02 2008 +1100 + + Moved generic (triple fault) reset code + + Moved from interrupts.c to cpu.c and made into a weak function to + allow vendor specific override + + Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be + added to the vendor specific code without the need to remember to + #undef usage of the generic method and if you forget to include your + custom reset method, you will always get the default. + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 9933d609020c297788f53f334c8465fa7a99b10c +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:29:01 2008 +1100 + + Moved definition of set_vector() to new header file + + This allows for future tidy ups and functionality that will require + set_vector () + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 407976185e0dda2c90e89027121a1071b9c77bfb +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:29:00 2008 +1100 + + Moved sc520 specific code into new cpu/i386/sc520 folder + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 85ffbbd51914925a542d8528be7f072e5ab02157 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:28:58 2008 +1100 + + Renamed cpu/i386/reset.S to resetvec.S + + Brings i386 in line with other CPUs with a reset vector and frees up reset.c + for CPU reset functions + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit a3f4c123f569474e80ea012b8db0de46afdb6443 +Author: Wolfgang Denk <wd@denx.de> +Date: Sat Jan 24 01:01:49 2009 +0100 + + Makefile: keep lists sorted. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit c620c01e96814558470698ed5cab1bf2f504d1b5 +Author: Graeme Russ <graeme.russ@gmail.com> +Date: Sun Dec 7 10:28:57 2008 +1100 + + Added initial eNET board support + + Signed-off-by: Graeme Russ <graeme.russ@gmail.com> + +commit 0c0ccf401ee03a5008fc2c19b05a662bce1a1086 +Author: Gary Jennejohn <garyj@denx.de> +Date: Thu Nov 20 11:37:26 2008 +0100 + + POWERPC 82xx: add the SCC as an HDLC controller + + Right now this is only used by keymile. + + Signed-off-by: Gary Jennejohn <garyj@denx.de> + +commit 1e8f4e78ca393b3d8e86bd8055758dd465d9113f +Author: Heiko Schocher <hs@denx.de> +Date: Thu Nov 20 09:59:09 2008 +0100 + + powerpc, keymile boards: extract identical config options + + This patch extracts the identical config options for the + keymile boards mgcoge, mgsuvd and kmeter1 in a new + common config file keymile-common.h. + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit 210c8c00aad3328145204adab434bb7d70b06b75 +Author: Heiko Schocher <hs@denx.de> +Date: Fri Nov 21 08:29:40 2008 +0100 + + powerpc: keymile: Add a check for the PIGGY debug board + + Check the presence of the PIGGY on the keymile boards mgcoge, + mgsuvd and kmeter1. If the PIGGY is not present, dont register + this Ethernet device. + + Signed-off-by: Heiko Schocher <hs@denx.de> + Acked-by: Ben Warren <biggerbadderben@gmail.com> + +commit de0443614af4d16675ab436665aeb11ddc9f7214 +Author: Heiko Schocher <hs@denx.de> +Date: Thu Nov 20 09:57:47 2008 +0100 + + powerpc: 83xx: add support for the kmeter1 board + + This patch adds support for the kmeter1 board from Keymile, + based on a Freescale MPC8360 CPU. + + - serial console on UART 1 + - 256 MB DDR2 RAM + - 64 MB NOR Flash + - Ethernet RMII Mode over UCC4 + - PHY SMSC LAN8700 + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit 3feb647f3fd0881382c7a29f4cf280b66473ae0a +Author: Sergei Poselenov <sposelenov@emcraft.com> +Date: Tue Nov 4 13:51:18 2008 +0100 + + Add a do_div() wrapper macro, lldiv(). + + Add a do_div() wrapper, lldiv(). The new inline function doesn't modify + the dividend and returns the result of division, so it is useful + in complex expressions, i.e. "return(a/b)" -> "return(lldiv(a,b))" + + Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> + +commit 18af1c5f0f7402dc0d6a71b012c68025dd97cf72 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Jan 23 14:22:14 2009 -0600 + + 85xx: Add a 36-bit physical configuration for MPC8572DS + + We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary + to allow for larger memory sizes. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit c51fc5d53c4560abc4d0a6126c06fc68133d1528 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Jan 23 14:22:13 2009 -0600 + + 85xx: Handle eLBC difference w/36-bit physical + + The eLBC only handles 32-bit physical address in systems with 36-bit + physical. The previos generation of LBC handled 34-bit physical + address in 36-bit systems. Added a new CONFIG option to convey + the difference between the LBC and eLBC. + + Also added defines for XAM bits used in LBC for the extended 34-bit + support. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 72a9414a8e21e9536822c7353bc08d21ce5ad53d +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Fri Jan 23 14:22:12 2009 -0600 + + 85xx: Use BR_ADDR macro for NAND chipselects + + Use the new BR_ADDR macro to properly setup the address field of the + localbus chipselects used by NAND. + + This allows us to deal with 36-bit phys on these boards in the future. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 2fc7eb0cfc608c9369001d57a0411af5e6a58f7c +Author: Haiying Wang <Haiying.Wang@freescale.com> +Date: Thu Jan 15 11:58:35 2009 -0500 + + Add secondary CPUs processor frequency for e500 core + + This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, + and prints each CPU's frequency separately. It also fixes up each CPU's + frequency in "clock-frequency" of fdt blob. + + Signed-off-by: James Yang <James.Yang@freescale.com> + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> + +commit bf5b1f0c0d28ce062e1d368680632dfb099de692 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Nov 21 16:31:53 2008 +0800 + + 85xx: enable the auto self refresh for wake up ARP + + The wake up ARP feature need use the memory to process + wake up packet, we enable auto self refresh to support it. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit b4983e16d150ab7d039704c310aacbd2f4dc1e0f +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Nov 21 16:31:43 2008 +0800 + + fsl-ddr: use the 1T timing as default configuration + + For light loaded system, we use the 1T timing to gain better + memory performance, but for some heavily loaded system, + you have to add the 2T timing options to board files. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 22cca7e1cd54590e967c73558b07ffbdccd39504 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Nov 21 16:31:35 2008 +0800 + + fsl-ddr: make the self refresh idle threshold configurable + + Some 85xx processors have the advanced power management feature, + such as wake up ARP, that needs enable the automatic self refresh. + + If the DDR controller pass the SR_IT (self refresh idle threshold) + idle cycles, it will automatically enter self refresh. However, + anytime one transaction is issued to the DDR controller, it will + reset the counter and exit self refresh state. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 22ff3d01348e0a2dc369b7efcbac30e4ce86d178 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Nov 21 16:31:29 2008 +0800 + + fsl-ddr: clean up the ddr code for DDR3 controller + + - The DDR3 controller is expanding the bits for timing config + - Add the DDR3 32-bit bus mode support + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Nov 21 16:31:22 2008 +0800 + + fsl-ddr: update the bit mask for DDR3 controller + + According to the latest 8572 UM, the DDR3 controller + is expanding the bit mask, and we use the extend ACTTOPRE + mode when tRAS more than 19 MCLK. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit aca5f018a8386b85469482ed9867e3e29a2437d0 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Dec 2 16:08:40 2008 -0600 + + 85xx: Introduce CONFIG_SYS_PCI*_IO_VIRT for FSL boards + + Introduce a new define to seperate out the virtual address that PCI + IO space is at from the physical address. In most situations these are + mapped 1:1. However any code accessing the bus should use VIRT. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 5af0fdd81c3370c3a51421208fda568bdcbbec23 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Dec 2 16:08:39 2008 -0600 + + 85xx: Introduce CONFIG_SYS_PCI*_MEM_VIRT for FSL boards + + Introduce a new define to seperate out the virtual address that PCI + memory is at from the physical address. In most situations these are + mapped 1:1. However any code accessing the bus should use VIRT. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit a6e04c344ad1eefd47a75484441b385da815b8df +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Dec 2 16:08:38 2008 -0600 + + 85xx: Use CONFIG_SYS_{PCI*,RIO*}_MEM_PHYS for physical address on FSL boards + + Use the _MEM_PHYS defines instead of _MEM_BUS for LAW and real address fields + of TLBs. This is what we should have always been using from the start. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 5f91ef6acdbadec33e0192049e2b24a1d9692f1d +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Dec 2 16:08:37 2008 -0600 + + 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boards + + Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead + of _IO_BASE so we are more explicit. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit 10795f42cb94e71bcb262b615084f69dd886399a +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Dec 2 16:08:36 2008 -0600 + + 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boards + + Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead + of _MEM_BASE so we are more explicit. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit c953ddfd56b3ae3f28910fe3aed6de6968d1c9aa +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Dec 2 14:19:34 2008 -0600 + + 85xx: separate FLASH BASE virtual from physical address + + Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and + maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. + + This allows us to deal with 36-bit phys on these boards in the future. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 52b565f5ad23b682489055b187767d8bf1c2e444 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Dec 2 14:19:33 2008 -0600 + + 85xx: separate PIXIS virtual from physical address + + Added a PIXIS_BASE_PHYS for use as the physical address and maintain + PIXIS_BASE as the virtual address of the PIXIS fpga registers. + + This allows us to deal with 36-bit phys on these boards in the future. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 30837e5b21d5a742983581ab9ee3fac085311d19 +Author: Haiying Wang <Haiying.Wang@freescale.com> +Date: Tue Nov 11 08:52:09 2008 -0500 + + Add README file for MPC8572DS board + + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> + Acked-by: Andy Fleming <afleming@freescale.com> + +commit 6dadc9195ad642cc662632f4d92f92d3d71e8bf2 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Mon Oct 20 16:15:04 2008 -0400 + + Blackfin: use common strmhz() in system output + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + +commit 5bb907a4925397789c90d074f4f7e92ce6b39402 +Author: Ron Madrid <ron_madrid@sbcglobal.net> +Date: Thu Jan 22 15:05:24 2009 -0800 + + mpc83xx: New board support for SIMPC8313 + + This patch will create a new board, SIMPC8313, from Sheldon Instruments. This + board boots from NAND devices and is configureable for either large or small + page devices. The board supports non-soldered DDR2, one ethernet port, a + Marvell 88E1118 PHY, and PCI host support. The board also has a FPGA connected + to the eLBC providing glue logic to a TMS320C67xx DSP. + + Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit d4bade8d77aa20e2846fa4accff0e7fa7961a134 +Author: Mike Frysinger <vapier@gentoo.org> +Date: Sun Jan 18 19:46:06 2009 -0500 + + nand: fixup printf modifiers to match types used + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 389e6620e2271096df3316917528003627db4021 +Author: Schlaegl Manfred jun <manfred.schlaegl@gmx.at> +Date: Tue Jan 20 16:57:55 2009 +0100 + + nand read.jffs2 (nand_legacy) in common/cmd_nand.c + + Error with CONFIG_NAND_LEGACY in common/cmd_nand.c: + With current code "nand read.jffs2s" (read and skip bad blocks) is always interpreted as + "nand read.jffs2" (read and fill bad blocks with 0xff). This is because ".jffs2" is + tested before ".jffs2s" and only the first two characters are compared. + + Correction: + Test for ".jffs2s" first and compare the first 7 characters. + + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 6c869637fef31e66380f0ea1d49690a2e26ec0d7 +Author: Wolfgang Grandegger <wg@grandegger.com> +Date: Fri Jan 16 18:55:54 2009 +0100 + + NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS + + This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and + changes the default from 8 to 1 for the legacy and the new MTD + NAND layer. This allows to remove all NAND_MAX_CHIPS definitions + in the board config files because none of the boards use multi + chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 + define + + #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE + + but that's bogus and did not work anyhow. + + Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit c70564e6b1bd08f3230182392238907f3531a87e +Author: Dave Liu <daveliu@freescale.com> +Date: Tue Dec 2 11:48:51 2008 +0800 + + NAND: Fix cache and memory inconsistency issue + + We load the secondary stage u-boot image from NAND to + system memory by nand_load, but we did not flush d-cache + to memory, nor invalidate i-cache before we jump to RAM. + When the system has cache enabled and the TLB/page attribute + of system memory is cacheable, it will cause issues. + + - 83xx family is using the d-cache lock, so all of d-cache + access is cache-inhibited. so you can't see the issue. + - 85xx family is using d-cache, i-cache enable, partial + cache lock. you will see the issue. + + This patch fixes the cache issue. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 50657c273278f74378e1ac39b41d612b92fdffa0 +Author: Nishanth Menon <menon.nishanth@gmail.com> +Date: Sat Dec 13 09:43:06 2008 -0600 + + NAND: Enable nand lock, unlock feature + + Enable nand lock, unlock and status of lock feature. + Not every device and platform requires this, hence, + it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK + + Nand unlock and status operate on block boundary instead + of page boundary. Details in: + http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT + + Intial solution provided by Vikram Pandita <vikram.pandita@ti.com> + Includes preliminary suggestions from Scott Wood + + Signed-off-by: Nishanth Menon <nm@ti.com> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 69fb8be4fc07162fdf6edf04bdc7233b0e9a920e +Author: Mike Frysinger <vapier@gentoo.org> +Date: Sat Dec 6 02:40:55 2008 -0500 + + NAND: move board_nand_init to nand.h + + Rather than putting the function prototype for board_nand_init() in the one + place where it gets called, put it into nand.h so that every place that also + defines it gets the prototype. Otherwise, errors can go silently unnoticed + such as using the wrong return value (void rather than int) when defining + the function. + + Signed-off-by: Mike Frysinger <vapier@gentoo.org> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 1ae39862044ebb1e682234b51f94421e3f871d6a +Author: Stefan Roese <sr@denx.de> +Date: Tue Dec 2 11:06:47 2008 +0100 + + OneNAND: Additional sync with 2.6.27 + + - Add subpage write support + - Add onenand_oob_64/32 ecclayout + + This has been missing and without it UBI has some incompatibilies issues + with the current (>= 2.6.27) Linux kernel version. vid_hdr_offset is + placed differently (2048 instead of 512) without this fix. + + Signed-off-by: Stefan Roese <sr@denx.de> + Signed-off-by: Scott Wood <scottwood@freescale.com> + +commit 1714f51a2009baaecf3d4f6e3bd8c4e93a8d3f23 +Author: Kyungmin Park <kmpark@infradead.org> +Date: Thu Nov 13 15:14:33 2008 +0900 + + Add markbad function + + Add missing markbad function + If not, it's hang when it entered the mtd->mark_bad(). + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit c438ea175d8d002c1063b7a94b0c0e26668d1ac9 +Author: Stefan Roese <sr@denx.de> +Date: Wed Nov 12 13:47:24 2008 +0100 + + OneNAND: Bad block aware read/write command support + + Update OneNAND command to support bad block awareness. + Also change the OneNAND command style to better match the + NAND version. + + Signed-off-by: Stefan Roese <sr@denx.de> + Acked-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit 8cf11f3aa78673730e9ecbbe4b75213b53f212c8 +Author: Stefan Roese <sr@denx.de> +Date: Tue Nov 11 10:29:09 2008 +0100 + + OneNAND: Save version_id in onenand_chip struct + + The version (ver_id) was not stored in the onenand_chip structure and + because of this the continuous locking scheme could be enabled on some + chips. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 4fca3310d611cc0f51d7295ef3557afbdbd91dc3 +Author: Stefan Roese <sr@denx.de> +Date: Tue Nov 11 10:28:53 2008 +0100 + + OneNAND: Fix compiler warnings + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 1ac5744e33ee0aa6d6ddab3b99f9e70953156e69 +Author: Dave Liu <daveliu@freescale.com> +Date: Tue Nov 4 14:55:06 2008 +0800 + + mpc83xx: enable eLBC NAND support for MPC8315ERDB board + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit ef0921d6b05aeb9034158f9bef5323d6da9c925e +Author: Kyungmin Park <kmpark@infradead.org> +Date: Tue Nov 4 09:24:07 2008 +0900 + + Sync with 2.6.27 + + Sync with OneNAND kernel codes + + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> + +commit e7f325be9edeb84bb457301776bbac1f7257dafc +Author: Michal Simek <monstr@monstr.eu> +Date: Mon Jan 5 13:35:31 2009 +0100 + + microblaze: Use cache functions (especially cache status) + in systems which are configured without flash + +commit e9b737deb2c30125362d20e24170617476026e94 +Author: Michal Simek <monstr@monstr.eu> +Date: Mon Jan 5 13:29:32 2009 +0100 + + microblaze: Add cache flush + +commit b4f8dda35bfad447b4106828232705b2e878d168 +Author: Michal Simek <monstr@monstr.eu> +Date: Mon Jan 5 13:28:40 2009 +0100 + + microblaze: Add bootup messages to board.c + +commit 330e55459bc9983341da6c1d5c7fe00a664436fe +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Dec 19 13:25:55 2008 +0100 + + microblaze: Change microblaze-generic config file + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 52a822ed9c37a2ea0ed112a26d8ff5a6cb1c6f10 +Author: Michal Simek <monstr@monstr.eu> +Date: Fri Dec 19 13:14:05 2008 +0100 + + microblaze: Rename ml401 to microblaze-generic + + Signed-off-by: Michal Simek <monstr@monstr.eu> + +commit 6677876181cc8772bca8a372479a500d160f3993 +Author: Scott Wood <scottwood@freescale.com> +Date: Tue Jan 20 11:56:11 2009 -0600 + + 83xx: Use the proper sequence for updating IMMR. + + This ensures that subsequent accesses properly hit the new window. + + The dcbi during the NAND loop was accidentally working around this; + it's no longer necessary, as the cache is not enabled. + + Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> + Signed-off-by: Scott Wood <scottwood@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 8b34557c546e5e9f34ebf83c93413dad973d93df +Author: Anton Vorontsov <avorontsov@ru.mvista.com> +Date: Thu Jan 8 04:26:19 2009 +0300 + + mpc83xx: Add PCI-E support for MPC837XEMDS boards + + MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card + provides two PCI-E (x2) ports. Though, only one port can be used in x2 + mode. Two ports can function simultaneously in x1 mode. + + PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. + + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 8f11e34b31a7be124a3239653f33af9510502045 +Author: Anton Vorontsov <avorontsov@ru.mvista.com> +Date: Thu Jan 8 04:26:17 2009 +0300 + + mpc83xx: Add PCI-E support for MPC8315ERDB boards + + MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's + support them. + + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit fd6646c0b9ebe7e5afc4ae4c78097d9cd317a5e8 +Author: Anton Vorontsov <avorontsov@ru.mvista.com> +Date: Thu Jan 8 04:26:12 2009 +0300 + + mpc83xx: Add support for MPC83xx PCI-E controllers + + This patch adds support for MPC83xx PCI-E controllers in Root Complex + mode. + + The patch is based on Tony Li and Dave Liu work[1]. + + Though unlike the original patch, by default we don't register PCI-E + buses for use in U-Boot, we only configure the controllers for future + use in other OSes (Linux). This is done because we don't have enough + of spare BATs to map all the PCI-E regions. + + To actually use PCI-E in U-Boot, users should explicitly define + CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And + only then U-Boot will able to access PCI-E, but at the cost of disabled + address translation. + + [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html + + Signed-off-by: Tony Li <tony.li@freescale.com> + Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> + Acked-by: Dave Liu <daveliu@freescale.com> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 88ecf55cabd7aea28fe8093720e208f53ccfdcf5 +Author: Ira Snyder <iws@ovro.caltech.edu> +Date: Mon Jan 12 13:33:17 2009 -0800 + + MPC8349EMDS: do not setup unused PCI clock outputs in PCI agent mode + + When running in PCI agent mode, the PCI_CLK_OUT signals are not used, so do + not enable them. See the MPC8349EA Reference Manual, Section 4.4.2 + "Clocking in PCI Agent Mode". + + Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 75f35209f702bb26826855ed8c8e4d108ab5f412 +Author: Ira Snyder <iws@ovro.caltech.edu> +Date: Mon Jan 12 13:32:26 2009 -0800 + + 83xx: PCI agent mode fixes for multi-board systems + + When running a system with 2 or more MPC8349EMDS boards in PCI agent mode, + the boards will lock up the PCI bus by scanning against each other. + + The boards lock against each other by trying to access the PCI bus before + clearing their configuration lock bit. Both boards end up in a loop, + sending and receiving "Target Not Ready" messages forever. + + When running in PCI agent mode, the scanning now takes place after the + boards have cleared their configuration lock bit. + + Also, add a missing declaration to the mpc83xx.h header file, fixing a + build warning. + + Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 455a46915b82896cc2070eb326d075555c2bc580 +Author: Ron Madrid <ron_madrid@sbcglobal.net> +Date: Fri Dec 12 13:12:45 2008 -0800 + + mpc83xx: Size optimization of start.S + + Currently there are in excess of 100 bytes located at the beginning of the image + built by start.S that are not being utilized. This patch moves a few functions + into this part of the image. This will create a greater number of *available* + bytes that can be used by board specific code in NAND builds and will decrease + the size of the assembled code in other builds. + + Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 72d15e705bc3983884105cb7755c7ba80e74a0a5 +Author: Wolfgang Denk <wd@denx.de> +Date: Wed Jan 21 23:08:12 2009 +0100 + + Prepare v2009.01 + + Signed-off-by: Wolfgang Denk <wd@denx.de> + commit 635e5f8fc82365e6e9734b3132bc95135a6de679 Author: Wolfgang Denk <wd@denx.de> Date: Sun Jan 18 21:37:48 2009 +0100 @@ -725,6 +1895,20 @@ Date: Wed Oct 29 12:39:26 2008 -0500 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> +commit 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb +Author: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> +Date: Wed Dec 17 16:43:18 2008 +0100 + + avr32: Remove second definition of virt_to_phys() + + The second definition introduced by 65e43a1063 conflicts with the + existing one. + + Also, convert the existing definition to use phys_addr_t. The volatile + qualifier is still needed due to brain damage elsewhere. + + Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> + commit b616f2b545f73757669b37386f0b37bb61fc6797 Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Date: Mon Sep 8 22:27:18 2008 +0200 @@ -2357,6 +3541,32 @@ Date: Mon Nov 24 15:11:08 2008 +0100 Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de> +commit 633639587e3596f0dbf5e6247dd3faf80b1d9063 +Author: Heiko Schocher <hs@denx.de> +Date: Thu Nov 20 09:59:09 2008 +0100 + + powerpc, keymile boards: extract identical config options + + This patch extracts the identical config options for the + keymile boards mgcoge, mgsuvd and kmeter1 in a new + common config file keymile-common.h. + + Signed-off-by: Heiko Schocher <hs@denx.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 9482a8e3d6ac766d90e5059dce777b1e4c868a30 +Author: Heiko Schocher <hs@denx.de> +Date: Fri Nov 21 08:29:40 2008 +0100 + + powerpc: keymile: Add a check for the PIGGY debug board + + Check the presence of the PIGGY on the keymile boards mgcoge, + mgsuvd and kmeter1. If the PIGGY is not present, dont register + this Ethernet device. + + Signed-off-by: Heiko Schocher <hs@denx.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + commit 58c696eed839af894e0265064669c402dc28b371 Author: Wolfgang Denk <wd@xpert.denx.de> Date: Mon Nov 24 21:50:59 2008 +0100 @@ -2631,6 +3841,24 @@ Date: Fri Nov 7 13:55:14 2008 +0100 Signed-off-by: Stelian Pop <stelian@popies.net> +commit fed36ac5ae613773b6cd90e61e292c45440e10c8 +Author: Heiko Schocher <hs@denx.de> +Date: Thu Nov 20 09:57:47 2008 +0100 + + powerpc: 83xx: add support for the kmeter1 board + + This patch adds support for the kmeter1 board from Keymile, + based on a Freescale MPC8360 CPU. + + - serial console on UART 1 + - 256 MB DDR2 RAM + - 64 MB NOR Flash + - Ethernet RMII Mode over UCC4 + - PHY SMSC LAN8700 + + Signed-off-by: Heiko Schocher <hs@denx.de> + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + commit 25fb4eaaeab3f8866020818f4729d990dcc91cf0 Author: Stefan Roese <sr@denx.de> Date: Thu Nov 20 11:46:20 2008 +0100 diff --git a/MAINTAINERS b/MAINTAINERS index fcc2043c7..88cf1e9ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -132,6 +132,7 @@ Jon Diekema <jon.diekema@smiths-aerospace.com> Dirk Eibach <eibach@gdsys.de> + gdppc440etx PPC440EP/GR neo PPC405EP Dave Ellis <DGE@sixnetio.com> @@ -668,6 +669,10 @@ Thomas Lange <thomas@corelatus.se> Vlad Lungu <vlad.lungu@windriver.com> qemu_mips MIPS32 +Stefan Roese <sr@denx.de> + + vct_xxx MIPS32 4Kc + ######################################################################### # Nios-32 Systems: # # # @@ -197,6 +197,7 @@ LIST_4xx=" \ EXBITGEN \ fx12mm \ G2000 \ + gdppc440etx \ glacier \ haleakala \ haleakala_nand \ @@ -615,6 +616,18 @@ LIST_arm=" \ LIST_mips4kc=" \ incaip \ qemu_mips \ + vct_platinum \ + vct_platinum_small \ + vct_platinum_onenand \ + vct_platinum_onenand_small \ + vct_platinumavc \ + vct_platinumavc_small \ + vct_platinumavc_onenand \ + vct_platinumavc_onenand_small \ + vct_premium \ + vct_premium_small \ + vct_premium_onenand \ + vct_premium_onenand_small \ " LIST_mips5kc=" \ @@ -317,7 +317,7 @@ $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(obj)u-boot.ldr: $(obj)u-boot - $(LDR) -T $(CONFIG_BFIN_CPU) -f -c $@ $< $(LDR_FLAGS) + $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) $(obj)u-boot.ldr.hex: $(obj)u-boot.ldr $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary @@ -1325,6 +1325,9 @@ fx12mm_config: unconfig G2000_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000 +gdppc440etx_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx gdppc440etx gdsys + hcu4_config: unconfig @mkdir -p $(obj)board/netstal/common @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal @@ -3057,6 +3060,41 @@ incaip_config: unconfig tb0229_config: unconfig @$(MKCONFIG) $(@:_config=) mips mips tb0229 +vct_premium_config \ +vct_premium_small_config \ +vct_premium_onenand_config \ +vct_premium_onenand_small_config \ +vct_platinum_config \ +vct_platinum_small_config \ +vct_platinum_onenand_config \ +vct_platinum_onenand_small_config \ +vct_platinumavc_config \ +vct_platinumavc_small_config \ +vct_platinumavc_onenand_config \ +vct_platinumavc_onenand_small_config: unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _premium,$@)" ] ; then \ + echo "#define CONFIG_VCT_PREMIUM" > $(obj)include/config.h ; \ + $(XECHO) "... on Premium board variant" ; \ + fi + @if [ "$(findstring _platinum_,$@)" ] ; then \ + echo "#define CONFIG_VCT_PLATINUM" > $(obj)include/config.h ; \ + $(XECHO) "... on Platinum board variant" ; \ + fi + @if [ "$(findstring _platinumavc,$@)" ] ; then \ + echo "#define CONFIG_VCT_PLATINUMAVC" > $(obj)include/config.h ; \ + $(XECHO) "... on PlatinumAVC board variant" ; \ + fi + @if [ "$(findstring _onenand,$@)" ] ; then \ + echo "#define CONFIG_VCT_ONENAND" >> $(obj)include/config.h ; \ + $(XECHO) "... on OneNAND board variant" ; \ + fi + @if [ "$(findstring _small,$@)" ] ; then \ + echo "#define CONFIG_VCT_SMALL_IMAGE" >> $(obj)include/config.h ; \ + $(XECHO) "... stripped down image variant" ; \ + fi + @$(MKCONFIG) -a vct mips mips vct micronas + ######################################################################### ## MIPS32 AU1X00 ######################################################################### @@ -1509,6 +1509,15 @@ The following options need to be configured: Bus on the MPC8260. But it should be not so difficult to add this option to other architectures. + CONFIG_SOFT_I2C_READ_REPEATED_START + + defining this will force the i2c_read() function in + the soft_i2c driver to perform an I2C repeated start + between writing the address pointer and reading the + data. If this define is omitted the default behaviour + of doing a stop-start sequence will be used. Most I2C + devices can use either method, but some require one or + the other. - SPI Support: CONFIG_SPI @@ -2036,6 +2045,9 @@ Configuration Settings: - CONFIG_SYS_LONGHELP: Defined when you want long help messages included; undefine this when you're short of memory. +- CONFIG_SYS_HELP_CMD_WIDTH: Defined when you want to override the default + width of the commands listed in the 'help' command output. + - CONFIG_SYS_PROMPT: This is what U-Boot prints on the console to prompt for user input. diff --git a/blackfin_config.mk b/blackfin_config.mk index c8be75e08..7bde44926 100644 --- a/blackfin_config.mk +++ b/blackfin_config.mk @@ -33,7 +33,11 @@ endif SYM_PREFIX = _ +LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE)) LDR_FLAGS += --use-vmas +ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) +LDR_FLAGS += --initcode $(obj)cpu/$(CPU)/initcode.o +endif ifneq (,$(findstring s,$(MAKEFLAGS))) LDR_FLAGS += --quiet endif diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c index d509a8fdb..02a095ef8 100644 --- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c +++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c @@ -144,7 +144,7 @@ int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) rcode = 0; break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); rcode = 1; break; } @@ -155,7 +155,7 @@ int do_vcimage (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( vcimage, 2, 0, do_vcimage, - "vcimage - loads an image to Display\n", + "loads an image to Display", "vcimage addr\n" ); diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c index 949af1802..6b955d835 100644 --- a/board/MAI/AmigaOneG3SE/cmd_boota.c +++ b/board/MAI/AmigaOneG3SE/cmd_boota.c @@ -122,7 +122,7 @@ int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_AMIGAONEG3SE) && defined(CONFIG_CMD_BSP) U_BOOT_CMD( boota, 3, 1, do_boota, - "boota - boot an Amiga kernel\n", + "boot an Amiga kernel", "address disk" ); #endif /* _CMD_BOOTA_H */ diff --git a/board/MAI/menu/cmd_menu.c b/board/MAI/menu/cmd_menu.c index 079f1ff16..2b97d2321 100644 --- a/board/MAI/menu/cmd_menu.c +++ b/board/MAI/menu/cmd_menu.c @@ -10,7 +10,7 @@ int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] ) #if defined(CONFIG_AMIGAONEG3SE) && defined(CONFIG_CMD_BSP) U_BOOT_CMD( menu, 1, 1, do_menu, - "menu - display BIOS setup menu\n", + "display BIOS setup menu", "" ); #endif diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c index 11450aabc..4f7dda0e3 100644 --- a/board/ads5121/ads5121_diu.c +++ b/board/ads5121/ads5121_diu.c @@ -79,7 +79,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, unsigned int addr; if (argc < 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -101,7 +101,7 @@ int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, U_BOOT_CMD( diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp, - "diufb init | addr - Init or Display BMP file\n", + "Init or Display BMP file", "init\n - initialize DIU\n" "addr\n - display bmp at address 'addr'\n" ); diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c index 052cf6184..d47cf1af5 100644 --- a/board/amcc/acadia/cmd_acadia.c +++ b/board/amcc/acadia/cmd_acadia.c @@ -45,7 +45,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int cpu_freq; if (argc < 3) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -96,6 +96,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( bootstrap, 3, 0, do_bootstrap, - "bootstrap - program the I2C bootstrap EEPROM\n", + "program the I2C bootstrap EEPROM", "<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n" ); diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c index b1f4a213d..30046fee3 100644 --- a/board/amcc/canyonlands/bootstrap.c +++ b/board/amcc/canyonlands/bootstrap.c @@ -99,7 +99,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) extern char console_buffer[]; if (argc < 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -190,6 +190,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( bootstrap, 2, 0, do_bootstrap, - "bootstrap - program the I2C bootstrap EEPROM\n", + "program the I2C bootstrap EEPROM", "<nand|nor> - strap to boot from NAND or NOR flash\n" ); diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c index ba71bd55c..2c2849b01 100644 --- a/board/amcc/katmai/cmd_katmai.c +++ b/board/amcc/katmai/cmd_katmai.c @@ -43,7 +43,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char pcixClock[4]; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -213,6 +213,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( bootstrap, 3, 1, do_bootstrap, - "bootstrap - program the serial device strap\n", + "program the serial device strap", "wrclk [prom0|prom1] - program the serial device strap\n" ); diff --git a/board/amcc/kilauea/cmd_pll.c b/board/amcc/kilauea/cmd_pll.c index 0f571fefe..6b38493e5 100644 --- a/board/amcc/kilauea/cmd_pll.c +++ b/board/amcc/kilauea/cmd_pll.c @@ -183,7 +183,7 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char c = '\0'; pll_freq_t pll_freq; if (argc < 2) { - printf("Usage: \n%s\n", cmdtp->usage); + cmd_usage(cmdtp); goto ret; } @@ -222,8 +222,8 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto ret; default: - printf("Invalid options" - "\n\nUsage: \n%s\n", cmdtp->usage); + printf("Invalid options\n\n"); + cmd_usage(cmdtp); goto ret; } @@ -237,7 +237,7 @@ ret: U_BOOT_CMD( pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, - "pllalter- change pll frequence \n", + "change pll frequence", "pllalter <selection> - change pll frequence \n\n\ ** New freq take effect after reset. ** \n\ ----------------------------------------------\n\ diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index de3e3d8b9..d2a3b9ec3 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -319,7 +319,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) l2cache_status() ? "ON" : "OFF"); return 0; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -329,7 +329,7 @@ int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) U_BOOT_CMD( l2cache, 2, 1, do_l2cache, - "l2cache - enable or disable L2 cache\n", + "enable or disable L2 cache", "[on, off]\n" " - enable or disable L2 cache\n" ); diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c index 0f571fefe..6b38493e5 100644 --- a/board/amcc/makalu/cmd_pll.c +++ b/board/amcc/makalu/cmd_pll.c @@ -183,7 +183,7 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char c = '\0'; pll_freq_t pll_freq; if (argc < 2) { - printf("Usage: \n%s\n", cmdtp->usage); + cmd_usage(cmdtp); goto ret; } @@ -222,8 +222,8 @@ do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto ret; default: - printf("Invalid options" - "\n\nUsage: \n%s\n", cmdtp->usage); + printf("Invalid options\n\n"); + cmd_usage(cmdtp); goto ret; } @@ -237,7 +237,7 @@ ret: U_BOOT_CMD( pllalter, CONFIG_SYS_MAXARGS, 1, do_pll_alter, - "pllalter- change pll frequence \n", + "change pll frequence", "pllalter <selection> - change pll frequence \n\n\ ** New freq take effect after reset. ** \n\ ----------------------------------------------\n\ diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c index 3402f84a3..6dfd8ba38 100644 --- a/board/amcc/sequoia/cmd_sequoia.c +++ b/board/amcc/sequoia/cmd_sequoia.c @@ -128,7 +128,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) extern char console_buffer[]; if (argc < 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -226,6 +226,6 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( bootstrap, 2, 0, do_bootstrap, - "bootstrap - program the I2C bootstrap EEPROM\n", + "program the I2C bootstrap EEPROM", "<nand|nor> - strap to boot from NAND or NOR flash\n" ); diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c index 3d042dfa7..6b68f3356 100644 --- a/board/amcc/taihu/lcd.c +++ b/board/amcc/taihu/lcd.c @@ -140,7 +140,7 @@ static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf("%s", cmdtp->usage); + cmd_usage(cmdtp); return 1; } lcd_puts(argv[1]); @@ -151,7 +151,7 @@ static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf("%s", cmdtp->usage); + cmd_usage(cmdtp); return 1; } lcd_putc((char)argv[1][0]); @@ -166,7 +166,7 @@ static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) char cur_addr; if (argc < 3) { - printf("%s", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -232,25 +232,25 @@ static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( lcd_cls, 1, 1, do_lcd_clear, - "lcd_cls - lcd clear display\n", + "lcd clear display", NULL ); U_BOOT_CMD( lcd_puts, 2, 1, do_lcd_puts, - "lcd_puts - display string on lcd\n", + "display string on lcd", "<string> - <string> to be displayed\n" ); U_BOOT_CMD( lcd_putc, 2, 1, do_lcd_putc, - "lcd_putc - display char on lcd\n", + "display char on lcd", "<char> - <char> to be displayed\n" ); U_BOOT_CMD( lcd_cur, 3, 1, do_lcd_cur, - "lcd_cur - shift cursor on lcd\n", + "shift cursor on lcd", "<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n" " <count> - 0..31\n" " <dir> - 0=backward 1=forward\n" diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index 6e9330f68..522437805 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -93,7 +93,7 @@ static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) U_BOOT_CMD ( sw2_stat, 1, 1, do_sw_stat, - "sw2_stat - show status of switch 2\n", + "show status of switch 2", NULL ); @@ -102,13 +102,13 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) int led_no; if (argc != 3) { - printf("%s", cmd_tp->usage); + cmd_usage(cmd_tp); return -1; } led_no = simple_strtoul(argv[1], NULL, 16); if (led_no != 1 && led_no != 2) { - printf("%s", cmd_tp->usage); + cmd_usage(cmd_tp); return -1; } @@ -123,7 +123,7 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) else gpio_write_bit(31, 0); } else { - printf("%s", cmd_tp->usage); + cmd_usage(cmd_tp); return -1; } @@ -132,7 +132,7 @@ static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[]) U_BOOT_CMD ( led_ctl, 3, 1, do_led_ctl, - "led_ctl - make led 1 or 2 on or off\n", + "make led 1 or 2 on or off", "<led_no> <on/off> - make led <led_no> on/off,\n" "\tled_no is 1 or 2\t" ); diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c index 52bad56bf..8e969056c 100644 --- a/board/amcc/taihu/update.c +++ b/board/amcc/taihu/update.c @@ -127,6 +127,6 @@ static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[] U_BOOT_CMD ( update_boot_eeprom, 1, 1, update_boot_eeprom, - "update_boot_eeprom - update boot eeprom content\n", + "update boot eeprom content", NULL ); diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c index 624ae40f6..e4d070570 100644 --- a/board/amcc/taishan/lcd.c +++ b/board/amcc/taishan/lcd.c @@ -167,7 +167,7 @@ static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf("%s", cmdtp->usage); + cmd_usage(cmdtp); return 1; } lcd_puts(argv[1]); @@ -176,7 +176,7 @@ static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf("%s", cmdtp->usage); + cmd_usage(cmdtp); return 1; } lcd_putc((char)argv[1][0]); @@ -189,7 +189,7 @@ static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) char cur_addr; if (argc < 3) { - printf("%s", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -254,16 +254,16 @@ static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } -U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd_test - lcd test display\n", NULL); -U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd_cls - lcd clear display\n", NULL); +U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", NULL); +U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", NULL); U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts, - "lcd_puts - display string on lcd\n", + "display string on lcd", "<string> - <string> to be displayed\n"); U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc, - "lcd_putc - display char on lcd\n", + "display char on lcd", "<char> - <char> to be displayed\n"); U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur, - "lcd_cur - shift cursor on lcd\n", + "shift cursor on lcd", "<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n" " <count> - 0~31\n" " <dir> - 0,backward; 1, forward\n"); @@ -373,8 +373,8 @@ static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(ledon, 1, 1, do_led_test_on, - "ledon - led test light on\n", NULL); + "led test light on", NULL); U_BOOT_CMD(ledoff, 1, 1, do_led_test_off, - "ledoff - led test light off\n", NULL); + "led test light off", NULL); #endif diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index 5b8b88e85..b471c956e 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -168,7 +168,7 @@ int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info, - "xbriinfo - Show PCIX bridge info\n", NULL); + "Show PCIX bridge info", NULL); #define TAISHAN_PCI_DEV_ID0 0x800 #define TAISHAN_PCI_DEV_ID1 0x1000 @@ -222,7 +222,7 @@ int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc, } U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info, - "xdevinfo - Show PCIX Device info\n", NULL); + "Show PCIX Device info", NULL); extern void show_reset_reg(void); @@ -233,4 +233,4 @@ int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info, - "resetinfo - Show Reset REG info\n", NULL); + "Show Reset REG info", NULL); diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c index 96b918be0..63f874488 100644 --- a/board/amcc/taishan/update.c +++ b/board/amcc/taishan/update.c @@ -74,5 +74,5 @@ int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom, - "update_boot_eeprom - update bootstrap eeprom content\n", NULL); + "update bootstrap eeprom content", NULL); #endif diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c index d9698602b..d2ca2572d 100644 --- a/board/amcc/yucca/cmd_yucca.c +++ b/board/amcc/yucca/cmd_yucca.c @@ -59,7 +59,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, char pcixClock[4]; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -281,6 +281,6 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag, U_BOOT_CMD( evb440spe, 3, 1, do_evb440spe, - "evb440spe - program the serial device strap\n", + "program the serial device strap", "wrclk [prom0|prom1] - program the serial device strap\n" ); diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c index e9f80ff5c..fcf26984f 100644 --- a/board/amirix/ap1000/ap1000.c +++ b/board/amirix/ap1000/ap1000.c @@ -659,7 +659,7 @@ done: } U_BOOT_CMD (temp, 6, 0, do_temp_sensor, - "temp - interact with the temperature sensor\n", + "interact with the temperature sensor", "temp [s]\n" " - Show status.\n" "temp l LOW [HIGH] [THERM]\n" @@ -674,28 +674,28 @@ U_BOOT_CMD (temp, 6, 0, do_temp_sensor, #if 0 U_BOOT_CMD (loadace, 2, 0, do_loadace, - "loadace - load fpga configuration from System ACE compact flash\n", + "load fpga configuration from System ACE compact flash", "N\n" " - Load configuration N (0-7) from System ACE compact flash\n" "loadace\n" " - loads default configuration\n"); #endif U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte, - "swconfig- display or modify the software configuration byte\n", + "display or modify the software configuration byte", "N [ADDRESS]\n" " - set software configuration byte to N, optionally use ADDRESS as\n" " location of buffer for flash copy\n" "swconfig\n" " - display software configuration byte\n"); U_BOOT_CMD (pause, 2, 0, do_pause, - "pause - sleep processor until any key is pressed with poll time of N seconds\n", + "sleep processor until any key is pressed with poll time of N seconds", "N\n" " - sleep processor until any key is pressed with poll time of N seconds\n" "pause\n" " - sleep processor until any key is pressed with poll time of 1 second\n"); U_BOOT_CMD (swrecon, 1, 0, do_swreconfig, - "swrecon - trigger a board reconfigure to the software selected configuration\n", + "trigger a board reconfigure to the software selected configuration", "\n" " - trigger a board reconfigure to the software selected configuration\n"); diff --git a/board/amirix/ap1000/powerspan.c b/board/amirix/ap1000/powerspan.c index f0481553f..f727061df 100644 --- a/board/amirix/ap1000/powerspan.c +++ b/board/amirix/ap1000/powerspan.c @@ -478,7 +478,7 @@ int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD (eeprom, 4, 0, do_eeprom, - "eeprom - read/write/copy to/from the PowerSpan II eeprom\n", + "read/write/copy to/from the PowerSpan II eeprom", "eeprom r OFF [NUM]\n" " - read NUM words starting at OFF\n" "eeprom w OFF VAL\n" diff --git a/board/barco/barco.c b/board/barco/barco.c index ed3557219..a19e1edab 100644 --- a/board/barco/barco.c +++ b/board/barco/barco.c @@ -292,7 +292,7 @@ int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { #if 0 if (argc > 1) { - printf ("Usage:\n (%d) %s\n", argc, cmdtp->usage); + cmd_usage(cmdtp); return 1; } #endif @@ -306,19 +306,19 @@ int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD ( try_working, 1, 1, barcobcd_boot_image, - " try_working - check flash value and boot the appropriate image\n", + "check flash value and boot the appropriate image", "\n" ); U_BOOT_CMD ( boot_working, 1, 1, barcobcd_boot_image, - " boot_working - check flash value and boot the appropriate image\n", + "check flash value and boot the appropriate image", "\n" ); U_BOOT_CMD ( boot_default, 1, 1, barcobcd_boot_image, - " boot_default - check flash value and boot the appropriate image\n", + "check flash value and boot the appropriate image", "\n" ); /* diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c index ae5061f94..aa46e5812 100644 --- a/board/bc3450/cmd_bc3450.c +++ b/board/bc3450/cmd_bc3450.c @@ -194,7 +194,7 @@ int cmd_dip (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD (dip, 1, 1, cmd_dip, - "dip - read dip switch and config inputs\n", + "read dip switch and config inputs", "\n" " - prints the state of the dip switch and/or\n" " external configuration inputs as hex value.\n" @@ -228,7 +228,7 @@ static int cmd_buz (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD (buz, 2, 1, cmd_buz, - "buz - turns buzzer on/off\n", + "turns buzzer on/off", "\n" "buz <on/off>\n" " - turns the buzzer on or off\n"); #endif /* CONFIG_BC3450_BUZZER */ @@ -322,7 +322,7 @@ static int cmd_fp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD (fp, 3, 1, cmd_fp, - "fp - front panes access functions\n", + "front panes access functions", "\n" "fp bl <on/off>\n" " - turns the CCFL backlight of the display on/off\n" @@ -523,7 +523,7 @@ static int cmd_temp (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD (temp, 3, 1, cmd_temp, - "temp - print current temperature\n", + "print current temperature", "\n" "temp\n" " - print current temperature\n"); #ifdef CONFIG_BC3450_CAN @@ -816,7 +816,7 @@ int cmd_test (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } -U_BOOT_CMD (test, 2, 1, cmd_test, "test - unit test routines\n", "\n" +U_BOOT_CMD (test, 2, 1, cmd_test, "unit test routines", "\n" #ifdef CONFIG_BC3450_CAN "test can\n" " - connect CAN1 (X8) with CAN2 (X9) for this test\n" diff --git a/board/bf533-ezkit/Makefile b/board/bf533-ezkit/Makefile index 6a45b7cb2..1260277a8 100644 --- a/board/bf533-ezkit/Makefile +++ b/board/bf533-ezkit/Makefile @@ -29,11 +29,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o flash.o +COBJS-y := $(BOARD).o flash.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index 42c4b5055..d5f0b7c68 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -1,7 +1,7 @@ /* - * U-boot - ezkit533.c + * U-boot - main board file * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -26,9 +26,8 @@ */ #include <common.h> -#if defined(CONFIG_MISC_INIT_R) #include "psd4256.h" -#endif +#include "flash-defines.h" DECLARE_GLOBAL_DATA_PTR; @@ -41,24 +40,11 @@ int checkboard(void) phys_size_t initdram(int board_type) { -#ifdef DEBUG - int brate; - char *tmp = getenv("baudrate"); - brate = simple_strtoul(tmp, NULL, 16); - printf("Serial Port initialized with Baud rate = %x\n", brate); - printf("SDRAM attributes:\n"); - printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" - "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", - 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); - printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); -#endif gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; } -#if defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ int misc_init_r(void) { @@ -71,4 +57,3 @@ int misc_init_r(void) return 0; } -#endif diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h index 1a4aa5f2f..eb0af9479 100644 --- a/board/bf533-ezkit/flash-defines.h +++ b/board/bf533-ezkit/flash-defines.h @@ -50,6 +50,7 @@ #define FLASH_SIZE 0x220000 #define FLASH_MAN_ST 2 #define CONFIG_SYS_FLASH0_BASE 0x20000000 +#define CONFIG_SYS_FLASH1_BASE 0x20200000 #define RESET_VAL 0xF0 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; @@ -68,9 +69,6 @@ int write_flash(long nOffset, int nValue); void get_sector_number(long lOffset, int *pnSector); int GetSectorProtectionStatus(flash_info_t * info, int nSector); int GetOffset(int nBlock); -int AFP_NumSectors = 40; -long AFP_SectorSize1 = 0x10000; -int AFP_SectorSize2 = 0x4000; #define WRITESEQ1 0x0AAA #define WRITESEQ2 0x0554 diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index a861e16a3..ab808d86b 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -29,6 +29,10 @@ #include <asm/io.h> #include "flash-defines.h" +int AFP_NumSectors = 40; +long AFP_SectorSize1 = 0x10000; +int AFP_SectorSize2 = 0x4000; + void flash_reset(void) { reset_flash(); @@ -123,7 +127,7 @@ void flash_print_info(flash_info_t * info) printf("ST Microelectronics "); break; default: - printf("Unknown Vendor: (0x%08X) ", info->flash_id); + printf("Unknown Vendor: (0x%08lX) ", info->flash_id); break; } for (i = 0; i < info->sector_count; ++i) { @@ -211,7 +215,7 @@ int write_data(long lStart, long lCount, uchar * pnData) read_flash(ulOffset, &d); if (d != 0xffff) { printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", + ("Flash not erased at offset 0x%lx Please erase to reprogram\n", ulOffset); return FLASH_FAIL; } @@ -230,7 +234,7 @@ int write_data(long lStart, long lCount, uchar * pnData) read_flash(ulOffset, &d); if (d != 0xffff) { printf - ("Flash not erased at offset 0x%x Please erase to reprogram \n", + ("Flash not erased at offset 0x%lx Please erase to reprogram\n", ulOffset); return FLASH_FAIL; } diff --git a/board/bf533-stamp/Makefile b/board/bf533-stamp/Makefile index 5ae022885..a03fe89af 100644 --- a/board/bf533-stamp/Makefile +++ b/board/bf533-stamp/Makefile @@ -1,7 +1,7 @@ # # U-boot - Makefile # -# Copyright (c) 2005-2007 Analog Device Inc. +# Copyright (c) 2005-2008 Analog Device Inc. # # (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -29,11 +29,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o spi_flash.o +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o +COBJS-$(CONFIG_VIDEO) += video.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 0c6324b4b..44ebc9319 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -49,43 +49,28 @@ int checkboard(void) phys_size_t initdram(int board_type) { -#ifdef DEBUG - printf("SDRAM attributes:\n"); - printf - (" tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; " - "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11), - (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2)); - printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); - printf("Bank size = %d MB\n", 128); -#endif gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return (gd->bd->bi_memsize); + return gd->bd->bi_memsize; } +/* PF0 and PF1 are used to switch between the ethernet and flash: + * PF0 PF1 + * flash: 0 0 + * ether: 1 0 + */ void swap_to(int device_id) { - - if (device_id == ETHERNET) { - *pFIO_DIR = PF0; - SSYNC(); - *pFIO_FLAG_S = PF0; - SSYNC(); - } else if (device_id == FLASH) { - *pFIO_DIR = (PF4 | PF3 | PF2 | PF1 | PF0); - *pFIO_FLAG_S = (PF4 | PF3 | PF2); - *pFIO_MASKA_D = (PF8 | PF6 | PF5); - *pFIO_MASKB_D = (PF7); - *pFIO_POLAR = (PF8 | PF6 | PF5); - *pFIO_EDGE = (PF8 | PF7 | PF6 | PF5); - *pFIO_INEN = (PF8 | PF7 | PF6 | PF5); - *pFIO_FLAG_D = (PF4 | PF3 | PF2); - SSYNC(); - } else { - printf("Unknown bank to switch\n"); - } - - return; + bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); + SSYNC(); + bfin_write_FIO_FLAG_C(PF1); + if (device_id == ETHERNET) + bfin_write_FIO_FLAG_S(PF0); + else if (device_id == FLASH) + bfin_write_FIO_FLAG_C(PF0); + else + printf("Unknown device to switch\n"); + SSYNC(); } #if defined(CONFIG_MISC_INIT_R) @@ -113,9 +98,6 @@ int misc_init_r(void) if (cf_stat) { printf("Booting from COMPACT flash\n"); - /* Set cycle time for CF */ - *(volatile unsigned long *)ambctl1 = CF_AMBCTL1VAL; - for (i = 0; i < 0x1000; i++) asm("nop;"); for (i = 0; i < 0x1000; i++) diff --git a/board/bf533-stamp/bf533-stamp.h b/board/bf533-stamp/bf533-stamp.h index 3b0d620b3..ebd39c773 100644 --- a/board/bf533-stamp/bf533-stamp.h +++ b/board/bf533-stamp/bf533-stamp.h @@ -34,9 +34,6 @@ extern volatile unsigned long *ambctl0; extern volatile unsigned long *ambctl1; extern volatile unsigned long *amgctl; -extern unsigned long pll_div_fact; -extern void serial_setbrg(void); - /* Definitions used in Compact Flash Boot support */ #define FIO_EDGE_CF_BITS 0x0000 #define FIO_POLAR_CF_BITS 0x0000 diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c new file mode 100644 index 000000000..3c15eaa76 --- /dev/null +++ b/board/bf533-stamp/video.c @@ -0,0 +1,167 @@ +/* + * BF533-STAMP splash driver + * + * Copyright (c) 2006-2008 Analog Devices Inc. + * (C) Copyright 2000 + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it + * (C) Copyright 2002 + * Wolfgang Denk, wd@denx.de + * + * Licensed under the GPL-2 or later. + */ + +#include <stdarg.h> +#include <common.h> +#include <config.h> +#include <malloc.h> +#include <asm/blackfin.h> +#include <asm/mach-common/bits/dma.h> +#include <i2c.h> +#include <linux/types.h> +#include <devices.h> + +int gunzip(void *, int, unsigned char *, unsigned long *); + +#define DMA_SIZE16 2 + +#include <asm/mach-common/bits/ppi.h> + +#define NTSC_FRAME_ADDR 0x06000000 +#include "video.h" + +/* NTSC OUTPUT SIZE 720 * 240 */ +#define VERTICAL 2 +#define HORIZONTAL 4 + +int is_vblank_line(const int line) +{ + /* + * This array contains a single bit for each line in + * an NTSC frame. + */ + if ((line <= 18) || (line >= 264 && line <= 281) || (line == 528)) + return true; + + return false; +} + +int NTSC_framebuffer_init(char *base_address) +{ + const int NTSC_frames = 1; + const int NTSC_lines = 525; + char *dest = base_address; + int frame_num, line_num; + + for (frame_num = 0; frame_num < NTSC_frames; ++frame_num) { + for (line_num = 1; line_num <= NTSC_lines; ++line_num) { + unsigned int code; + int offset = 0; + int i; + + if (is_vblank_line(line_num)) + offset++; + + if (line_num > 266 || line_num < 3) + offset += 2; + + /* Output EAV code */ + code = system_code_map[offset].eav; + write_dest_byte((char)(code >> 24) & 0xff); + write_dest_byte((char)(code >> 16) & 0xff); + write_dest_byte((char)(code >> 8) & 0xff); + write_dest_byte((char)(code) & 0xff); + + /* Output horizontal blanking */ + for (i = 0; i < 67 * 2; ++i) { + write_dest_byte(0x80); + write_dest_byte(0x10); + } + + /* Output SAV */ + code = system_code_map[offset].sav; + write_dest_byte((char)(code >> 24) & 0xff); + write_dest_byte((char)(code >> 16) & 0xff); + write_dest_byte((char)(code >> 8) & 0xff); + write_dest_byte((char)(code) & 0xff); + + /* Output empty horizontal data */ + for (i = 0; i < 360 * 2; ++i) { + write_dest_byte(0x80); + write_dest_byte(0x10); + } + } + } + + return dest - base_address; +} + +void fill_frame(char *Frame, int Value) +{ + int *OddPtr32; + int OddLine; + int *EvenPtr32; + int EvenLine; + int i; + int *data; + int m, n; + + /* fill odd and even frames */ + for (OddLine = 22, EvenLine = 285; OddLine < 263; OddLine++, EvenLine++) { + OddPtr32 = (int *)((Frame + (OddLine * 1716)) + 276); + EvenPtr32 = (int *)((Frame + (EvenLine * 1716)) + 276); + for (i = 0; i < 360; i++, OddPtr32++, EvenPtr32++) { + *OddPtr32 = Value; + *EvenPtr32 = Value; + } + } + + for (m = 0; m < VERTICAL; m++) { + data = (int *)u_boot_logo.data; + for (OddLine = (22 + m), EvenLine = (285 + m); + OddLine < (u_boot_logo.height * VERTICAL) + (22 + m); + OddLine += VERTICAL, EvenLine += VERTICAL) { + OddPtr32 = (int *)((Frame + ((OddLine) * 1716)) + 276); + EvenPtr32 = + (int *)((Frame + ((EvenLine) * 1716)) + 276); + for (i = 0; i < u_boot_logo.width / 2; i++) { + /* enlarge one pixel to m x n */ + for (n = 0; n < HORIZONTAL; n++) { + *OddPtr32++ = *data; + *EvenPtr32++ = *data; + } + data++; + } + } + } +} + +static void video_init(char *NTSCFrame) +{ + NTSC_framebuffer_init(NTSCFrame); + fill_frame(NTSCFrame, BLUE); + + bfin_write_PPI_CONTROL(0x0082); + bfin_write_PPI_FRAME(0x020D); + + bfin_write_DMA0_START_ADDR(NTSCFrame); + bfin_write_DMA0_X_COUNT(0x035A); + bfin_write_DMA0_X_MODIFY(0x0002); + bfin_write_DMA0_Y_COUNT(0x020D); + bfin_write_DMA0_Y_MODIFY(0x0002); + bfin_write_DMA0_CONFIG(0x1015); + bfin_write_PPI_CONTROL(0x0083); +} + +int drv_video_init(void) +{ + device_t videodev; + + video_init((void *)NTSC_FRAME_ADDR); + + memset(&videodev, 0, sizeof(videodev)); + strcpy(videodev.name, "video"); + videodev.ext = DEV_EXT_VIDEO; + videodev.flags = DEV_FLAGS_SYSTEM; + + return device_register(&videodev); +} diff --git a/board/bf533-stamp/video.h b/board/bf533-stamp/video.h new file mode 100644 index 000000000..80837e232 --- /dev/null +++ b/board/bf533-stamp/video.h @@ -0,0 +1,25 @@ +#include <video_logo.h> +#define write_dest_byte(val) {*dest++=val;} +#define BLACK (0x01800180) /* black pixel pattern */ +#define BLUE (0x296E29F0) /* blue pixel pattern */ +#define RED (0x51F0515A) /* red pixel pattern */ +#define MAGENTA (0x6ADE6ACA) /* magenta pixel pattern */ +#define GREEN (0x91229136) /* green pixel pattern */ +#define CYAN (0xAA10AAA6) /* cyan pixel pattern */ +#define YELLOW (0xD292D210) /* yellow pixel pattern */ +#define WHITE (0xFE80FE80) /* white pixel pattern */ + +#define true 1 +#define false 0 + +typedef struct { + unsigned int sav; + unsigned int eav; +} system_code_type; + +const system_code_type system_code_map[] = { + { 0xFF000080, 0xFF00009D }, + { 0xFF0000AB, 0xFF0000B6 }, + { 0xFF0000C7, 0xFF0000DA }, + { 0xFF0000EC, 0xFF0000F1 }, +}; diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile index e5ef9af5c..cb38b96a3 100644 --- a/board/bf537-stamp/Makefile +++ b/board/bf537-stamp/Makefile @@ -29,11 +29,13 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o post-memory.o spi_flash.o cmd_bf537led.o nand.o +COBJS-y := $(BOARD).o post-memory.o cmd_bf537led.o +COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o +COBJS-$(CONFIG_CMD_NAND) += nand.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 7303f1b41..63992f609 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -100,21 +100,9 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words) phys_size_t initdram(int board_type) { -#ifdef DEBUG - int brate; - char *tmp = getenv("baudrate"); - brate = simple_strtoul(tmp, NULL, 16); - printf("Serial Port initialized with Baud rate = %x\n", brate); - printf("SDRAM attributes:\n"); - printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" - "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", - 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); - printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); -#endif gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; } #if defined(CONFIG_MISC_INIT_R) diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c index fa650f26f..e77bb0cb1 100644 --- a/board/bf537-stamp/cmd_bf537led.c +++ b/board/bf537-stamp/cmd_bf537led.c @@ -196,6 +196,6 @@ void show_cmd_usage() /* Register information for u-boot to find this command */ U_BOOT_CMD(led, 3, 1, do_bf537led, - "led- Control BF537 stamp LEDs\n", USAGE_LONG); + "Control BF537 stamp LEDs", USAGE_LONG); #endif diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c index 20a7d0ef4..181e83d6a 100644 --- a/board/bf537-stamp/nand.c +++ b/board/bf537-stamp/nand.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 Aubrey.Li, aubrey.li@analog.com + * Copyright (c) 2006-2007 Analog Devices Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,8 +23,6 @@ #include <common.h> #include <asm/io.h> -#if defined(CONFIG_CMD_NAND) - #include <nand.h> #define CONCAT(a,b,c,d) a ## b ## c ## d @@ -43,11 +41,11 @@ static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) u32 IO_ADDR_W = (u32) this->IO_ADDR_W; if (ctrl & NAND_CTRL_CHANGE) { - if( ctrl & NAND_CLE ) + if (ctrl & NAND_CLE) IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE; else IO_ADDR_W = CONFIG_SYS_NAND_BASE; - if( ctrl & NAND_ALE ) + if (ctrl & NAND_ALE) IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE; else IO_ADDR_W = CONFIG_SYS_NAND_BASE; @@ -100,4 +98,3 @@ int board_nand_init(struct nand_chip *nand) return 0; } -#endif diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c index 889aa5c4f..9626f4cd7 100644 --- a/board/bf537-stamp/post-memory.c +++ b/board/bf537-stamp/post-memory.c @@ -21,10 +21,10 @@ int post_init_sdram(int sclk); void post_init_uart(int sclk); const int pll[CCLK_NUM][SCLK_NUM][2] = { - {{20, 4}, {20, 5}, {20, 10}}, /* CCLK = 500M */ - {{16, 4}, {16, 5}, {16, 8}}, /* CCLK = 400M */ - {{8, 2}, {8, 4}, {8, 5}}, /* CCLK = 200M */ - {{4, 1}, {4, 2}, {4, 4}} /* CCLK = 100M */ + { {20, 4}, {20, 5}, {20, 10} }, /* CCLK = 500M */ + { {16, 4}, {16, 5}, {16, 8} }, /* CCLK = 400M */ + { {8, 2}, {8, 4}, {8, 5} }, /* CCLK = 200M */ + { {4, 1}, {4, 2}, {4, 4} } /* CCLK = 100M */ }; const char *const log[CCLK_NUM][SCLK_NUM] = { {"CCLK-500MHz SCLK-125MHz: Writing...\0", @@ -119,7 +119,8 @@ void post_out_buff(char *buff) { int i = 0; - for (i = 0; i < 0x80000; i++) ; + for (i = 0; i < 0x80000; i++) + ; i = 0; while ((buff[i] != '\0') && (i != 100)) { while (!(*pUART_LSR & 0x20)) ; @@ -127,7 +128,8 @@ void post_out_buff(char *buff) SSYNC(); i++; } - for (i = 0; i < 0x80000; i++) ; + for (i = 0; i < 0x80000; i++) + ; } /* Using sw10-PF5 as the hotkey */ @@ -150,9 +152,8 @@ int post_key_pressed(void) value = 0; goto key_pressed; } - if (value != 0) { + if (value != 0) goto key_pressed; - } for (n = 0; n < KEY_DELAY; n++) asm("nop"); } @@ -164,9 +165,8 @@ int post_key_pressed(void) value = 0; goto key_pressed; } - if (value != 0) { + if (value != 0) goto key_pressed; - } for (n = 0; n < KEY_DELAY; n++) asm("nop"); } @@ -178,9 +178,8 @@ int post_key_pressed(void) value = 0; goto key_pressed; } - if (value != 0) { + if (value != 0) goto key_pressed; - } for (n = 0; n < KEY_DELAY; n++) asm("nop"); } diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c index 11a2803e6..99caa96c4 100644 --- a/board/bf537-stamp/spi_flash.c +++ b/board/bf537-stamp/spi_flash.c @@ -182,8 +182,8 @@ static struct manufacturer_info flash_manufacturers[] = { * BF533, BF561: SSEL2 */ #ifndef CONFIG_SPI_FLASH_SSEL -# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \ - defined(__ADSPBF533__) || defined(__ADSPBF561__) +# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) # define CONFIG_SPI_FLASH_SSEL 2 # else # define CONFIG_SPI_FLASH_SSEL 1 @@ -797,8 +797,8 @@ int eeprom_info(void) ret = 1; else printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n" - "Parameters: num sectors = %i, sector size = %i, write size = %i\n" - "Flash Size: %i mbit (%i mbyte)\n" + "Parameters: num sectors = %lu, sector size = %lu, write size = %i\n" + "Flash Size: %lu mbit (%lu mbyte)\n" "Status: 0x%02X\n", flash.flash->name, flash.manufacturer_id, flash.manufacturer->name, flash.device_id1, flash.device_id2, flash.num_sectors, diff --git a/board/bf561-ezkit/Makefile b/board/bf561-ezkit/Makefile index e7ee24356..daebb7457 100644 --- a/board/bf561-ezkit/Makefile +++ b/board/bf561-ezkit/Makefile @@ -29,11 +29,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o +COBJS-y := $(BOARD).o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 7f8598c71..5aede174d 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -39,19 +39,7 @@ int checkboard(void) phys_size_t initdram(int board_type) { -#ifdef DEBUG - int brate; - char *tmp = getenv("baudrate"); - brate = simple_strtoul(tmp, NULL, 16); - printf("Serial Port initialized with Baud rate = %x\n", brate); - printf("SDRAM attributes:\n"); - printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" - "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", - 3, 3, 6, 2, 3); - printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); - printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); -#endif gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; - return CONFIG_SYS_MAX_RAM_SIZE; + return gd->bd->bi_memsize; } diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c index 00f0671d7..52f031cbb 100644 --- a/board/cm5200/cmd_cm5200.c +++ b/board/cm5200/cmd_cm5200.c @@ -435,7 +435,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( fkt, 4, 1, cmd_fkt, - "fkt - Function test routines\n", + "Function test routines", "i2c\n" " - Test I2C communication\n" "fkt led\n" diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index abf60b35b..bf36f7360 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -52,6 +52,7 @@ int board_init(void) lpsc_on(DAVINCI_LPSC_UART0); lpsc_on(DAVINCI_LPSC_TIMER1); lpsc_on(DAVINCI_LPSC_GPIO); + lpsc_on(DAVINCI_LPSC_USB); #if !defined(CONFIG_SYS_USE_DSPLINK) /* Powerup the DSP */ @@ -101,3 +102,26 @@ int misc_init_r(void) return(0); } + +#ifdef CONFIG_USB_DAVINCI + +/* IO Expander I2C address and USB VBUS enable mask */ +#define IOEXP_I2C_ADDR 0x3A +#define IOEXP_VBUSEN_MASK 1 + +/* + * This function enables USB VBUS by writting to IO expander using I2C. + * Note that the I2C is already initialized at this stage. This + * function is used by davinci specific USB wrapper code. + */ +void enable_vbus(void) +{ + uchar data; /* IO Expander data to enable VBUS */ + + /* Write to IO expander to enable VBUS */ + i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1); + data &= ~IOEXP_VBUSEN_MASK; + i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1); +} +#endif + diff --git a/board/delta/delta.c b/board/delta/delta.c index 878416f73..73e6c3e37 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -259,7 +259,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", + "read keyboard status", NULL ); diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S index eef631854..1664f3ba1 100644 --- a/board/delta/lowlevel_init.S +++ b/board/delta/lowlevel_init.S @@ -74,7 +74,7 @@ mem_init: /* 3. wait nop power up waiting period (200ms) * optimization: Steps 4+6 can be done during this */ - wait #300 + wait #0x300 /* 4. Perform an initial Rcomp-calibration cycle */ ldr r0, =RCOMP diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index 3abcfe690..c4b4b6767 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -247,7 +247,7 @@ int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( digtest, 3, 1, do_digtest, - "digtest - Test digital in-/output\n", + "Test digital in-/output", NULL ); @@ -341,7 +341,7 @@ int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( anatest, 2, 1, do_anatest, - "anatest - Test analog in-/output\n", + "Test analog in-/output", NULL ); @@ -408,7 +408,7 @@ int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( inctest, 3, 1, do_inctest, - "inctest - Test incremental encoder inputs\n", + "Test incremental encoder inputs", NULL ); #endif diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 5709d4504..d0ee19329 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -198,7 +198,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", + "Enable / disable / query EEPROM write access", NULL); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 633f64178..4ea373a7c 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -550,7 +550,7 @@ int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( autoupd, 1, 1, auto_update, - "autoupd - Automatically update images\n", + "Automatically update images", NULL ); #endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index ad490c349..0a6626e07 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -123,7 +123,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( loadpci, 1, 1, do_loadpci, - "loadpci - Wait for pci bootcmd and boot it\n", + "Wait for pci bootcmd and boot it", NULL ); diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 1eea59ecb..066df74bf 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -346,7 +346,7 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *str; #endif if (argc != 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -372,6 +372,6 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( esdbmp, 2, 1, do_esdbmp, - "esdbmp - display BMP image\n", + "display BMP image", "<imageAddr> - display image\n" ); diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c index 318f229fe..9b2cf90d4 100644 --- a/board/esd/common/xilinx_jtag/micro.c +++ b/board/esd/common/xilinx_jtag/micro.c @@ -1859,6 +1859,6 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( cpld, 1, 1, do_cpld, - "cpld - Program onboard CPLD\n", + "Program onboard CPLD", NULL ); diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index dcab9060b..517b1740a 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -176,7 +176,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", + "Enable / disable / query EEPROM write access", NULL ); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index bd569a629..0aca825c1 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -689,7 +689,7 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( onewire, 1, 1, do_onewire, - "onewire - Read 1-write ID\n", + "Read 1-write ID", NULL ); @@ -750,7 +750,7 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( getbpip, 1, 1, do_get_bpip, - "getbpip - Update IP-Address with Backplane IP-Address\n", + "Update IP-Address with Backplane IP-Address", NULL ); @@ -786,7 +786,7 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( setbpip, 2, 1, do_set_bpip, - "setbpip - Write Backplane IP-Address\n", + "Write Backplane IP-Address", NULL ); diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index 6eedb83ff..b6b50fb46 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -294,5 +294,5 @@ int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(writepci, 3, 1, do_writepci, - "writepci- Write some data to pcibus\n", + "Write some data to pcibus", "<addr> <size>\n" " - Write some data to pcibus.\n"); diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 70bae60c6..482663398 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -993,6 +993,6 @@ int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( show_config, 1, 1, do_show_config, - "show_config - Show Marvell strapping register\n", + "Show Marvell strapping register", "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n" ); diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index 36dd58c3e..f405be948 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -220,14 +220,14 @@ int do_pci9054 (cmd_tbl_t * cmdtp, int flag, int argc, return 0; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( pci9054, 3, 1, do_pci9054, - "pci9054 - PLX PCI9054 EEPROM access\n", + "PLX PCI9054 EEPROM access", "pci9054 info - print EEPROM values\n" "pci9054 update - updates EEPROM with default values\n" ); diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 2f97a1262..f9b91b593 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -606,7 +606,7 @@ int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dcf77, 1, 1, do_dcf77, - "dcf77 - Check DCF77 receiver\n", + "Check DCF77 receiver", NULL ); @@ -656,7 +656,7 @@ int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( hubinit, 1, 1, do_hubinit, - "hubinit - Initialize USB hub\n", + "Initialize USB hub", NULL ); #endif /* CONFIG_I2C_MULTI_BUS */ @@ -789,7 +789,7 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( sbe, 2, 0, do_setup_boot_eeprom, - "sbe - setup boot eeprom\n", + "setup boot eeprom", NULL ); @@ -863,7 +863,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", + "Enable / disable / query EEPROM write access", NULL); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ @@ -914,7 +914,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( wpi, 1, 1, do_waitpwrirq, - "wpi - Wait for power change interrupt\n", + "Wait for power change interrupt", NULL ); @@ -959,7 +959,7 @@ int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dviinit, 1, 1, do_dviinit, - "dviinit - Initialize DVI Panellink transmitter\n", + "Initialize DVI Panellink transmitter", NULL ); @@ -999,7 +999,7 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( time, CONFIG_SYS_MAXARGS, 1, do_time, - "time - run command and output execution time\n", + "run command and output execution time", NULL ); @@ -1049,6 +1049,6 @@ int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo, - "gfxdemo - demo\n", + "demo", NULL ); diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index efadf1646..ae3bc80aa 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -733,7 +733,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", + "Enable / disable / query EEPROM write access", NULL); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c index f83dfe870..db2c54842 100644 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ b/board/esd/ocrtc/cmd_ocrtc.c @@ -54,7 +54,7 @@ int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( setdevice, 1, 1, do_setdevice, - "setdevice - Set device number on pci adapter boards\n", + "Set device number on pci adapter boards", NULL ); @@ -77,7 +77,7 @@ int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( getdevice, 1, 1, do_getdevice, - "getdevice - Get device number and set slot env variable\n", + "Get device number and set slot env variable", NULL ); diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index f558a2bc6..a0d1f3f0d 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -108,7 +108,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( loadpci, 1, 1, do_loadpci, - "loadpci - Wait for pci-image and boot it\n", + "Wait for pci-image and boot it", NULL ); #endif diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 42774ad20..0602abf9c 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -375,7 +375,7 @@ int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( wpeeprom, 2, 1, do_wpeeprom, - "wpeeprom - Check/Enable/Disable I2C EEPROM write protection\n", + "Check/Enable/Disable I2C EEPROM write protection", "wpeeprom\n" " - check I2C EEPROM write protection state\n" "wpeeprom 1\n" diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index f7962afa5..f225f0e19 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -294,7 +294,7 @@ int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return (0); } -U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "poweroff- Switch off power\n", NULL); +U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", NULL); int phypower(int flag) { @@ -338,7 +338,7 @@ int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(phypower, 2, 2, do_phypower, - "phypower- Switch power of ethernet phy\n", NULL); + "Switch power of ethernet phy", NULL); int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { @@ -369,5 +369,5 @@ int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(writepci, 3, 1, do_writepci, - "writepci- Write some data to pcibus\n", + "Write some data to pcibus", "<addr> <size>\n" " - Write some data to pcibus.\n"); diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 85057a268..7c0aaa2e3 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -333,6 +333,6 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", + "Enable / disable / query EEPROM write access", NULL); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index c0781dc95..975b6d6d9 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -203,6 +203,6 @@ int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( cantest, 3, 1, do_cantest, - "cantest - Test CAN controller", + "Test CAN controller", NULL ); diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 16c9c7eea..7808d4d17 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -98,7 +98,7 @@ int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( waithci, 1, 1, do_waithci, - "waithci - Wait for host control interrupt\n", + "Wait for host control interrupt", NULL ); @@ -258,7 +258,7 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( fifo, 5, 1, do_fifo, - "fifo - Fifo module operations\n", + "Fifo module operations", "wait\nfifo read\n" "fifo write fifo(0..3) data [cnt=1]\n" "fifo write address(>=4) data [cnt=1]\n" @@ -336,7 +336,7 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] } U_BOOT_CMD( sbe, 4, 0, do_setup_bootstrap_eeprom, - "sbe - setup bootstrap eeprom\n", + "setup bootstrap eeprom", "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]" ); @@ -399,7 +399,7 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( painit, 1, 1, do_painit, - "painit - prepare PciAccess system\n", + "prepare PciAccess system", NULL ); #endif /* CONFIG_PRAM */ @@ -411,7 +411,7 @@ int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( selfreset, 1, 1, do_selfreset, - "selfreset- assert self-reset# signal\n", + "assert self-reset# signal", NULL ); @@ -448,7 +448,7 @@ int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( resetout, 2, 1, do_resetout, - "resetout - assert PMC-RESETOUT# signal\n", + "assert PMC-RESETOUT# signal", NULL ); @@ -480,7 +480,7 @@ int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( inta, 2, 1, do_inta, - "inta - Assert/Deassert or query INTA# state in non-monarch mode\n", + "Assert/Deassert or query INTA# state in non-monarch mode", NULL ); @@ -513,7 +513,7 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( pmm, 2, 1, do_pmm, - "pmm - Setup pmm[1] registers\n", + "Setup pmm[1] registers", "<pciaddr> (pciaddr will be aligned to 256MB)\n" ); @@ -549,7 +549,7 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return state; } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", + "Enable / disable / query EEPROM write access", NULL); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c index 64e6d6329..80ff2376b 100644 --- a/board/esd/tasreg/tasreg.c +++ b/board/esd/tasreg/tasreg.c @@ -248,7 +248,7 @@ int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( iploop, 2, 1, do_iploop, - "iploop - iprobe loop <addr>\n", + "iprobe loop <addr>", NULL ); @@ -301,7 +301,7 @@ int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( codec, 1, 1, do_codec, - "codec - Enable codec\n", + "Enable codec", NULL ); @@ -334,7 +334,7 @@ int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( saa, 5, 1, do_saa, - "saa - Write to SAA1064 <addr> <instr> <cntrl> <data>\n", + "Write to SAA1064 <addr> <instr> <cntrl> <data>", NULL ); @@ -373,7 +373,7 @@ int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( iwrite, 6, 1, do_iwrite, - "iwrite - Write n bytes to I2C-device\n", + "Write n bytes to I2C-device", "addr cnt data0 ... datan\n" ); @@ -405,7 +405,7 @@ int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( iread, 3, 1, do_iread, - "iread - Read from I2C <addr> <cnt>\n", + "Read from I2C <addr> <cnt>", NULL ); @@ -443,7 +443,7 @@ int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( ireadl, 2, 1, do_ireadl, - "ireadl - Read-loop from I2C <addr>\n", + "Read-loop from I2C <addr>", NULL ); #endif diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index ec65ffd43..5480105b4 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -392,6 +392,6 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "eepwren - Enable / disable / query EEPROM write access\n", + "Enable / disable / query EEPROM write access", NULL); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/evb64260/zuma_pbb.c b/board/evb64260/zuma_pbb.c index 1d0357093..aef9c27e7 100644 --- a/board/evb64260/zuma_pbb.c +++ b/board/evb64260/zuma_pbb.c @@ -202,19 +202,19 @@ do_zuma_init_mbox (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( zinit, 1, 0, do_zuma_init_pbb, - "zinit - init zuma pbb\n", + "init zuma pbb", "\n" " - init zuma pbb\n" ); U_BOOT_CMD( zdtest, 3, 1, do_zuma_test_dma, - "zdtest - run dma test\n", + "run dma test", "[cmd [count]]\n" " - run dma cmd (w=0,v=1,cp=2,cmp=3,wi=4,vi=5), count bytes\n" ); U_BOOT_CMD( zminit, 1, 0, do_zuma_init_mbox, - "zminit - init zuma mbox\n", + "init zuma mbox", "\n" " - init zuma mbox\n" ); diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 96820ac60..eb76d937f 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -280,7 +280,7 @@ int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, U_BOOT_CMD( diswd, 1, 0, pixis_disable_watchdog_cmd, - "diswd - Disable watchdog timer \n", + "Disable watchdog timer", NULL); #ifdef CONFIG_PIXIS_SGMII_CMD @@ -539,7 +539,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd, - "pixis_reset - Reset the board using the FPGA sequencer\n", + "Reset the board using the FPGA sequencer", " pixis_reset\n" " pixis_reset [altbank]\n" " pixis_reset altbank wd\n" diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index eb58c7fd5..988cb94aa 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -328,7 +328,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) prog_eeprom(); break; default: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); break; } @@ -362,7 +362,7 @@ int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; case 'h': /* help */ default: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); break; } diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 1e2e2dc13..eb805007b 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -37,6 +37,7 @@ #include <fdt_support.h> #include <tsec.h> #include <netdev.h> +#include <sata.h> #include "../common/pixis.h" #include "../common/sgmii_riser.h" @@ -582,15 +583,15 @@ get_board_ddr_clk(ulong dummy) } #endif -int is_sata_supported(void) +int sata_initialize(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint sdrs2_io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; if (sdrs2_io_sel & 0x04) - return 0; + return 1; - return 1; + return __sata_initialize(); } int board_eth_init(bd_t *bis) diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index cd25d4aa8..2b2d5d7ec 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -116,7 +116,7 @@ int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp, unsigned int addr; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -138,7 +138,7 @@ int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp, U_BOOT_CMD( diufb, CONFIG_SYS_MAXARGS, 1, mpc8610diu_init_show_bmp, - "diufb init | addr - Init or Display BMP file\n", + "Init or Display BMP file", "init\n - initialize DIU\n" "addr\n - display bmp at address 'addr'\n" ); diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index 48fc643dc..b35038dc4 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -185,7 +185,7 @@ int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dumpebc, 1, 1, do_dumpebc, - "dumpebc - Dump all EBC registers\n", + "Dump all EBC registers", NULL ); @@ -207,7 +207,7 @@ int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dumpdcr, 1, 1, do_dumpdcr, - "dumpdcr - Dump all DCR registers\n", + "Dump all DCR registers", NULL ); @@ -271,7 +271,7 @@ int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( dumpspr, 1, 1, do_dumpspr, - "dumpspr - Dump all SPR registers\n", + "Dump all SPR registers", NULL ); #endif diff --git a/board/gdsys/gdppc440etx/Makefile b/board/gdsys/gdppc440etx/Makefile new file mode 100644 index 000000000..b93f2c389 --- /dev/null +++ b/board/gdsys/gdppc440etx/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/gdsys/gdppc440etx/config.mk b/board/gdsys/gdppc440etx/config.mk new file mode 100644 index 000000000..045f3e98b --- /dev/null +++ b/board/gdsys/gdppc440etx/config.mk @@ -0,0 +1,44 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# G&D 440EP/GR ETX-Module +# + +#TEXT_BASE = 0x00001000 + +ifeq ($(ramsym),1) +TEXT_BASE = 0xFBD00000 +else +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 +endif diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c new file mode 100644 index 000000000..a66105743 --- /dev/null +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -0,0 +1,323 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * Based on board/amcc/yosemite/yosemite.c + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* info for FLASH chips */ +extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +int board_early_init_f(void) +{ + register uint reg; + + /* + * Setup the external bus controller/chip selects + */ + mfebc(xbcfg, reg); + mtebc(xbcfg, reg | 0x04000000); /* Set ATC */ + + /* + * Setup the GPIO pins + */ + + /* setup Address lines for flash size 64Meg. */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x54000000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x54000000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x54000000); + + /* setup emac */ + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55); + out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000); + out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000); + + /* UART0 and UART1*/ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x16000000); + out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x02180000); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00400000); + out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x04010000); + + /* disable boot-eeprom WP */ + out32(GPIO0_OSRL, in32(GPIO0_OSRL) & ~0x00C00000); + out32(GPIO0_TSRL, in32(GPIO0_TSRL) & ~0x00C00000); + out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) & ~0x00C00000); + out32(GPIO0_TCR, in32(GPIO0_TCR) | 0x08000000); + out32(GPIO0_OR, in32(GPIO0_OR) & ~0x08000000); + + /* external interrupts IRQ0...3 */ + out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000); + out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500); + out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500); + + + /* + * Setup the interrupt controller polarities, triggers, etc. + */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */ + mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */ + mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */ + mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + /* + * Setup other serial configuration + */ + mfsdr(sdr_pci0, reg); + mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ + mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + + return 0; +} + +int misc_init_r(void) +{ + uint pbcr; + int size_val; + uint sz; + + /* Re-do sizing to get full correct info */ + mfebc(pb0cr, pbcr); + + if (gd->bd->bi_flashsize > 0x08000000) + panic("Max. flash banksize is 128 MB!\n"); + + for (sz = gd->bd->bi_flashsize, size_val = 7; + ((sz & 0x08000000) == 0) && (size_val > 0); --size_val) + sz <<= 1; + + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(pb0cr, pbcr); + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CONFIG_SYS_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: GDPPC440ETX - G&D PPC440EP/GR ETX-module"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} + +/* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + */ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /* + * Set priority for all PLB3 devices to 0. + * Set PLB3 arbiter to fair mode. + */ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /* + * Set priority for all PLB4 devices to 0. + */ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /* + * Set Nebula PLB4 arbiter to fair mode. + */ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + /* enable 66 MHz ext. Clock */ + out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); + out32(GPIO1_OR, in32(GPIO1_OR) | 0x00008000); + + return 1; +} +#endif /* defined(CONFIG_PCI) */ + +/* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /* + * Set up Direct MMIO registers + */ + + /* + * PowerPC440 EP PCI Master configuration. + * Map one 1Gig range of PLB/processor addresses to PCI memory space. + * PLB address 0xA0000000-0xDFFFFFFF + * ==> PCI address 0xA0000000-0xDFFFFFFF + * Use byte reversed out routines to handle endianess. + * Make this region non-prefetchable. + */ + out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIX0_PMM0PCIHA, 0x00000000); + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIX0_PMM1PCIHA, 0x00000000); + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); + out32r(PCIX0_PTM1LA, 0); + out32r(PCIX0_PTM2MS, 0); + out32r(PCIX0_PTM2LA, 0); + + /* + * Set up Configuration registers + */ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CONFIG_SYS_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ + +/* + * pci_master_init + * + */ +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /* + * Write the PowerPC440 EP PCI Configuration regs. + * Enable PowerPC440 EP to be a master on the PCI bus (PMM). + * Enable PowerPC440 EP to act as a PCI memory target (PTM). + */ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ + +/* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + */ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + return 1; +} +#endif /* defined(CONFIG_PCI) */ diff --git a/board/gdsys/gdppc440etx/init.S b/board/gdsys/gdppc440etx/init.S new file mode 100644 index 000000000..0bbd45a62 --- /dev/null +++ b/board/gdsys/gdppc440etx/init.S @@ -0,0 +1,75 @@ +/* +* (C) Copyright 2008 +* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de +* +* based on board/amcc/yosemite/init.S +* original Copyright not specified there +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 59 Temple Place, Suite 330, Boston, +* MA 02111-1307 USA +*/ + +#include <ppc_asm.tmpl> +#include <config.h> + +#include <asm/mmu.h> + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use + * the speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, + 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, + 0, AC_R|AC_W|AC_X|SA_G ) + + tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, + 0, AC_R|AC_W|AC_X|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, + 0, AC_R|AC_W|SA_G|SA_I ) + + /* PCI */ + tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, + 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, + 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/gdsys/gdppc440etx/u-boot.lds b/board/gdsys/gdppc440etx/u-boot.lds new file mode 100644 index 000000000..1df817b9e --- /dev/null +++ b/board/gdsys/gdppc440etx/u-boot.lds @@ -0,0 +1,144 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + board/gdsys/gdppc440etx/init.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c index 1848bb3fc..092d36844 100644 --- a/board/hymod/bsp.c +++ b/board/hymod/bsp.c @@ -272,12 +272,12 @@ do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) break; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( fpga, 6, 1, do_fpga, - "fpga - FPGA sub-system\n", + "FPGA sub-system", "load [type] addr size\n" " - write the configuration data at memory address `addr',\n" " size `size' bytes, into the FPGA of type `type' (either\n" @@ -324,7 +324,7 @@ do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* fall through ... */ default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -336,7 +336,7 @@ do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( eeclear, 1, 0, do_eecl, - "eeclear - Clear the eeprom on a Hymod board \n", + "Clear the eeprom on a Hymod board", "[type]\n" " - write zeroes into the EEPROM on the board of type `type'\n" " (`type' is either `main' or `mezz' - default `main')\n" diff --git a/board/keymile/common/keymile_hdlc_enet.c b/board/keymile/common/keymile_hdlc_enet.c index 141371b8f..57978800f 100644 --- a/board/keymile/common/keymile_hdlc_enet.c +++ b/board/keymile/common/keymile_hdlc_enet.c @@ -590,7 +590,7 @@ int hdlc_enet_stest(struct cmd_tbl_s *a, int b, int c, char **d) } U_BOOT_CMD( stest, 1, 1, hdlc_enet_stest, - "stest - simple send test for hdlc_enet\n", + "simple send test for hdlc_enet", "no arguments\n" ); /* simple receive test routine */ @@ -612,7 +612,7 @@ int hdlc_enet_rtest(struct cmd_tbl_s *a, int b, int c, char **d) } U_BOOT_CMD( rtest, 1, 1, hdlc_enet_rtest, - "rtest - simple receive test for hdlc_enet\n", + "simple receive test for hdlc_enet", "no arguments\n" ); #endif diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c index 878752c66..1b665a918 100644 --- a/board/lwmon/lwmon.c +++ b/board/lwmon/lwmon.c @@ -846,12 +846,12 @@ int do_pic (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) default: break; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( pic, 4, 1, do_pic, - "pic - read and write PIC registers\n", + "read and write PIC registers", "read reg - read PIC register `reg'\n" "pic write reg val - write value `val' to PIC register `reg'\n" ); @@ -910,7 +910,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", + "read keyboard status", NULL ); @@ -976,13 +976,13 @@ int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) default: break; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( lsb, 2, 1, do_lsb, - "lsb - check and set LSB switch\n", + "check and set LSB switch", "on - switch LSB on\n" "lsb off - switch LSB off\n" "lsb - print current setting\n" diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c index 0a8787a91..bafd39c62 100644 --- a/board/lwmon5/kbd.c +++ b/board/lwmon5/kbd.c @@ -432,7 +432,7 @@ int do_kbd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", + "read keyboard status", NULL ); diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index aa62f3790..4c04b9841 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -467,7 +467,7 @@ void hw_watchdog_reset(void) int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -476,7 +476,7 @@ int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else if ((strcmp(argv[1], "off") == 0)) { gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0); } else { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -486,7 +486,7 @@ int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( eepromwp, 2, 0, do_eeprom_wp, - "eepromwp- eeprom write protect off/on\n", + "eeprom write protect off/on", "<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n" ); diff --git a/board/micronas/vct/Makefile b/board/micronas/vct/Makefile new file mode 100644 index 000000000..2737ade0e --- /dev/null +++ b/board/micronas/vct/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-y += ebi.o +COBJS-$(CONFIG_VCT_NOR) += ebi_nor_flash.o +COBJS-$(CONFIG_VCT_ONENAND) += ebi_onenand.o +COBJS-$(CONFIG_DRIVER_SMC911X) += ebi_smc911x.o smc_eeprom.o +COBJS-y += gpio.o +COBJS-y += top.o +COBJS-$(CONFIG_USB_EHCI_VCT) += dcgu.o ehci.o scc.o + +COBJS := $(sort $(COBJS-y)) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/micronas/vct/bcu.h b/board/micronas/vct/bcu.h new file mode 100644 index 000000000..cac31f21f --- /dev/null +++ b/board/micronas/vct/bcu.h @@ -0,0 +1,170 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BCU_H +#define _BCU_H + +enum bcu_tags { + BCU_VBV1 = 0, + BCU_VBV2 = 1, + BCU_BSS1 = 2, + BCU_BSS2 = 3, + BCU_TSD_TXT = 4, + BCU_TSD_SUBTITLES = 5, + BCU_TSD_PES_0 = 6, + BCU_TSD_PES_1 = 7, + BCU_TSD_PES_2 = 8, + BCU_TSD_PES_3 = 9, + BCU_TSIO_RECORD_0 = 10, + BCU_TSIO_RECORD_1 = 11, + BCU_TSIO_PLAYBACK_0 = 12, + BCU_TSIO_PLAYBACK_1 = 13, + BCU_SECURE_BUFFER = 14, + BCU_PCM1 = 15, + BCU_PCM2 = 16, + BCU_BSS_COPY = 17, + BCU_BSS_EXT1 = 18, + BCU_BSS_EXT2 = 19, + BCU_PCM_JINGLE = 20, + BCU_EBI_CPU_BUFFER = 21, + BCU_PCM_DELAY = 22, + BCU_FH_BUFFER_0 = 23, + BCU_FH_BUFFER_1 = 24, + BCU_TSD_SECTION_0 = 25, + BCU_TSD_SECTION_1 = 26, + BCU_TSD_SECTION_2 = 27, + BCU_TSD_SECTION_3 = 28, + BCU_TSD_SECTION_4 = 29, + BCU_TSD_SECTION_5 = 30, + BCU_TSD_SECTION_6 = 31, + BCU_TSD_SECTION_7 = 32, + BCU_TSD_SECTION_8 = 33, + BCU_TSD_SECTION_9 = 34, + BCU_TSD_SECTION_10 = 35, + BCU_TSD_SECTION_11 = 36, + BCU_TSD_SECTION_12 = 37, + BCU_TSD_SECTION_13 = 38, + BCU_TSD_SECTION_14 = 39, + BCU_TSD_SECTION_15 = 40, + BCU_TSD_SECTION_16 = 41, + BCU_TSD_SECTION_17 = 42, + BCU_TSD_SECTION_18 = 43, + BCU_TSD_SECTION_19 = 44, + BCU_TSD_SECTION_20 = 45, + BCU_TSD_SECTION_21 = 46, + BCU_TSD_SECTION_22 = 47, + BCU_TSD_SECTION_23 = 48, + BCU_TSD_SECTION_24 = 49, + BCU_TSD_SECTION_25 = 50, + BCU_TSD_SECTION_26 = 51, + BCU_TSD_SECTION_27 = 52, + BCU_TSD_SECTION_28 = 53, + BCU_TSD_SECTION_29 = 54, + BCU_TSD_SECTION_30 = 55, + BCU_TSD_SECTION_31 = 56, + BCU_TSD_SECTION_32 = 57, + BCU_TSD_SECTION_33 = 58, + BCU_TSD_SECTION_34 = 59, + BCU_TSD_SECTION_35 = 60, + BCU_TSD_SECTION_36 = 61, + BCU_TSD_SECTION_37 = 62, + BCU_TSD_SECTION_38 = 63, + BCU_TSD_SECTION_39 = 64, + BCU_TSD_SECTION_40 = 65, + BCU_TSD_SECTION_41 = 66, + BCU_TSD_SECTION_42 = 67, + BCU_TSD_SECTION_43 = 68, + BCU_TSD_SECTION_44 = 69, + BCU_TSD_SECTION_45 = 70, + BCU_TSD_SECTION_46 = 71, + BCU_TSD_SECTION_47 = 72, + BCU_TSD_SECTION_48 = 73, + BCU_TSD_SECTION_49 = 74, + BCU_TSD_SECTION_50 = 75, + BCU_TSD_SECTION_51 = 76, + BCU_TSD_SECTION_52 = 77, + BCU_TSD_SECTION_53 = 78, + BCU_TSIO_RECORD_2 = 79, + BCU_TSIO_RECORD_3 = 80, + BCU_TSIO_RECORD_4 = 81, + BCU_TSIO_RECORD_5 = 82, + BCU_TSIO_RECORD_6 = 83, + BCU_TSIO_RECORD_7 = 84, + BCU_TSIO_RECORD_8 = 85, + BCU_TSIO_RECORD_9 = 86, + BCU_PCM_DELAY_LINEAR = 87, + BCU_VD_MASTER_USER_DATA = 88, + BCU_VD_SLAVE_USER_DATA = 89, + BCU_VD_MASTER_REF0 = 90, + BCU_VD_MASTER_REF1 = 91, + BCU_VD_SLAVE_REF0 = 92, + BCU_VD_SLAVE_REF1 = 93, + BCU_VD_MASTER_DISP0_Y = 94, + BCU_VD_MASTER_DISP1_Y = 95, + BCU_VD_MASTER_DISP2_Y = 96, + BCU_VD_MASTER_DISP0_C = 97, + BCU_VD_MASTER_DISP1_C = 98, + BCU_VD_MASTER_DISP2_C = 99, + BCU_VD_SLAVE_DISP0_Y = 100, + BCU_VD_SLAVE_DISP1_Y = 101, + BCU_VD_SLAVE_DISP2_Y = 102, + BCU_VD_SLAVE_DISP0_C = 103, + BCU_VD_SLAVE_DISP1_C = 104, + BCU_VD_SLAVE_DISP2_C = 105, + BCU_CLUT_BUFFER_0 = 106, + BCU_CLUT_BUFFER_1 = 107, + BCU_OSD_FRAME_BUFFER_0 = 108, + BCU_OSD_FRAME_BUFFER_1 = 109, + BCU_GRAPHIC_FRAME_BUFFER0 = 110, + BCU_GRAPHIC_FRAME_BUFFER1 = 111, + BCU_DVP_VBI_REINSERTION = 112, + BCU_DVP_OSD_FRAME_BUFFER0 = 113, + BCU_DVP_OSD_FRAME_BUFFER1 = 114, + BCU_GAI_BUFFER = 115, + BCU_GA_SRC_BUFFER_0 = 116, + BCU_GA_SRC_BUFFER_1 = 117, + BCU_USB_BUFFER_0 = 118, + BCU_USB_BUFFER_1 = 119, + BCU_FE_3DCOMB_0 = 120, + BCU_FE_3DCOMB_1 = 121, + BCU_FE_3DCOMB_2 = 122, + BCU_FE_3DCOMB_3 = 123, + BCU_TNR_BUFFER_0 = 124, + BCU_TNR_BUFFER_1 = 125, + BCU_TNR_BUFFER_2 = 126, + BCU_MVAL_BUFFER = 127, + BCU_RC_BUFFER_0 = 128, + BCU_RC_BUFFER_1 = 129, + BCU_RC_BUFFER_2 = 130, + BCU_RC_BUFFER_3 = 131, + BCU_PIP_BUFFER_0 = 132, + BCU_PIP_BUFFER_1 = 133, + BCU_PIP_BUFFER_2 = 134, + BCU_PIP_BUFFER_3 = 135, + BCU_EWARP_BUFFER = 136, + BCU_OSD_BUFFER_0 = 137, + BCU_OSD_BUFFER_1 = 138, + BCU_GLOBAL_BUFFER_0 = 139, + BCU_GLOBAL_BUFFER_1 = 140, + BCU_MAX = 141 +}; + +#endif /* _BCU_H */ diff --git a/board/micronas/vct/config.mk b/board/micronas/vct/config.mk new file mode 100644 index 000000000..2a71dad66 --- /dev/null +++ b/board/micronas/vct/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# vct_xxx boards with MIPS 4Kc CPU core +# + +sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0x87000000 +endif diff --git a/board/micronas/vct/dcgu.c b/board/micronas/vct/dcgu.c new file mode 100644 index 000000000..b2e86b72e --- /dev/null +++ b/board/micronas/vct/dcgu.c @@ -0,0 +1,258 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Original Author Guenter Gebhardt + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> + +#include "vct.h" + +int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup) +{ + u32 enable; + union dcgu_clk_en1 en1; + union dcgu_clk_en2 en2; + + switch (setup) { + case DCGU_SWITCH_ON: + enable = 1; + break; + case DCGU_SWITCH_OFF: + enable = 0; + break; + default: + printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__, + setup); + return -EINVAL; + } + + if (module == DCGU_HW_MODULE_CPU) + en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); + else + en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); + + switch (module) { + case DCGU_HW_MODULE_MSMC: + en1.bits.en_clkmsmc = enable; + break; + case DCGU_HW_MODULE_SSI_S: + en1.bits.en_clkssi_s = enable; + break; + case DCGU_HW_MODULE_SSI_M: + en1.bits.en_clkssi_m = enable; + break; + case DCGU_HW_MODULE_SMC: + en1.bits.en_clksmc = enable; + break; + case DCGU_HW_MODULE_EBI: + en1.bits.en_clkebi = enable; + break; + case DCGU_HW_MODULE_USB_PLL: + en1.bits.en_usbpll = enable; + break; + case DCGU_HW_MODULE_USB_60: + en1.bits.en_clkusb60 = enable; + break; + case DCGU_HW_MODULE_USB_24: + en1.bits.en_clkusb24 = enable; + break; + case DCGU_HW_MODULE_UART_2: + en1.bits.en_clkuart2 = enable; + break; + case DCGU_HW_MODULE_UART_1: + en1.bits.en_clkuart1 = enable; + break; + case DCGU_HW_MODULE_PERI: + en1.bits.en_clkperi20 = enable; + break; + case DCGU_HW_MODULE_CPU: + en2.bits.en_clkcpu = enable; + break; + case DCGU_HW_MODULE_I2S: + en1.bits.en_clk_i2s_dly = enable; + break; + case DCGU_HW_MODULE_ABP_SCC: + en1.bits.en_clk_scc_abp = enable; + break; + case DCGU_HW_MODULE_SPDIF: + en1.bits.en_clk_dtv_spdo = enable; + break; + case DCGU_HW_MODULE_AD: + en1.bits.en_clkad = enable; + break; + case DCGU_HW_MODULE_MVD: + en1.bits.en_clkmvd = enable; + break; + case DCGU_HW_MODULE_TSD: + en1.bits.en_clktsd = enable; + break; + case DCGU_HW_MODULE_GA: + en1.bits.en_clkga = enable; + break; + case DCGU_HW_MODULE_DVP: + en1.bits.en_clkdvp = enable; + break; + case DCGU_HW_MODULE_MR2: + en1.bits.en_clkmr2 = enable; + break; + case DCGU_HW_MODULE_MR1: + en1.bits.en_clkmr1 = enable; + break; + default: + printf("%s:%i:Invalid hardware module: %i\n", __FILE__, + __LINE__, module); + return -EINVAL; + } + + /* + * The reg_read() following the reg_write() below forces the write to + * be really done on the bus. + * Otherwise the clock may not be switched on when this API function + * returns, which may cause an bus error if a registers of the hardware + * module connected to the clock is accessed. + */ + if (module == DCGU_HW_MODULE_CPU) { + reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg); + en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE)); + } else { + reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg); + en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); + } + + return 0; +} + +int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup) +{ + union dcgu_reset_unit1 val; + u32 enable; + + switch (setup) { + case DCGU_SWITCH_ON: + enable = 1; + break; + case DCGU_SWITCH_OFF: + enable = 0; + break; + default: + printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__, + setup); + return -EINVAL; + } + + val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE)); + switch (module) { + case DCGU_HW_MODULE_MSMC: + val.bits.swreset_clkmsmc = enable; + break; + case DCGU_HW_MODULE_SSI_S: + val.bits.swreset_clkssi_s = enable; + break; + case DCGU_HW_MODULE_SSI_M: + val.bits.swreset_clkssi_m = enable; + break; + case DCGU_HW_MODULE_SMC: + val.bits.swreset_clksmc = enable; + break; + case DCGU_HW_MODULE_EBI: + val.bits.swreset_clkebi = enable; + break; + case DCGU_HW_MODULE_USB_60: + val.bits.swreset_clkusb60 = enable; + break; + case DCGU_HW_MODULE_USB_24: + val.bits.swreset_clkusb24 = enable; + break; + case DCGU_HW_MODULE_UART_2: + val.bits.swreset_clkuart2 = enable; + break; + case DCGU_HW_MODULE_UART_1: + val.bits.swreset_clkuart1 = enable; + break; + case DCGU_HW_MODULE_PWM: + val.bits.swreset_pwm = enable; + break; + case DCGU_HW_MODULE_GPT: + val.bits.swreset_gpt = enable; + break; + case DCGU_HW_MODULE_I2C2: + val.bits.swreset_i2c2 = enable; + break; + case DCGU_HW_MODULE_I2C1: + val.bits.swreset_i2c1 = enable; + break; + case DCGU_HW_MODULE_GPIO2: + val.bits.swreset_gpio2 = enable; + break; + case DCGU_HW_MODULE_GPIO1: + val.bits.swreset_gpio1 = enable; + break; + case DCGU_HW_MODULE_CPU: + val.bits.swreset_clkcpu = enable; + break; + case DCGU_HW_MODULE_I2S: + val.bits.swreset_clk_i2s_dly = enable; + break; + case DCGU_HW_MODULE_ABP_SCC: + val.bits.swreset_clk_scc_abp = enable; + break; + case DCGU_HW_MODULE_SPDIF: + val.bits.swreset_clk_dtv_spdo = enable; + break; + case DCGU_HW_MODULE_AD: + val.bits.swreset_clkad = enable; + break; + case DCGU_HW_MODULE_MVD: + val.bits.swreset_clkmvd = enable; + break; + case DCGU_HW_MODULE_TSD: + val.bits.swreset_clktsd = enable; + break; + case DCGU_HW_MODULE_TSIO: + val.bits.swreset_clktsio = enable; + break; + case DCGU_HW_MODULE_GA: + val.bits.swreset_clkga = enable; + break; + case DCGU_HW_MODULE_MPC: + val.bits.swreset_clkmpc = enable; + break; + case DCGU_HW_MODULE_CVE: + val.bits.swreset_clkcve = enable; + break; + case DCGU_HW_MODULE_DVP: + val.bits.swreset_clkdvp = enable; + break; + case DCGU_HW_MODULE_MR2: + val.bits.swreset_clkmr2 = enable; + break; + case DCGU_HW_MODULE_MR1: + val.bits.swreset_clkmr1 = enable; + break; + default: + printf("%s:%i:Invalid hardware module: %i\n", __FILE__, + __LINE__, module); + return -EINVAL; + } + reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg); + + return 0; +} diff --git a/board/micronas/vct/dcgu.h b/board/micronas/vct/dcgu.h new file mode 100644 index 000000000..ca129c012 --- /dev/null +++ b/board/micronas/vct/dcgu.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DCGU_H +#define _DCGU_H + +enum dcgu_switch { + DCGU_SWITCH_OFF, /* Switch off */ + DCGU_SWITCH_ON /* Switch on */ +}; + +enum dcgu_hw_module { + DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */ + + DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */ + DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/ + + DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */ + DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */ + DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */ + DCGU_HW_MODULE_DVP, /* Selects dig video processing module */ + DCGU_HW_MODULE_CVE, /* Selects color video encoder module */ + DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */ + + DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */ + DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */ + + DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */ + DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */ + + DCGU_HW_MODULE_UART_1, /* Selects first UART module */ + DCGU_HW_MODULE_UART_2, /* Selects second UART module */ + + DCGU_HW_MODULE_AD, /* Selects audio decoder module */ + DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */ + DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/ + DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */ + + DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/ + DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */ + DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */ + + DCGU_HW_MODULE_USBH, /* Selects USB hub module */ + DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */ + DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */ + DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */ + + DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/ + DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/ + DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/ + DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */ + DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */ + DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */ + + DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/ + DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/ + + DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */ + DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */ + + DCGU_HW_MODULE_COM, /* Selects COM unit module */ + DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */ + DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */ + + DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/ + DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */ + DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */ + DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */ + + DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */ + DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */ + DCGU_HW_MODULE_SRAM, /* Selects SRAM module */ + DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/ + DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */ + DCGU_HW_MODULE_SCC, /* Selects SCC module */ + DCGU_HW_MODULE_MM, /* Selects Memory Manager module */ + DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */ + DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */ + DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */ + DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */ + DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/ +}; + +union dcgu_clk_en1 { + u32 reg; + struct { + u32 res1:8; /* reserved */ + u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */ + u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */ + u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */ + u32 en_clksmc:1; /* Enable bit for clksmc (#) */ + u32 en_clkebi:1; /* Enable bit for clkebi (#) */ + u32 en_usbpll:1; /* Enable bit for the USB PLL */ + u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */ + u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */ + u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */ + u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */ + u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */ + u32 res2:3; /* reserved */ + u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */ + u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */ + u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */ + u32 en_clkad:1; /* Enable bit for clkad (#) */ + u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */ + u32 en_clktsd:1; /* Enable bit for clktsd (#) */ + u32 en_clkga:1; /* Enable bit for clkga (#) */ + u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */ + u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */ + u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */ + } bits; +}; + +union dcgu_clk_en2 { + u32 reg; + struct { + u32 res1:31; /* reserved */ + u32 en_clkcpu:1; /* Enable bit for clkcpu */ + } bits; +}; + +union dcgu_reset_unit1 { + u32 reg; + struct { + u32 res1:1; + u32 swreset_clkmsmc:1; + u32 swreset_clkssi_s:1; + u32 swreset_clkssi_m:1; + u32 swreset_clksmc:1; + u32 swreset_clkebi:1; + u32 swreset_clkusb60:1; + u32 swreset_clkusb24:1; + u32 swreset_clkuart2:1; + u32 swreset_clkuart1:1; + u32 swreset_pwm:1; + u32 swreset_gpt:1; + u32 swreset_i2c2:1; + u32 swreset_i2c1:1; + u32 swreset_gpio2:1; + u32 swreset_gpio1:1; + u32 swreset_clkcpu:1; + u32 res2:2; + u32 swreset_clk_i2s_dly:1; + u32 swreset_clk_scc_abp:1; + u32 swreset_clk_dtv_spdo:1; + u32 swreset_clkad:1; + u32 swreset_clkmvd:1; + u32 swreset_clktsd:1; + u32 swreset_clktsio:1; + u32 swreset_clkga:1; + u32 swreset_clkmpc:1; + u32 swreset_clkcve:1; + u32 swreset_clkdvp:1; + u32 swreset_clkmr2:1; + u32 swreset_clkmr1:1; + } bits; +}; + +int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup); +int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup); + +#endif /* _DCGU_H */ diff --git a/board/micronas/vct/ebi.c b/board/micronas/vct/ebi.c new file mode 100644 index 000000000..8e93f6932 --- /dev/null +++ b/board/micronas/vct/ebi.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +int ebi_initialize(void) +{ +#if defined(CONFIG_VCT_NOR) + if (ebi_init_nor_flash()) + return -1; +#endif + +#if defined(CONFIG_VCT_ONENAND) + if (ebi_init_onenand()) + return -1; +#endif + +#if defined(CONFIG_DRIVER_SMC911X) + if (ebi_init_smc911x()) + return -1; +#endif + + reg_write(EBI_CTRL_SIG_ACTLV(EBI_BASE), 0x00004100); + + ebi_wait(); + + return 0; +} diff --git a/board/micronas/vct/ebi.h b/board/micronas/vct/ebi.h new file mode 100644 index 000000000..69456bdc9 --- /dev/null +++ b/board/micronas/vct/ebi.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __EBI__ +#define __EBI__ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +#define EXT_DEVICE_CHANNEL_3 (0x30000000) +#define EXT_DEVICE_CHANNEL_2 (0x20000000) +#define EXT_DEVICE_CHANNEL_1 (0x10000000) +#define EXT_CPU_ACCESS_ACTIVE (0x00000001) +#define EXT_DMA_ACCESS_ACTIVE (1 << 14) +#define EXT_CPU_IORDY_SL (0x00000001) + +#define EBI_CPU_WRITE (1 << 31) +#define EBI_CPU_ID_SHIFT (28) +#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT) + +/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */ +#define ADDR_LATCH_ENABLE 0 +#define ADDR_ACTIVATION 4 +#define CHIP_SELECT_START 8 +#define OUTPUT_ENABLE_START 12 +#define WAIT_TIME 28 +#define READ_DURATION 20 + +/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */ +#define OUTPUT_ENABLE_END 0 +#define CHIP_SELECT_END 4 +#define ADDR_DEACTIVATION 8 +#define RECOVER_TIME 12 +#define ACK_TIME 20 + +/* various bits in configuration register EBI_DEV[01]_CONFIG1 */ +#define EBI_EXTERNAL_DATA_8 (1 << 8) +#define EBI_EXT_ADDR_SHIFT (1 << 22) +#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT +#define EBI_CHIP_SELECT_1 0x2 +#define EBI_CHIP_SELECT_2 0x4 +#define EBI_BUSY_EN_RD (1 << 12) +#define DIR_ACCESS_WRITE (1 << 20) +#define DIR_ACCESS_MASK (1 << 20) + +/* various bits in configuration register EBI_DEV[01]_CONFIG2 */ +#define ADDRESS_INCREMENT_ON 0x0 +#define ADDRESS_INCREMENT_OFF 0x100 +#define QUEUE_LENGTH_1 0x40 +#define QUEUE_LENGTH_2 0x80 +#define QUEUE_LENGTH_3 0xC0 +#define QUEUE_LENGTH_4 0 +#define CPU_TRANSFER_SIZE_32 0 +#define CPU_TRANSFER_SIZE_16 0x10 +#define CPU_TRANSFER_SIZE_8 0x20 +#define READ_ENDIANNESS_ABCD 0 +#define READ_ENDIANNESS_DCBA 0x4 +#define READ_ENDIANNESS_BADC 0x8 +#define READ_ENDIANNESS_CDAB 0xC +#define WRITE_ENDIANNESS_ABCD 0 +#define WRITE_ENDIANNESS_DCBA 0x1 +#define WRITE_ENDIANNESS_BADC 0x2 +#define WRITE_ENDIANNESS_CDAB 0x3 + +/* various bits in configuration register EBI_CTRL_SIG_ACTLV */ +#define IORDY_ACTIVELEVEL_HIGH (1 << 14) +#define ALE_ACTIVELEVEL_HIGH (1 << 8) + +/* bits in register EBI_SIG_LEVEL */ +#define IORDY_LEVEL_MASK 1 + +static inline void ebi_wait(void) +{ + while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE) + ; /* wait */ +} + +#endif diff --git a/board/micronas/vct/ebi_nor_flash.c b/board/micronas/vct/ebi_nor_flash.c new file mode 100644 index 000000000..ae8764395 --- /dev/null +++ b/board/micronas/vct/ebi_nor_flash.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +static u32 ebi_read(u32 addr) +{ + addr &= ~0xFC000000; + + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); + ebi_wait(); + + return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); +} + +static int ebi_write_u16(u32 addr, u32 data, int fetchIO) +{ + u32 val = (data << 16); + + addr &= ~0xFC000000; + + ebi_wait(); + + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | addr); + ebi_wait(); + + if (fetchIO) { + u32 counter = 0; + while (!(reg_read(EBI_SIG_LEVEL(EBI_BASE)) & EXT_CPU_IORDY_SL)) { + if (counter++ > 0xFFFFFF) + return 1; + } + } + + return 0; +} + +static u16 ebi_read_u16(u32 addr) +{ + return ((ebi_read(addr) >> 16) & 0xFFFF); +} + +static u8 ebi_read_u8(u32 addr) +{ + u32 val = ebi_read(addr) >> 16; + + if (addr & 0x1) + return val & 0xff; + else + return (val >> 8) & 0xff; +} + +/* + * EBI initialization for NOR FLASH access + */ +int ebi_init_nor_flash(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); + + reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); + reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); + + reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); + reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); + reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); + reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); + reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); + + return 0; +} + +/* + * Accessor functions replacing the "weak" functions in + * drivers/mtd/cfi_flash.c + */ +void flash_write8(u8 value, void *addr) +{ + ebi_write_u16((u32)addr, value, 0); +} + +void flash_write16(u16 value, void *addr) +{ + ebi_write_u16((u32)addr, value, 0); +} + +u8 flash_read8(void *addr) +{ + return ebi_read_u8((u32)addr); +} + +u16 flash_read16(void *addr) +{ + return ebi_read_u16((u32)addr); +} + +u32 flash_read32(void *addr) +{ + return ((u32)ebi_read_u16((u32)addr) << 16) | + ebi_read_u16((u32)addr + 2); +} + +void *board_flash_read_memcpy(void *dest, const void *src, size_t count) +{ + u16 *tmp = (u16 *)dest, *s = (u16 *)src; + int i; + + for (i = 0; i < count; i += 2) + *tmp++ = flash_read16(s++); + + return dest; +} diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c new file mode 100644 index 000000000..522b88f8e --- /dev/null +++ b/board/micronas/vct/ebi_onenand.c @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/onenand.h> +#include "vct.h" + +#define BURST_SIZE_WORDS 4 + +static u16 ebi_nand_read_word(void __iomem *addr) +{ + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr)); + ebi_wait(); + + return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16; +} + +static void ebi_nand_write_word(u16 data, void __iomem * addr) +{ + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr); + ebi_wait(); +} + +/* + * EBI initialization for OneNAND FLASH access + */ +int ebi_init_onenand(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); + + reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); + reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); + + reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); + reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */ + + reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000); + reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000); + reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223); + reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220); + reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000); + reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000); + reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000); + reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200); + + reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + /* prepare DMA configuration for EBI */ + reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00); + + /* READ only no byte order change, TAG 1 used */ + reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004); + + reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */ + reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1); + reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2); + reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3); + + return 0; +} + +static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u16 *d = dst; + u16 *s = (u16 *)src; + + len >>= 1; + while (len-- > 0) + *d++ = ebi_nand_read_word(s++); + + return ret; +} + +static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u32 *d = (u32 *)dst; + u32 s = (u32)src; + u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int); + u32 n_blocks = len / bytes_per_block; + u32 block = 0; + u32 burst_word; + + for (block = 0; block < n_blocks; block++) { + /* Trigger read channel 3 */ + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + (EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block)))); + /* Poll status to see whether read has finished */ + ebi_wait(); + + /* Squirrel the data away in a safe place */ + for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++) + *d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + } + + return ret; +} + +static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + u16 *d = dst; + u16 *s = (u16 *)src; + + len >>= 1; + while (len-- > 0) + ebi_nand_write_word(*s++, d++); + + return ret; +} + +static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) +{ + struct onenand_chip *this = mtd->priv; + + if (ONENAND_CURRENT_BUFFERRAM(this)) { + if (area == ONENAND_DATARAM) + return mtd->writesize; + if (area == ONENAND_SPARERAM) + return mtd->oobsize; + } + + return 0; +} + +static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area, + unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + if (count < 4) + memcpy_16_from_onenand(buffer, bufferram + offset, count); + else + memcpy_32_from_onenand(buffer, bufferram + offset, count); + + return 0; +} + +static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, + const unsigned char *buffer, int offset, + size_t count) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *bufferram; + + bufferram = this->base + area; + bufferram += onenand_bufferram_offset(mtd, area); + + memcpy_16_to_onenand(bufferram + offset, buffer, count); + + return 0; +} + +void onenand_board_init(struct mtd_info *mtd) +{ + struct onenand_chip *chip = mtd->priv; + + /* + * Insert board specific OneNAND access functions + */ + chip->read_word = ebi_nand_read_word; + chip->write_word = ebi_nand_write_word; + + chip->read_bufferram = ebi_read_bufferram; + chip->read_spareram = ebi_read_bufferram; + chip->write_bufferram = ebi_write_bufferram; +} diff --git a/board/micronas/vct/ebi_smc911x.c b/board/micronas/vct/ebi_smc911x.c new file mode 100644 index 000000000..e1b67a075 --- /dev/null +++ b/board/micronas/vct/ebi_smc911x.c @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +/* + * EBI initialization for SMC911x access + */ +int ebi_init_smc911x(void) +{ + reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + + reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); + reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); + + reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); + reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); + + reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); + reg_write(EBI_DEV1_TIM1_WR2(EBI_BASE), 0x3FC21110); + + return 0; +} + +/* + * Accessor functions replacing the "weak" functions in + * drivers/net/smc911x.c + */ +u32 smc911x_reg_read(u32 addr) +{ + volatile u32 data; + + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + ebi_wait(); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); + ebi_wait(); + data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + + return (data); +} + +void smc911x_reg_write(u32 addr, u32 data) +{ + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); + ebi_wait(); +} + +void pkt_data_push(u32 addr, u32 data) +{ + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); + ebi_wait(); + reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), + EXT_DEVICE_CHANNEL_1 | EBI_CPU_WRITE | addr); + ebi_wait(); + + return; +} + +u32 pkt_data_pull(u32 addr) +{ + volatile u32 data; + + reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004A); + ebi_wait(); + reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_1 | addr)); + ebi_wait(); + data = reg_read(EBI_IO_ACCS_DATA(EBI_BASE)); + + return data; +} diff --git a/board/micronas/vct/ehci.c b/board/micronas/vct/ehci.c new file mode 100644 index 000000000..d04bdceac --- /dev/null +++ b/board/micronas/vct/ehci.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Original Author Guenter Gebhardt + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include "vct.h" + +int vct_ehci_hcd_init(u32 *hccr, u32 *hcor) +{ + int retval; + u32 val; + u32 addr; + + dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON); + dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON); + dcgu_set_clk_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_ON); + dcgu_set_clk_switch(DCGU_HW_MODULE_USB_PLL, DCGU_SWITCH_ON); + dcgu_set_reset_switch(DCGU_HW_MODULE_USB_24, DCGU_SWITCH_OFF); + + /* Wait until (DCGU_USBPHY_STAT == 7) */ + addr = DCGU_USBPHY_STAT(DCGU_BASE); + val = reg_read(addr); + while (val != 7) + val = reg_read(addr); + + dcgu_set_clk_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_ON); + dcgu_set_reset_switch(DCGU_HW_MODULE_USB_60, DCGU_SWITCH_OFF); + + retval = scc_reset(SCC_USB_RW, 0); + if (retval) { + printf("scc_reset(SCC_USB_RW, 0) returned: 0x%x\n", retval); + return retval; + } else { + retval = scc_reset(SCC_CPU1_SPDMA_RW, 0); + if (retval) { + printf("scc_reset(SCC_CPU1_SPDMA_RW, 0) returned: 0x%x\n", + retval); + return retval; + } + } + + if (!retval) { + /* + * For the AGU bypass, where the SCC client provides full + * physical address + */ + scc_set_usb_address_generation_mode(1); + scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_1, DMA_LINEAR, + USE_NO_FH, DMA_READ, 0); + scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_1, DMA_LINEAR, + USE_NO_FH, DMA_WRITE, 0); + scc_setup_dma(SCC_USB_RW, BCU_USB_BUFFER_0, DMA_LINEAR, + USE_NO_FH, DMA_WRITE, 0); + scc_setup_dma(SCC_CPU1_SPDMA_RW, BCU_USB_BUFFER_0, DMA_LINEAR, + USE_NO_FH, DMA_READ, 0); + + /* Enable memory interface */ + scc_enable(SCC_USB_RW, 1); + + /* Start (start_cmd=0) DMAs */ + scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_READ); + scc_dma_cmd(SCC_USB_RW, DMA_START, 0, DMA_WRITE); + } else { + printf("Cannot configure USB memory channel.\n"); + printf("USB can not access RAM. SCC configuration failed.\n"); + return retval; + } + + /* Wait a short while */ + udelay(300000); + + reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); + + /* Set EHCI structures and DATA in RAM */ + reg_write(USBH_USBHMISC(USBH_BASE), 0x00840003); + /* Set USBMODE to bigendian and set host mode */ + reg_write(USBH_USBMODE(USBH_BASE), 0x00000007); + + /* + * USBH_BURSTSIZE MUST EQUAL 0x00001c1c in order for + * 512 byte USB transfers on the bulk pipe to work properly. + * Set USBH_BURSTSIZE to 0x00001c1c + */ + reg_write(USBH_BURSTSIZE(USBH_BASE), 0x00001c1c); + + /* Insert access register addresses */ + *hccr = REG_GLOBAL_START_ADDR + USBH_CAPLENGTH(USBH_BASE); + *hcor = REG_GLOBAL_START_ADDR + USBH_USBCMD(USBH_BASE); + + return 0; +} diff --git a/board/micronas/vct/gpio.c b/board/micronas/vct/gpio.c new file mode 100644 index 000000000..2c113be26 --- /dev/null +++ b/board/micronas/vct/gpio.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include "vct.h" + +/* + * Find out to which of the 2 gpio modules the pin specified in the + * argument belongs: + * GPIO_MODULE yields 0 for pins 0 to 31, + * 1 for pins 32 to 63 + */ +#define GPIO_MODULE(pin) ((pin) >> 5) + +/* + * Bit position within a 32-bit peripheral register (where every + * bit is one bitslice) + */ +#define MASK(pin) (1 << ((pin) & 0x1F)) +#define BASE_ADDR(mod) module_base[mod] + +/* + * Lookup table for transforming gpio module number 0 to 2 to + * address offsets + */ +static u32 module_base[] = { + GPIO1_BASE, + GPIO2_BASE +}; + +static void clrsetbits(u32 addr, u32 and_mask, u32 or_mask) +{ + reg_write(addr, (reg_read(addr) & ~and_mask) | or_mask); +} + +int vct_gpio_dir(int pin, int dir) +{ + u32 gpio_base; + + gpio_base = BASE_ADDR(GPIO_MODULE(pin)); + + if (dir == 0) + clrsetbits(GPIO_SWPORTA_DDR(gpio_base), MASK(pin), 0); + else + clrsetbits(GPIO_SWPORTA_DDR(gpio_base), 0, MASK(pin)); + + return 0; +} + +void vct_gpio_set(int pin, int val) +{ + u32 gpio_base; + + gpio_base = BASE_ADDR(GPIO_MODULE(pin)); + + if (val == 0) + clrsetbits(GPIO_SWPORTA_DR(gpio_base), MASK(pin), 0); + else + clrsetbits(GPIO_SWPORTA_DR(gpio_base), 0, MASK(pin)); +} + +int vct_gpio_get(int pin) +{ + u32 gpio_base; + u32 value; + + gpio_base = BASE_ADDR(GPIO_MODULE(pin)); + value = reg_read(GPIO_EXT_PORTA(gpio_base)); + + return ((value & MASK(pin)) ? 1 : 0); +} diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c new file mode 100644 index 000000000..0368183e0 --- /dev/null +++ b/board/micronas/vct/scc.c @@ -0,0 +1,669 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> + +#include "vct.h" + +/* + * List of statically defined buffers per SCC. + * The first entry in the table is the number of fixed buffers + * followed by the list of buffer IDs + */ +static u32 buffer_list_0[] = { 6, 120, 121, 122, 123, 139, 140 }; +static u32 buffer_list_1[] = { 6, 120, 121, 122, 123, 139, 140 }; +static u32 buffer_list_2[] = { 5, 124, 125, 126, 139, 140 }; +static u32 buffer_list_3[] = { 5, 124, 125, 126, 139, 140 }; +static u32 buffer_list_4[] = { 5, 124, 125, 126, 139, 140 }; +static u32 buffer_list_5[] = { 3, 127, 139, 140 }; +static u32 buffer_list_6[] = { 3, 127, 139, 140 }; +static u32 buffer_list_7[] = { 6, 128, 129, 130, 131, 139, 140 }; +static u32 buffer_list_8[] = { 6, 128, 129, 130, 131, 139, 140 }; +static u32 buffer_list_9[] = { 5, 124, 125, 126, 139, 140 }; +static u32 buffer_list_10[] = { 5, 124, 125, 126, 139, 140 }; +static u32 buffer_list_11[] = { 5, 124, 125, 126, 139, 140 }; +static u32 buffer_list_12[] = { 6, 132, 133, 134, 135, 139, 140 }; +static u32 buffer_list_13[] = { 6, 132, 133, 134, 135, 139, 140 }; +static u32 buffer_list_14[] = { 4, 137, 138, 139, 140 }; +static u32 buffer_list_15[] = { 6, 136, 136, 137, 138, 139, 140 }; + +/** Issue#7674 (new) - DP/DVP buffer assignment */ +static u32 buffer_list_16[] = { 6, 106, 108, 109, 107, 139, 140 }; +static u32 buffer_list_17[] = { 6, 106, 110, 107, 111, 139, 140 }; +static u32 buffer_list_18[] = { 6, 106, 113, 107, 114, 139, 140 }; +static u32 buffer_list_19[] = { 3, 112, 139, 140 }; +static u32 buffer_list_20[] = { 35, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 79, 80, 81, 82, 83, 84, 85, 86, 139, 140 }; +static u32 buffer_list_21[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 139, 140 }; +static u32 buffer_list_22[] = { 81, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, + 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, 139, 140 }; +static u32 buffer_list_23[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 88, 89, 139, 140 }; +static u32 buffer_list_24[] = { 6, 90, 91, 92, 93, 139, 140 }; +static u32 buffer_list_25[] = { 18, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, + 100, 101, 102, 103, 104, 105, 139, 140 }; +static u32 buffer_list_26[] = { 5, 94, 95, 96, 139, 140 }; +static u32 buffer_list_27[] = { 5, 97, 98, 99, 139, 140 }; +static u32 buffer_list_28[] = { 5, 100, 101, 102, 139, 140 }; +static u32 buffer_list_29[] = { 5, 103, 104, 105, 139, 140 }; +static u32 buffer_list_30[] = { 10, 108, 109, 110, 111, 113, 114, 116, 117, + 139, 140 }; +static u32 buffer_list_31[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114, + 115, 116, 117, 139, 140 }; +static u32 buffer_list_32[] = { 13, 106, 107, 108, 109, 110, 111, 113, 114, + 115, 116, 117, 139, 140 }; +static u32 buffer_list_33[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 139, 140 }; +static u32 buffer_list_34[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 139, 140 }; +static u32 buffer_list_35[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 87, 139, 140 }; +static u32 buffer_list_36[] = { 28, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 87, 139, 140 }; +static u32 buffer_list_37[] = { 27, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 139, 140 }; +static u32 buffer_list_38[] = { 29, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 118, 119, 139, 140 }; +static u32 buffer_list_39[] = { 91, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, + 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, + 85, 86, 118, 119, 139, 140 }; +static u32 buffer_list_40[] = { 0 }; + +/* + * List of statically defined vcid.csize values. + * The first entry in the table is the number of possible csize values + * followed by the list of data path values in bits. + */ +static u32 csize_list_0[] = { 2, 0, 1 }; +static u32 csize_list_1[] = { 2, 0, 1 }; +static u32 csize_list_2[] = { 1, 1 }; +static u32 csize_list_3[] = { 1, 1 }; +static u32 csize_list_4[] = { 1, 1 }; +static u32 csize_list_5[] = { 1, 0 }; +static u32 csize_list_6[] = { 1, 0 }; +static u32 csize_list_7[] = { 1, 1 }; +static u32 csize_list_8[] = { 1, 1 }; +static u32 csize_list_9[] = { 1, 1 }; +static u32 csize_list_10[] = { 1, 1 }; +static u32 csize_list_11[] = { 1, 1 }; +static u32 csize_list_12[] = { 1, 1 }; +static u32 csize_list_13[] = { 1, 1 }; +static u32 csize_list_14[] = { 1, 2 }; +static u32 csize_list_15[] = { 1, 4 }; +static u32 csize_list_16[] = { 3, 0, 1, 2 }; +static u32 csize_list_17[] = { 3, 0, 1, 2 }; +static u32 csize_list_18[] = { 3, 0, 1, 2 }; +static u32 csize_list_19[] = { 1, 2 }; +static u32 csize_list_20[] = { 1, 0 }; +static u32 csize_list_21[] = { 1, 0 }; +static u32 csize_list_22[] = { 1, 2 }; +static u32 csize_list_23[] = { 1, 3 }; +static u32 csize_list_24[] = { 1, 3 }; +static u32 csize_list_25[] = { 1, 3 }; +static u32 csize_list_26[] = { 1, 0 }; +static u32 csize_list_27[] = { 1, 0 }; +static u32 csize_list_28[] = { 1, 0 }; +static u32 csize_list_29[] = { 1, 0 }; +static u32 csize_list_30[] = { 1, 2 }; +static u32 csize_list_31[] = { 1, 2 }; +static u32 csize_list_32[] = { 1, 2 }; +static u32 csize_list_33[] = { 1, 2 }; +static u32 csize_list_34[] = { 1, 2 }; +static u32 csize_list_35[] = { 1, 2 }; +static u32 csize_list_36[] = { 1, 2 }; +static u32 csize_list_37[] = { 2, 0, 1 }; +static u32 csize_list_38[] = { 1, 2 }; +static u32 csize_list_39[] = { 1, 3 }; +static u32 csize_list_40[] = { 1, 3 }; + +/* + * SCC_Configuration table + */ +static const struct scc_descriptor scc_descriptor_table[] = { +/* scn scc_name profile SCC scc_id mci_id rd wr m p fh si cfg sta */ + {"fe_", "fe_3dcomb_wr", STRM_P, SCC0_BASE, 0, 0, 0, 4, 1, 1, 0, 0, 0, 1, + buffer_list_0, csize_list_0}, + {"fe_", "fe_3dcomb_rd", STRM_P, SCC1_BASE, 1, 18, 4, 0, 1, 1, 0, 1, 0, + 1, buffer_list_1, csize_list_1}, + {"di_", "di_tnr_wr", STRM_P, SCC2_BASE, 2, 1, 0, 3, 1, 1, 0, 2, 0, 1, + buffer_list_2, csize_list_2}, + {"di_", "di_tnr_field_rd", STRM_P, SCC3_BASE, 3, 19, 3, 0, 1, 1, 0, 3, + 0, 1, buffer_list_3, csize_list_3}, + {"di_", "di_tnr_frame_rd", STRM_P, SCC4_BASE, 4, 20, 3, 0, 1, 1, 0, 4, + 0, 1, buffer_list_4, csize_list_4}, + {"di_", "di_mval_wr", STRM_P, SCC5_BASE, 5, 2, 0, 1, 1, 1, 0, 5, 0, 1, + buffer_list_5, csize_list_5}, + {"di_", "di_mval_rd", STRM_P, SCC6_BASE, 6, 21, 1, 0, 1, 1, 0, 6, 0, 1, + buffer_list_6, csize_list_6}, + {"rc_", "rc_frame_wr", STRM_P, SCC7_BASE, 7, 3, 0, 4, 1, 1, 0, 7, 0, 1, + buffer_list_7, csize_list_7}, + {"rc_", "rc_frame0_rd", STRM_P, SCC8_BASE, 8, 22, 4, 0, 1, 1, 0, 8, 0, + 1, buffer_list_8, csize_list_8}, + {"opt", "opt_field0_rd", STRM_P, SCC9_BASE, 9, 23, 3, 0, 1, 1, 0, 9, 0, + 1, buffer_list_9, csize_list_9}, + {"opt", "opt_field1_rd", STRM_P, SCC10_BASE, 10, 24, 3, 0, 1, 1, 0, 10, + 0, 1, buffer_list_10, csize_list_10}, + {"opt", "opt_field2_rd", STRM_P, SCC11_BASE, 11, 25, 3, 0, 1, 1, 0, 11, + 0, 1, buffer_list_11, csize_list_11}, + {"pip", "pip_frame_wr", STRM_P, SCC12_BASE, 12, 4, 0, 4, 1, 1, 0, 12, 0, + 1, buffer_list_12, csize_list_12}, + {"pip", "pip_frame_rd", STRM_P, SCC13_BASE, 13, 26, 4, 0, 1, 1, 0, 13, + 0, 1, buffer_list_13, csize_list_13}, + {"dp_", "dp_agpu_rd", STRM_P, SCC14_BASE, 14, 27, 2, 0, 2, 1, 0, 14, 0, + 1, buffer_list_14, csize_list_14}, + {"ewa", "ewarp_rw", SRMD, SCC15_BASE, 15, 11, 1, 1, 0, 0, 0, -1, 0, 0, + buffer_list_15, csize_list_15}, + {"dp_", "dp_osd_rd", STRM_P, SCC16_BASE, 16, 28, 3, 0, 2, 1, 0, 15, 0, + 1, buffer_list_16, csize_list_16}, + {"dp_", "dp_graphic_rd", STRM_P, SCC17_BASE, 17, 29, 3, 0, 2, 1, 0, 16, + 0, 1, buffer_list_17, csize_list_17}, + {"dvp", "dvp_osd_rd", STRM_P, SCC18_BASE, 18, 30, 2, 0, 2, 1, 0, 17, 0, + 1, buffer_list_18, csize_list_18}, + {"dvp", "dvp_vbi_rd", STRM_D, SCC19_BASE, 19, 31, 1, 0, 0, 1, 0, -1, 0, + 0, buffer_list_19, csize_list_19}, + {"tsi", "tsio_wr", STRM_P, SCC20_BASE, 20, 5, 0, 8, 2, 1, 1, -1, 0, 0, + buffer_list_20, csize_list_20}, + {"tsi", "tsio_rd", STRM_P, SCC21_BASE, 21, 32, 4, 0, 2, 1, 1, -1, 0, 0, + buffer_list_21, csize_list_21}, + {"tsd", "tsd_wr", SRMD, SCC22_BASE, 22, 6, 0, 64, 0, 0, 1, -1, 0, 0, + buffer_list_22, csize_list_22}, + {"vd_", "vd_ud_st_rw", SRMD, SCC23_BASE, 23, 12, 2, 2, 0, 0, 1, -1, 0, + 0, buffer_list_23, csize_list_23}, + {"vd_", "vd_frr_rd", SRMD, SCC24_BASE, 24, 33, 4, 0, 0, 0, 0, -1, 0, 0, + buffer_list_24, csize_list_24}, + {"vd_", "vd_frw_disp_wr", SRMD, SCC25_BASE, 25, 7, 0, 16, 0, 0, 0, -1, + 0, 0, buffer_list_25, csize_list_25}, + {"mr_", "mr_vd_m_y_rd", STRM_P, SCC26_BASE, 26, 34, 3, 0, 2, 1, 0, 18, + 0, 1, buffer_list_26, csize_list_26}, + {"mr_", "mr_vd_m_c_rd", STRM_P, SCC27_BASE, 27, 35, 3, 0, 2, 1, 0, 19, + 0, 1, buffer_list_27, csize_list_27}, + {"mr_", "mr_vd_s_y_rd", STRM_P, SCC28_BASE, 28, 36, 3, 0, 2, 1, 0, 20, + 0, 1, buffer_list_28, csize_list_28}, + {"mr_", "mr_vd_s_c_rd", STRM_P, SCC29_BASE, 29, 37, 3, 0, 2, 1, 0, 21, + 0, 1, buffer_list_29, csize_list_29}, + {"ga_", "ga_wr", STRM_P, SCC30_BASE, 30, 8, 0, 1, 1, 1, 0, -1, 1, 1, + buffer_list_30, csize_list_30}, + {"ga_", "ga_src1_rd", STRM_P, SCC31_BASE, 31, 38, 1, 0, 1, 1, 0, -1, 1, + 1, buffer_list_31, csize_list_31}, + {"ga_", "ga_src2_rd", STRM_P, SCC32_BASE, 32, 39, 1, 0, 1, 1, 0, -1, 1, + 1, buffer_list_32, csize_list_32}, + {"ad_", "ad_rd", STRM_D, SCC33_BASE, 33, 40, 2, 0, 0, 1, 1, -1, 0, 0, + buffer_list_33, csize_list_33}, + {"ad_", "ad_wr", STRM_D, SCC34_BASE, 34, 9, 0, 3, 0, 1, 1, -1, 0, 0, + buffer_list_34, csize_list_34}, + {"abp", "abp_rd", STRM_D, SCC35_BASE, 35, 41, 5, 0, 0, 1, 1, -1, 0, 0, + buffer_list_35, csize_list_35}, + {"abp", "abp_wr", STRM_D, SCC36_BASE, 36, 10, 0, 3, 0, 1, 1, -1, 0, 0, + buffer_list_36, csize_list_36}, + {"ebi", "ebi_rw", STRM_P, SCC37_BASE, 37, 13, 4, 4, 2, 1, 1, -1, 0, 0, + buffer_list_37, csize_list_37}, + {"usb", "usb_rw", SRMD, SCC38_BASE, 38, 14, 1, 1, 0, 0, 1, -1, 0, 0, + buffer_list_38, csize_list_38}, + {"cpu", "cpu1_spdma_rw", SRMD, SCC39_BASE, 39, 15, 1, 1, 0, 0, 1, -1, 0, + 0, buffer_list_39, csize_list_39}, + {"cpu", "cpu1_bridge_rw", SRMD, SCC40_BASE, 40, 16, 0, 0, 0, 0, 0, -1, + 0, 0, buffer_list_40, csize_list_40}, +}; + +/* DMA state structures for read and write channels for each SCC */ + +static struct scc_dma_state scc_state_rd_0[] = { {-1} }; +static struct scc_dma_state scc_state_wr_0[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_1[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_1[] = { {-1} }; +static struct scc_dma_state scc_state_rd_2[] = { {-1} }; +static struct scc_dma_state scc_state_wr_2[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_3[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_3[] = { {-1} }; +static struct scc_dma_state scc_state_rd_4[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_4[] = { {-1} }; +static struct scc_dma_state scc_state_rd_5[] = { {-1} }; +static struct scc_dma_state scc_state_wr_5[] = { {0} }; +static struct scc_dma_state scc_state_rd_6[] = { {0} }; +static struct scc_dma_state scc_state_wr_6[] = { {-1} }; +static struct scc_dma_state scc_state_rd_7[] = { {-1} }; +static struct scc_dma_state scc_state_wr_7[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_8[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_8[] = { {-1} }; +static struct scc_dma_state scc_state_rd_9[] = { {0}, {0}, {0}, }; +static struct scc_dma_state scc_state_wr_9[] = { {-1} }; +static struct scc_dma_state scc_state_rd_10[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_10[] = { {-1} }; +static struct scc_dma_state scc_state_rd_11[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_11[] = { {-1} }; +static struct scc_dma_state scc_state_rd_12[] = { {-1} }; +static struct scc_dma_state scc_state_wr_12[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_13[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_13[] = { {-1} }; +static struct scc_dma_state scc_state_rd_14[] = { {0}, {0} }; +static struct scc_dma_state scc_state_wr_14[] = { {-1} }; +static struct scc_dma_state scc_state_rd_15[] = { {0} }; +static struct scc_dma_state scc_state_wr_15[] = { {0} }; +static struct scc_dma_state scc_state_rd_16[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_16[] = { {-1} }; +static struct scc_dma_state scc_state_rd_17[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_17[] = { {-1} }; +static struct scc_dma_state scc_state_rd_18[] = { {0}, {0} }; +static struct scc_dma_state scc_state_wr_18[] = { {-1} }; +static struct scc_dma_state scc_state_rd_19[] = { {0} }; +static struct scc_dma_state scc_state_wr_19[] = { {-1} }; +static struct scc_dma_state scc_state_rd_20[] = { {-1} }; +static struct scc_dma_state scc_state_wr_20[] = { + {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_21[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_21[] = { {-1} }; +static struct scc_dma_state scc_state_rd_22[] = { {-1} }; +static struct scc_dma_state scc_state_wr_22[] = { + {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, + {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, + {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, + {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, + {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_23[] = { {0}, {0} }; +static struct scc_dma_state scc_state_wr_23[] = { {0}, {0} }; +static struct scc_dma_state scc_state_rd_24[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_24[] = { {-1} }; +static struct scc_dma_state scc_state_rd_25[] = { {-1} }; +static struct scc_dma_state scc_state_wr_25[] = { + {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, {0}, + {0}, {0} }; +static struct scc_dma_state scc_state_rd_26[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_26[] = { {-1} }; +static struct scc_dma_state scc_state_rd_27[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_27[] = { {-1} }; +static struct scc_dma_state scc_state_rd_28[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_28[] = { {-1} }; +static struct scc_dma_state scc_state_rd_29[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_29[] = { {-1} }; +static struct scc_dma_state scc_state_rd_30[] = { {-1} }; +static struct scc_dma_state scc_state_wr_30[] = { {0} }; +static struct scc_dma_state scc_state_rd_31[] = { {0} }; +static struct scc_dma_state scc_state_wr_31[] = { {-1} }; +static struct scc_dma_state scc_state_rd_32[] = { {0} }; +static struct scc_dma_state scc_state_wr_32[] = { {-1} }; +static struct scc_dma_state scc_state_rd_33[] = { {0}, {0} }; +static struct scc_dma_state scc_state_wr_33[] = { {-1} }; +static struct scc_dma_state scc_state_rd_34[] = { {-1} }; +static struct scc_dma_state scc_state_wr_34[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_35[] = { {0}, {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_35[] = { {-1} }; +static struct scc_dma_state scc_state_rd_36[] = { {-1} }; +static struct scc_dma_state scc_state_wr_36[] = { {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_37[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_wr_37[] = { {0}, {0}, {0}, {0} }; +static struct scc_dma_state scc_state_rd_38[] = { {0} }; +static struct scc_dma_state scc_state_wr_38[] = { {0} }; +static struct scc_dma_state scc_state_rd_39[] = { {0} }; +static struct scc_dma_state scc_state_wr_39[] = { {0} }; +static struct scc_dma_state scc_state_rd_40[] = { {-1} }; +static struct scc_dma_state scc_state_wr_40[] = { {-1} }; + +/* DMA state references to access from the driver */ +static struct scc_dma_state *scc_state_rd[] = { + scc_state_rd_0, + scc_state_rd_1, + scc_state_rd_2, + scc_state_rd_3, + scc_state_rd_4, + scc_state_rd_5, + scc_state_rd_6, + scc_state_rd_7, + scc_state_rd_8, + scc_state_rd_9, + scc_state_rd_10, + scc_state_rd_11, + scc_state_rd_12, + scc_state_rd_13, + scc_state_rd_14, + scc_state_rd_15, + scc_state_rd_16, + scc_state_rd_17, + scc_state_rd_18, + scc_state_rd_19, + scc_state_rd_20, + scc_state_rd_21, + scc_state_rd_22, + scc_state_rd_23, + scc_state_rd_24, + scc_state_rd_25, + scc_state_rd_26, + scc_state_rd_27, + scc_state_rd_28, + scc_state_rd_29, + scc_state_rd_30, + scc_state_rd_31, + scc_state_rd_32, + scc_state_rd_33, + scc_state_rd_34, + scc_state_rd_35, + scc_state_rd_36, + scc_state_rd_37, + scc_state_rd_38, + scc_state_rd_39, + scc_state_rd_40, +}; + +static struct scc_dma_state *scc_state_wr[] = { + scc_state_wr_0, + scc_state_wr_1, + scc_state_wr_2, + scc_state_wr_3, + scc_state_wr_4, + scc_state_wr_5, + scc_state_wr_6, + scc_state_wr_7, + scc_state_wr_8, + scc_state_wr_9, + scc_state_wr_10, + scc_state_wr_11, + scc_state_wr_12, + scc_state_wr_13, + scc_state_wr_14, + scc_state_wr_15, + scc_state_wr_16, + scc_state_wr_17, + scc_state_wr_18, + scc_state_wr_19, + scc_state_wr_20, + scc_state_wr_21, + scc_state_wr_22, + scc_state_wr_23, + scc_state_wr_24, + scc_state_wr_25, + scc_state_wr_26, + scc_state_wr_27, + scc_state_wr_28, + scc_state_wr_29, + scc_state_wr_30, + scc_state_wr_31, + scc_state_wr_32, + scc_state_wr_33, + scc_state_wr_34, + scc_state_wr_35, + scc_state_wr_36, + scc_state_wr_37, + scc_state_wr_38, + scc_state_wr_39, + scc_state_wr_40, +}; + +static u32 scc_takeover_mode = SCC_TO_IMMEDIATE; + +/* Change mode of the SPDMA for given direction */ +static u32 scc_agu_mode_sp = AGU_BYPASS; + +/* Change mode of the USB for given direction */ +static u32 scc_agu_mode_usb = AGU_BYPASS; + +static union scc_softwareconfiguration scc_software_configuration[SCC_MAX]; + +static u32 dma_fsm[4][4] = { + /* DMA_CMD_RESET DMA_CMD_SETUP DMA_CMD_START DMA_CMD_STOP */ + /* DMA_STATE_RESET */ + {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_ERROR, DMA_STATE_ERROR}, + /* DMA_STATE_SETUP */ + {DMA_STATE_RESET, DMA_STATE_SETUP, DMA_STATE_START, DMA_STATE_SETUP}, + /* DMA_STATE_START */ + {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_START, DMA_STATE_SETUP}, + /* DMA_STATE_ERROR */ + {DMA_STATE_RESET, DMA_STATE_ERROR, DMA_STATE_ERROR, DMA_STATE_ERROR}, +}; + +static void dma_state_process(struct scc_dma_state *dma_state, u32 cmd) +{ + dma_state->dma_status = dma_fsm[dma_state->dma_status][cmd]; + dma_state->dma_cmd = cmd; +} + +static void dma_state_process_dma_command(struct scc_dma_state *dma_state, + u32 dma_cmd) +{ + dma_state->dma_cmd = dma_cmd; + switch (dma_cmd) { + case DMA_START: + case DMA_START_FH_RESET: + dma_state_process(dma_state, DMA_CMD_START); + break; + case DMA_STOP: + dma_state_process(dma_state, DMA_CMD_STOP); + break; + default: + break; + } +} + +static void scc_takeover_dma(enum scc_id id, u32 dma_id, u32 drs) +{ + union scc_cmd dma_cmd; + + dma_cmd.reg = 0; + + /* Prepare the takeover for the DMA channel */ + dma_cmd.bits.action = DMA_TAKEOVER; + dma_cmd.bits.id = dma_id; + dma_cmd.bits.rid = TO_DMA_CFG; /* this is DMA_CFG register takeover */ + if (drs == DMA_WRITE) + dma_cmd.bits.drs = DMA_WRITE; + + reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg); +} + +int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs) +{ + union scc_cmd dma_cmd; + struct scc_dma_state *dma_state; + + if ((id >= SCC_MAX) || (id < 0)) + return -EINVAL; + + dma_cmd.reg = 0; + + /* Prepare the takeover for the DMA channel */ + dma_cmd.bits.action = cmd; + dma_cmd.bits.id = dma_id; + if (drs == DMA_WRITE) { + dma_cmd.bits.drs = DMA_WRITE; + dma_state = &scc_state_wr[id][dma_id]; + } else { + dma_state = &scc_state_rd[id][dma_id]; + } + + dma_state->scc_id = id; + dma_state->dma_id = dma_id; + dma_state_process_dma_command(dma_state, cmd); + + reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg); + + return 0; +} + +int scc_set_usb_address_generation_mode(u32 agu_mode) +{ + if (AGU_ACTIVE == agu_mode) { + /* Ensure both DMAs are stopped */ + scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_WRITE); + scc_dma_cmd(SCC_USB_RW, DMA_STOP, 0, DMA_READ); + } else { + agu_mode = AGU_BYPASS; + } + + scc_agu_mode_usb = agu_mode; + + return 0; +} + +int scc_setup_dma(enum scc_id id, u32 buffer_tag, + u32 type, u32 fh_mode, u32 drs, u32 dma_id) +{ + struct scc_dma_state *dma_state; + int return_value = 0; + union scc_dma_cfg dma_cfg; + u32 *buffer_tag_list = scc_descriptor_table[id].buffer_tag_list; + u32 tag_count, t, t_valid; + + if ((id >= SCC_MAX) || (id < 0)) + return -EINVAL; + + /* if the register is only configured by hw, cannot write! */ + if (1 == scc_descriptor_table[id].hw_dma_cfg) + return -EACCES; + + if (DMA_WRITE == drs) { + if (dma_id >= scc_descriptor_table[id].p_dma_channels_wr) + return -EINVAL; + dma_state = &scc_state_wr[id][dma_id]; + } else { + if (dma_id >= scc_descriptor_table[id].p_dma_channels_rd) + return -EINVAL; + dma_state = &scc_state_rd[id][dma_id]; + } + + /* Compose the DMA configuration register */ + tag_count = buffer_tag_list[0]; + t_valid = 0; + for (t = 1; t <= tag_count; t++) { + if (buffer_tag == buffer_tag_list[t]) { + /* Tag found - validate */ + t_valid = 1; + break; + } + } + + if (!t_valid) + return -EACCES; + + /* + * Read the register first -- two functions write into the register + * it does not make sense to read the DMA config back, because there + * are two register configuration sets (drs) + */ + dma_cfg.reg = 0; + dma_cfg.bits.buffer_id = buffer_tag; + dma_state_process(dma_state, DMA_CMD_SETUP); + + /* + * This is Packet CFG set select - usable for TSIO, EBI and those SCCs + * which habe 2 packet configs + */ + dma_cfg.bits.packet_cfg_id = + scc_software_configuration[id].bits.packet_select; + + if (type == DMA_CYCLIC) + dma_cfg.bits.buffer_type = 1; + else + dma_cfg.bits.buffer_type = 0; + + if (fh_mode == USE_FH) + dma_cfg.bits.fh_mode = 1; + else + dma_cfg.bits.fh_mode = 0; + + if (id == SCC_CPU1_SPDMA_RW) + dma_cfg.bits.agu_mode = scc_agu_mode_sp; + + if (id == SCC_USB_RW) + dma_cfg.bits.agu_mode = scc_agu_mode_usb; + + reg_write(SCC_DMA_CFG(scc_descriptor_table[id].base_address), + dma_cfg.reg); + + /* The DMA_CFG needs a takeover! */ + if (SCC_TO_IMMEDIATE == scc_takeover_mode) + scc_takeover_dma(id, dma_id, drs); + + /* if (buffer_tag is not used) */ + dma_state->buffer_tag = buffer_tag; + + dma_state->scc_id = id; + dma_state->dma_id = dma_id; + + return return_value; +} + +int scc_enable(enum scc_id id, u32 value) +{ + if ((id >= SCC_MAX) || (id < 0)) + return -EINVAL; + + if (value == 0) { + scc_software_configuration[id].bits.enable_status = 0; + } else { + value = 1; + scc_software_configuration[id].bits.enable_status = 1; + } + reg_write(SCC_ENABLE(scc_descriptor_table[id].base_address), value); + + return 0; +} + +static inline void ehb(void) +{ + __asm__ __volatile__( + " .set mips32r2 \n" + " ehb \n" + " .set mips0 \n"); +} + +int scc_reset(enum scc_id id, u32 value) +{ + if ((id >= SCC_MAX) || (id < 0)) + return -EINVAL; + + /* Invert value to the strait logic from the negative hardware logic */ + if (value == 0) + value = 1; + else + value = 0; + + /* Write the value to the register */ + reg_write(SCC_RESET(scc_descriptor_table[id].base_address), value); + + /* sync flush */ + asm("sync"); /* request bus write queue flush */ + ehb(); /* wait until previous bus commit instr has finished */ + asm("nop"); /* wait for flush to occur */ + asm("nop"); /* wait for flush to occur */ + + udelay(100); + + return 0; +} diff --git a/board/micronas/vct/scc.h b/board/micronas/vct/scc.h new file mode 100644 index 000000000..8415167c9 --- /dev/null +++ b/board/micronas/vct/scc.h @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SCC_H +#define _SCC_H + +#define DMA_READ 0 /* SCC read DMA */ +#define DMA_WRITE 1 /* SCC write DMA */ + +#define DMA_LINEAR 0 /* DMA linear buffer access method */ +#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */ + +#define DMA_START 0 /* DMA command - start DMA */ +#define DMA_STOP 1 /* DMA command - stop DMA */ +#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */ +#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */ + +#define AGU_ACTIVE 0 /* enable AGU address calculation */ +#define AGU_BYPASS 1 /* set AGU to bypass mode */ + +#define USE_NO_FH 0 /* order the DMA to not use FH */ +#define USE_FH 1 /* order the DMA to work with FH*/ + +#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */ +#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */ + +#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/ +#define TO_DMA_CFG 2 /* takeover command for the DMA config*/ + +#define DMA_CMD_RESET 0 +#define DMA_CMD_SETUP 1 +#define DMA_CMD_START 2 +#define DMA_CMD_STOP 3 + +#define DMA_STATE_RESET 0 +#define DMA_STATE_SETUP 1 +#define DMA_STATE_START 2 +#define DMA_STATE_ERROR 3 + +#define SRMD 0 +#define STRM_D 1 +#define STRM_P 2 + +/* + * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks) + */ +#define RESET_TIME 2 /* cycle calc see in SCC_Reset */ + +struct scc_descriptor { + char *pu_name; /* PU identifier */ + char *scc_instance; /* SCC Name */ + u32 profile; /* SCC VCI_D profile */ + + u32 base_address; /* base address of the SCC unit reg shell*/ + + /* SCS Interconnect configuration */ + u32 p_scc_id; /* instance number of SCC unit */ + u32 p_mci_id; /* memory channel ID */ + + /* DMA Registers configuration */ + u32 p_dma_channels_rd; /* Number of Read DMA channels */ + u32 p_dma_channels_wr; /* Number of Write DMA channels */ + + u32 p_dma_packet_desc; /* Number of packet descriptors */ + u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */ + + int use_fh; /* the flag tells if SCC uses an FH */ + + int p_si2ocp_id; /* instance number of SI2OCP unit */ + int hw_dma_cfg; /* HW or SW DMA config flag */ + int hw_dma_start; /* HW or SW DMA start/stop flag */ + + u32 *buffer_tag_list; /* list of the buffer tags available */ + u32 *csize_list; /* list of the valid CSIZE values */ +}; + +struct scc_dma_state { + u32 scc_id:8; /* SCC id */ + u32 dma_id:8; /* DMA id, used for match with array idx*/ + u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */ + u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/ + u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/ + u32 dma_cmd:4; /* last executed command on this DMA */ +}; + +union scc_cmd { + u32 reg; + struct { + u32 res1:19; /* reserved */ + u32 drs:1; /* DMA Register Set */ + u32 rid:2; /* Register Identifier */ + u32 id:6; /* DMA Identifier */ + u32 action:4; /* DMA Command encoding */ + } bits; +}; + +union scc_dma_cfg { + u32 reg; + struct { + u32 res1:17; /* reserved */ + u32 agu_mode:1; /* AGU Mode */ + u32 res2:1; /* reserved */ + u32 fh_mode:1; /* Fifo Handler */ + u32 buffer_type:1; /* Defines type of mem buffers */ + u32 mci_cfg_id:1; /* MCI_CFG register selector */ + u32 packet_cfg_id:1; /* PACKET_CFG register selector */ + u32 buffer_id:8; /* DMA Buffer Identifier */ + } bits; +}; + +union scc_debug { + u32 reg; + struct { + u32 res1:20; /* reserved */ + u32 arg:8; /* SCC Debug Command Argument (#) */ + u32 cmd:4; /* SCC Debug Command Register */ + } bits; +}; + +union scc_softwareconfiguration { + u32 reg; + struct { + u32 res1:28; /* reserved */ + u32 clock_status:1; /* clock on/off */ + u32 packet_select:1; /* active SCC packet id */ + u32 enable_status:1; /* enabled [1/0] */ + u32 active_status:1; /* 1=active 0=reset */ + } bits; +}; + +/* + * System on Chip Channel ID + */ +enum scc_id { + SCC_NULL = -1, /* illegal SCC identifier */ + SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */ + SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */ + SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */ + SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */ + SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */ + SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */ + SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */ + SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */ + SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */ + SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */ + SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */ + SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */ + SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */ + SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */ + SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */ + SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */ + SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */ + SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */ + SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */ + SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */ + SCC_TSIO_WR, /* SCC_TSIO Write channel */ + SCC_TSIO_RD, /* SCC_TSIO Read channel */ + SCC_TSD_WR, /* SCC_TSD Write channel */ + SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */ + SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */ + SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */ + SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */ + SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */ + SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */ + SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */ + SCC_GA_WR, /* SCC_GA Write channel */ + SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */ + SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */ + SCC_AD_RD, /* SCC_AD Read channel */ + SCC_AD_WR, /* SCC_AD Write channel */ + SCC_ABP_RD, /* SCC_ABP Read channel */ + SCC_ABP_WR, /* SCC_ABP Write channel */ + SCC_EBI_RW, /* SCC_EBI Read/Write channel */ + SCC_USB_RW, /* SCC_USB Read/Write channel */ + SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */ + SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */ + SCC_MAX /* maximum limit on the SCC id */ +}; + +int scc_set_usb_address_generation_mode(u32 agu_mode); +int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs); +int scc_setup_dma(enum scc_id id, u32 buffer_tag, + u32 type, u32 fh_mode, u32 drs, u32 dma_id); +int scc_enable(enum scc_id id, u32 value); +int scc_reset(enum scc_id id, u32 value); + +#endif /* _SCC_H */ diff --git a/board/micronas/vct/smc_eeprom.c b/board/micronas/vct/smc_eeprom.c new file mode 100644 index 000000000..2bc7ad4c4 --- /dev/null +++ b/board/micronas/vct/smc_eeprom.c @@ -0,0 +1,394 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright 2005, Seagate Technology LLC + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#undef DEBUG + +#include <common.h> +#include <command.h> +#include <config.h> +#include <net.h> + +#include "vct.h" + +#define SMSC9118_BASE CONFIG_DRIVER_SMC911X_BASE +#define BYTE_TEST (SMSC9118_BASE + 0x64) +#define GPIO_CFG (SMSC9118_BASE + 0x88) +#define MAC_CSR_CMD (SMSC9118_BASE + 0xA4) +#define MAC_CSR_CMD_CSR_BUSY (0x80000000) +#define MAC_CSR_CMD_RNW (0x40000000) +#define MAC_RD_CMD(reg) ((reg & 0x000000FF) | \ + (MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_RNW)) +#define MAC_WR_CMD(reg) ((reg & 0x000000FF) | \ + (MAC_CSR_CMD_CSR_BUSY)) +#define MAC_CSR_DATA (SMSC9118_BASE + 0xA8) +#define E2P_CMD (SMSC9118_BASE + 0xB0) +#define E2P_CMD_EPC_BUSY_ (0x80000000UL) /* Self Clearing */ +#define E2P_CMD_EPC_CMD_ (0x70000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) /* R/W */ +#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) /* R/W */ +#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) /* R */ +#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) /* RO */ +#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) /* R/W */ +#define E2P_DATA (SMSC9118_BASE + 0xB4) + +#define MAC_ADDRH (0x2) +#define MAC_ADDRL (0x3) + +#define MAC_TIMEOUT 200 + +#define HIBYTE(word) ((u8)(((u16)(word)) >> 8)) +#define LOBYTE(word) ((u8)(((u16)(word)) & 0x00FFU)) +#define HIWORD(dword) ((u16)(((u32)(dword)) >> 16)) +#define LOWORD(dword) ((u16)(((u32)(dword)) & 0x0000FFFFUL)) + +static int mac_busy(int req_to) +{ + int timeout = req_to; + + while (timeout--) { + if (!(smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)) + goto done; + } + return 1; /* Timeout */ + +done: + return 0; /* No timeout */ +} + +static ulong get_mac_reg(int reg) +{ + ulong reg_val = 0xffffffff; + + if (smc911x_reg_read(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) { + printf("get_mac_reg: previous command not complete\n"); + goto done; + } + + smc911x_reg_write(MAC_CSR_CMD, MAC_RD_CMD(reg)); + udelay(10000); + + if (mac_busy(MAC_TIMEOUT) == 1) { + printf("get_mac_reg: timeout waiting for response from MAC\n"); + goto done; + } + + reg_val = smc911x_reg_read(MAC_CSR_DATA); + +done: + return (reg_val); +} + +static ulong eeprom_enable_access(void) +{ + ulong gpio; + + gpio = smc911x_reg_read(GPIO_CFG); + debug("%s: gpio= 0x%08lx ---> 0x%08lx\n", __func__, gpio, + (gpio & 0xFF0FFFFFUL)); + + smc911x_reg_write(GPIO_CFG, (gpio & 0xFF0FFFFFUL)); + return gpio; +} + +static void eeprom_disable_access(ulong gpio) +{ + debug("%s: gpio= 0x%08lx\n", __func__, gpio); + smc911x_reg_write(GPIO_CFG, gpio); +} + +static int eeprom_is_mac_address_loaded(void) +{ + int ret; + + ret = smc911x_reg_read(MAC_CSR_CMD) & E2P_CMD_MAC_ADDR_LOADED_; + debug("%s: ret = %x\n", __func__, ret); + + return ret; +} + +static int eeprom_read_location(unchar address, u8 *data) +{ + ulong timeout = 100000; + ulong temp = 0; + + if ((temp = smc911x_reg_read(E2P_CMD)) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start, E2P_CMD=0x%08lX\n", __func__, temp); + return 0; + } + + smc911x_reg_write(E2P_CMD, + (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_ | + ((ulong) address))); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout\n"); + return 0; + } + (*data) = (unchar) (smc911x_reg_read(E2P_DATA)); + debug("%s: ret = %x\n", __func__, (*data)); + + return 1; +} + +static int eeprom_enable_erase_and_write(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[1]\n"); + return 0; + } + + return 1; +} + +static int eeprom_disable_erase_and_write(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWDS_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[2]\n"); + return 0; + } + + return 1; +} + +static int eeprom_write_location(unchar address, unchar data) +{ + ulong timeout = 100000; + + debug("%s: address: %x data = %x\n", __func__, address, data); + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + + smc911x_reg_write(E2P_DATA, ((ulong) data)); + smc911x_reg_write(E2P_CMD, + (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_ | + ((ulong) address))); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[3]\n"); + return 0; + } + + return 1; +} + +static int eeprom_erase_all(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return 0; + } + + smc911x_reg_write(E2P_CMD, (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_ERAL_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) { + printf("Timeout[4]\n"); + return 0; + } + + return 1; +} + +static int eeprom_reload(void) +{ + ulong timeout = 100000; + + if (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_) { + printf("%s: Busy at start\n", __func__); + return -1; + } + smc911x_reg_write(E2P_CMD, + (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_)); + + while ((timeout > 0) && (smc911x_reg_read(E2P_CMD) & E2P_CMD_EPC_BUSY_)) { + udelay(10); + timeout--; + } + + if (timeout == 0) + return 0; + + return 1; +} + +static int eeprom_save_mac_address(ulong dwHi16, ulong dwLo32) +{ + int result = 0; + + debug("%s: dwHI: 0x%08lx dwLO: %08lx, \n", __func__, dwHi16, dwLo32); + + if (!eeprom_enable_erase_and_write()) + goto DONE; + if (!eeprom_erase_all()) + goto DONE; + if (!eeprom_write_location(0, 0xA5)) + goto DONE; + if (!eeprom_write_location(1, LOBYTE(LOWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(2, HIBYTE(LOWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(3, LOBYTE(HIWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(4, HIBYTE(HIWORD(dwLo32)))) + goto DONE; + if (!eeprom_write_location(5, LOBYTE(LOWORD(dwHi16)))) + goto DONE; + if (!eeprom_write_location(6, HIBYTE(LOWORD(dwHi16)))) + goto DONE; + if (!eeprom_disable_erase_and_write()) + goto DONE; + + result = 1; + +DONE: + return result; +} + +static int do_eeprom_dump(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unchar data = 0, index = 0; + ulong gpio_old_val; + + gpio_old_val = eeprom_enable_access(); + + printf("EEPROM content: \n"); + for (index = 0; index < 8; index++) { + if (eeprom_read_location(index, &data)) + printf("%02x ", data); + else + printf("FAILED"); + } + + eeprom_disable_access(gpio_old_val); + printf("\n"); + + return 0; +} + +static int do_eeprom_erase_all(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + eeprom_erase_all(); + + return 0; +} + +static int do_eeprom_save_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + ulong hi16, lo32; + unchar ethaddr[6], i; + ulong gpio; + char *tmp, *end; + + tmp = argv[1]; + for (i = 0; i < 6; i++) { + ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end + 1 : end; + } + + hi16 = (ethaddr[5] << 8) | (ethaddr[4]); + lo32 = (ethaddr[3] << 24) | (ethaddr[2] << 16) | + (ethaddr[1] << 8) | (ethaddr[0]); + + gpio = eeprom_enable_access(); + + eeprom_save_mac_address(hi16, lo32); + + eeprom_reload(); + + /* Check new values */ + if (eeprom_is_mac_address_loaded()) { + ulong mac_hi16, mac_lo32; + + mac_hi16 = get_mac_reg(MAC_ADDRH); + mac_lo32 = get_mac_reg(MAC_ADDRL); + printf("New MAC address: %lx, %lx\n", mac_hi16, mac_lo32); + } else { + printf("Address is not reloaded \n"); + } + eeprom_disable_access(gpio); + + return 0; +} + +U_BOOT_CMD(smcee, 1, 0, do_eeprom_erase_all, + "smcee - Erase content of SMC EEPROM\n",); + +U_BOOT_CMD(smced, 1, 0, do_eeprom_dump, + "smced - Dump content of SMC EEPROM\n",); + +U_BOOT_CMD(smcew, 2, 0, do_eeprom_save_mac, + "smcew - Write MAC address to SMC EEPROM\n", + "aa:bb:cc:dd:ee:ff new mac address\n"); diff --git a/board/micronas/vct/top.c b/board/micronas/vct/top.c new file mode 100644 index 000000000..092395484 --- /dev/null +++ b/board/micronas/vct/top.c @@ -0,0 +1,289 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include "vct.h" + +typedef union _TOP_PINMUX_t +{ + u32 reg; + struct { + u32 res : 24; /* reserved */ + u32 drive : 2; /* Driver strength */ + u32 slew : 1; /* Slew rate */ + u32 strig : 1; /* Schmitt trigger input*/ + u32 pu_pd : 2; /* Pull up/ pull down */ + u32 funsel : 2; /* Pin function */ + } Bits; +} TOP_PINMUX_t; + +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) + +static TOP_PINMUX_t top_read_pin(int pin) +{ + TOP_PINMUX_t reg; + + switch (pin) { + case 2: + case 3: + case 6: + case 9: + reg.reg = 0xdeadbeef; + break; + case 4: + reg.reg = reg_read(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE)); + break; + case 5: + reg.reg = reg_read(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE)); + break; + case 7: + reg.reg = reg_read(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE)); + break; + case 8: + reg.reg = reg_read(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE)); + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + reg.reg = reg_read(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + + ((pin - 10) * 4)); + break; + default: + reg.reg = reg_read(TOP_BASE + (pin * 4)); + break; + } + + return reg; +} + +static void top_write_pin(int pin, TOP_PINMUX_t reg) +{ + + switch (pin) { + case 4: + reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg); + break; + case 5: + reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg); + break; + case 7: + reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg); + break; + case 8: + reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg); + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + case 16: + reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + + ((pin - 10) * 4), reg.reg); + break; + default: + reg_write(TOP_BASE + (pin * 4), reg.reg); + break; + } +} + +int top_set_pin(int pin, int func) +{ + TOP_PINMUX_t reg; + + /* check global range */ + if ((pin < 0) || (pin > 170) || (func < 0) || (func > 3)) + return -1; /* pin number or function out of valid range */ + + /* check undefined values; */ + if ((pin == 2) || (pin == 3) || (pin == 6) || (pin == 9)) + return -1; /* pin number out of valid range */ + + reg = top_read_pin(pin); + reg.Bits.funsel = func; + top_write_pin(pin, reg); + + return 0; +} + +#endif + +#if defined(CONFIG_VCT_PLATINUMAVC) + +int top_set_pin(int pin, int func) +{ + TOP_PINMUX_t reg; + + /* check global range */ + if ((pin < 0) || (pin > 158)) + return -1; /* pin number or function out of valid range */ + + reg.reg = reg_read(TOP_BASE + (pin * 4)); + reg.Bits.funsel = func; + reg_write(TOP_BASE + (pin * 4), reg.reg); + + return 0; +} + +#endif + +void vct_pin_mux_initialize(void) +{ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) + top_set_pin(34, 01); /* EBI_CS0 */ + top_set_pin(33, 01); /* EBI_CS1 */ + top_set_pin(32, 01); /* EBI_CS2 */ + top_set_pin(100, 02); /* EBI_CS3 */ + top_set_pin(101, 02); /* EBI_CS4 */ + top_set_pin(102, 02); /* EBI_CS5 */ + top_set_pin(103, 02); /* EBI_CS6 */ + top_set_pin(104, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(35, 01); /* EBI_ALE */ + top_set_pin(36, 01); /* EBI_ADDR15 */ + top_set_pin(37, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ + top_set_pin(38, 01); /* EBI_ADDR13 */ + top_set_pin(39, 01); /* EBI_ADDR12 */ + top_set_pin(40, 01); /* EBI_ADDR11 */ + top_set_pin(41, 01); /* EBI_ADDR10 */ + top_set_pin(42, 01); /* EBI_ADDR9 */ + top_set_pin(43, 01); /* EBI_ADDR8 */ + top_set_pin(44, 01); /* EBI_ADDR7 */ + top_set_pin(45, 01); /* EBI_ADDR6 */ + top_set_pin(46, 01); /* EBI_ADDR5 */ + top_set_pin(47, 01); /* EBI_ADDR4 */ + top_set_pin(48, 01); /* EBI_ADDR3 */ + top_set_pin(49, 01); /* EBI_ADDR2 */ + top_set_pin(50, 01); /* EBI_ADDR1 */ + top_set_pin(51, 01); /* EBI_ADDR0 */ + top_set_pin(52, 01); /* EBI_DIR */ + top_set_pin(53, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ + top_set_pin(54, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ + top_set_pin(55, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ + top_set_pin(56, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ + top_set_pin(57, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ + top_set_pin(58, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ + top_set_pin(59, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ + top_set_pin(60, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ + top_set_pin(61, 01); /* EBI_DAT7 */ + top_set_pin(62, 01); /* EBI_DAT6 */ + top_set_pin(63, 01); /* EBI_DAT5 */ + top_set_pin(64, 01); /* EBI_DAT4 */ + top_set_pin(65, 01); /* EBI_DAT3 */ + top_set_pin(66, 01); /* EBI_DAT2 */ + top_set_pin(67, 01); /* EBI_DAT1 */ + top_set_pin(68, 01); /* EBI_DAT0 */ + top_set_pin(69, 01); /* EBI_IORD */ + top_set_pin(70, 01); /* EBI_IOWR */ + top_set_pin(71, 01); /* EBI_WE */ + top_set_pin(72, 01); /* EBI_OE */ + top_set_pin(73, 01); /* EBI_IORDY */ + top_set_pin(95, 02); /* EBI_EBI_DMACK*/ + top_set_pin(112, 02); /* EBI_IRQ0 */ + top_set_pin(111, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ + top_set_pin(107, 02); /* EBI_IRQ2 */ + top_set_pin(108, 02); /* EBI_IRQ3 */ + top_set_pin(30, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ + top_set_pin(31, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ + top_set_pin(105, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(106, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ + top_set_pin(109, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ + top_set_pin(110, 02); /* EBI_BURST_CLK */ +#endif + +#if defined(CONFIG_VCT_PLATINUMAVC) + top_set_pin(19, 01); /* EBI_CS0 */ + top_set_pin(18, 01); /* EBI_CS1 */ + top_set_pin(17, 01); /* EBI_CS2 */ + top_set_pin(92, 02); /* EBI_CS3 */ + top_set_pin(93, 02); /* EBI_CS4 */ + top_set_pin(95, 02); /* EBI_CS6 */ + top_set_pin(96, 02); /* EBI_CS7 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(20, 01); /* EBI_ALE */ + top_set_pin(21, 01); /* EBI_ADDR15 */ + top_set_pin(22, 01); /* EBI_ADDR14 top_set_pin(78,03); EBI_ADDR14 */ + top_set_pin(23, 01); /* EBI_ADDR13 */ + top_set_pin(24, 01); /* EBI_ADDR12 */ + top_set_pin(25, 01); /* EBI_ADDR11 */ + top_set_pin(26, 01); /* EBI_ADDR10 */ + top_set_pin(27, 01); /* EBI_ADDR9 */ + top_set_pin(28, 01); /* EBI_ADDR8 */ + top_set_pin(29, 01); /* EBI_ADDR7 */ + top_set_pin(30, 01); /* EBI_ADDR6 */ + top_set_pin(31, 01); /* EBI_ADDR5 */ + top_set_pin(32, 01); /* EBI_ADDR4 */ + top_set_pin(33, 01); /* EBI_ADDR3 */ + top_set_pin(34, 01); /* EBI_ADDR2 */ + top_set_pin(35, 01); /* EBI_ADDR1 */ + top_set_pin(36, 01); /* EBI_ADDR0 */ + top_set_pin(37, 01); /* EBI_DIR */ + top_set_pin(38, 01); /* EBI_DAT15 top_set_pin(81,01); EBI_DAT15 */ + top_set_pin(39, 01); /* EBI_DAT14 top_set_pin(82,01); EBI_DAT14 */ + top_set_pin(40, 01); /* EBI_DAT13 top_set_pin(83,01); EBI_DAT13 */ + top_set_pin(41, 01); /* EBI_DAT12 top_set_pin(84,01); EBI_DAT12 */ + top_set_pin(42, 01); /* EBI_DAT11 top_set_pin(85,01); EBI_DAT11 */ + top_set_pin(43, 01); /* EBI_DAT10 top_set_pin(86,01); EBI_DAT10 */ + top_set_pin(44, 01); /* EBI_DAT9 top_set_pin(87,01); EBI_DAT9 */ + top_set_pin(45, 01); /* EBI_DAT8 top_set_pin(88,01); EBI_DAT8 */ + top_set_pin(46, 01); /* EBI_DAT7 */ + top_set_pin(47, 01); /* EBI_DAT6 */ + top_set_pin(48, 01); /* EBI_DAT5 */ + top_set_pin(49, 01); /* EBI_DAT4 */ + top_set_pin(50, 01); /* EBI_DAT3 */ + top_set_pin(51, 01); /* EBI_DAT2 */ + top_set_pin(52, 01); /* EBI_DAT1 */ + top_set_pin(53, 01); /* EBI_DAT0 */ + top_set_pin(54, 01); /* EBI_IORD */ + top_set_pin(55, 01); /* EBI_IOWR */ + top_set_pin(56, 01); /* EBI_WE */ + top_set_pin(57, 01); /* EBI_OE */ + top_set_pin(58, 01); /* EBI_IORDY */ + top_set_pin(87, 02); /* EBI_EBI_DMACK*/ + top_set_pin(106, 02); /* EBI_IRQ0 */ + top_set_pin(105, 02); /* EBI_IRQ1 top_set_pin(111,03); EBI_DMARQ */ + top_set_pin(101, 02); /* EBI_IRQ2 */ + top_set_pin(102, 02); /* EBI_IRQ3 */ + top_set_pin(15, 01); /* EBI_GENIO1 top_set_pin(99,03); EBI_GENIO1 */ + top_set_pin(16, 01); /* EBI_GENIO2 top_set_pin(98,03); EBI_GENIO2 */ + top_set_pin(99, 02); /* EBI_GENIO3 top_set_pin(104,03); EBI_GENIO3 */ + top_set_pin(100, 02); /* EBI_GENIO4 top_set_pin(144,02); EBI_GENIO4 */ + top_set_pin(103, 02); /* EBI_GENIO5 top_set_pin(142,02); EBI_GENIO5 */ + top_set_pin(104, 02); /* EBI_BURST_CLK */ +#endif + + /* I2C: Configure I2C-2 as GPIO to enable soft-i2c */ + top_set_pin(0, 2); /* SCL2 on GPIO 11 */ + top_set_pin(1, 2); /* SDA2 on GPIO 10 */ + + /* UART pins */ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) + top_set_pin(141, 1); + top_set_pin(143, 1); +#endif +#if defined(CONFIG_VCT_PLATINUMAVC) + top_set_pin(107, 1); + top_set_pin(109, 1); +#endif +} diff --git a/board/micronas/vct/u-boot.lds b/board/micronas/vct/u-boot.lds new file mode 100644 index 000000000..da9e60533 --- /dev/null +++ b/board/micronas/vct/u-boot.lds @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, <wd@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = .; + _gp = ALIGN(16) + 0x7ff0; + + .got : { + __got_start = .; + *(.got) + __got_end = .; + } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + . = ALIGN(4); + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } + + . = ALIGN(4); + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss (NOLOAD) : { *(.sbss) } + . = ALIGN(4); + .bss (NOLOAD) : { *(.bss) } + uboot_end = .; +} diff --git a/board/micronas/vct/vct.c b/board/micronas/vct/vct.c new file mode 100644 index 000000000..d320e0b5f --- /dev/null +++ b/board/micronas/vct/vct.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/mipsregs.h> +#include "vct.h" + +#if defined(CONFIG_VCT_PREMIUM) +#define BOARD_NAME "PremiumD" +#elif defined(CONFIG_VCT_PLATINUM) +#define BOARD_NAME "PlatinumD" +#elif defined(CONFIG_VCT_PLATINUMAVC) +#define BOARD_NAME "PlatinumAVC" +#else +#error "vct: No board variant defined!" +#endif + +#if defined(CONFIG_VCT_ONENAND) +#define BOARD_NAME_ADD " OneNAND" +#else +#define BOARD_NAME_ADD " NOR" +#endif + +int board_early_init_f(void) +{ + /* + * First initialize the PIN mulitplexing + */ + vct_pin_mux_initialize(); + + /* + * Init the EBI very early so that FLASH can be accessed + */ + ebi_initialize(); + + return 0; +} + +void _machine_restart(void) +{ + reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT); + reg_write(WDT_TORR(WDT_BASE), 0x00); + reg_write(WDT_CR(WDT_BASE), 0x1D); + + /* + * Now wait for the watchdog to trigger the reset + */ + udelay(1000000); +} + +/* + * SDRAM is already configured by the bootstrap code, only return the + * auto-detected size here + */ +phys_size_t initdram(int board_type) +{ + return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_MBYTES_SDRAM << 20); +} + +int checkboard(void) +{ + u32 config0 = read_c0_prid(); + char *s = getenv("serial#"); + + if ((config0 & 0xff0000) == PRID_COMP_LEGACY + && (config0 & 0xff00) == PRID_IMP_LX4280) { + puts("Board: MDED \n"); + printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n", + (config0 >> 8) & 0xFF, config0 & 0xFF); + } else if ((config0 & 0xff0000) == PRID_COMP_MIPS + && (config0 & 0xff00) == PRID_IMP_VGC) { + u32 jedec_id = *((u32 *) 0xBEBC71A0); + if ((((jedec_id) >> 12) & 0xFF) == 0x40) { + puts("Board: VGCA \n"); + } else if ((((jedec_id) >> 12) & 0xFF) == 0x48 + || (((jedec_id) >> 12) & 0xFF) == 0x49) { + puts("Board: VGCB \n"); + } + printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n", + (config0 >> 8) & 0xFF, config0 & 0xFF); + } else if (config0 == 0x19378) { + printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n", + (config0 >> 8) & 0xFF, config0 & 0xFF); + } else { + printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24, + config0); + } + + printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return 0; +} diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h new file mode 100644 index 000000000..f1a485113 --- /dev/null +++ b/board/micronas/vct/vct.h @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/io.h> + +#include "bcu.h" +#include "dcgu.h" +#include "ebi.h" +#include "scc.h" + +#ifdef CONFIG_VCT_PREMIUM +/* Global start address of all memory mapped registers */ +#define REG_GLOBAL_START_ADDR 0xbf800000 +#define TOP_BASE 0x000c8000 + +#include "vcth/reg_ebi.h" +#include "vcth/reg_dcgu.h" +#include "vcth/reg_wdt.h" +#include "vcth/reg_gpio.h" +#include "vcth/reg_fwsram.h" +#include "vcth/reg_scc.h" +#include "vcth/reg_usbh.h" +#endif + +#ifdef CONFIG_VCT_PLATINUM +/* Global start address of all memory mapped registers */ +#define REG_GLOBAL_START_ADDR 0xbf800000 +#define TOP_BASE 0x000c8000 + +#include "vcth2/reg_ebi.h" +#include "vcth/reg_dcgu.h" +#include "vcth/reg_wdt.h" +#include "vcth/reg_gpio.h" +#include "vcth/reg_fwsram.h" +#include "vcth/reg_scc.h" +#include "vcth/reg_usbh.h" +#endif + +#ifdef CONFIG_VCT_PLATINUMAVC +/* Global start address of all memory mapped registers */ +#define REG_GLOBAL_START_ADDR 0xbdc00000 +#define TOP_BASE 0x00050000 + +#include "vctv/reg_ebi.h" +#include "vctv/reg_dcgu.h" +#include "vctv/reg_wdt.h" +#include "vctv/reg_gpio.h" +#endif + +#ifndef _VCT_H +#define _VCT_H + +/* + * Defines + */ +#define PRID_COMP_LEGACY 0x000000 +#define PRID_COMP_MIPS 0x010000 +#define PRID_IMP_LX4280 0xc200 +#define PRID_IMP_VGC 0x9000 + +/* + * Prototypes + */ +int ebi_initialize(void); +int ebi_init_nor_flash(void); +int ebi_init_onenand(void); +int ebi_init_smc911x(void); +u32 smc911x_reg_read(u32 addr); +void smc911x_reg_write(u32 addr, u32 data); +int top_set_pin(int pin, int func); +void vct_pin_mux_initialize(void); + +/* + * static inlines + */ +static inline void reg_write(u32 addr, u32 data) +{ + __raw_writel(data, addr + REG_GLOBAL_START_ADDR); +} + +static inline u32 reg_read(u32 addr) +{ + return __raw_readl(addr + REG_GLOBAL_START_ADDR); +} + +#endif /* _VCT_H */ diff --git a/board/micronas/vct/vcth/reg_dcgu.h b/board/micronas/vct/vcth/reg_dcgu.h new file mode 100644 index 000000000..6ac0dddc4 --- /dev/null +++ b/board/micronas/vct/vcth/reg_dcgu.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008-2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DCGU_BASE 0x00084000 + +/* Relative offsets of the register adresses */ + +#define DCGU_CLK_EN1_OFFS 0x00000010 +#define DCGU_CLK_EN1(base) ((base) + DCGU_CLK_EN1_OFFS) +#define DCGU_CLK_EN2_OFFS 0x00000014 +#define DCGU_CLK_EN2(base) ((base) + DCGU_CLK_EN2_OFFS) +#define DCGU_RESET_UNIT1_OFFS 0x00000018 +#define DCGU_RESET_UNIT1(base) ((base) + DCGU_RESET_UNIT1_OFFS) +#define DCGU_USBPHY_STAT_OFFS 0x00000054 +#define DCGU_USBPHY_STAT(base) ((base) + DCGU_USBPHY_STAT_OFFS) +#define DCGU_EN_WDT_RESET_OFFS 0x00000064 +#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) + +/* The magic value to write in order to activate the WDT */ +#define DCGU_MAGIC_WDT 0x1909 diff --git a/board/micronas/vct/vcth/reg_ebi.h b/board/micronas/vct/vcth/reg_ebi.h new file mode 100644 index 000000000..7a1e11542 --- /dev/null +++ b/board/micronas/vct/vcth/reg_ebi.h @@ -0,0 +1,242 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_EBI_PREMIUM_H_ +#define _REG_EBI_PREMIUM_H_ + +#define EBI_BASE 0x00000000 + +/* Relative offsets of the register adresses */ + +#define EBI_CPU_IO_ACCS_OFFS 0x00000000 +#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) +#define EBI_IO_ACCS_DATA_OFFS 0x00000004 +#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) +#define EBI_CTRL_OFFS 0x00000008 +#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) +#define EBI_IRQ_MASK_OFFS 0x00000010 +#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) +#define EBI_TAG1_SYS_ID_OFFS 0x00000030 +#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) +#define EBI_TAG2_SYS_ID_OFFS 0x00000040 +#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) +#define EBI_TAG3_SYS_ID_OFFS 0x00000050 +#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) +#define EBI_TAG4_SYS_ID_OFFS 0x00000060 +#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) +#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 +#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) +#define EBI_STATUS_OFFS 0x00000080 +#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) +#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 +#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) +#define EBI_SIG_LEVEL_OFFS 0x00000088 +#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) +#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C +#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) +#define EBI_EXT_ADDR_OFFS 0x000000A0 +#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) +#define EBI_IRQ_STATUS_OFFS 0x000000B0 +#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) +#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 +#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) +#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 +#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) +#define EBI_DEV1_CONFIG1_OFFS 0x00000108 +#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) +#define EBI_DEV1_CONFIG2_OFFS 0x0000010C +#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) +#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 +#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) +#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 +#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) +#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 +#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) +#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C +#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) +#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 +#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) +#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 +#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) +#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C +#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) +#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 +#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) +#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 +#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) +#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 +#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) +#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C +#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) +#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 +#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) +#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 +#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) +#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 +#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) +#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 +#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) +#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 +#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) +#define EBI_DEV2_CONFIG1_OFFS 0x00000208 +#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) +#define EBI_DEV2_CONFIG2_OFFS 0x0000020C +#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) +#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 +#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) +#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 +#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) +#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 +#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) +#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C +#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) +#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 +#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) +#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 +#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) +#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C +#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) +#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 +#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) +#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 +#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) +#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 +#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) +#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C +#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) +#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 +#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) +#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 +#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) +#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 +#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) +#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 +#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) +#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 +#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) +#define EBI_DEV3_CONFIG1_OFFS 0x00000308 +#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) +#define EBI_DEV3_CONFIG2_OFFS 0x0000030C +#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) +#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 +#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) +#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 +#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) +#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 +#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) +#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C +#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) +#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 +#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) +#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 +#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) +#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C +#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) +#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 +#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) +#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 +#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) +#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 +#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) +#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C +#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) +#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 +#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) +#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 +#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) +#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 +#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) +#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 +#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) +#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 +#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) +#define EBI_DEV4_CONFIG1_OFFS 0x00000408 +#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) +#define EBI_DEV4_CONFIG2_OFFS 0x0000040C +#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) +#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 +#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) +#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 +#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) +#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 +#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) +#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C +#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) +#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 +#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) +#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 +#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) +#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C +#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) +#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 +#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) +#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 +#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) +#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 +#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) +#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C +#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) +#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 +#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) +#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 +#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) +#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 +#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) +#define EBI_CNT_FL_PROGR_OFFS 0x00000904 +#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) +#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C +#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) +#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 +#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) +#define EBI_CNT_ACK_OFFS 0x00000918 +#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) +#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 +#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) +#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 +#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) +#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 +#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) +#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 +#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) +#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 +#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) +#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 +#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) +#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 +#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) +#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 +#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) +#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 +#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) +#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 +#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) +#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 +#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) +#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 +#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) +#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 +#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) +#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 +#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) +#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 +#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) + +#endif diff --git a/board/micronas/vct/vcth/reg_fwsram.h b/board/micronas/vct/vcth/reg_fwsram.h new file mode 100644 index 000000000..19afb6bf3 --- /dev/null +++ b/board/micronas/vct/vcth/reg_fwsram.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Premium & Platinum register addresses/definitions seem to be + * identical, so we only need to use one file for both platforms. + */ + +#ifndef _REG_FWSRAM_H_ +#define _REG_FWSRAM_H_ + +#define FWSRAM_BASE 0x00030000 + +/* Relative offsets of the register adresses */ + +#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000 +#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS) +#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004 +#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS) +#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008 +#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS) +#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C +#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS) +#define FWSRAM_TOP_CID1_L_OFFS 0x00002010 +#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS) +#define FWSRAM_TOP_CID2_H_OFFS 0x00002014 +#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS) +#define FWSRAM_TOP_CID2_L_OFFS 0x00002018 +#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS) +#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C +#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040 +#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044 +#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048 +#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C +#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050 +#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054 +#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058 +#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS) +#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C +#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS) +#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060 +#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS) +#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064 +#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS) +#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068 +#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS) + +#endif diff --git a/board/micronas/vct/vcth/reg_gpio.h b/board/micronas/vct/vcth/reg_gpio.h new file mode 100644 index 000000000..7ada9c916 --- /dev/null +++ b/board/micronas/vct/vcth/reg_gpio.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define GPIO1_BASE 0x00088000 +#define GPIO2_BASE 0x0008c000 + +/* Instances */ +#define GPIO_INSTANCES 2 + +/* Relative offsets of the register adresses */ +#define GPIO_SWPORTA_DR_OFFS 0x00000000 +#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) +#define GPIO_SWPORTA_DDR_OFFS 0x00000004 +#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) +#define GPIO_EXT_PORTA_OFFS 0x00000050 +#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) diff --git a/board/micronas/vct/vcth/reg_scc.h b/board/micronas/vct/vcth/reg_scc.h new file mode 100644 index 000000000..5e4bfc573 --- /dev/null +++ b/board/micronas/vct/vcth/reg_scc.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_SCC_PREMIUM_H_ +#define _REG_SCC_PREMIUM_H_ + +#define SCC0_BASE 0x00110000 +#define SCC1_BASE 0x00110080 +#define SCC2_BASE 0x00110100 +#define SCC3_BASE 0x00110180 +#define SCC4_BASE 0x00110200 +#define SCC5_BASE 0x00110280 +#define SCC6_BASE 0x00110300 +#define SCC7_BASE 0x00110380 +#define SCC8_BASE 0x00110400 +#define SCC9_BASE 0x00110480 +#define SCC10_BASE 0x00110500 +#define SCC11_BASE 0x00110580 +#define SCC12_BASE 0x00110600 +#define SCC13_BASE 0x00110680 +#define SCC14_BASE 0x00110700 +#define SCC15_BASE 0x00110780 +#define SCC16_BASE 0x00110800 +#define SCC17_BASE 0x00110880 +#define SCC18_BASE 0x00110900 +#define SCC19_BASE 0x00110980 +#define SCC20_BASE 0x00110a00 +#define SCC21_BASE 0x00110a80 +#define SCC22_BASE 0x00110b00 +#define SCC23_BASE 0x00110b80 +#define SCC24_BASE 0x00110c00 +#define SCC25_BASE 0x00110c80 +#define SCC26_BASE 0x00110d00 +#define SCC27_BASE 0x00110d80 +#define SCC28_BASE 0x00110e00 +#define SCC29_BASE 0x00110e80 +#define SCC30_BASE 0x00110f00 +#define SCC31_BASE 0x00110f80 +#define SCC32_BASE 0x00111000 +#define SCC33_BASE 0x00111080 +#define SCC34_BASE 0x00111100 +#define SCC35_BASE 0x00111180 +#define SCC36_BASE 0x00111200 +#define SCC37_BASE 0x00111280 +#define SCC38_BASE 0x00111300 +#define SCC39_BASE 0x00111380 +#define SCC40_BASE 0x00111400 + +/* Relative offsets of the register adresses */ + +#define SCC_ENABLE_OFFS 0x00000000 +#define SCC_ENABLE(base) ((base) + SCC_ENABLE_OFFS) +#define SCC_RESET_OFFS 0x00000004 +#define SCC_RESET(base) ((base) + SCC_RESET_OFFS) +#define SCC_VCID_OFFS 0x00000008 +#define SCC_VCID(base) ((base) + SCC_VCID_OFFS) +#define SCC_MCI_CFG_OFFS 0x0000000C +#define SCC_MCI_CFG(base) ((base) + SCC_MCI_CFG_OFFS) +#define SCC_PACKET_CFG1_OFFS 0x00000010 +#define SCC_PACKET_CFG1(base) ((base) + SCC_PACKET_CFG1_OFFS) +#define SCC_PACKET_CFG2_OFFS 0x00000014 +#define SCC_PACKET_CFG2(base) ((base) + SCC_PACKET_CFG2_OFFS) +#define SCC_PACKET_CFG3_OFFS 0x00000018 +#define SCC_PACKET_CFG3(base) ((base) + SCC_PACKET_CFG3_OFFS) +#define SCC_DMA_CFG_OFFS 0x0000001C +#define SCC_DMA_CFG(base) ((base) + SCC_DMA_CFG_OFFS) +#define SCC_CMD_OFFS 0x00000020 +#define SCC_CMD(base) ((base) + SCC_CMD_OFFS) +#define SCC_PRIO_OFFS 0x00000024 +#define SCC_PRIO(base) ((base) + SCC_PRIO_OFFS) +#define SCC_DEBUG_OFFS 0x00000028 +#define SCC_DEBUG(base) ((base) + SCC_DEBUG_OFFS) +#define SCC_STATUS_OFFS 0x0000002C +#define SCC_STATUS(base) ((base) + SCC_STATUS_OFFS) +#define SCC_IMR_OFFS 0x00000030 +#define SCC_IMR(base) ((base) + SCC_IMR_OFFS) +#define SCC_ISR_OFFS 0x00000034 +#define SCC_ISR(base) ((base) + SCC_ISR_OFFS) +#define SCC_DMA_OFFSET_OFFS 0x00000038 +#define SCC_DMA_OFFSET(base) ((base) + SCC_DMA_OFFSET_OFFS) +#define SCC_RS_CTLSTS_OFFS 0x0000003C +#define SCC_RS_CTLSTS(base) ((base) + SCC_RS_CTLSTS_OFFS) + +#endif diff --git a/board/micronas/vct/vcth/reg_usbh.h b/board/micronas/vct/vcth/reg_usbh.h new file mode 100644 index 000000000..9187a342e --- /dev/null +++ b/board/micronas/vct/vcth/reg_usbh.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define USBH_BASE 0x00080000 + +/* Relative offsets of the register adresses */ + +#define USBH_CAPLENGTH_OFFS 0x00000100 +#define USBH_CAPLENGTH(base) ((base) + USBH_CAPLENGTH_OFFS) +#define USBH_USBCMD_OFFS 0x00000140 +#define USBH_USBCMD(base) ((base) + USBH_USBCMD_OFFS) +#define USBH_BURSTSIZE_OFFS 0x00000160 +#define USBH_BURSTSIZE(base) ((base) + USBH_BURSTSIZE_OFFS) +#define USBH_USBMODE_OFFS 0x000001A8 +#define USBH_USBMODE(base) ((base) + USBH_USBMODE_OFFS) +#define USBH_USBHMISC_OFFS 0x00000200 +#define USBH_USBHMISC(base) ((base) + USBH_USBHMISC_OFFS) diff --git a/board/micronas/vct/vcth/reg_wdt.h b/board/micronas/vct/vcth/reg_wdt.h new file mode 100644 index 000000000..a9b4bf03a --- /dev/null +++ b/board/micronas/vct/vcth/reg_wdt.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define WDT_BASE 0x000b0000 +#define WDT_CR_OFFS 0x00000000 +#define WDT_CR(base) ((base) + WDT_CR_OFFS) +#define WDT_TORR_OFFS 0x00000004 +#define WDT_TORR(base) ((base) + WDT_TORR_OFFS) diff --git a/board/micronas/vct/vcth2/reg_ebi.h b/board/micronas/vct/vcth2/reg_ebi.h new file mode 100644 index 000000000..37f071195 --- /dev/null +++ b/board/micronas/vct/vcth2/reg_ebi.h @@ -0,0 +1,290 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_EBI_PREMIUM_H_ +#define _REG_EBI_PREMIUM_H_ + +#define EBI_BASE 0x00000000 + +/* Relative offsets of the register adresses */ + +#define EBI_CPU_IO_ACCS_OFFS 0x00000000 +#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) +#define EBI_IO_ACCS_DATA_OFFS 0x00000004 +#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) +#define EBI_CPU_IO_ACCS2_OFFS 0x00000008 +#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) +#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C +#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) +#define EBI_CTRL_OFFS 0x00000010 +#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) +#define EBI_IRQ_MASK_OFFS 0x00000018 +#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) +#define EBI_IRQ_MASK2_OFFS 0x0000001C +#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) +#define EBI_TAG1_SYS_ID_OFFS 0x00000030 +#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) +#define EBI_TAG2_SYS_ID_OFFS 0x00000040 +#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) +#define EBI_TAG3_SYS_ID_OFFS 0x00000050 +#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) +#define EBI_TAG4_SYS_ID_OFFS 0x00000060 +#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) +#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 +#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) +#define EBI_STATUS_OFFS 0x00000080 +#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) +#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 +#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) +#define EBI_SIG_LEVEL_OFFS 0x00000088 +#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) +#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C +#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) +#define EBI_CRC_GEN_OFFS 0x00000090 +#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) +#define EBI_EXT_ADDR_OFFS 0x000000A0 +#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) +#define EBI_IRQ_STATUS_OFFS 0x000000B0 +#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) +#define EBI_IRQ_STATUS2_OFFS 0x000000B4 +#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS) +#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0 +#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS) +#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4 +#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS) +#define EBI_ECC0_OFFS 0x000000D0 +#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) +#define EBI_ECC1_OFFS 0x000000D4 +#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) +#define EBI_ECC2_OFFS 0x000000D8 +#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) +#define EBI_ECC3_OFFS 0x000000DC +#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS) +#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 +#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) +#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 +#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) +#define EBI_DEV1_CONFIG1_OFFS 0x00000108 +#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) +#define EBI_DEV1_CONFIG2_OFFS 0x0000010C +#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) +#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 +#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) +#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 +#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) +#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 +#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) +#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C +#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) +#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120 +#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS) +#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 +#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) +#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 +#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) +#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C +#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) +#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 +#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) +#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 +#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) +#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 +#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) +#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C +#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) +#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 +#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) +#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 +#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) +#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148 +#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS) +#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C +#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS) +#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 +#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) +#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 +#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) +#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 +#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) +#define EBI_DEV2_CONFIG1_OFFS 0x00000208 +#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) +#define EBI_DEV2_CONFIG2_OFFS 0x0000020C +#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) +#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 +#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) +#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 +#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) +#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 +#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) +#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C +#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) +#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220 +#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS) +#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 +#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) +#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 +#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) +#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C +#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) +#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 +#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) +#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 +#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) +#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 +#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) +#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C +#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) +#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 +#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) +#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 +#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) +#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248 +#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS) +#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C +#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS) +#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 +#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) +#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 +#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) +#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 +#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) +#define EBI_DEV3_CONFIG1_OFFS 0x00000308 +#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) +#define EBI_DEV3_CONFIG2_OFFS 0x0000030C +#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) +#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 +#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) +#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 +#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) +#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 +#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) +#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C +#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) +#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320 +#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS) +#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 +#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) +#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 +#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) +#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C +#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) +#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 +#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) +#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 +#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) +#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 +#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) +#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C +#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) +#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 +#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) +#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 +#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) +#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348 +#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS) +#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C +#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS) +#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 +#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) +#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 +#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) +#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 +#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) +#define EBI_DEV4_CONFIG1_OFFS 0x00000408 +#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) +#define EBI_DEV4_CONFIG2_OFFS 0x0000040C +#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) +#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 +#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) +#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 +#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) +#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 +#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) +#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C +#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) +#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420 +#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS) +#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 +#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) +#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 +#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) +#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C +#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) +#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 +#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) +#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 +#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) +#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 +#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) +#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C +#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) +#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 +#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) +#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 +#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) +#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448 +#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS) +#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C +#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS) +#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 +#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) +#define EBI_INTERLEAVE_CNT_OFFS 0x00000900 +#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS) +#define EBI_CNT_FL_PROGR_OFFS 0x00000904 +#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) +#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C +#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) +#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 +#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) +#define EBI_CNT_ACK_OFFS 0x00000918 +#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) +#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 +#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) +#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 +#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) +#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 +#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) +#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 +#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) +#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 +#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) +#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 +#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) +#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 +#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) +#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 +#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) +#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 +#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) +#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 +#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) +#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 +#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) +#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 +#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) +#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 +#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) +#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 +#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) +#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 +#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) + +#endif diff --git a/board/micronas/vct/vctv/reg_dcgu.h b/board/micronas/vct/vctv/reg_dcgu.h new file mode 100644 index 000000000..6f5c96842 --- /dev/null +++ b/board/micronas/vct/vctv/reg_dcgu.h @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define DCGU_BASE 0x0004c000 +#define DCGU_EN_WDT_RESET_OFFS 0x000000FC +#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS) + +/* The magic value to write in order to activate the WDT */ +#define DCGU_MAGIC_WDT 0x1909 diff --git a/board/micronas/vct/vctv/reg_ebi.h b/board/micronas/vct/vctv/reg_ebi.h new file mode 100644 index 000000000..82f345e36 --- /dev/null +++ b/board/micronas/vct/vctv/reg_ebi.h @@ -0,0 +1,290 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * Copyright (C) 2006 Micronas GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _REG_EBI_PLATINUMAVC_H_ +#define _REG_EBI_PLATINUMAVC_H_ + +#define EBI_BASE 0x00014000 + +/* Relative offsets of the register adresses */ + +#define EBI_CPU_IO_ACCS_OFFS 0x00000000 +#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS) +#define EBI_IO_ACCS_DATA_OFFS 0x00000004 +#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS) +#define EBI_CPU_IO_ACCS2_OFFS 0x00000008 +#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS) +#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C +#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS) +#define EBI_CTRL_OFFS 0x00000010 +#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS) +#define EBI_IRQ_MASK_OFFS 0x00000018 +#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS) +#define EBI_IRQ_MASK2_OFFS 0x0000001C +#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS) +#define EBI_TAG1_SYS_ID_OFFS 0x00000030 +#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS) +#define EBI_TAG2_SYS_ID_OFFS 0x00000040 +#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS) +#define EBI_TAG3_SYS_ID_OFFS 0x00000050 +#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS) +#define EBI_TAG4_SYS_ID_OFFS 0x00000060 +#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS) +#define EBI_GEN_DMA_CTRL_OFFS 0x00000070 +#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS) +#define EBI_STATUS_OFFS 0x00000080 +#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS) +#define EBI_STATUS_DMA_CNT_OFFS 0x00000084 +#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS) +#define EBI_SIG_LEVEL_OFFS 0x00000088 +#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS) +#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C +#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS) +#define EBI_CRC_GEN_OFFS 0x00000090 +#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS) +#define EBI_EXT_ADDR_OFFS 0x000000A0 +#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS) +#define EBI_IRQ_STATUS_OFFS 0x000000B0 +#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS) +#define EBI_IRQ_STATUS2_OFFS 0x000000B4 +#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS) +#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0 +#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS) +#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4 +#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS) +#define EBI_ECC0_OFFS 0x000000D0 +#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS) +#define EBI_ECC1_OFFS 0x000000D4 +#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS) +#define EBI_ECC2_OFFS 0x000000D8 +#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS) +#define EBI_ECC3_OFFS 0x000000DC +#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS) +#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100 +#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS) +#define EBI_DEV1_EXT_ACC_OFFS 0x00000104 +#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS) +#define EBI_DEV1_CONFIG1_OFFS 0x00000108 +#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS) +#define EBI_DEV1_CONFIG2_OFFS 0x0000010C +#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS) +#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110 +#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS) +#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114 +#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS) +#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118 +#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS) +#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C +#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS) +#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120 +#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS) +#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124 +#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS) +#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128 +#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS) +#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C +#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS) +#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130 +#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS) +#define EBI_DEV1_TIM_EXT_OFFS 0x00000134 +#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS) +#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138 +#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS) +#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C +#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS) +#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140 +#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS) +#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144 +#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS) +#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148 +#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS) +#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C +#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS) +#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150 +#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS) +#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200 +#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS) +#define EBI_DEV2_EXT_ACC_OFFS 0x00000204 +#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS) +#define EBI_DEV2_CONFIG1_OFFS 0x00000208 +#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS) +#define EBI_DEV2_CONFIG2_OFFS 0x0000020C +#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS) +#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210 +#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS) +#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214 +#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS) +#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218 +#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS) +#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C +#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS) +#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220 +#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS) +#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224 +#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS) +#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228 +#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS) +#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C +#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS) +#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230 +#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS) +#define EBI_DEV2_TIM_EXT_OFFS 0x00000234 +#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS) +#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238 +#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS) +#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C +#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS) +#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240 +#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS) +#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244 +#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS) +#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248 +#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS) +#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C +#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS) +#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250 +#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS) +#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300 +#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS) +#define EBI_DEV3_EXT_ACC_OFFS 0x00000304 +#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS) +#define EBI_DEV3_CONFIG1_OFFS 0x00000308 +#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS) +#define EBI_DEV3_CONFIG2_OFFS 0x0000030C +#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS) +#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310 +#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS) +#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314 +#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS) +#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318 +#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS) +#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C +#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS) +#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320 +#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS) +#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324 +#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS) +#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328 +#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS) +#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C +#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS) +#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330 +#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS) +#define EBI_DEV3_TIM_EXT_OFFS 0x00000334 +#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS) +#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338 +#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS) +#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C +#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS) +#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340 +#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS) +#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344 +#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS) +#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348 +#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS) +#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C +#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS) +#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350 +#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS) +#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400 +#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS) +#define EBI_DEV4_EXT_ACC_OFFS 0x00000404 +#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS) +#define EBI_DEV4_CONFIG1_OFFS 0x00000408 +#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS) +#define EBI_DEV4_CONFIG2_OFFS 0x0000040C +#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS) +#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410 +#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS) +#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414 +#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS) +#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418 +#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS) +#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C +#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS) +#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420 +#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS) +#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424 +#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS) +#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428 +#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS) +#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C +#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS) +#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430 +#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS) +#define EBI_DEV4_TIM_EXT_OFFS 0x00000434 +#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS) +#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438 +#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS) +#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C +#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS) +#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440 +#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS) +#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444 +#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS) +#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448 +#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS) +#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C +#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS) +#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450 +#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS) +#define EBI_INTERLEAVE_CNT_OFFS 0x00000900 +#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS) +#define EBI_CNT_FL_PROGR_OFFS 0x00000904 +#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS) +#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C +#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS) +#define EBI_CNT_WAIT_RDY_OFFS 0x00000914 +#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS) +#define EBI_CNT_ACK_OFFS 0x00000918 +#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS) +#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00 +#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS) +#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04 +#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS) +#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08 +#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS) +#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10 +#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS) +#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14 +#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS) +#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18 +#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS) +#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20 +#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS) +#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24 +#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS) +#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28 +#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS) +#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30 +#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS) +#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34 +#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS) +#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38 +#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS) +#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40 +#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS) +#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44 +#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS) +#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48 +#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS) + +#endif diff --git a/board/micronas/vct/vctv/reg_gpio.h b/board/micronas/vct/vctv/reg_gpio.h new file mode 100644 index 000000000..24eb8e965 --- /dev/null +++ b/board/micronas/vct/vctv/reg_gpio.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define GPIO1_BASE 0x00044000 +#define GPIO2_BASE 0x00048000 + +/* Instances */ +#define GPIO_INSTANCES 2 + +/* Relative offsets of the register adresses */ +#define GPIO_SWPORTA_DR_OFFS 0x00000000 +#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS) +#define GPIO_SWPORTA_DDR_OFFS 0x00000004 +#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS) +#define GPIO_EXT_PORTA_OFFS 0x00000050 +#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS) diff --git a/board/micronas/vct/vctv/reg_wdt.h b/board/micronas/vct/vctv/reg_wdt.h new file mode 100644 index 000000000..04842e59d --- /dev/null +++ b/board/micronas/vct/vctv/reg_wdt.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define WDT_BASE 0x00040000 +#define WDT_CR_OFFS 0x00000000 +#define WDT_CR(base) ((base) + WDT_CR_OFFS) +#define WDT_TORR_OFFS 0x00000004 +#define WDT_TORR(base) ((base) + WDT_TORR_OFFS) diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index bf270f4ce..72a1ad32f 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -50,7 +50,7 @@ int checkboard (void) get_sys_info (&sysinfo); printf ("Board: Freescale MPC8540EVAL Board\n"); - printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); + printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000); printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000); printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 877a2d004..d16939120 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -559,7 +559,7 @@ int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } #endif - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } diff --git a/board/mpl/mip405/cmd_mip405.c b/board/mpl/mip405/cmd_mip405.c index 6ad95b5dd..dc1380445 100644 --- a/board/mpl/mip405/cmd_mip405.c +++ b/board/mpl/mip405/cmd_mip405.c @@ -55,7 +55,7 @@ int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( mip405, 8, 1, do_mip405, - "mip405 - MIP405 specific Cmds\n", + "MIP405 specific Cmds", "flash mem [SrcAddr] - updates U-Boot with image in memory\n" "mip405 flash mps - updates U-Boot with image from MPS\n" "mip405 info - displays board information\n" diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c index 9d9531b54..95bfdcc8c 100644 --- a/board/mpl/pati/cmd_pati.c +++ b/board/mpl/pati/cmd_pati.c @@ -427,7 +427,7 @@ int do_pati(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( pati, 8, 1, do_pati, - "pati - PATI specific Cmds\n", + "PATI specific Cmds", "info - displays board information\n" "pati pci - displays PCI registers\n" "pati led <nr> <on> \n" diff --git a/board/mpl/pip405/cmd_pip405.c b/board/mpl/pip405/cmd_pip405.c index 945e5c958..ad5e0a1e1 100644 --- a/board/mpl/pip405/cmd_pip405.c +++ b/board/mpl/pip405/cmd_pip405.c @@ -60,7 +60,7 @@ int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( pip405, 6, 1, do_pip405, - "pip405 - PIP405 specific Cmds\n", + "PIP405 specific Cmds", "flash mem [SrcAddr] - updates U-Boot with image in memory\n" "pip405 flash floppy [SrcAddr] - updates U-Boot with image from floppy\n" "pip405 flash mps - updates U-Boot with image from MPS\n" diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index d3629c589..2748fa97f 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -175,6 +175,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( vcma9, 6, 1, do_vcma9, - "vcma9 - VCMA9 specific commands\n", + "VCMA9 specific commands", "flash mem [SrcAddr]\n - updates U-Boot with image in memory\n" ); diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c index a3dbdc846..80c2cb58e 100644 --- a/board/pcippc2/pcippc2.c +++ b/board/pcippc2/pcippc2.c @@ -230,13 +230,13 @@ int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) default: break; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( wd, 2, 1, do_wd, - "wd - check and set watchdog\n", + "check and set watchdog", "on - switch watchDog on\n" "wd off - switch watchdog off\n" "wd - print current status\n" diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 271005f0f..5fd3291e4 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -761,7 +761,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( led, 2, 1, do_led, - "led [bitmask] - set the DIAG-LED\n", + "set the DIAG-LED", "[bitmask] 0x01 = DIAG 1 on\n" " 0x02 = DIAG 2 on\n" " 0x04 = DIAG 3 on\n" @@ -780,7 +780,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argc < 2) { usage: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -823,7 +823,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sha1, 4, 1, do_sha1, - "sha1 - calculate the SHA1 Sum\n", + "calculate the SHA1 Sum", "address len [addr] calculate the SHA1 sum [save at addr]\n" " -p calculate the SHA1 sum from the U-Boot image in flash and print\n" " -c check the U-Boot image in flash\n" diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c index 3f53e4b7c..10d0df63a 100644 --- a/board/pn62/cmd_pn62.c +++ b/board/pn62/cmd_pn62.c @@ -41,7 +41,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned int number, function; if (argc != 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } number = simple_strtoul(argv[1], NULL, 10); @@ -53,7 +53,7 @@ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( led , 3, 1, do_led, - "led - set LED 0..11 on the PN62 board\n", + "set LED 0..11 on the PN62 board", "i fun\n" " - set 'i'th LED to function 'fun'\n" ); @@ -83,7 +83,7 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[1], NULL, 16); break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -174,7 +174,7 @@ int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( loadpci, 2, 1, do_loadpci, - "loadpci - load binary file over PCI\n", + "load binary file over PCI", "[addr]\n" " - load binary file over PCI to address 'addr'\n" ); diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c index 3773ba181..877728403 100644 --- a/board/prodrive/pdnb3/pdnb3.c +++ b/board/prodrive/pdnb3/pdnb3.c @@ -216,7 +216,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong addr; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -227,7 +227,7 @@ int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( fpga, 2, 0, do_fpga, - "fpga - boot FPGA\n", + "boot FPGA", "address size\n - boot FPGA with gzipped image at <address>\n" ); diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index b0aa8dda8..aa598aaa4 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -128,7 +128,7 @@ int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd, - "idpcmd - custom IDP command\n", + "custom IDP command", "no args at this time\n" ); diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c index b502e4d78..1871984a6 100644 --- a/board/r360mpi/r360mpi.c +++ b/board/r360mpi/r360mpi.c @@ -414,6 +414,6 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", + "read keyboard status", NULL ); diff --git a/board/renesas/sh7785lcr/rtl8169_mac.c b/board/renesas/sh7785lcr/rtl8169_mac.c index bf0ba145d..6d0bbc0c2 100644 --- a/board/renesas/sh7785lcr/rtl8169_mac.c +++ b/board/renesas/sh7785lcr/rtl8169_mac.c @@ -305,7 +305,7 @@ int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *s, *e; if (argc != 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -323,7 +323,7 @@ int do_set_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( setmac, 2, 1, do_set_mac, - "setmac - write MAC address for RTL8110SCL\n", + "write MAC address for RTL8110SCL", "\n" "setmac <mac address> - write MAC address for RTL8110SCL\n" ); @@ -331,7 +331,7 @@ U_BOOT_CMD( int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc != 1) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -342,7 +342,7 @@ int do_print_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( printmac, 1, 1, do_print_mac, - "printmac - print MAC address for RTL8110\n", + "print MAC address for RTL8110", "\n" " - print MAC address for RTL8110\n" ); diff --git a/board/renesas/sh7785lcr/selfcheck.c b/board/renesas/sh7785lcr/selfcheck.c index ce0620f68..6dbb7842e 100644 --- a/board/renesas/sh7785lcr/selfcheck.c +++ b/board/renesas/sh7785lcr/selfcheck.c @@ -113,7 +113,7 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) char *cmd; if (argc != 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -150,7 +150,7 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) test_net(); break; default: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -159,7 +159,7 @@ int do_hw_test(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( hwtest, 2, 1, do_hw_test, - "hwtest - hardware test for R0P7785LC0011RL board\n", + "hardware test for R0P7785LC0011RL board", "\n" "hwtest all - test all hardware\n" "hwtest pld - output PLD version\n" diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c index 9af6b8d88..c1af70cea 100644 --- a/board/sandburst/common/ppc440gx_i2c.c +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -500,7 +500,7 @@ int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( iprobe1, 1, 1, do_i2c1_probe, - "iprobe1 - probe to discover valid I2C chip addresses\n", + "probe to discover valid I2C chip addresses", "\n -discover valid I2C chip addresses\n" ); diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 8d97a9c35..9b94af550 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -578,7 +578,7 @@ int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(kasetup, 1, 1, karefSetupVars, - "kasetup - Set environment to factory defaults\n", NULL); + "Set environment to factory defaults", NULL); U_BOOT_CMD(karecover, 1, 1, karefRecover, - "karecover - Set environment to allow for fs recovery\n", NULL); + "Set environment to allow for fs recovery", NULL); diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index 19302dc61..ec4c45153 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -544,7 +544,7 @@ int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars, - "mbsetup - Set environment to factory defaults\n", NULL); + "Set environment to factory defaults", NULL); U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover, - "mbrecover - Set environment to allow for fs recovery\n", NULL); + "Set environment to allow for fs recovery", NULL); diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 3d4008b00..7f032c8fa 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -247,7 +247,7 @@ int checkboard (void) #else printf ("Board: Wind River SBC8540 Board\n"); #endif - printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor)); + printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0])); printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus)); printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2)); if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \ diff --git a/board/siemens/common/fpga.c b/board/siemens/common/fpga.c index ac0022e7b..c9a93e158 100644 --- a/board/siemens/common/fpga.c +++ b/board/siemens/common/fpga.c @@ -286,13 +286,13 @@ int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; failure: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( fpga, 4, 1, do_fpga, - "fpga - access FPGA(s)\n", + "access FPGA(s)", "fpga status [name] - print FPGA status\n" "fpga reset [name] - reset FPGA\n" "fpga load [name] addr - load FPGA configuration data\n" diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c index a60c825b2..f87d6bc00 100644 --- a/board/siemens/pcu_e/pcu_e.c +++ b/board/siemens/pcu_e/pcu_e.c @@ -399,12 +399,12 @@ int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) default: break; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD (puma, 4, 1, do_puma, - "puma - access PUMA FPGA\n", + "access PUMA FPGA", "status - print PUMA status\n" "puma load addr len - load PUMA configuration data\n"); diff --git a/board/ssv/common/cmd_sled.c b/board/ssv/common/cmd_sled.c index 2208580fa..99ff50760 100644 --- a/board/ssv/common/cmd_sled.c +++ b/board/ssv/common/cmd_sled.c @@ -133,7 +133,7 @@ int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) default: break; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -156,7 +156,7 @@ int do_sled (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #endif U_BOOT_CMD (sled, 3, 0, do_sled, - "sled - check and set status led\n", + "check and set status led", "sled [name [state]]\n" __NAME_STR " - state: on|off|blink\n"); #endif #endif /* CONFIG_STATUS_LED */ diff --git a/board/ssv/common/wd_pio.c b/board/ssv/common/wd_pio.c index 9945c5987..9b384259e 100644 --- a/board/ssv/common/wd_pio.c +++ b/board/ssv/common/wd_pio.c @@ -145,13 +145,13 @@ int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) default: break; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( wd, 2, 1, do_wd, - "wd - check and set watchdog\n", + "check and set watchdog", "on - switch watchDog on\n" "wd off - switch watchdog off\n" "wd - print current status\n" diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c index 5483fcaf7..20632a7f1 100644 --- a/board/tqc/tqm5200/cmd_stk52xx.c +++ b/board/tqc/tqm5200/cmd_stk52xx.c @@ -327,7 +327,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) switch (argc) { case 0: case 1: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 2: if (strncmp(argv[1],"saw",3) == 0) { @@ -342,7 +342,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return rcode; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 3: if (strncmp(argv[1],"saw",3) == 0) { @@ -358,7 +358,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) LEFT_RIGHT); return rcode; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 4: if (strncmp(argv[1],"saw",3) == 0) { @@ -382,7 +382,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) pcm1772_write_reg((uchar)reg, (uchar)val); return 0; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 5: if (strncmp(argv[1],"saw",3) == 0) { @@ -412,7 +412,7 @@ static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) channel); return rcode; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } printf ("Usage:\nsound cmd [arg1] [arg2] ...\n"); @@ -513,7 +513,7 @@ static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) channel = LEFT_RIGHT; break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -1194,7 +1194,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sound , 5, 1, cmd_sound, - "sound - Sound sub-system\n", + "Sound sub-system", "saw [duration] [freq] [channel]\n" " - generate sawtooth for 'duration' ms with frequency 'freq'\n" " on left \"l\" or right \"r\" channel\n" @@ -1206,14 +1206,14 @@ U_BOOT_CMD( U_BOOT_CMD( wav , 3, 1, cmd_wav, - "wav - play wav file\n", + "play wav file", "[addr] [bytes]\n" " - play wav file at address 'addr' with length 'bytes'\n" ); U_BOOT_CMD( beep , 2, 1, cmd_beep, - "beep - play short beep\n", + "play short beep", "[channel]\n" " - play short beep on \"l\"eft or \"r\"ight channel\n" ); @@ -1222,7 +1222,7 @@ U_BOOT_CMD( #if defined(CONFIG_STK52XX) U_BOOT_CMD( fkt , 4, 1, cmd_fkt, - "fkt - Function test routines\n", + "Function test routines", "led number on/off\n" " - 'number's like printed on STK52XX board\n" "fkt can\n" @@ -1237,7 +1237,7 @@ U_BOOT_CMD( #elif defined(CONFIG_FO300) U_BOOT_CMD( fkt , 3, 1, cmd_fkt, - "fkt - Function test routines\n", + "Function test routines", "fkt can\n" " - loopback plug for X16/X29 required\n" "fkt rs232 number\n" diff --git a/board/tqc/tqm5200/cmd_tb5200.c b/board/tqc/tqm5200/cmd_tb5200.c index 214dca65e..b9c9e7e19 100644 --- a/board/tqc/tqm5200/cmd_tb5200.c +++ b/board/tqc/tqm5200/cmd_tb5200.c @@ -90,13 +90,13 @@ int cmd_backlight(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( led , 2, 1, cmd_led, - "led - switch status LED on or off\n", + "switch status LED on or off", "on/off\n" ); U_BOOT_CMD( backlight , 2, 1, cmd_backlight, - "backlight - switch backlight on or off\n", + "switch backlight on or off", "on/off\n" ); diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c index 5d0741d80..5bc080ff8 100644 --- a/board/tqc/tqm8272/tqm8272.c +++ b/board/tqc/tqm8272/tqm8272.c @@ -866,7 +866,7 @@ int do_hwib_dump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( hwib, 1, 1, do_hwib_dump, - "hwib - dump HWIB'\n", + "dump HWIB'", "\n" ); diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index daa6aeefc..7e2a67234 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -168,7 +168,7 @@ int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int cycle_status; if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -258,7 +258,7 @@ int do_burn_in (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( burn_in, 1, 1, do_burn_in, - "burn_in - start burn-in test application on TRAB\n", + "start burn-in test application on TRAB", "\n" " - start burn-in test application\n" " The burn-in test could took a while to finish!\n" @@ -271,7 +271,7 @@ int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int i, dip; if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -292,7 +292,7 @@ int do_dip (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( dip, 1, 1, do_dip, - "dip - read dip switch on TRAB\n", + "read dip switch on TRAB", "\n" " - read state of dip switch (S1) on TRAB board\n" " read sequence: 1-2-3-4; ON=1; OFF=0; e.g.: \"0100\"\n" @@ -304,7 +304,7 @@ int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int vcc5v; if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -321,7 +321,7 @@ int do_vcc5v (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( vcc5v, 1, 1, do_vcc5v, - "vcc5v - read VCC5V on TRAB\n", + "read VCC5V on TRAB", "\n" " - read actual value of voltage VCC5V\n" ); @@ -332,7 +332,7 @@ int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int contact_temp; if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -346,7 +346,7 @@ int do_contact_temp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( c_temp, 1, 1, do_contact_temp, - "c_temp - read contact temperature on TRAB\n", + "read contact temperature on TRAB", "\n" " - reads the onboard temperature (=contact temperature)\n" ); @@ -355,7 +355,7 @@ U_BOOT_CMD( int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc > 1) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -398,7 +398,7 @@ int do_burn_in_status (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( bis, 1, 1, do_burn_in_status, - "bis - print burn in status on TRAB\n", + "print burn in status on TRAB", "\n" " - prints the status variables of the last burn in test\n" " stored in the onboard EEPROM on TRAB board\n" @@ -851,7 +851,7 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif if (argc > 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -886,7 +886,7 @@ int do_temp_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( tlog, 2, 1, do_temp_log, - "tlog - log contact temperature [1/100 C] to console (endlessly)\n", + "log contact temperature [1/100 C] to console (endlessly)", "delay\n" " - contact temperature [1/100 C] is printed endlessly to console\n" " <delay> specifies the seconds to wait between two measurements\n" diff --git a/board/trab/trab.c b/board/trab/trab.c index 57ff71878..7fcc4507f 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -322,7 +322,7 @@ int do_kbd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( kbd, 1, 1, do_kbd, - "kbd - read keyboard status\n", + "read keyboard status", NULL ); diff --git a/board/trizepsiv/eeprom.c b/board/trizepsiv/eeprom.c index 7a2b90585..63f1c6cdf 100644 --- a/board/trizepsiv/eeprom.c +++ b/board/trizepsiv/eeprom.c @@ -43,7 +43,7 @@ static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * int offset,value; if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -51,7 +51,7 @@ static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * value=simple_strtoul(argv[3],NULL,16); if (offset > 0x40) { printf("Wrong offset : 0x%x\n",offset); - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } write_srom_word(offset, value); @@ -60,7 +60,7 @@ static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -69,14 +69,14 @@ int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { } else if (strcmp (argv[1],"write") == 0) { return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv)); } else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } } U_BOOT_CMD( dm9000ee,4,1,do_dm9000_eeprom, - "dm9000ee- Read/Write eeprom connected to Ethernet Controller\n", + "Read/Write eeprom connected to Ethernet Controller", "\ndm9000ee write <word offset> <value> \n" "\tdm9000ee read \n" "\tword:\t\t00-02 : MAC Address\n" diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c index 310fde052..eaec940e6 100644 --- a/board/w7o/cmd_vpd.c +++ b/board/w7o/cmd_vpd.c @@ -39,7 +39,7 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* Validate usage */ if (argc > 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -58,7 +58,7 @@ int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( vpd, 2, 1, do_vpd, - "vpd - Read Vital Product Data\n", + "Read Vital Product Data", "[dev_addr]\n" " - Read VPD Data from default address, or device address 'dev_addr'.\n" ); diff --git a/board/zeus/update.c b/board/zeus/update.c index 2f2a127f7..ce1f34fee 100644 --- a/board/zeus/update.c +++ b/board/zeus/update.c @@ -98,7 +98,7 @@ int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) U_BOOT_CMD ( update_boot_eeprom, 1, 1, do_update_boot_eeprom, - "update_boot_eeprom - update boot eeprom content\n", + "update boot eeprom content", NULL ); diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 974bdf29c..3f329c2fc 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -327,7 +327,7 @@ int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( setdef, 4, 1, do_set_default, - "setdef - write board-specific values to EEPROM (ethaddr...)\n", + "write board-specific values to EEPROM (ethaddr...)", "ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n" ); @@ -418,7 +418,7 @@ int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[]) U_BOOT_CMD ( chkreset, 1, 1, do_chkreset, - "chkreset- Check for status of SW-reset button and act accordingly\n", + "Check for status of SW-reset button and act accordingly", NULL ); diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S index ff17c7e7b..6f2ad236d 100644 --- a/board/zylonite/lowlevel_init.S +++ b/board/zylonite/lowlevel_init.S @@ -121,7 +121,7 @@ lowlevel_init: /* ldr r2, [r3] */ /* cmp r4, r2 */ /* bgt 1b */ - wait #300 + wait #0x300 mem_init: diff --git a/common/cmd_ambapp.c b/common/cmd_ambapp.c index 43427bb3c..06531f12b 100644 --- a/common/cmd_ambapp.c +++ b/common/cmd_ambapp.c @@ -273,6 +273,6 @@ int ambapp_init_reloc(void) } U_BOOT_CMD(ambapp, 1, 1, do_ambapp_print, - "ambapp - list AMBA Plug&Play information\n", + "list AMBA Plug&Play information", "ambapp\n" " - lists AMBA (AHB & APB) Plug&Play devices present on the system\n"); diff --git a/common/cmd_autoscript.c b/common/cmd_autoscript.c index 4517ac83c..e5a9bc02d 100644 --- a/common/cmd_autoscript.c +++ b/common/cmd_autoscript.c @@ -230,7 +230,7 @@ do_autoscript (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( autoscr, 2, 0, do_autoscript, - "autoscr - run script from memory\n", + "run script from memory", "[addr] - run script starting at addr" " - A valid autoscr header must be present\n" #if defined(CONFIG_FIT) diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index b660d2ab9..8e9251d4a 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -444,6 +444,6 @@ static void print_str(const char *name, const char *str) U_BOOT_CMD( bdinfo, 1, 1, do_bdinfo, - "bdinfo - print Board Info structure\n", + "print Board Info structure", NULL ); diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index e6277c940..cd9e720fc 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -85,7 +85,7 @@ int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) len = dis_last_len; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -107,7 +107,7 @@ int do_bedbug_dis (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_dis */ U_BOOT_CMD (ds, 3, 1, do_bedbug_dis, - "ds - disassemble memory\n", + "disassemble memory", "ds <address> [# instructions]\n"); /* ====================================================================== @@ -126,7 +126,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int rcode = 0; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -160,7 +160,7 @@ int do_bedbug_asm (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_asm */ U_BOOT_CMD (as, 2, 0, do_bedbug_asm, - "as - assemble memory\n", "as <address>\n"); + "assemble memory", "as <address>\n"); /* ====================================================================== * Used to set a break point from the interpreter. Simply calls into the @@ -177,7 +177,7 @@ int do_bedbug_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_break */ U_BOOT_CMD (break, 3, 0, do_bedbug_break, - "break - set or clear a breakpoint\n", + "set or clear a breakpoint", " - Set or clear a breakpoint\n" "break <address> - Break at an address\n" "break off <bp#> - Disable breakpoint.\n" @@ -277,7 +277,7 @@ int do_bedbug_continue (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_continue */ U_BOOT_CMD (continue, 1, 0, do_bedbug_continue, - "continue- continue from a breakpoint\n", + "continue from a breakpoint", " - continue from a breakpoint.\n"); /* ====================================================================== @@ -308,7 +308,7 @@ int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_step */ U_BOOT_CMD (step, 1, 1, do_bedbug_step, - "step - single step execution.\n", + "single step execution.", " - single step execution.\n"); /* ====================================================================== @@ -339,7 +339,7 @@ int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_next */ U_BOOT_CMD (next, 1, 1, do_bedbug_next, - "next - single step execution, stepping over subroutines.\n", + "single step execution, stepping over subroutines.", " - single step execution, stepping over subroutines.\n"); /* ====================================================================== @@ -384,7 +384,7 @@ int do_bedbug_stack (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_stack */ U_BOOT_CMD (where, 1, 1, do_bedbug_stack, - "where - Print the running stack.\n", + "Print the running stack.", " - Print the running stack.\n"); /* ====================================================================== @@ -405,7 +405,7 @@ int do_bedbug_rdump (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } /* do_bedbug_rdump */ U_BOOT_CMD (rdump, 1, 1, do_bedbug_rdump, - "rdump - Show registers.\n", " - Show registers.\n"); + "Show registers.", " - Show registers.\n"); /* ====================================================================== */ diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index bc08b2655..abbb0704f 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -120,7 +120,7 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) y = simple_strtoul(argv[4], NULL, 10); break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -132,14 +132,14 @@ int do_bmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else if (strncmp(argv[1],"display",1) == 0) { return (bmp_display(addr, x, y)); } else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } } U_BOOT_CMD( bmp, 5, 1, do_bmp, - "bmp - manipulate BMP image data\n", + "manipulate BMP image data", "info <imageAddr> - display image info\n" "bmp display <imageAddr> [x y] - display image at x,y\n" ); diff --git a/common/cmd_boot.c b/common/cmd_boot.c index 6024ffeb4..efc1a0262 100644 --- a/common/cmd_boot.c +++ b/common/cmd_boot.c @@ -41,7 +41,7 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int rcode = 0; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -64,7 +64,7 @@ int do_go (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( go, CONFIG_SYS_MAXARGS, 1, do_go, - "go - start application at address 'addr'\n", + "start application at address 'addr'", "addr [arg ...]\n - start application at address 'addr'\n" " passing 'arg' as arguments\n" ); @@ -73,6 +73,6 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( reset, 1, 0, do_reset, - "reset - Perform RESET of the CPU\n", + "Perform RESET of the CPU", NULL ); diff --git a/common/cmd_bootldr.c b/common/cmd_bootldr.c index e6474aab2..48d113f1f 100644 --- a/common/cmd_bootldr.c +++ b/common/cmd_bootldr.c @@ -16,6 +16,125 @@ #include <asm/blackfin.h> #include <asm/mach-common/bits/bootrom.h> +/* Simple sanity check on the specified address to make sure it contains + * an LDR image of some sort. + */ +static bool ldr_valid_signature(uint8_t *data) +{ +#if defined(__ADSPBF561__) + + /* BF56x has a 4 byte global header */ + if (data[3] == 0xA0) + return true; + +#elif defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) + + /* all the BF53x should start at this address mask */ + uint32_t addr; + memmove(&addr, data, sizeof(addr)); + if ((addr & 0xFF0FFF0F) == 0xFF000000) + return true; +#else + + /* everything newer has a magic byte */ + uint32_t count; + memmove(&count, data + 8, sizeof(count)); + if (data[3] == 0xAD && count == 0) + return true; + +#endif + + return false; +} + +/* If the Blackfin is new enough, the Blackfin on-chip ROM supports loading + * LDRs from random memory addresses. So whenever possible, use that. In + * the older cases (BF53x/BF561), parse the LDR format ourselves. + */ +#define ZEROFILL 0x0001 +#define RESVECT 0x0002 +#define INIT 0x0008 +#define IGNORE 0x0010 +#define FINAL 0x8000 +static void ldr_load(uint8_t *base_addr) +{ +#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + /*defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) ||*/\ + defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) + + uint32_t addr; + uint32_t count; + uint16_t flags; + + /* the bf56x has a 4 byte global header ... but it is useless to + * us when booting an LDR from a memory address, so skip it + */ +# ifdef __ADSPBF561__ + base_addr += 4; +# endif + + memmove(&flags, base_addr + 8, sizeof(flags)); + bfin_write_EVT1(flags & RESVECT ? 0xFFA00000 : 0xFFA08000); + + do { + /* block header may not be aligned */ + memmove(&addr, base_addr, sizeof(addr)); + memmove(&count, base_addr+4, sizeof(count)); + memmove(&flags, base_addr+8, sizeof(flags)); + base_addr += sizeof(addr) + sizeof(count) + sizeof(flags); + + printf("loading to 0x%08x (0x%x bytes) flags: 0x%04x\n", + addr, count, flags); + + if (!(flags & IGNORE)) { + if (flags & ZEROFILL) + memset((void *)addr, 0x00, count); + else + memcpy((void *)addr, base_addr, count); + + if (flags & INIT) { + void (*init)(void) = (void *)addr; + init(); + } + } + + if (!(flags & ZEROFILL)) + base_addr += count; + } while (!(flags & FINAL)); + +#endif +} + +/* For BF537, we use the _BOOTROM_BOOT_DXE_FLASH funky ROM function. + * For all other BF53x/BF56x, we just call the entry point. + * For everything else (newer), we use _BOOTROM_MEMBOOT ROM function. + */ +static void ldr_exec(void *addr) +{ +#if defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) + + /* restore EVT1 to reset value as this is what the bootrom uses as + * the default entry point when booting the final block of LDRs + */ + bfin_write_EVT1(L1_INST_SRAM); + __asm__("call (%0);" : : "a"(_BOOTROM_MEMBOOT), "q7"(addr) : "RETS", "memory"); + +#elif defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) + + void (*ldr_entry)(void) = (void *)bfin_read_EVT1(); + ldr_entry(); + +#else + + int32_t (*BOOTROM_MEM)(void *, int32_t, int32_t, void *) = (void *)_BOOTROM_MEMBOOT; + BOOTROM_MEM(addr, 0, 0, NULL); + +#endif +} + /* * the bootldr command loads an address, checks to see if there * is a Boot stream that the on-chip BOOTROM can understand, @@ -23,11 +142,9 @@ * to also add booting from SPI, or TWI, but this function does * not currently support that. */ - int do_bootldr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { void *addr; - uint32_t *data; /* Get the address */ if (argc < 2) @@ -36,22 +153,14 @@ int do_bootldr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = (void *)simple_strtoul(argv[1], NULL, 16); /* Check if it is a LDR file */ - data = addr; -#if defined(__ADSPBF54x__) || defined(__ADSPBF52x__) - if ((*data & 0xFF000000) == 0xAD000000 && data[2] == 0x00000000) { -#else - if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) { -#endif - /* We want to boot from FLASH or SDRAM */ + if (ldr_valid_signature(addr)) { printf("## Booting ldr image at 0x%p ...\n", addr); + ldr_load(addr); icache_disable(); dcache_disable(); - __asm__( - "jump (%1);" - : - : "q7" (addr), "a" (_BOOTROM_MEMBOOT)); + ldr_exec(addr); } else printf("## No ldr image at address 0x%p\n", addr); @@ -59,6 +168,6 @@ int do_bootldr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(bootldr, 2, 0, do_bootldr, - "bootldr - boot ldr image from memory\n", + "boot ldr image from memory", "[addr]\n" " - boot ldr image stored in memory\n"); diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a8f85e93b..07f6c6bca 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -350,7 +350,7 @@ static int bootm_load_os(image_info_t os, ulong *load_end, int boot_progress) printf (" Uncompressing %s ... ", type_name); if (gunzip ((void *)load, unc_len, (uchar *)image_start, &image_len) != 0) { - puts ("GUNZIP: uncompress or overwrite error " + puts ("GUNZIP: uncompress, out-of-mem or overwrite error " "- must RESET board to recover\n"); if (boot_progress) show_boot_progress (-6); @@ -454,13 +454,13 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } /* Unrecognized command */ else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } if (images.state >= state) { printf ("Trying to execute a command out of order\n"); - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -913,7 +913,7 @@ static void *boot_get_kernel (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] U_BOOT_CMD( bootm, CONFIG_SYS_MAXARGS, 1, do_bootm, - "bootm - boot application image from memory\n", + "boot application image from memory", "[addr [arg ...]]\n - boot application image stored in memory\n" "\tpassing arguments 'arg ...'; when booting a Linux kernel,\n" "\t'arg' can be the address of an initrd image\n" @@ -970,14 +970,14 @@ int do_bootd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( boot, 1, 1, do_bootd, - "boot - boot default, i.e., run 'bootcmd'\n", + "boot default, i.e., run 'bootcmd'", NULL ); /* keep old command name "bootd" for backward compatibility */ U_BOOT_CMD( bootd, 1, 1, do_bootd, - "bootd - boot default, i.e., run 'bootcmd'\n", + "boot default, i.e., run 'bootcmd'", NULL ); @@ -1062,7 +1062,7 @@ static int image_info (ulong addr) U_BOOT_CMD( iminfo, CONFIG_SYS_MAXARGS, 1, do_iminfo, - "iminfo - print header information for application image\n", + "print header information for application image", "addr [addr ...]\n" " - print header information for application image starting at\n" " address 'addr' in memory; this includes verification of the\n" @@ -1130,7 +1130,7 @@ next_bank: ; U_BOOT_CMD( imls, 1, 1, do_imls, - "imls - list all images found in flash\n", + "list all images found in flash", "\n" " - Prints information about all images found at sector\n" " boundaries in flash.\n" diff --git a/common/cmd_cache.c b/common/cmd_cache.c index 675d43fa1..c0f2cbaf6 100644 --- a/common/cmd_cache.c +++ b/common/cmd_cache.c @@ -37,7 +37,7 @@ int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 2: /* on / off */ switch (on_off(argv[1])) { #if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */ - default: printf ("Usage:\n%s\n", cmdtp->usage); + default: cmd_usage(cmdtp); return; #endif case 0: icache_disable(); @@ -51,7 +51,7 @@ int do_icache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) icache_status() ? "ON" : "OFF"); return 0; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } return 0; @@ -63,7 +63,7 @@ int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 2: /* on / off */ switch (on_off(argv[1])) { #if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */ - default: printf ("Usage:\n%s\n", cmdtp->usage); + default: cmd_usage(cmdtp); return; #endif case 0: dcache_disable(); @@ -77,7 +77,7 @@ int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) dcache_status() ? "ON" : "OFF"); return 0; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } return 0; @@ -97,14 +97,14 @@ static int on_off (const char *s) U_BOOT_CMD( icache, 2, 1, do_icache, - "icache - enable or disable instruction cache\n", + "enable or disable instruction cache", "[on, off]\n" " - enable or disable instruction cache\n" ); U_BOOT_CMD( dcache, 2, 1, do_dcache, - "dcache - enable or disable data cache\n", + "enable or disable data cache", "[on, off]\n" " - enable or disable data (writethrough) cache\n" ); diff --git a/common/cmd_console.c b/common/cmd_console.c index e2bc2a30d..f861f8300 100644 --- a/common/cmd_console.c +++ b/common/cmd_console.c @@ -65,6 +65,6 @@ int do_coninfo (cmd_tbl_t * cmd, int flag, int argc, char *argv[]) U_BOOT_CMD( coninfo, 3, 1, do_coninfo, - "coninfo - print console devices and information\n", + "print console devices and information", "" ); diff --git a/common/cmd_cplbinfo.c b/common/cmd_cplbinfo.c index b2bbec12e..56e70d615 100644 --- a/common/cmd_cplbinfo.c +++ b/common/cmd_cplbinfo.c @@ -26,11 +26,11 @@ static const char *cplb_page_size(uint32_t data) */ static void show_cplb_table(uint32_t *addr, uint32_t *data) { - size_t i; + int i; printf(" Address Data Size Valid Locked\n"); for (i = 1; i <= 16; ++i) { printf(" %2i 0x%p 0x%05X %s %c %c\n", - i, *addr, *data, + i, (void *)*addr, *data, cplb_page_size(*data), (*data & CPLB_VALID ? 'Y' : 'N'), (*data & CPLB_LOCK ? 'Y' : 'N')); @@ -54,6 +54,6 @@ int do_cplbinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(cplbinfo, 1, 0, do_cplbinfo, - "cplbinfo- display current CPLB tables\n", + "display current CPLB tables", "\n" " - display current CPLB tables\n"); diff --git a/common/cmd_date.c b/common/cmd_date.c index b4d9649bd..3d78be269 100644 --- a/common/cmd_date.c +++ b/common/cmd_date.c @@ -89,7 +89,7 @@ int do_date (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); rcode = 1; } @@ -214,7 +214,7 @@ int mk_date (char *datestr, struct rtc_time *tmp) U_BOOT_CMD( date, 2, 1, do_date, - "date - get/set/reset date & time\n", + "get/set/reset date & time", "[MMDDhhmm[[CC]YY][.ss]]\ndate reset\n" " - without arguments: print date & time\n" " - with numeric argument: set the system date & time\n" diff --git a/common/cmd_dcr.c b/common/cmd_dcr.c index 439d07a65..7aed06c11 100644 --- a/common/cmd_dcr.c +++ b/common/cmd_dcr.c @@ -45,7 +45,7 @@ int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) /* Validate arguments */ if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -74,7 +74,7 @@ int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* Validate arguments */ if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -121,7 +121,7 @@ int do_getidcr (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Validate arguments */ if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -177,7 +177,7 @@ int do_setidcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* Validate arguments */ if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -223,23 +223,23 @@ int do_setidcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( getdcr, 2, 1, do_getdcr, - "getdcr - Get an AMCC PPC 4xx DCR's value\n", + "Get an AMCC PPC 4xx DCR's value", "dcrn - return a DCR's value.\n" ); U_BOOT_CMD( setdcr, 2, 1, do_setdcr, - "setdcr - Set an AMCC PPC 4xx DCR's value\n", + "Set an AMCC PPC 4xx DCR's value", "dcrn - set a DCR's value.\n" ); U_BOOT_CMD( getidcr, 3, 1, do_getidcr, - "getidcr - Get a register value via indirect DCR addressing\n", + "Get a register value via indirect DCR addressing", "adr_dcrn[.dat_dcrn] offset - write offset to adr_dcrn, read value from dat_dcrn.\n" ); U_BOOT_CMD( setidcr, 4, 1, do_setidcr, - "setidcr - Set a register value via indirect DCR addressing\n", + "Set a register value via indirect DCR addressing", "adr_dcrn[.dat_dcrn] offset value - write offset to adr_dcrn, write value to dat_dcrn.\n" ); diff --git a/common/cmd_df.c b/common/cmd_df.c index 5f650442c..d64f9009d 100644 --- a/common/cmd_df.c +++ b/common/cmd_df.c @@ -27,11 +27,11 @@ static int do_df(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } usage: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( sf, 2, 1, do_serial_flash, - "sf - Serial flash sub-system\n", + "Serial flash sub-system", "probe [bus:]cs - init flash device on given SPI bus and CS\n") diff --git a/common/cmd_diag.c b/common/cmd_diag.c index 13d4225fb..c2a617547 100644 --- a/common/cmd_diag.c +++ b/common/cmd_diag.c @@ -66,7 +66,7 @@ int do_diag (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( diag, CONFIG_SYS_MAXARGS, 0, do_diag, - "diag - perform board diagnostics\n", + "perform board diagnostics", " - print list of available tests\n" "diag [test1 [test2]]\n" " - print information about specified tests\n" diff --git a/common/cmd_display.c b/common/cmd_display.c index 982e09dab..4102424d1 100644 --- a/common/cmd_display.c +++ b/common/cmd_display.c @@ -71,7 +71,7 @@ int do_display (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( display, CONFIG_SYS_MAXARGS, 1, do_display, - "display- display string on dot matrix display\n", + "display string on dot matrix display", "[<string>]\n" " - with <string> argument: display <string> on dot matrix display\n" " - without arguments: clear dot matrix display\n" diff --git a/common/cmd_doc.c b/common/cmd_doc.c index 02502cc81..e2d4a42d1 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -96,7 +96,7 @@ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) switch (argc) { case 0: case 1: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 2: if (strcmp(argv[1],"info") == 0) { @@ -121,7 +121,7 @@ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) doc_print(&doc_dev_desc[curr_device]); return 0; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 3: if (strcmp(argv[1],"device") == 0) { @@ -146,7 +146,7 @@ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; default: /* at least 4 args */ @@ -182,7 +182,7 @@ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return ret; } else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); rcode = 1; } @@ -191,7 +191,7 @@ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( doc, 5, 1, do_doc, - "doc - Disk-On-Chip sub-system\n", + "Disk-On-Chip sub-system", "info - show available DOC devices\n" "doc device [dev] - show or set current device\n" "doc read addr off size\n" @@ -235,7 +235,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) offset = simple_strtoul(argv[3], NULL, 16); break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); show_boot_progress (-35); return 1; } @@ -337,7 +337,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( docboot, 4, 1, do_docboot, - "docboot - boot from DOC device\n", + "boot from DOC device", "loadAddr dev\n" ); diff --git a/common/cmd_dtt.c b/common/cmd_dtt.c index c5b1d4d8f..7783c880b 100644 --- a/common/cmd_dtt.c +++ b/common/cmd_dtt.c @@ -55,6 +55,6 @@ int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( dtt, 1, 1, do_dtt, - "dtt - Digital Thermometer and Thermostat\n", + "Digital Thermometer and Thermostat", " - Read temperature from digital thermometer and thermostat.\n" ); diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index 2451bef74..e598bf1ec 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -104,7 +104,7 @@ int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } #endif @@ -425,7 +425,7 @@ void eeprom_init (void) #ifdef CONFIG_SYS_I2C_MULTI_EEPROMS U_BOOT_CMD( eeprom, 6, 1, do_eeprom, - "eeprom - EEPROM sub-system\n", + "EEPROM sub-system", "read devaddr addr off cnt\n" "eeprom write devaddr addr off cnt\n" " - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'\n" @@ -433,7 +433,7 @@ U_BOOT_CMD( #else /* One EEPROM */ U_BOOT_CMD( eeprom, 5, 1, do_eeprom, - "eeprom - EEPROM sub-system\n", + "EEPROM sub-system", "read addr off cnt\n" "eeprom write addr off cnt\n" " - read/write `cnt' bytes at EEPROM offset `off'\n" diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 27a4b73ed..19e12493a 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -310,12 +310,12 @@ unsigned long load_elf_image (unsigned long addr) /* ====================================================================== */ U_BOOT_CMD( bootelf, 2, 0, do_bootelf, - "bootelf - Boot from an ELF image in memory\n", + "Boot from an ELF image in memory", " [address] - load address of ELF image.\n" ); U_BOOT_CMD( bootvx, 2, 0, do_bootvx, - "bootvx - Boot vxWorks from an ELF image\n", + "Boot vxWorks from an ELF image", " [address] - load address of vxWorks ELF image.\n" ); diff --git a/common/cmd_ext2.c b/common/cmd_ext2.c index 9c43792f3..c2dcc6436 100644 --- a/common/cmd_ext2.c +++ b/common/cmd_ext2.c @@ -66,7 +66,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int part_length; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return(1); } dev = (int)simple_strtoul (argv[2], &ep, 16); @@ -116,7 +116,7 @@ int do_ext2ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( ext2ls, 4, 1, do_ext2ls, - "ext2ls - list files in a directory (default /)\n", + "list files in a directory (default /)", "<interface> <dev[:part]> [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'\n" ); @@ -164,7 +164,7 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return(1); } @@ -252,7 +252,7 @@ int do_ext2load (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( ext2load, 6, 0, do_ext2load, - "ext2load- load binary file from a Ext2 filesystem\n", + "load binary file from a Ext2 filesystem", "<interface> <dev[:part]> [addr] [filename] [bytes]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from ext2 filesystem\n" diff --git a/common/cmd_fat.c b/common/cmd_fat.c index ebe9e090c..4a26b8072 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -88,7 +88,7 @@ int do_fat_fsload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( fatload, 6, 0, do_fat_fsload, - "fatload - load binary file from a dos filesystem\n", + "load binary file from a dos filesystem", "<interface> <dev[:part]> <addr> <filename> [bytes]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from dos filesystem\n" @@ -136,7 +136,7 @@ int do_fat_ls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( fatls, 4, 1, do_fat_ls, - "fatls - list files in a directory (default /)\n", + "list files in a directory (default /)", "<interface> <dev[:part]> [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'\n" ); @@ -174,7 +174,7 @@ int do_fat_fsinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( fatinfo, 3, 1, do_fat_fsinfo, - "fatinfo - print information about filesystem\n", + "print information about filesystem", "<interface> <dev[:part]>\n" " - print information about filesystem from 'dev' on 'interface'\n" ); diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index d995ff21e..c043b9765 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -801,7 +801,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) boot_drive=simple_strtoul(argv[2], NULL, 10); break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } /* setup FDC and scan for drives */ @@ -902,7 +902,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( fdcboot, 3, 1, do_fdcboot, - "fdcboot - boot from floppy device\n", + "boot from floppy device", "loadAddr drive\n" ); #endif diff --git a/common/cmd_fdos.c b/common/cmd_fdos.c index aa13b5261..bcf98d9e4 100644 --- a/common/cmd_fdos.c +++ b/common/cmd_fdos.c @@ -73,7 +73,7 @@ int do_fdosboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) name = argv [2]; break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); break; } @@ -142,12 +142,12 @@ int do_fdosls(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( fdosboot, 3, 0, do_fdosboot, - "fdosboot- boot from a dos floppy file\n", + "boot from a dos floppy file", "[loadAddr] [filename]\n" ); U_BOOT_CMD( fdosls, 2, 0, do_fdosls, - "fdosls - list files in a directory\n", + "list files in a directory", "[directory]\n" ); diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 4274a773a..0947b72d2 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -66,7 +66,7 @@ void set_working_fdt_addr(void *addr) int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -125,7 +125,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int err; if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -179,7 +179,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Parameters: Node path, new node to be appended to the path. */ if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -217,7 +217,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) * Parameters: Node path, property, optional value. */ if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -427,7 +427,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } } else { /* Unrecognized command */ - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } } @@ -441,7 +441,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) unsigned long initrd_start = 0, initrd_end = 0; if ((argc != 2) && (argc != 4)) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -459,7 +459,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } else { /* Unrecognized command */ - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -819,7 +819,7 @@ static int fdt_print(const char *pathp, char *prop, int depth) U_BOOT_CMD( fdt, 255, 0, do_fdt, - "fdt - flattened device tree utility commands\n", + "flattened device tree utility commands", "addr <addr> [<length>] - Set the fdt location to <addr>\n" #ifdef CONFIG_OF_BOARD_SETUP "fdt boardsetup - Do board-specific set up\n" diff --git a/common/cmd_flash.c b/common/cmd_flash.c index 93eefa964..510654e1a 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -333,7 +333,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int rcode = 0; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -384,7 +384,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif if (argc != 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -407,7 +407,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if (addr_first >= addr_last) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -481,7 +481,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -490,7 +490,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else if (strcmp(argv[1], "on") == 0) { p = 1; } else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -591,7 +591,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif if (argc != 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -633,7 +633,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if (addr_first >= addr_last) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } rcode = flash_sect_protect (p, addr_first, addr_last); @@ -710,14 +710,14 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last) U_BOOT_CMD( flinfo, 2, 1, do_flinfo, - "flinfo - print FLASH memory information\n", + "print FLASH memory information", "\n - print information for all FLASH memory banks\n" "flinfo N\n - print information for FLASH memory bank # N\n" ); U_BOOT_CMD( erase, 3, 0, do_flerase, - "erase - erase FLASH memory\n", + "erase FLASH memory", "start end\n" " - erase FLASH from addr 'start' to addr 'end'\n" "erase start +len\n" @@ -731,7 +731,7 @@ U_BOOT_CMD( U_BOOT_CMD( protect, 4, 0, do_protect, - "protect - enable or disable FLASH write protection\n", + "enable or disable FLASH write protection", "on start end\n" " - protect FLASH from addr 'start' to addr 'end'\n" "protect on start +len\n" diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index dcbbc993d..362bffdcd 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -320,7 +320,7 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) static void fpga_usage (cmd_tbl_t * cmdtp) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); } /* @@ -350,7 +350,7 @@ static int fpga_get_op (char *opstr) } U_BOOT_CMD (fpga, 6, 1, do_fpga, - "fpga - loadable FPGA image support\n", + "loadable FPGA image support", "fpga [operation type] [device number] [image address] [image size]\n" "fpga operations:\n" "\tinfo\tlist known device information\n" diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 448f2fedd..16439ac48 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -159,7 +159,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) length = i2c_dp_last_length; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -184,7 +184,7 @@ int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } break; @@ -269,7 +269,7 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int j; if ((argc < 4) || (argc > 5)) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -287,7 +287,7 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } break; @@ -355,7 +355,7 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int j; if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -373,7 +373,7 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } break; @@ -427,7 +427,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) extern char console_buffer[]; if (argc != 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -463,7 +463,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } break; @@ -601,7 +601,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int j; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -619,7 +619,7 @@ int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if (alen > 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } break; @@ -764,7 +764,7 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) }; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } /* @@ -1293,7 +1293,7 @@ int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return do_sdram(cmdtp, flag, --argc, ++argv); #endif else - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 0; } #endif /* CONFIG_I2C_CMD_TREE */ @@ -1303,7 +1303,7 @@ int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_I2C_CMD_TREE) U_BOOT_CMD( i2c, 6, 1, do_i2c, - "i2c - I2C sub-system\n", + "I2C sub-system", #if defined(CONFIG_I2C_MUX) "bus [muxtype:muxaddr:muxchannel] - add a new bus reached over muxes.\n" #endif /* CONFIG_I2C_MUX */ @@ -1326,37 +1326,37 @@ U_BOOT_CMD( #endif /* CONFIG_I2C_CMD_TREE */ U_BOOT_CMD( imd, 4, 1, do_i2c_md, \ - "imd - i2c memory display\n", \ + "i2c memory display", \ "chip address[.0, .1, .2] [# of objects]\n - i2c memory display\n" \ ); U_BOOT_CMD( imm, 3, 1, do_i2c_mm, - "imm - i2c memory modify (auto-incrementing)\n", + "i2c memory modify (auto-incrementing)", "chip address[.0, .1, .2]\n" " - memory modify, auto increment address\n" ); U_BOOT_CMD( inm, 3, 1, do_i2c_nm, - "inm - memory modify (constant address)\n", + "memory modify (constant address)", "chip address[.0, .1, .2]\n - memory modify, read and keep address\n" ); U_BOOT_CMD( imw, 5, 1, do_i2c_mw, - "imw - memory write (fill)\n", + "memory write (fill)", "chip address[.0, .1, .2] value [count]\n - memory write (fill)\n" ); U_BOOT_CMD( icrc32, 5, 1, do_i2c_crc, - "icrc32 - checksum calculation\n", + "checksum calculation", "chip address[.0, .1, .2] count\n - compute CRC32 checksum\n" ); U_BOOT_CMD( iprobe, 1, 1, do_i2c_probe, - "iprobe - probe to discover valid I2C chip addresses\n", + "probe to discover valid I2C chip addresses", "\n -discover valid I2C chip addresses\n" ); @@ -1365,7 +1365,7 @@ U_BOOT_CMD( */ U_BOOT_CMD( iloop, 5, 1, do_i2c_loop, - "iloop - infinite loop on address range\n", + "infinite loop on address range", "chip address[.0, .1, .2] [# of objects]\n" " - loop, reading a set of addresses\n" ); @@ -1373,7 +1373,7 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_SDRAM) U_BOOT_CMD( isdram, 2, 1, do_sdram, - "isdram - print SDRAM configuration information\n", + "print SDRAM configuration information", "chip\n - print SDRAM configuration information\n" " (valid chip values 50..57)\n" ); diff --git a/common/cmd_ide.c b/common/cmd_ide.c index db05f76e5..c9b9a4799 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -188,7 +188,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) switch (argc) { case 0: case 1: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 2: if (strncmp(argv[1],"res",3) == 0) { @@ -238,7 +238,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return rcode; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 3: if (strncmp(argv[1],"dev",3) == 0) { @@ -287,7 +287,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; default: /* at least 4 args */ @@ -347,7 +347,7 @@ int do_ide (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } } else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); rcode = 1; } @@ -383,7 +383,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) boot_device = argv[2]; break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); show_boot_progress (-42); return 1; } @@ -2140,7 +2140,7 @@ ulong atapi_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) U_BOOT_CMD( ide, 5, 1, do_ide, - "ide - IDE sub-system\n", + "IDE sub-system", "reset - reset IDE controller\n" "ide info - show available IDE devices\n" "ide device [dev] - show or set current device\n" @@ -2153,6 +2153,6 @@ U_BOOT_CMD( U_BOOT_CMD( diskboot, 3, 1, do_diskboot, - "diskboot- boot from IDE device\n", + "boot from IDE device", "loadAddr dev:part\n" ); diff --git a/common/cmd_immap.c b/common/cmd_immap.c index 13ad94e20..c8367f0fb 100644 --- a/common/cmd_immap.c +++ b/common/cmd_immap.c @@ -614,105 +614,105 @@ do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( siuinfo, 1, 1, do_siuinfo, - "siuinfo - print System Interface Unit (SIU) registers\n", + "print System Interface Unit (SIU) registers", NULL ); U_BOOT_CMD( memcinfo, 1, 1, do_memcinfo, - "memcinfo- print Memory Controller registers\n", + "print Memory Controller registers", NULL ); U_BOOT_CMD( sitinfo, 1, 1, do_sitinfo, - "sitinfo - print System Integration Timers (SIT) registers\n", + "print System Integration Timers (SIT) registers", NULL ); #ifdef CONFIG_8260 U_BOOT_CMD( icinfo, 1, 1, do_icinfo, - "icinfo - print Interrupt Controller registers\n", + "print Interrupt Controller registers", NULL ); #endif U_BOOT_CMD( carinfo, 1, 1, do_carinfo, - "carinfo - print Clocks and Reset registers\n", + "print Clocks and Reset registers", NULL ); U_BOOT_CMD( iopinfo, 1, 1, do_iopinfo, - "iopinfo - print I/O Port registers\n", + "print I/O Port registers", NULL ); U_BOOT_CMD( iopset, 5, 0, do_iopset, - "iopset - set I/O Port registers\n", + "set I/O Port registers", "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" ); U_BOOT_CMD( dmainfo, 1, 1, do_dmainfo, - "dmainfo - print SDMA/IDMA registers\n", + "print SDMA/IDMA registers", NULL ); U_BOOT_CMD( fccinfo, 1, 1, do_fccinfo, - "fccinfo - print FCC registers\n", + "print FCC registers", NULL ); U_BOOT_CMD( brginfo, 1, 1, do_brginfo, - "brginfo - print Baud Rate Generator (BRG) registers\n", + "print Baud Rate Generator (BRG) registers", NULL ); U_BOOT_CMD( i2cinfo, 1, 1, do_i2cinfo, - "i2cinfo - print I2C registers\n", + "print I2C registers", NULL ); U_BOOT_CMD( sccinfo, 1, 1, do_sccinfo, - "sccinfo - print SCC registers\n", + "print SCC registers", NULL ); U_BOOT_CMD( smcinfo, 1, 1, do_smcinfo, - "smcinfo - print SMC registers\n", + "print SMC registers", NULL ); U_BOOT_CMD( spiinfo, 1, 1, do_spiinfo, - "spiinfo - print Serial Peripheral Interface (SPI) registers\n", + "print Serial Peripheral Interface (SPI) registers", NULL ); U_BOOT_CMD( muxinfo, 1, 1, do_muxinfo, - "muxinfo - print CPM Multiplexing registers\n", + "print CPM Multiplexing registers", NULL ); U_BOOT_CMD( siinfo, 1, 1, do_siinfo, - "siinfo - print Serial Interface (SI) registers\n", + "print Serial Interface (SI) registers", NULL ); U_BOOT_CMD( mccinfo, 1, 1, do_mccinfo, - "mccinfo - print MCC registers\n", + "print MCC registers", NULL ); diff --git a/common/cmd_irq.c b/common/cmd_irq.c index 04914c621..a21aedea4 100644 --- a/common/cmd_irq.c +++ b/common/cmd_irq.c @@ -28,7 +28,7 @@ int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc != 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -44,7 +44,7 @@ int do_interrupts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( interrupts, 5, 0, do_interrupts, - "interrupts - enable or disable interrupts\n", + "enable or disable interrupts", "[on, off]\n" " - enable or disable interrupts\n" ); diff --git a/common/cmd_itest.c b/common/cmd_itest.c index 9e77fa913..309b08bb0 100644 --- a/common/cmd_itest.c +++ b/common/cmd_itest.c @@ -161,7 +161,7 @@ int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) /* Validate arguments */ if ((argc != 4)){ - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -190,6 +190,6 @@ int do_itest ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) U_BOOT_CMD( itest, 4, 0, do_itest, - "itest\t- return true/false on integer compare\n", + "return true/false on integer compare", "[.b, .w, .l, .s] [*]value1 <op> [*]value2\n" ); diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c index 7866c808d..d0a7ceaa5 100644 --- a/common/cmd_jffs2.c +++ b/common/cmd_jffs2.c @@ -1778,6 +1778,96 @@ int mtdparts_init(void) */ /** + * Calculate sector size. + * + * @return sector size + */ +static inline u32 get_part_sector_size_nand(struct mtdids *id) +{ +#if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND) +#if defined(CONFIG_NAND_LEGACY) + extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE]; + + return nand_dev_desc[id->num].erasesize; +#else + nand_info_t *nand; + + nand = &nand_info[id->num]; + + return nand->erasesize; +#endif +#else + BUG(); + return 0; +#endif +} + +static inline u32 get_part_sector_size_nor(struct mtdids *id, struct part_info *part) +{ +#if defined(CONFIG_CMD_FLASH) + extern flash_info_t flash_info[]; + + u32 end_phys, start_phys, sector_size = 0, size = 0; + int i; + flash_info_t *flash; + + flash = &flash_info[id->num]; + + start_phys = flash->start[0] + part->offset; + end_phys = start_phys + part->size; + + for (i = 0; i < flash->sector_count; i++) { + if (flash->start[i] >= end_phys) + break; + + if (flash->start[i] >= start_phys) { + if (i == flash->sector_count - 1) { + size = flash->start[0] + flash->size - flash->start[i]; + } else { + size = flash->start[i+1] - flash->start[i]; + } + + if (sector_size < size) + sector_size = size; + } + } + + return sector_size; +#else + BUG(); + return 0; +#endif +} + +static inline u32 get_part_sector_size_onenand(void) +{ +#if defined(CONFIG_CMD_ONENAND) + struct mtd_info *mtd; + + mtd = &onenand_mtd; + + return mtd->erasesize; +#else + BUG(); + return 0; +#endif +} + +static inline u32 get_part_sector_size(struct mtdids *id, struct part_info *part) +{ + if (id->type == MTD_DEV_TYPE_NAND) + return get_part_sector_size_nand(id); + else if (id->type == MTD_DEV_TYPE_NOR) + return get_part_sector_size_nor(id, part); + else if (id->type == MTD_DEV_TYPE_ONENAND) + return get_part_sector_size_onenand(); + else + DEBUGF("Error: Unknown device type.\n"); + + return 0; +} + +/** * Parse and initialize global mtdids mapping and create global * device/partition list. * @@ -1846,6 +1936,8 @@ int mtdparts_init(void) part->offset = 0x00000000; #endif + part->sector_size = get_part_sector_size(id, part); + part->dev = current_dev; INIT_LIST_HEAD(&part->link); @@ -2197,7 +2289,7 @@ int do_jffs2_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return delete_partition(argv[2]); } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } #endif /* #ifdef CONFIG_JFFS2_CMDLINE */ @@ -2205,35 +2297,35 @@ int do_jffs2_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /***************************************************/ U_BOOT_CMD( fsload, 3, 0, do_jffs2_fsload, - "fsload\t- load binary file from a filesystem image\n", + "load binary file from a filesystem image", "[ off ] [ filename ]\n" " - load binary file from flash bank\n" " with offset 'off'\n" ); U_BOOT_CMD( ls, 2, 1, do_jffs2_ls, - "ls\t- list files in a directory (default /)\n", + "list files in a directory (default /)", "[ directory ]\n" " - list files in a directory.\n" ); U_BOOT_CMD( fsinfo, 1, 1, do_jffs2_fsinfo, - "fsinfo\t- print information about filesystems\n", + "print information about filesystems", " - print information about filesystems\n" ); #ifdef CONFIG_JFFS2_CMDLINE U_BOOT_CMD( chpart, 2, 0, do_jffs2_chpart, - "chpart\t- change active partition\n", + "change active partition", "part-id\n" " - change active partition (e.g. part-id = nand0,1)\n" ); U_BOOT_CMD( mtdparts, 6, 0, do_jffs2_mtdparts, - "mtdparts- define flash/nand partitions\n", + "define flash/nand partitions", "\n" " - list partition table\n" "mtdparts delall\n" diff --git a/common/cmd_license.c b/common/cmd_license.c index 301af8d96..c3c34967d 100644 --- a/common/cmd_license.c +++ b/common/cmd_license.c @@ -53,7 +53,7 @@ int do_license(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(license, 1, 1, do_license, - "license - print GPL license text\n", + "print GPL license text", NULL); #endif /* CONFIG_CMD_LICENSE */ diff --git a/common/cmd_load.c b/common/cmd_load.c index 65a4d692a..88fba8899 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -1045,7 +1045,7 @@ static ulong load_serial_ymodem (ulong offset) #ifdef CONFIG_SYS_LOADS_BAUD_CHANGE U_BOOT_CMD( loads, 3, 0, do_load_serial, - "loads - load S-Record file over serial line\n", + "load S-Record file over serial line", "[ off ] [ baud ]\n" " - load S-Record file over serial line" " with offset 'off' and baudrate 'baud'\n" @@ -1054,7 +1054,7 @@ U_BOOT_CMD( #else /* ! CONFIG_SYS_LOADS_BAUD_CHANGE */ U_BOOT_CMD( loads, 2, 0, do_load_serial, - "loads - load S-Record file over serial line\n", + "load S-Record file over serial line", "[ off ]\n" " - load S-Record file over serial line with offset 'off'\n" ); @@ -1069,7 +1069,7 @@ U_BOOT_CMD( #ifdef CONFIG_SYS_LOADS_BAUD_CHANGE U_BOOT_CMD( saves, 4, 0, do_save_serial, - "saves - save S-Record file over serial line\n", + "save S-Record file over serial line", "[ off ] [size] [ baud ]\n" " - save S-Record file over serial line" " with offset 'off', size 'size' and baudrate 'baud'\n" @@ -1077,7 +1077,7 @@ U_BOOT_CMD( #else /* ! CONFIG_SYS_LOADS_BAUD_CHANGE */ U_BOOT_CMD( saves, 3, 0, do_save_serial, - "saves - save S-Record file over serial line\n", + "save S-Record file over serial line", "[ off ] [size]\n" " - save S-Record file over serial line with offset 'off' and size 'size'\n" ); @@ -1089,7 +1089,7 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_LOADB) U_BOOT_CMD( loadb, 3, 0, do_load_serial_bin, - "loadb - load binary file over serial line (kermit mode)\n", + "load binary file over serial line (kermit mode)", "[ off ] [ baud ]\n" " - load binary file over serial line" " with offset 'off' and baudrate 'baud'\n" @@ -1097,7 +1097,7 @@ U_BOOT_CMD( U_BOOT_CMD( loady, 3, 0, do_load_serial_bin, - "loady - load binary file over serial line (ymodem mode)\n", + "load binary file over serial line (ymodem mode)", "[ off ] [ baud ]\n" " - load binary file over serial line" " with offset 'off' and baudrate 'baud'\n" @@ -1119,7 +1119,7 @@ int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (strcmp(argv[1], "on") == 0) hwflow_onoff(1); else - printf("Usage: %s\n", cmdtp->usage); + cmd_usage(cmdtp); } printf("RTS/CTS hardware flow control: %s\n", hwflow_onoff(0) ? "on" : "off"); return 0; @@ -1129,7 +1129,7 @@ int do_hwflow (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( hwflow, 2, 0, do_hwflow, - "hwflow - turn the harwdare flow control on/off\n", + "turn the harwdare flow control on/off", "[on|off]\n - change RTS/CTS hardware flow control over serial line\n" ); diff --git a/common/cmd_log.c b/common/cmd_log.c index febdb90cf..a03835d02 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -241,18 +241,18 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return 0; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } } U_BOOT_CMD( log, 255, 1, do_log, - "log - manipulate logbuffer\n", + "manipulate logbuffer", "info - show pointer details\n" "log reset - clear contents\n" "log show - show contents\n" diff --git a/common/cmd_mac.c b/common/cmd_mac.c index 4453299fe..cf601e4e6 100644 --- a/common/cmd_mac.c +++ b/common/cmd_mac.c @@ -28,7 +28,7 @@ extern int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( mac, 3, 1, do_mac, - "mac - display and program the system ID and MAC addresses in EEPROM\n", + "display and program the system ID and MAC addresses in EEPROM", "[read|save|id|num|errata|date|ports|0|1|2|3|4|5|6|7]\n" "read\n" " - show content of EEPROM\n" diff --git a/common/cmd_mem.c b/common/cmd_mem.c index c209d62d8..a203e0d3e 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -77,7 +77,7 @@ int do_mem_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) length = dp_last_length; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -173,7 +173,7 @@ int do_mem_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int size; if ((argc < 3) || (argc > 4)) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -217,7 +217,7 @@ int do_mem_mdc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong count; if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -246,7 +246,7 @@ int do_mem_mwc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong count; if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -277,7 +277,7 @@ int do_mem_cmp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int rcode = 0; if (argc != 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -361,7 +361,7 @@ int do_mem_cp ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int size; if (argc != 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -525,7 +525,7 @@ int do_mem_loop (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) volatile u_char *cp; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -596,7 +596,7 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) volatile u_char *cp; if (argc < 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -1001,7 +1001,7 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) extern char console_buffer[]; if (argc != 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -1106,7 +1106,7 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong *ptr; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -1142,7 +1142,7 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (argc < 3) { usage: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -1202,7 +1202,7 @@ int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) dst = simple_strtoul(argv[2], NULL, 16); break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -1214,39 +1214,39 @@ int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /**************************************************/ U_BOOT_CMD( md, 3, 1, do_mem_md, - "md - memory display\n", + "memory display", "[.b, .w, .l] address [# of objects]\n - memory display\n" ); U_BOOT_CMD( mm, 2, 1, do_mem_mm, - "mm - memory modify (auto-incrementing)\n", + "memory modify (auto-incrementing)", "[.b, .w, .l] address\n" " - memory modify, auto increment address\n" ); U_BOOT_CMD( nm, 2, 1, do_mem_nm, - "nm - memory modify (constant address)\n", + "memory modify (constant address)", "[.b, .w, .l] address\n - memory modify, read and keep address\n" ); U_BOOT_CMD( mw, 4, 1, do_mem_mw, - "mw - memory write (fill)\n", + "memory write (fill)", "[.b, .w, .l] address value [count]\n - write memory\n" ); U_BOOT_CMD( cp, 4, 1, do_mem_cp, - "cp - memory copy\n", + "memory copy", "[.b, .w, .l] source target count\n - copy memory\n" ); U_BOOT_CMD( cmp, 4, 1, do_mem_cmp, - "cmp - memory compare\n", + "memory compare", "[.b, .w, .l] addr1 addr2 count\n - compare memory\n" ); @@ -1254,7 +1254,7 @@ U_BOOT_CMD( U_BOOT_CMD( crc32, 4, 1, do_mem_crc, - "crc32 - checksum calculation\n", + "checksum calculation", "address count [addr]\n - compute CRC32 checksum [save at addr]\n" ); @@ -1262,7 +1262,7 @@ U_BOOT_CMD( U_BOOT_CMD( crc32, 5, 1, do_mem_crc, - "crc32 - checksum calculation\n", + "checksum calculation", "address count [addr]\n - compute CRC32 checksum [save at addr]\n" "-v address count crc\n - verify crc of memory area\n" ); @@ -1271,14 +1271,14 @@ U_BOOT_CMD( U_BOOT_CMD( base, 2, 1, do_mem_base, - "base - print or set address offset\n", + "print or set address offset", "\n - print address offset for memory commands\n" "base off\n - set address offset for memory commands to 'off'\n" ); U_BOOT_CMD( loop, 3, 1, do_mem_loop, - "loop - infinite loop on address range\n", + "infinite loop on address range", "[.b, .w, .l] address number_of_objects\n" " - loop on a set of addresses\n" ); @@ -1286,7 +1286,7 @@ U_BOOT_CMD( #ifdef CONFIG_LOOPW U_BOOT_CMD( loopw, 4, 1, do_mem_loopw, - "loopw - infinite write loop on address range\n", + "infinite write loop on address range", "[.b, .w, .l] address number_of_objects data_to_write\n" " - loop on a set of addresses\n" ); @@ -1294,7 +1294,7 @@ U_BOOT_CMD( U_BOOT_CMD( mtest, 5, 1, do_mem_mtest, - "mtest - simple RAM test\n", + "simple RAM test", "[start [end [pattern [iterations]]]]\n" " - simple RAM read/write test\n" ); @@ -1302,13 +1302,13 @@ U_BOOT_CMD( #ifdef CONFIG_MX_CYCLIC U_BOOT_CMD( mdc, 4, 1, do_mem_mdc, - "mdc - memory display cyclic\n", + "memory display cyclic", "[.b, .w, .l] address count delay(ms)\n - memory display cyclic\n" ); U_BOOT_CMD( mwc, 4, 1, do_mem_mwc, - "mwc - memory write cyclic\n", + "memory write cyclic", "[.b, .w, .l] address value delay(ms)\n - memory write cyclic\n" ); #endif /* CONFIG_MX_CYCLIC */ @@ -1316,7 +1316,7 @@ U_BOOT_CMD( #ifdef CONFIG_CMD_UNZIP U_BOOT_CMD( unzip, 4, 1, do_unzip, - "unzip - unzip a memory region\n", + "unzip a memory region", "srcaddr dstaddr [dstsize]\n" ); #endif /* CONFIG_CMD_UNZIP */ diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c index c2442eed1..6470baceb 100644 --- a/common/cmd_mfsl.c +++ b/common/cmd_mfsl.c @@ -38,7 +38,7 @@ int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) unsigned int blocking; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -46,7 +46,7 @@ int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) blocking = (unsigned int)simple_strtoul (argv[2], NULL, 16); if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) { puts ("Bad number of FSL\n"); - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -196,7 +196,7 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) unsigned int blocking; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -204,7 +204,7 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) num = (unsigned int)simple_strtoul (argv[2], NULL, 16); blocking = (unsigned int)simple_strtoul (argv[3], NULL, 16); if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) { - printf ("Bad number of FSL\nUsage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -354,7 +354,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) unsigned int val = 0; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } reg = (unsigned int)simple_strtoul (argv[1], NULL, 16); @@ -389,7 +389,7 @@ int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /***************************************************/ U_BOOT_CMD (frd, 3, 1, do_frd, - "frd - read data from FSL\n", + "read data from FSL", "- [fslnum [0|1|2|3]]\n" " 0 - non blocking data read\n" " 1 - non blocking control read\n" @@ -398,7 +398,7 @@ U_BOOT_CMD (frd, 3, 1, do_frd, U_BOOT_CMD (fwr, 4, 1, do_fwr, - "fwr - write data to FSL\n", + "write data to FSL", "- [fslnum [0|1|2|3]]\n" " 0 - non blocking data write\n" " 1 - non blocking control write\n" @@ -406,7 +406,7 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr, " 3 - blocking control write\n"); U_BOOT_CMD (rspr, 3, 1, do_rspr, - "rspr - read/write special purpose register\n", + "read/write special purpose register", "- reg_num [write value] read/write special purpose register\n" " 1 - MSR - Machine status register\n" " 3 - EAR - Exception address register\n" diff --git a/common/cmd_mii.c b/common/cmd_mii.c index bcbd7aa4e..d70031aaa 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -302,7 +302,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) char *devname; if (argc < 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -431,7 +431,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) else miiphy_set_current_dev (argv[2]); } else { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -453,7 +453,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( mii, 5, 1, do_mii, - "mii - MII utility commands\n", + "MII utility commands", "device - list available devices\n" "mii device <devname> - set current device\n" "mii info <addr> - display MII PHY info\n" diff --git a/common/cmd_misc.c b/common/cmd_misc.c index 3ea8ee07f..024299a87 100644 --- a/common/cmd_misc.c +++ b/common/cmd_misc.c @@ -33,7 +33,7 @@ int do_sleep (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong delay; if (argc != 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -55,14 +55,14 @@ int do_irqinfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( irqinfo, 1, 1, do_irqinfo, - "irqinfo - print information about IRQs\n", + "print information about IRQs", NULL ); #endif U_BOOT_CMD( sleep , 2, 1, do_sleep, - "sleep - delay execution for some time\n", + "delay execution for some time", "N\n" " - delay execution for N seconds (N is _decimal_ !!!)\n" ); diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 25c970257..473825edd 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -36,6 +36,6 @@ int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( mmcinit, 1, 0, do_mmc, - "mmcinit - init mmc card\n", + "init mmc card", NULL ); diff --git a/common/cmd_mp.c b/common/cmd_mp.c index f3a7f49e1..a0839c2fb 100644 --- a/common/cmd_mp.c +++ b/common/cmd_mp.c @@ -29,7 +29,7 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned long cpuid; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -47,7 +47,7 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else if (strncmp(argv[2], "status", 6) == 0) { cpu_status(cpuid); } else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } return 0; @@ -55,12 +55,12 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* 4 or greater, make sure its release */ if (strncmp(argv[2], "release", 7) != 0) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } if (cpu_release(cpuid, argc - 3, argv + 3)) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -83,7 +83,7 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd, - "cpu - Multiprocessor CPU boot manipulation and release\n", + "Multiprocessor CPU boot manipulation and release", "<num> reset - Reset cpu <num>\n" "cpu <num> status - Status of cpu <num>\n" "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]\n" diff --git a/common/cmd_nand.c b/common/cmd_nand.c index aedf8a624..11f909662 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -463,12 +463,12 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #endif usage: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD(nand, 5, 1, do_nand, - "nand - NAND sub-system\n", + "NAND sub-system", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read - addr off|partition size\n" @@ -638,7 +638,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_CMD_JFFS2) && defined(CONFIG_JFFS2_CMDLINE) usage: #endif - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); show_boot_progress(-53); return 1; } @@ -664,7 +664,7 @@ usage: } U_BOOT_CMD(nboot, 4, 1, do_nandboot, - "nboot - boot from NAND device\n", + "boot from NAND device", "[partition] | [[[loadAddr] dev] offset]\n"); #endif @@ -751,7 +751,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) switch (argc) { case 0: case 1: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 2: if (strcmp (argv[1], "info") == 0) { @@ -789,7 +789,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 3: if (strcmp (argv[1], "device") == 0) { @@ -828,7 +828,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return ret; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; default: /* at least 4 args */ @@ -877,7 +877,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } #endif /* CONFIG_SYS_NAND_SKIP_BAD_DOT_I */ else if (cmdtail) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -913,7 +913,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return ret; } else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); rcode = 1; } @@ -923,7 +923,7 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( nand, 5, 1, do_nand, - "nand - legacy NAND sub-system\n", + "legacy NAND sub-system", "info - show available NAND devices\n" "nand device [dev] - show or set current device\n" "nand read[.jffs2[s]] addr off size\n" @@ -970,7 +970,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) offset = simple_strtoul(argv[3], NULL, 16); break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); show_boot_progress (-53); return 1; } @@ -1072,7 +1072,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( nboot, 4, 1, do_nandboot, - "nboot - boot from NAND device\n", + "boot from NAND device", "loadAddr dev\n" ); diff --git a/common/cmd_net.c b/common/cmd_net.c index c053d7b97..a68784919 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -39,7 +39,7 @@ int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( bootp, 3, 1, do_bootp, - "bootp\t- boot image via network using BOOTP/TFTP protocol\n", + "boot image via network using BOOTP/TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]\n" ); @@ -50,7 +50,7 @@ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( tftpboot, 3, 1, do_tftpb, - "tftpboot- boot image via network using TFTP protocol\n", + "boot image via network using TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]\n" ); @@ -61,7 +61,7 @@ int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( rarpboot, 3, 1, do_rarpb, - "rarpboot- boot image via network using RARP/TFTP protocol\n", + "boot image via network using RARP/TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]\n" ); @@ -73,7 +73,7 @@ int do_dhcp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( dhcp, 3, 1, do_dhcp, - "dhcp\t- boot image via network using DHCP/TFTP protocol\n", + "boot image via network using DHCP/TFTP protocol", "[loadAddress] [[hostIPaddr:]bootfilename]\n" ); #endif @@ -86,7 +86,7 @@ int do_nfs (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( nfs, 3, 1, do_nfs, - "nfs\t- boot image via network using NFS protocol\n", + "boot image via network using NFS protocol", "[loadAddress] [[hostIPaddr:]bootfilename]\n" ); #endif @@ -186,7 +186,7 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) break; - default: printf ("Usage:\n%s\n", cmdtp->usage); + default: cmd_usage(cmdtp); show_boot_progress (-80); return 1; } @@ -251,7 +251,7 @@ int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) NetPingIP = string_to_ip(argv[1]); if (NetPingIP == 0) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return -1; } @@ -267,7 +267,7 @@ int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( ping, 2, 1, do_ping, - "ping\t- send ICMP ECHO_REQUEST to network host\n", + "send ICMP ECHO_REQUEST to network host", "pingAddress\n" ); #endif @@ -311,7 +311,7 @@ int do_cdp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( cdp, 1, 1, do_cdp, - "cdp\t- Perform CDP network configuration\n", + "Perform CDP network configuration", ); #endif @@ -348,7 +348,7 @@ int do_sntp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sntp, 2, 1, do_sntp, - "sntp\t- synchronize RTC via network\n", + "synchronize RTC via network", "[NTP server IP]\n" ); #endif diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 85025daec..1fcb4c96a 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -408,7 +408,7 @@ void forceenv (char *varname, char *varvalue) int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -434,13 +434,13 @@ int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) local_args[3] = NULL; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } /* Check the syntax */ switch (argc) { case 1: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 2: /* askenv envname */ @@ -546,11 +546,8 @@ int getenv_r (char *name, char *buf, unsigned len) return (-1); } -#if ((defined(CONFIG_ENV_IS_IN_NVRAM) || defined(CONFIG_ENV_IS_IN_EEPROM) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))) \ - && !defined(CONFIG_ENV_IS_NOWHERE)) +#if defined(CONFIG_CMD_ENV) && !defined(CONFIG_ENV_IS_NOWHERE) + int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { extern char * env_name_spec; @@ -560,6 +557,12 @@ int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (saveenv() ? 1 : 0); } +U_BOOT_CMD( + saveenv, 1, 0, do_saveenv, + "save environment variables to persistent storage", + NULL +); + #endif @@ -587,7 +590,7 @@ int envmatch (uchar *s1, int i2) U_BOOT_CMD( printenv, CONFIG_SYS_MAXARGS, 1, do_printenv, - "printenv- print environment variables\n", + "print environment variables", "\n - print values of all environment variables\n" "printenv name ...\n" " - print value of environment variable 'name'\n" @@ -595,31 +598,18 @@ U_BOOT_CMD( U_BOOT_CMD( setenv, CONFIG_SYS_MAXARGS, 0, do_setenv, - "setenv - set environment variables\n", + "set environment variables", "name value ...\n" " - set environment variable 'name' to 'value ...'\n" "setenv name\n" " - delete environment variable 'name'\n" ); -#if ((defined(CONFIG_ENV_IS_IN_NVRAM) || defined(CONFIG_ENV_IS_IN_EEPROM) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_FLASH)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_NAND)) \ - || (defined(CONFIG_CMD_ENV) && defined(CONFIG_CMD_ONENAND))) \ - && !defined(CONFIG_ENV_IS_NOWHERE)) -U_BOOT_CMD( - saveenv, 1, 0, do_saveenv, - "saveenv - save environment variables to persistent storage\n", - NULL -); - -#endif - #if defined(CONFIG_CMD_ASKENV) U_BOOT_CMD( askenv, CONFIG_SYS_MAXARGS, 1, do_askenv, - "askenv - get environment variables from stdin\n", + "get environment variables from stdin", "name [message] [size]\n" " - get environment variable 'name' from stdin (max 'size' chars)\n" "askenv name\n" @@ -636,7 +626,7 @@ U_BOOT_CMD( int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); U_BOOT_CMD( run, CONFIG_SYS_MAXARGS, 1, do_run, - "run - run commands in an environment variable\n", + "run commands in an environment variable", "var [...]\n" " - run the commands in the environment variable(s) 'var'\n" ); diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 6a2c92492..5832ff8d3 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -465,13 +465,13 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; usage: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( onenand, 6, 1, do_onenand, - "onenand - OneNAND sub-system\n", + "OneNAND sub-system", "info - show available OneNAND devices\n" "onenand bad - show bad blocks\n" "onenand read[.oob] addr off size\n" diff --git a/common/cmd_otp.c b/common/cmd_otp.c index 825fa34ce..65232903b 100644 --- a/common/cmd_otp.c +++ b/common/cmd_otp.c @@ -6,7 +6,7 @@ * Licensed under the GPL-2 or later. */ -/* There are 512 128-bit "pages" (0x000 to 0x1FF). +/* There are 512 128-bit "pages" (0x000 through 0x1FF). * The pages are accessable as 64-bit "halfpages" (an upper and lower half). * The pages are not part of the memory map. There is an OTP controller which * handles scanning in/out of bits. While access is done through OTP MMRs, @@ -17,8 +17,6 @@ #include <common.h> #include <command.h> -#ifdef CONFIG_CMD_OTP - #include <asm/blackfin.h> #include <asm/mach-common/bits/otp.h> @@ -40,30 +38,87 @@ static const char *otp_strerror(uint32_t err) #define lowup(x) ((x) % 2 ? "upper" : "lower") -int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +static int check_voltage(void) +{ + /* Make sure voltage limits are within datasheet spec */ + uint16_t vr_ctl = bfin_read_VR_CTL(); + +#ifdef __ADSPBF54x__ + /* 0.9V <= VDDINT <= 1.1V */ + if ((vr_ctl & 0xc) && (vr_ctl & 0xc0) == 0xc0) + return 1; +#else + /* for the parts w/out qualification yet */ + (void)vr_ctl; +#endif + + return 0; +} + +static void set_otp_timing(bool write) { - bool force = false; - if (!strcmp(argv[1], "--force")) { - force = true; - argv[1] = argv[0]; - argv++; - --argc; + static uint32_t timing; + if (!timing) { + uint32_t tp1, tp2, tp3; + /* OTP_TP1 = 1000 / sclk_period (in nanoseconds) + * OTP_TP1 = 1000 / (1 / get_sclk() * 10^9) + * OTP_TP1 = (1000 * get_sclk()) / 10^9 + * OTP_TP1 = get_sclk() / 10^6 + */ + tp1 = get_sclk() / 1000000; + /* OTP_TP2 = 400 / (2 * sclk_period) + * OTP_TP2 = 400 / (2 * 1 / get_sclk() * 10^9) + * OTP_TP2 = (400 * get_sclk()) / (2 * 10^9) + * OTP_TP2 = (2 * get_sclk()) / 10^7 + */ + tp2 = (2 * get_sclk() / 10000000) << 8; + /* OTP_TP3 = magic constant */ + tp3 = (0x1401) << 15; + timing = tp1 | tp2 | tp3; } + bfrom_OtpCommand(OTP_INIT, write ? timing : timing & ~(-1 << 15)); +} + +int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + uint32_t ret, base_flags; + bool prompt_user, force_read; uint32_t (*otp_func)(uint32_t page, uint32_t flags, uint64_t *page_content); - if (!strcmp(argv[1], "read")) - otp_func = otp_read; - else if (!strcmp(argv[1], "write")) - otp_func = otp_write; - else { + + if (argc < 4) { usage: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } + prompt_user = false; + base_flags = 0; + if (!strcmp(argv[1], "read")) + otp_func = bfrom_OtpRead; + else if (!strcmp(argv[1], "dump")) { + otp_func = bfrom_OtpRead; + force_read = true; + } else if (!strcmp(argv[1], "write")) { + otp_func = bfrom_OtpWrite; + base_flags = OTP_CHECK_FOR_PREV_WRITE; + if (!strcmp(argv[2], "--force")) { + argv[2] = argv[1]; + argv++; + --argc; + } else + prompt_user = false; + } else if (!strcmp(argv[1], "lock")) { + if (argc != 4) + goto usage; + otp_func = bfrom_OtpWrite; + base_flags = OTP_LOCK; + } else + goto usage; + uint64_t *addr = (uint64_t *)simple_strtoul(argv[2], NULL, 16); uint32_t page = simple_strtoul(argv[3], NULL, 16); - uint32_t flags, ret; + uint32_t flags; size_t i, count; ulong half; @@ -81,14 +136,21 @@ int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else half = 0; + /* "otp lock" has slightly different semantics */ + if (base_flags & OTP_LOCK) { + count = page; + page = (uint32_t)addr; + addr = NULL; + } + /* do to the nature of OTP, make sure users are sure */ - if (!force && otp_func == otp_write) { + if (prompt_user) { printf( "Writing one time programmable memory\n" "Make sure your operating voltages and temperature are within spec\n" " source address: 0x%p\n" - " OTP destination: %s page 0x%03X - %s page 0x%03X\n" - " number to write: %ld halfpages\n" + " OTP destination: %s page 0x%03X - %s page 0x%03lX\n" + " number to write: %lu halfpages\n" " type \"YES\" (no quotes) to confirm: ", addr, lowup(half), page, @@ -111,30 +173,42 @@ int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } } - - /* Only supported in newer silicon ... enable writing */ -#if (0) - otp_command(OTP_INIT, ...); -#else - *pOTP_TIMING = 0x32149485; -#endif } - printf("OTP memory %s: addr 0x%08lx page 0x%03X count %ld ... ", + printf("OTP memory %s: addr 0x%p page 0x%03X count %zu ... ", argv[1], addr, page, count); + set_otp_timing(otp_func == bfrom_OtpWrite); + if (otp_func == bfrom_OtpWrite && check_voltage()) { + puts("ERROR: VDDINT voltage is out of spec for writing\n"); + return -1; + } + + /* Do the actual reading/writing stuff */ ret = 0; for (i = half; i < count + half; ++i) { - flags = (i % 2) ? OTP_UPPER_HALF : OTP_LOWER_HALF; + flags = base_flags | (i % 2 ? OTP_UPPER_HALF : OTP_LOWER_HALF); + try_again: ret = otp_func(page, flags, addr); - if (ret & 0x1) - break; - else if (ret) + if (ret & OTP_MASTER_ERROR) { + if (force_read) { + if (flags & OTP_NO_ECC) + break; + else + flags |= OTP_NO_ECC; + puts("E"); + goto try_again; + } else + break; + } else if (ret) puts("W"); else puts("."); - ++addr; - if (i % 2) + if (!(base_flags & OTP_LOCK)) { + ++addr; + if (i % 2) + ++page; + } else ++page; } if (ret & 0x1) @@ -143,21 +217,20 @@ int do_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else puts(" done\n"); - if (otp_func == otp_write) - /* Only supported in newer silicon ... disable writing */ -#if (0) - otp_command(OTP_INIT, ...); -#else - *pOTP_TIMING = 0x1485; -#endif + /* Make sure we disable writing */ + set_otp_timing(false); + bfrom_OtpCommand(OTP_CLOSE, 0); return ret; } -U_BOOT_CMD(otp, 6, 0, do_otp, - "otp - One-Time-Programmable sub-system\n", +U_BOOT_CMD(otp, 7, 0, do_otp, + "One-Time-Programmable sub-system\n", "read <addr> <page> [count] [half]\n" + " - read 'count' half-pages starting at 'page' (offset 'half') to 'addr'\n" + "otp dump <addr> <page> [count] [half]\n" + " - like 'otp read', but skip read errors\n" "otp write [--force] <addr> <page> [count] [half]\n" - " - read/write 'count' half-pages starting at page 'page' (offset 'half')\n"); - -#endif + " - write 'count' half-pages starting at 'page' (offset 'half') from 'addr'\n" + "otp lock <page> <count>\n" + " - lock 'count' pages starting at 'page'\n"); diff --git a/common/cmd_pci.c b/common/cmd_pci.c index 67ff2fbc3..4a9317f16 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -534,7 +534,7 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; usage: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -543,7 +543,7 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( pci, 5, 1, do_pci, - "pci - list and access PCI Configuration Space\n", + "list and access PCI Configuration Space", "[bus] [long]\n" " - short or long list of PCI devices on bus 'bus'\n" "pci header b.d.f\n" diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c index 23fad3bcb..e44845697 100644 --- a/common/cmd_pcmcia.c +++ b/common/cmd_pcmcia.c @@ -88,7 +88,7 @@ int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( pinit, 2, 0, do_pinit, - "pinit - PCMCIA sub-system\n", + "PCMCIA sub-system", "on - power on PCMCIA socket\n" "pinit off - power off PCMCIA socket\n" ); diff --git a/common/cmd_portio.c b/common/cmd_portio.c index c88fcd5e4..41b1991a2 100644 --- a/common/cmd_portio.c +++ b/common/cmd_portio.c @@ -44,7 +44,7 @@ int do_portio_out (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) uint value = out_last_value; if (argc != 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -93,7 +93,7 @@ int do_portio_out (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( out, 3, 1, do_portio_out, - "out - write datum to IO port\n", + "write datum to IO port", "[.b, .w, .l] port value\n - output to IO port\n" ); @@ -103,7 +103,7 @@ int do_portio_in (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) uint size = in_last_size; if (argc != 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -157,7 +157,7 @@ int do_portio_in (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( in, 2, 1, do_portio_in, - "in - read data from an IO port\n", + "read data from an IO port", "[.b, .w, .l] port\n" " - read datum from IO port\n" ); diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index 4c8e61ab2..0e28c05b8 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -382,6 +382,6 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #if defined(CONFIG_CMD_REGINFO) U_BOOT_CMD( reginfo, 2, 1, do_reginfo, - "reginfo - print register information\n", + "print register information", ); #endif diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c index 4f4117ec7..14e4bd40e 100644 --- a/common/cmd_reiser.c +++ b/common/cmd_reiser.c @@ -57,7 +57,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int part_length; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } dev = (int)simple_strtoul (argv[2], &ep, 16); @@ -102,7 +102,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( reiserls, 4, 1, do_reiserls, - "reiserls- list files in a directory (default /)\n", + "list files in a directory (default /)", "<interface> <dev[:part]> [directory]\n" " - list files from 'dev' on 'interface' in a 'directory'\n" ); @@ -150,7 +150,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -232,7 +232,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( reiserload, 6, 0, do_reiserload, - "reiserload- load binary file from a Reiser filesystem\n", + "load binary file from a Reiser filesystem", "<interface> <dev[:part]> [addr] [filename] [bytes]\n" " - load binary file 'filename' from 'dev' on 'interface'\n" " to address 'addr' from dos filesystem\n" diff --git a/common/cmd_sata.c b/common/cmd_sata.c index dd6f1d9a5..e84977870 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -31,7 +31,7 @@ int curr_device = -1; block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; -int sata_initialize(void) +int __sata_initialize(void) { int rc; int i; @@ -55,6 +55,7 @@ int sata_initialize(void) curr_device = 0; return rc; } +int sata_initialize(void) __attribute__((weak,alias("__sata_initialize"))); block_dev_desc_t *sata_get_dev(int dev) { @@ -65,10 +66,18 @@ int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int rc = 0; + if (argc == 2 && strcmp(argv[1], "init") == 0) + return sata_initialize(); + + /* If the user has not yet run `sata init`, do it now */ + if (curr_device == -1) + if (sata_initialize()) + return 1; + switch (argc) { case 0: case 1: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 2: if (strncmp(argv[1],"inf", 3) == 0) { @@ -106,7 +115,7 @@ int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return rc; } - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 3: if (strncmp(argv[1], "dev", 3) == 0) { @@ -138,7 +147,7 @@ int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return rc; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; default: /* at least 4 args */ @@ -175,7 +184,7 @@ int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) n, (n == cnt) ? "OK" : "ERROR"); return (n == cnt) ? 0 : 1; } else { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); rc = 1; } @@ -185,7 +194,8 @@ int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sata, 5, 1, do_sata, - "sata - SATA sub system\n", + "SATA sub system", + "sata init - init SATA sub system\n" "sata info - show available SATA devices\n" "sata device [dev] - show or set current device\n" "sata part [dev] - print partition table\n" diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 066fd804a..dd2c1ae73 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -229,7 +229,7 @@ int do_scsiboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) boot_device = argv[2]; break; default: - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -346,7 +346,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { switch (argc) { case 0: - case 1: printf ("Usage:\n%s\n", cmdtp->usage); return 1; + case 1: cmd_usage(cmdtp); return 1; case 2: if (strncmp(argv[1],"res",3) == 0) { printf("\nReset SCSI\n"); @@ -392,7 +392,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf("\nno SCSI devices available\n"); return 1; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; case 3: if (strncmp(argv[1],"dev",3) == 0) { @@ -421,7 +421,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return 1; } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; default: /* at least 4 args */ @@ -437,7 +437,7 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } } /* switch */ - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -616,7 +616,7 @@ void scsi_setup_inquiry(ccb * pccb) U_BOOT_CMD( scsi, 5, 1, do_scsi, - "scsi - SCSI sub-system\n", + "SCSI sub-system", "reset - reset SCSI controller\n" "scsi info - show available SCSI devices\n" "scsi scan - (re-)scan SCSI bus\n" @@ -628,6 +628,6 @@ U_BOOT_CMD( U_BOOT_CMD( scsiboot, 3, 1, do_scsiboot, - "scsiboot- boot from SCSI device\n", + "boot from SCSI device", "loadAddr dev:part\n" ); diff --git a/common/cmd_setexpr.c b/common/cmd_setexpr.c index 2e49b6dd9..9a5e720d6 100644 --- a/common/cmd_setexpr.c +++ b/common/cmd_setexpr.c @@ -35,7 +35,7 @@ int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Validate arguments */ if ((argc != 5) || (strlen(argv[3]) != 1)) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -63,7 +63,7 @@ int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( setexpr, 5, 0, do_setexpr, - "setexpr - set environment variable as the result of eval expression\n", + "set environment variable as the result of eval expression", "name value1 <op> value2\n" " - set environment variable 'name' to the result of the evaluated\n" " express specified by <op>. <op> can be &, |, ^, +, -, *, /, %\n" diff --git a/common/cmd_sf.c b/common/cmd_sf.c index 8c0a7514d..6a60b1680 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -175,13 +175,13 @@ static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return do_spi_flash_erase(argc - 1, argv + 1); usage: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( sf, 5, 1, do_spi_flash, - "sf - SPI flash sub-system\n", + "SPI flash sub-system", "probe [bus:]cs [hz] [mode] - init flash device on given SPI bus\n" " and chip select\n" "sf read addr offset len - read `len' bytes starting at\n" diff --git a/common/cmd_spi.c b/common/cmd_spi.c index 1f0727b4a..746d14f21 100644 --- a/common/cmd_spi.c +++ b/common/cmd_spi.c @@ -138,7 +138,7 @@ int do_spi (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sspi, 5, 1, do_spi, - "sspi - SPI utility commands\n", + "SPI utility commands", "<device> <bit_len> <dout> - Send <bit_len> bits from <dout> out the SPI\n" "<device> - Identifies the chip select of the device\n" "<bit_len> - Number of bits to send (base 10)\n" diff --git a/common/cmd_strings.c b/common/cmd_strings.c index 7d05cf8e9..4517ba29e 100644 --- a/common/cmd_strings.c +++ b/common/cmd_strings.c @@ -15,7 +15,7 @@ static char *start_addr, *last_addr; int do_strings(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { if (argc == 1) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -41,6 +41,6 @@ int do_strings(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(strings, 3, 1, do_strings, - "strings - display strings\n", + "display strings", "<addr> [byte count]\n" " - display strings at <addr> for at least [byte count] or first double NUL\n"); diff --git a/common/cmd_terminal.c b/common/cmd_terminal.c index 67a254673..fd3dd4851 100644 --- a/common/cmd_terminal.c +++ b/common/cmd_terminal.c @@ -87,6 +87,6 @@ int do_terminal(cmd_tbl_t * cmd, int flag, int argc, char *argv[]) U_BOOT_CMD( terminal, 3, 1, do_terminal, - "terminal - start terminal emulator\n", + "start terminal emulator", "" ); diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 5c31f7b49..b99fd5863 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -441,7 +441,7 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int err = 0; if (argc < 2) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -459,7 +459,7 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } if (argc < 4) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -600,7 +600,7 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(ubi, 6, 1, do_ubi, - "ubi - ubi commands\n", + "ubi commands", "part [nand|nor|onenand] [part]" " - Show or set current partition\n" "ubi info [l[ayout]]" diff --git a/common/cmd_universe.c b/common/cmd_universe.c index ea977828a..bfb91b58c 100644 --- a/common/cmd_universe.c +++ b/common/cmd_universe.c @@ -364,7 +364,7 @@ int do_universe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( universe, 8, 1, do_universe, - "universe- initialize and configure Turndra Universe\n", + "initialize and configure Turndra Universe", "init\n" " - initialize universe\n" "universe vme [vme_addr] [pci_addr] [size] [vam] [pms]\n" diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 8b19240a8..a18e16e10 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -264,6 +264,16 @@ void usb_display_config(struct usb_device *dev) printf("\n"); } +static inline char *portspeed(int speed) +{ + if (speed == USB_SPEED_HIGH) + return "480 Mb/s"; + else if (speed == USB_SPEED_LOW) + return "1.5 Mb/s"; + else + return "12 Mb/s"; +} + /* shows the device tree recursively */ void usb_show_tree_graph(struct usb_device *dev, char *pre) { @@ -310,7 +320,7 @@ void usb_show_tree_graph(struct usb_device *dev, char *pre) pre[index] = 0; printf(" %s (%s, %dmA)\n", usb_get_class_desc( dev->config.if_desc[0].bInterfaceClass), - dev->slow ? "1.5MBit/s" : "12MBit/s", + portspeed(dev->speed), dev->config.MaxPower * 2); if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial)) printf(" %s %s %s %s\n", pre, dev->mf, dev->prod, dev->serial); @@ -366,7 +376,7 @@ int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) boot_device = argv[2]; break; default: - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -659,14 +669,14 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } #endif /* CONFIG_USB_STORAGE */ - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } #ifdef CONFIG_USB_STORAGE U_BOOT_CMD( usb, 5, 1, do_usb, - "usb - USB sub-system\n", + "USB sub-system", "reset - reset (rescan) USB controller\n" "usb stop [f] - stop USB [f]=force stop\n" "usb tree - show USB device tree\n" @@ -682,14 +692,14 @@ U_BOOT_CMD( U_BOOT_CMD( usbboot, 3, 1, do_usbboot, - "usbboot - boot from USB device\n", + "boot from USB device", "loadAddr dev:part\n" ); #else U_BOOT_CMD( usb, 5, 1, do_usb, - "usb - USB sub-system\n", + "USB sub-system", "reset - reset (rescan) USB controller\n" "usb tree - show USB device tree\n" "usb info [dev] - show available USB devices\n" diff --git a/common/cmd_vfd.c b/common/cmd_vfd.c index 45f427126..84d9530aa 100644 --- a/common/cmd_vfd.c +++ b/common/cmd_vfd.c @@ -50,7 +50,7 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong bitmap; if (argc != 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -67,7 +67,7 @@ int do_vfd (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( vfd, 2, 0, do_vfd, - "vfd - load a bitmap to the VFDs on TRAB\n", + "load a bitmap to the VFDs on TRAB", "/N\n" " - load bitmap N to the VFDs (N is _decimal_ !!!)\n" "vfd ADDR\n" diff --git a/common/cmd_ximg.c b/common/cmd_ximg.c index 2753389ea..a45d2480e 100644 --- a/common/cmd_ximg.c +++ b/common/cmd_ximg.c @@ -180,7 +180,7 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(imxtract, 4, 1, do_imgextract, - "imxtract- extract a part of a multi-image\n", + "extract a part of a multi-image", "addr part [dest]\n" " - extract <part> from legacy image at <addr> and copy to <dest>\n" #if defined(CONFIG_FIT) diff --git a/common/cmd_yaffs2.c b/common/cmd_yaffs2.c index 3732f7f98..c47ea769f 100644 --- a/common/cmd_yaffs2.c +++ b/common/cmd_yaffs2.c @@ -142,72 +142,72 @@ int do_ydump (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( ymount, 3, 0, do_ymount, - "ymount\t- mount yaffs\n", + "mount yaffs", "\n" ); U_BOOT_CMD( yumount, 3, 0, do_yumount, - "yumount\t- unmount yaffs\n", + "unmount yaffs", "\n" ); U_BOOT_CMD( yls, 4, 0, do_yls, - "yls\t- yaffs ls\n", + "yaffs ls", "[-l] name\n" ); U_BOOT_CMD( yrd, 2, 0, do_yrd, - "yrd\t- read file from yaffs\n", + "read file from yaffs", "filename\n" ); U_BOOT_CMD( ywr, 4, 0, do_ywr, - "ywr\t- write file to yaffs\n", + "write file to yaffs", "filename value num_vlues\n" ); U_BOOT_CMD( yrdm, 3, 0, do_yrdm, - "yrdm\t- read file to memory from yaffs\n", + "read file to memory from yaffs", "filename offset\n" ); U_BOOT_CMD( ywrm, 4, 0, do_ywrm, - "ywrm\t- write file from memory to yaffs\n", + "write file from memory to yaffs", "filename offset size\n" ); U_BOOT_CMD( ymkdir, 2, 0, do_ymkdir, - "ymkdir\t- YAFFS mkdir\n", + "YAFFS mkdir", "dirname\n" ); U_BOOT_CMD( yrmdir, 2, 0, do_yrmdir, - "yrmdir\t- YAFFS rmdir\n", + "YAFFS rmdir", "dirname\n" ); U_BOOT_CMD( yrm, 2, 0, do_yrm, - "yrm\t- YAFFS rm\n", + "YAFFS rm", "path\n" ); U_BOOT_CMD( ymv, 4, 0, do_ymv, - "ymv\t- YAFFS mv\n", + "YAFFS mv", "oldPath newPath\n" ); U_BOOT_CMD( ydump, 2, 0, do_ydump, - "ydump\t- YAFFS device struct\n", + "YAFFS device struct", "dirname\n" ); diff --git a/common/command.c b/common/command.c index a4a978c5f..3b9ccc9ed 100644 --- a/common/command.c +++ b/common/command.c @@ -38,7 +38,7 @@ do_version (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( version, 1, 1, do_version, - "version - print monitor version\n", + "print monitor version", NULL ); @@ -71,7 +71,7 @@ do_echo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( echo, CONFIG_SYS_MAXARGS, 1, do_echo, - "echo - echo args to console\n", + "echo args to console", "[args..]\n" " - echo args to console; \\c suppresses newline\n" ); @@ -203,7 +203,7 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( test, CONFIG_SYS_MAXARGS, 1, do_test, - "test - minimal test like /bin/sh\n", + "minimal test like /bin/sh", "[args..]\n" " - test functionality\n" ); @@ -222,7 +222,7 @@ do_exit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( exit, 2, 1, do_exit, - "exit - exit script\n", + "exit script", " - exit functionality\n" ); @@ -277,7 +277,8 @@ int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; if (usage == NULL) continue; - puts (usage); + printf("%-*s- %s\n", CONFIG_SYS_HELP_CMD_WIDTH, + cmd_array[i]->name, usage); } return 0; } @@ -299,7 +300,7 @@ int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) putc ('\n'); #else /* no long help available */ if (cmdtp->usage) - puts (cmdtp->usage); + printf ("%s - %s\n", cmdtp->name, cmdtp->usage); #endif /* CONFIG_SYS_LONGHELP */ } else { printf ("Unknown command '%s' - try 'help'" @@ -315,7 +316,7 @@ int do_help (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( help, CONFIG_SYS_MAXARGS, 1, do_help, - "help - print online help\n", + "print online help", "[command ...]\n" " - show help information (for 'command')\n" "'help' prints online help for the monitor commands.\n\n" @@ -328,13 +329,13 @@ U_BOOT_CMD( #ifdef CONFIG_SYS_LONGHELP cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = { "?", CONFIG_SYS_MAXARGS, 1, do_help, - "? - alias for 'help'\n", + "alias for 'help'", NULL }; #else cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = { "?", CONFIG_SYS_MAXARGS, 1, do_help, - "? - alias for 'help'\n" + "alias for 'help'" }; #endif /* CONFIG_SYS_LONGHELP */ @@ -379,6 +380,11 @@ cmd_tbl_t *find_cmd (const char *cmd) return find_cmd_tbl(cmd, &__u_boot_cmd_start, len); } +void cmd_usage(cmd_tbl_t *cmdtp) +{ + printf("Usage:\n%s - %s\n\n", cmdtp->name, cmdtp->usage); +} + #ifdef CONFIG_AUTO_COMPLETE int var_complete(int argc, char *argv[], char last_char, int maxv, char *cmdv[]) diff --git a/common/devices.c b/common/devices.c index ce3b7a00f..38f1bbc6a 100644 --- a/common/devices.c +++ b/common/devices.c @@ -240,6 +240,9 @@ int devices_init (void) #ifdef CONFIG_NETCONSOLE drv_nc_init (); #endif +#ifdef CONFIG_JTAG_CONSOLE + drv_jtag_console_init (); +#endif return (0); } diff --git a/common/hush.c b/common/hush.c index 9aef6e41d..01b74d782 100644 --- a/common/hush.c +++ b/common/hush.c @@ -1696,7 +1696,7 @@ static int run_pipe_real(struct pipe *pi) #endif /* found - check max args */ if ((child->argc - i) > cmdtp->maxargs) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return -1; } #endif @@ -3625,7 +3625,7 @@ int do_showvar (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( showvar, CONFIG_SYS_MAXARGS, 1, do_showvar, - "showvar- print local hushshell variables\n", + "print local hushshell variables", "\n - print values of all hushshell variables\n" "showvar name ...\n" " - print value of hushshell variable 'name'\n" diff --git a/common/kgdb.c b/common/kgdb.c index adc15dd79..888b96b68 100644 --- a/common/kgdb.c +++ b/common/kgdb.c @@ -575,7 +575,7 @@ do_kgdb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( kgdb, CONFIG_SYS_MAXARGS, 1, do_kgdb, - "kgdb - enter gdb remote debug mode\n", + "enter gdb remote debug mode", "[arg0 arg1 .. argN]\n" " - executes a breakpoint so that kgdb mode is\n" " entered via the exception handler. To return\n" diff --git a/common/lcd.c b/common/lcd.c index ae79051d1..5f73247f4 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -426,7 +426,7 @@ static int lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( cls, 1, 1, lcd_clear, - "cls - clear screen\n", + "clear screen", NULL ); diff --git a/common/main.c b/common/main.c index 4c4f78065..905d40f0e 100644 --- a/common/main.c +++ b/common/main.c @@ -1371,7 +1371,7 @@ int run_command (const char *cmd, int flag) /* found - check max args */ if (argc > cmdtp->maxargs) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); rc = -1; continue; } @@ -1415,7 +1415,7 @@ int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) int i; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } diff --git a/common/usb.c b/common/usb.c index ee181528c..87fca7070 100644 --- a/common/usb.c +++ b/common/usb.c @@ -681,7 +681,7 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size) err = usb_string_sub(dev, 0, 0, tbuf); if (err < 0) { USB_PRINTF("error getting string descriptor 0 " \ - "(error=%x)\n", dev->status); + "(error=%lx)\n", dev->status); return -1; } else if (tbuf[0] < 4) { USB_PRINTF("string descriptor 0 too short\n"); @@ -939,8 +939,10 @@ void usb_scan_devices(void) dev_index = 0; /* device 0 is always present (root hub, so let it analyze) */ dev = usb_alloc_new_device(); - usb_new_device(dev); - printf("%d USB Device(s) found\n", dev_index); + if (usb_new_device(dev)) + printf("No USB Device found\n"); + else + printf("%d USB Device(s) found\n", dev_index); /* insert "driver" if possible */ #ifdef CONFIG_USB_KEYBOARD drv_usb_kbd_init(); @@ -1041,6 +1043,16 @@ struct usb_hub_device *usb_hub_allocate(void) #define MAX_TRIES 5 +static inline char *portspeed(int portstatus) +{ + if (portstatus & (1 << USB_PORT_FEAT_HIGHSPEED)) + return "480 Mb/s"; + else if (portstatus & (1 << USB_PORT_FEAT_LOWSPEED)) + return "1.5 Mb/s"; + else + return "12 Mb/s"; +} + static int hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat) { @@ -1061,10 +1073,11 @@ static int hub_port_reset(struct usb_device *dev, int port, } portstatus = le16_to_cpu(portsts.wPortStatus); portchange = le16_to_cpu(portsts.wPortChange); + USB_HUB_PRINTF("portstatus %x, change %x, %s\n", portstatus, portchange, - portstatus&(1<<USB_PORT_FEAT_LOWSPEED) ? \ - "Low Speed" : "High Speed"); + portspeed(portstatus)); + USB_HUB_PRINTF("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \ " USB_PORT_STAT_ENABLE %d\n", (portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0, @@ -1109,9 +1122,7 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port) portstatus = le16_to_cpu(portsts.wPortStatus); portchange = le16_to_cpu(portsts.wPortChange); USB_HUB_PRINTF("portstatus %x, change %x, %s\n", - portstatus, portchange, - portstatus&(1 << USB_PORT_FEAT_LOWSPEED) ? \ - "Low Speed" : "High Speed"); + portstatus, portchange, portspeed(portstatus)); /* Clear the connection change status */ usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION); @@ -1136,7 +1147,13 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port) /* Allocate a new device struct for it */ usb = usb_alloc_new_device(); - usb->slow = (portstatus & USB_PORT_STAT_LOW_SPEED) ? 1 : 0; + + if (portstatus & USB_PORT_STAT_HIGH_SPEED) + usb->speed = USB_SPEED_HIGH; + else if (portstatus & USB_PORT_STAT_LOW_SPEED) + usb->speed = USB_SPEED_LOW; + else + usb->speed = USB_SPEED_FULL; dev->children[port] = usb; usb->parent = dev; diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 89e6ee7e5..e0d006c32 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -183,6 +183,7 @@ int drv_usb_kbd_init(void) usb_kbd_dev.puts = NULL; usb_kbd_dev.getc = usb_kbd_getc; usb_kbd_dev.tstc = usb_kbd_testc; + usb_kbd_dev.priv = (void *)dev; error = device_register (&usb_kbd_dev); if(error==0) { /* check if this is the standard input device */ diff --git a/common/usb_storage.c b/common/usb_storage.c index 94f659fd3..51f078948 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -45,8 +45,6 @@ * New Note: * Support for USB Mass Storage Devices (BBB) has been added. It has * only been tested with USB memory sticks. - * Nota bene: if you are using the BBB support with a little-endian - * CPU then you MUST define LITTLEENDIAN in the configuration file! */ @@ -63,9 +61,9 @@ #undef BBB_XPORT_TRACE #ifdef USB_STOR_DEBUG -#define USB_STOR_PRINTF(fmt,args...) printf (fmt ,##args) +#define USB_STOR_PRINTF(fmt, args...) printf(fmt , ##args) #else -#define USB_STOR_PRINTF(fmt,args...) +#define USB_STOR_PRINTF(fmt, args...) #endif #include <scsi.h> @@ -110,7 +108,7 @@ typedef struct { __u8 CBWCDB[CBWCDBLENGTH]; } umass_bbb_cbw_t; #define UMASS_BBB_CBW_SIZE 31 -static __u32 CBWTag = 0; +static __u32 CBWTag; /* Command Status Wrapper */ typedef struct { @@ -126,34 +124,35 @@ typedef struct { #define UMASS_BBB_CSW_SIZE 13 #define USB_MAX_STOR_DEV 5 -static int usb_max_devs = 0; /* number of highest available usb device */ +static int usb_max_devs; /* number of highest available usb device */ static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV]; struct us_data; -typedef int (*trans_cmnd)(ccb*, struct us_data*); -typedef int (*trans_reset)(struct us_data*); +typedef int (*trans_cmnd)(ccb *cb, struct us_data *data); +typedef int (*trans_reset)(struct us_data *data); struct us_data { - struct usb_device *pusb_dev; /* this usb_device */ - unsigned int flags; /* from filter initially */ - unsigned char ifnum; /* interface number */ - unsigned char ep_in; /* in endpoint */ - unsigned char ep_out; /* out ....... */ - unsigned char ep_int; /* interrupt . */ - unsigned char subclass; /* as in overview */ - unsigned char protocol; /* .............. */ - unsigned char attention_done; /* force attn on first cmd */ - unsigned short ip_data; /* interrupt data */ - int action; /* what to do */ - int ip_wanted; /* needed */ - int *irq_handle; /* for USB int requests */ - unsigned int irqpipe; /* pipe for release_irq */ - unsigned char irqmaxp; /* max packed for irq Pipe */ - unsigned char irqinterval; /* Intervall for IRQ Pipe */ - ccb *srb; /* current srb */ - trans_reset transport_reset; /* reset routine */ - trans_cmnd transport; /* transport routine */ + struct usb_device *pusb_dev; /* this usb_device */ + + unsigned int flags; /* from filter initially */ + unsigned char ifnum; /* interface number */ + unsigned char ep_in; /* in endpoint */ + unsigned char ep_out; /* out ....... */ + unsigned char ep_int; /* interrupt . */ + unsigned char subclass; /* as in overview */ + unsigned char protocol; /* .............. */ + unsigned char attention_done; /* force attn on first cmd */ + unsigned short ip_data; /* interrupt data */ + int action; /* what to do */ + int ip_wanted; /* needed */ + int *irq_handle; /* for USB int requests */ + unsigned int irqpipe; /* pipe for release_irq */ + unsigned char irqmaxp; /* max packed for irq Pipe */ + unsigned char irqinterval; /* Intervall for IRQ Pipe */ + ccb *srb; /* current srb */ + trans_reset transport_reset; /* reset routine */ + trans_cmnd transport; /* transport routine */ }; static struct us_data usb_stor[USB_MAX_STOR_DEV]; @@ -163,10 +162,12 @@ static struct us_data usb_stor[USB_MAX_STOR_DEV]; #define USB_STOR_TRANSPORT_FAILED -1 #define USB_STOR_TRANSPORT_ERROR -2 - -int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc); -int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data *ss); -unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer); +int usb_stor_get_info(struct usb_device *dev, struct us_data *us, + block_dev_desc_t *dev_desc); +int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, + struct us_data *ss); +unsigned long usb_stor_read(int device, unsigned long blknr, + unsigned long blkcnt, void *buffer); struct usb_device * usb_get_dev_index(int index); void uhci_show_temp_int_td(void); @@ -181,7 +182,7 @@ void usb_show_progress(void) printf("."); } -/********************************************************************************* +/******************************************************************************* * show info on storage devices; 'usb start/init' must be invoked earlier * as we only retrieve structures populated during devices initialization */ @@ -191,7 +192,7 @@ int usb_stor_info(void) if (usb_max_devs > 0) { for (i = 0; i < usb_max_devs; i++) { - printf (" Device %d: ", i); + printf(" Device %d: ", i); dev_print(&usb_dev_desc[i]); } return 0; @@ -201,7 +202,7 @@ int usb_stor_info(void) return 1; } -/********************************************************************************* +/******************************************************************************* * scan the usb and reports device info * to the user if mode = 1 * returns current device or -1 if no @@ -214,67 +215,69 @@ int usb_stor_scan(int mode) /* GJ */ memset(usb_stor_buf, 0, sizeof(usb_stor_buf)); - if(mode==1) { + if (mode == 1) printf(" scanning bus for storage devices... "); - } + usb_disable_asynch(1); /* asynch transfer not allowed */ - for(i=0;i<USB_MAX_STOR_DEV;i++) { - memset(&usb_dev_desc[i],0,sizeof(block_dev_desc_t)); - usb_dev_desc[i].target=0xff; - usb_dev_desc[i].if_type=IF_TYPE_USB; - usb_dev_desc[i].dev=i; - usb_dev_desc[i].part_type=PART_TYPE_UNKNOWN; - usb_dev_desc[i].block_read=usb_stor_read; + for (i = 0; i < USB_MAX_STOR_DEV; i++) { + memset(&usb_dev_desc[i], 0, sizeof(block_dev_desc_t)); + usb_dev_desc[i].target = 0xff; + usb_dev_desc[i].if_type = IF_TYPE_USB; + usb_dev_desc[i].dev = i; + usb_dev_desc[i].part_type = PART_TYPE_UNKNOWN; + usb_dev_desc[i].block_read = usb_stor_read; } - usb_max_devs=0; - for(i=0;i<USB_MAX_DEVICE;i++) { - dev=usb_get_dev_index(i); /* get device */ - USB_STOR_PRINTF("i=%d\n",i); - if(dev==NULL) { + usb_max_devs = 0; + for (i = 0; i < USB_MAX_DEVICE; i++) { + dev = usb_get_dev_index(i); /* get device */ + USB_STOR_PRINTF("i=%d\n", i); + if (dev == NULL) break; /* no more devices avaiable */ - } - if(usb_storage_probe(dev,0,&usb_stor[usb_max_devs])) { /* ok, it is a storage devices */ - /* get info and fill it in */ - if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs])) + + if (usb_storage_probe(dev, 0, &usb_stor[usb_max_devs])) { + /* ok, it is a storage devices + * get info and fill it in + */ + if (usb_stor_get_info(dev, &usb_stor[usb_max_devs], + &usb_dev_desc[usb_max_devs])) usb_max_devs++; - } /* if storage device */ - if(usb_max_devs==USB_MAX_STOR_DEV) { - printf("max USB Storage Device reached: %d stopping\n",usb_max_devs); + } + /* if storage device */ + if (usb_max_devs == USB_MAX_STOR_DEV) { + printf("max USB Storage Device reached: %d stopping\n", + usb_max_devs); break; } } /* for */ usb_disable_asynch(0); /* asynch transfer allowed */ printf("%d Storage Device(s) found\n", usb_max_devs); - if(usb_max_devs>0) + if (usb_max_devs > 0) return 0; - else - return-1; + return -1; } static int usb_stor_irq(struct usb_device *dev) { struct us_data *us; - us=(struct us_data *)dev->privptr; + us = (struct us_data *)dev->privptr; - if(us->ip_wanted) { - us->ip_wanted=0; - } + if (us->ip_wanted) + us->ip_wanted = 0; return 0; } #ifdef USB_STOR_DEBUG -static void usb_show_srb(ccb * pccb) +static void usb_show_srb(ccb *pccb) { int i; - printf("SRB: len %d datalen 0x%lX\n ",pccb->cmdlen,pccb->datalen); - for(i=0;i<12;i++) { - printf("%02X ",pccb->cmd[i]); - } + printf("SRB: len %d datalen 0x%lX\n ", pccb->cmdlen, pccb->datalen); + for (i = 0; i < 12; i++) + printf("%02X ", pccb->cmd[i]); printf("\n"); } @@ -322,11 +325,14 @@ static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) USB_STOR_PRINTF("Bulk xfer 0x%x(%d) try #%d\n", (unsigned int)buf, this_xfer, 11 - maxtry); result = usb_bulk_msg(us->pusb_dev, pipe, buf, - this_xfer, &partial, USB_CNTL_TIMEOUT*5); + this_xfer, &partial, + USB_CNTL_TIMEOUT * 5); USB_STOR_PRINTF("bulk_msg returned %d xferred %d/%d\n", result, partial, this_xfer); - if(us->pusb_dev->status!=0) { - /* if we stall, we need to clear it before we go on */ + if (us->pusb_dev->status != 0) { + /* if we stall, we need to clear it before + * we go on + */ #ifdef USB_STOR_DEBUG display_int_status(us->pusb_dev->status); #endif @@ -334,9 +340,9 @@ static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) USB_STOR_PRINTF("stalled ->clearing endpoint halt for pipe 0x%x\n", pipe); stat = us->pusb_dev->status; usb_clear_halt(us->pusb_dev, pipe); - us->pusb_dev->status=stat; - if(this_xfer == partial) { - USB_STOR_PRINTF("bulk transferred with error %X, but data ok\n",us->pusb_dev->status); + us->pusb_dev->status = stat; + if (this_xfer == partial) { + USB_STOR_PRINTF("bulk transferred with error %X, but data ok\n", us->pusb_dev->status); return 0; } else @@ -346,12 +352,15 @@ static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) USB_STOR_PRINTF("Device NAKed bulk_msg\n"); return result; } - if(this_xfer == partial) { - USB_STOR_PRINTF("bulk transferred with error %d, but data ok\n",us->pusb_dev->status); + USB_STOR_PRINTF("bulk transferred with error"); + if (this_xfer == partial) { + USB_STOR_PRINTF(" %d, but data ok\n", + us->pusb_dev->status); return 0; } /* if our try counter reaches 0, bail out */ - USB_STOR_PRINTF("bulk transferred with error %d, data %d\n",us->pusb_dev->status,partial); + USB_STOR_PRINTF(" %d, data %d\n", + us->pusb_dev->status, partial); if (!maxtry--) return result; } @@ -359,7 +368,7 @@ static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length) this_xfer -= partial; buf += partial; /* continue until this transfer is done */ - } while ( this_xfer ); + } while (this_xfer); } /* if we get here, we're done and successful */ @@ -386,29 +395,33 @@ static int usb_stor_BBB_reset(struct us_data *us) * This comment stolen from FreeBSD's /sys/dev/usb/umass.c. */ USB_STOR_PRINTF("BBB_reset\n"); - result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), - US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT*5); + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), + US_BBB_RESET, + USB_TYPE_CLASS | USB_RECIP_INTERFACE, + 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT * 5); - if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) - { + if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { USB_STOR_PRINTF("RESET:stall\n"); return -1; } /* long wait for reset */ wait_ms(150); - USB_STOR_PRINTF("BBB_reset result %d: status %X reset\n",result,us->pusb_dev->status); + USB_STOR_PRINTF("BBB_reset result %d: status %X reset\n", result, + us->pusb_dev->status); pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); result = usb_clear_halt(us->pusb_dev, pipe); /* long wait for reset */ wait_ms(150); - USB_STOR_PRINTF("BBB_reset result %d: status %X clearing IN endpoint\n",result,us->pusb_dev->status); + USB_STOR_PRINTF("BBB_reset result %d: status %X clearing IN endpoint\n", + result, us->pusb_dev->status); /* long wait for reset */ pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); result = usb_clear_halt(us->pusb_dev, pipe); wait_ms(150); - USB_STOR_PRINTF("BBB_reset result %d: status %X clearing OUT endpoint\n",result,us->pusb_dev->status); + USB_STOR_PRINTF("BBB_reset result %d: status %X" + " clearing OUT endpoint\n", result, + us->pusb_dev->status); USB_STOR_PRINTF("BBB_reset done\n"); return 0; } @@ -423,16 +436,20 @@ static int usb_stor_CB_reset(struct us_data *us) int result; USB_STOR_PRINTF("CB_reset\n"); - memset(cmd, 0xFF, sizeof(cmd)); + memset(cmd, 0xff, sizeof(cmd)); cmd[0] = SCSI_SEND_DIAG; cmd[1] = 4; - result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), - US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0, us->ifnum, cmd, sizeof(cmd), USB_CNTL_TIMEOUT*5); + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), + US_CBI_ADSC, + USB_TYPE_CLASS | USB_RECIP_INTERFACE, + 0, us->ifnum, cmd, sizeof(cmd), + USB_CNTL_TIMEOUT * 5); /* long wait for reset */ wait_ms(1500); - USB_STOR_PRINTF("CB_reset result %d: status %X clearing endpoint halt\n",result,us->pusb_dev->status); + USB_STOR_PRINTF("CB_reset result %d: status %X" + " clearing endpoint halt\n", result, + us->pusb_dev->status); usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_in)); usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_out)); @@ -455,9 +472,11 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) dir_in = US_DIRECTION(srb->cmd[0]); #ifdef BBB_COMDAT_TRACE - printf("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\n", dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen, srb->pdata); + printf("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\n", + dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen, + srb->pdata); if (srb->cmdlen) { - for(result = 0;result < srb->cmdlen;result++) + for (result = 0; result < srb->cmdlen; result++) printf("cmd[%d] %#x ", result, srb->cmd[result]); printf("\n"); } @@ -474,13 +493,14 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) cbw.dCBWSignature = cpu_to_le32(CBWSIGNATURE); cbw.dCBWTag = cpu_to_le32(CBWTag++); cbw.dCBWDataTransferLength = cpu_to_le32(srb->datalen); - cbw.bCBWFlags = (dir_in? CBWFLAGS_IN : CBWFLAGS_OUT); + cbw.bCBWFlags = (dir_in ? CBWFLAGS_IN : CBWFLAGS_OUT); cbw.bCBWLUN = srb->lun; cbw.bCDBLength = srb->cmdlen; /* copy the command data into the CBW command data buffer */ /* DST SRC LEN!!! */ memcpy(cbw.CBWCDB, srb->cmd, srb->cmdlen); - result = usb_bulk_msg(us->pusb_dev, pipe, &cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_CNTL_TIMEOUT*5); + result = usb_bulk_msg(us->pusb_dev, pipe, &cbw, UMASS_BBB_CBW_SIZE, + &actlen, USB_CNTL_TIMEOUT * 5); if (result < 0) USB_STOR_PRINTF("usb_stor_BBB_comdat:usb_bulk_msg error\n"); return result; @@ -492,46 +512,61 @@ int usb_stor_BBB_comdat(ccb *srb, struct us_data *us) int usb_stor_CB_comdat(ccb *srb, struct us_data *us) { int result = 0; - int dir_in,retry; + int dir_in, retry; unsigned int pipe; unsigned long status; - retry=5; - dir_in=US_DIRECTION(srb->cmd[0]); + retry = 5; + dir_in = US_DIRECTION(srb->cmd[0]); - if(dir_in) - pipe=usb_rcvbulkpipe(us->pusb_dev, us->ep_in); - else - pipe=usb_sndbulkpipe(us->pusb_dev, us->ep_out); - while(retry--) { - USB_STOR_PRINTF("CBI gets a command: Try %d\n",5-retry); + if (dir_in) + pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in); + else + pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out); + + while (retry--) { + USB_STOR_PRINTF("CBI gets a command: Try %d\n", 5 - retry); #ifdef USB_STOR_DEBUG usb_show_srb(srb); #endif /* let's send the command via the control pipe */ - result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), - US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, + result = usb_control_msg(us->pusb_dev, + usb_sndctrlpipe(us->pusb_dev , 0), + US_CBI_ADSC, + USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, - srb->cmd, srb->cmdlen, USB_CNTL_TIMEOUT*5); - USB_STOR_PRINTF("CB_transport: control msg returned %d, status %X\n",result,us->pusb_dev->status); + srb->cmd, srb->cmdlen, + USB_CNTL_TIMEOUT * 5); + USB_STOR_PRINTF("CB_transport: control msg returned %d," + " status %X\n", result, us->pusb_dev->status); /* check the return code for the command */ if (result < 0) { - if(us->pusb_dev->status & USB_ST_STALLED) { - status=us->pusb_dev->status; - USB_STOR_PRINTF(" stall during command found, clear pipe\n"); - usb_clear_halt(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0)); - us->pusb_dev->status=status; + if (us->pusb_dev->status & USB_ST_STALLED) { + status = us->pusb_dev->status; + USB_STOR_PRINTF(" stall during command found," + " clear pipe\n"); + usb_clear_halt(us->pusb_dev, + usb_sndctrlpipe(us->pusb_dev, 0)); + us->pusb_dev->status = status; } - USB_STOR_PRINTF(" error during command %02X Stat = %X\n",srb->cmd[0],us->pusb_dev->status); + USB_STOR_PRINTF(" error during command %02X" + " Stat = %X\n", srb->cmd[0], + us->pusb_dev->status); return result; } /* transfer the data payload for this command, if one exists*/ - USB_STOR_PRINTF("CB_transport: control msg returned %d, direction is %s to go 0x%lx\n",result,dir_in ? "IN" : "OUT",srb->datalen); + USB_STOR_PRINTF("CB_transport: control msg returned %d," + " direction is %s to go 0x%lx\n", result, + dir_in ? "IN" : "OUT", srb->datalen); if (srb->datalen) { - result = us_one_transfer(us, pipe, (char *)srb->pdata,srb->datalen); - USB_STOR_PRINTF("CBI attempted to transfer data, result is %d status %lX, len %d\n", result,us->pusb_dev->status,us->pusb_dev->act_len); - if(!(us->pusb_dev->status & USB_ST_NAK_REC)) + result = us_one_transfer(us, pipe, (char *)srb->pdata, + srb->datalen); + USB_STOR_PRINTF("CBI attempted to transfer data," + " result is %d status %lX, len %d\n", + result, us->pusb_dev->status, + us->pusb_dev->act_len); + if (!(us->pusb_dev->status & USB_ST_NAK_REC)) break; } /* if (srb->datalen) */ else @@ -543,21 +578,21 @@ int usb_stor_CB_comdat(ccb *srb, struct us_data *us) } -int usb_stor_CBI_get_status (ccb * srb, struct us_data *us) +int usb_stor_CBI_get_status(ccb *srb, struct us_data *us) { int timeout; us->ip_wanted = 1; - submit_int_msg (us->pusb_dev, us->irqpipe, + submit_int_msg(us->pusb_dev, us->irqpipe, (void *) &us->ip_data, us->irqmaxp, us->irqinterval); timeout = 1000; while (timeout--) { if ((volatile int *) us->ip_wanted == 0) break; - wait_ms (10); + wait_ms(10); } if (us->ip_wanted) { - printf (" Did not get interrupt on CBI\n"); + printf(" Did not get interrupt on CBI\n"); us->ip_wanted = 0; return USB_STOR_TRANSPORT_ERROR; } @@ -596,9 +631,9 @@ int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt) int result; /* ENDPOINT_HALT = 0, so set value to 0 */ - result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev,0), + result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, - 0, endpt, 0, 0, USB_CNTL_TIMEOUT*5); + 0, endpt, 0, 0, USB_CNTL_TIMEOUT * 5); return result; } @@ -638,12 +673,14 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) pipe = pipein; else pipe = pipeout; - result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT*5); + result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, + &data_actlen, USB_CNTL_TIMEOUT * 5); /* special handling of STALL in DATA phase */ - if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { + if ((result < 0) && (us->pusb_dev->status & USB_ST_STALLED)) { USB_STOR_PRINTF("DATA:stall\n"); /* clear the STALL on the endpoint */ - result = usb_stor_BBB_clear_endpt_stall(us, dir_in? us->ep_in : us->ep_out); + result = usb_stor_BBB_clear_endpt_stall(us, + dir_in ? us->ep_in : us->ep_out); if (result >= 0) /* continue on to STATUS phase */ goto st; @@ -660,15 +697,16 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) printf("\n"); #endif /* STATUS phase + error handling */ - st: +st: retry = 0; - again: +again: USB_STOR_PRINTF("STATUS phase\n"); result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE, &actlen, USB_CNTL_TIMEOUT*5); /* special handling of STALL in STATUS phase */ - if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED)) { + if ((result < 0) && (retry < 1) && + (us->pusb_dev->status & USB_ST_STALLED)) { USB_STOR_PRINTF("STATUS:stall\n"); /* clear the STALL on the endpoint */ result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in); @@ -722,32 +760,33 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us) int usb_stor_CB_transport(ccb *srb, struct us_data *us) { - int result,status; + int result, status; ccb *psrb; ccb reqsrb; - int retry,notready; + int retry, notready; psrb = &reqsrb; - status=USB_STOR_TRANSPORT_GOOD; - retry=0; - notready=0; + status = USB_STOR_TRANSPORT_GOOD; + retry = 0; + notready = 0; /* issue the command */ do_retry: - result=usb_stor_CB_comdat(srb,us); - USB_STOR_PRINTF("command / Data returned %d, status %X\n",result,us->pusb_dev->status); + result = usb_stor_CB_comdat(srb, us); + USB_STOR_PRINTF("command / Data returned %d, status %X\n", + result, us->pusb_dev->status); /* if this is an CBI Protocol, get IRQ */ - if(us->protocol==US_PR_CBI) { - status=usb_stor_CBI_get_status(srb,us); + if (us->protocol == US_PR_CBI) { + status = usb_stor_CBI_get_status(srb, us); /* if the status is error, report it */ - if(status==USB_STOR_TRANSPORT_ERROR) { + if (status == USB_STOR_TRANSPORT_ERROR) { USB_STOR_PRINTF(" USB CBI Command Error\n"); return status; } - srb->sense_buf[12]=(unsigned char)(us->ip_data>>8); - srb->sense_buf[13]=(unsigned char)(us->ip_data&0xff); - if(!us->ip_data) { - /* if the status is good, report it */ - if(status==USB_STOR_TRANSPORT_GOOD) { + srb->sense_buf[12] = (unsigned char)(us->ip_data >> 8); + srb->sense_buf[13] = (unsigned char)(us->ip_data & 0xff); + if (!us->ip_data) { + /* if the status is good, report it */ + if (status == USB_STOR_TRANSPORT_GOOD) { USB_STOR_PRINTF(" USB CBI Command Good\n"); return status; } @@ -755,51 +794,62 @@ do_retry: } /* do we have to issue an auto request? */ /* HERE we have to check the result */ - if((result<0) && !(us->pusb_dev->status & USB_ST_STALLED)) { - USB_STOR_PRINTF("ERROR %X\n",us->pusb_dev->status); + if ((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) { + USB_STOR_PRINTF("ERROR %X\n", us->pusb_dev->status); us->transport_reset(us); return USB_STOR_TRANSPORT_ERROR; } - if((us->protocol==US_PR_CBI) && - ((srb->cmd[0]==SCSI_REQ_SENSE) || - (srb->cmd[0]==SCSI_INQUIRY))) { /* do not issue an autorequest after request sense */ + if ((us->protocol == US_PR_CBI) && + ((srb->cmd[0] == SCSI_REQ_SENSE) || + (srb->cmd[0] == SCSI_INQUIRY))) { + /* do not issue an autorequest after request sense */ USB_STOR_PRINTF("No auto request and good\n"); return USB_STOR_TRANSPORT_GOOD; } /* issue an request_sense */ - memset(&psrb->cmd[0],0,12); - psrb->cmd[0]=SCSI_REQ_SENSE; - psrb->cmd[1]=srb->lun<<5; - psrb->cmd[4]=18; - psrb->datalen=18; + memset(&psrb->cmd[0], 0, 12); + psrb->cmd[0] = SCSI_REQ_SENSE; + psrb->cmd[1] = srb->lun << 5; + psrb->cmd[4] = 18; + psrb->datalen = 18; psrb->pdata = &srb->sense_buf[0]; - psrb->cmdlen=12; + psrb->cmdlen = 12; /* issue the command */ - result=usb_stor_CB_comdat(psrb,us); - USB_STOR_PRINTF("auto request returned %d\n",result); + result = usb_stor_CB_comdat(psrb, us); + USB_STOR_PRINTF("auto request returned %d\n", result); /* if this is an CBI Protocol, get IRQ */ - if(us->protocol==US_PR_CBI) { - status=usb_stor_CBI_get_status(psrb,us); - } - if((result<0)&&!(us->pusb_dev->status & USB_ST_STALLED)) { - USB_STOR_PRINTF(" AUTO REQUEST ERROR %d\n",us->pusb_dev->status); + if (us->protocol == US_PR_CBI) + status = usb_stor_CBI_get_status(psrb, us); + + if ((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED)) { + USB_STOR_PRINTF(" AUTO REQUEST ERROR %d\n", + us->pusb_dev->status); return USB_STOR_TRANSPORT_ERROR; } - USB_STOR_PRINTF("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\n",srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + USB_STOR_PRINTF("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\n", + srb->sense_buf[0], srb->sense_buf[2], + srb->sense_buf[12], srb->sense_buf[13]); /* Check the auto request result */ - if((srb->sense_buf[2]==0) && - (srb->sense_buf[12]==0) && - (srb->sense_buf[13]==0)) /* ok, no sense */ + if ((srb->sense_buf[2] == 0) && + (srb->sense_buf[12] == 0) && + (srb->sense_buf[13] == 0)) { + /* ok, no sense */ return USB_STOR_TRANSPORT_GOOD; + } + /* Check the auto request result */ - switch(srb->sense_buf[2]) { - case 0x01: /* Recovered Error */ + switch (srb->sense_buf[2]) { + case 0x01: + /* Recovered Error */ return USB_STOR_TRANSPORT_GOOD; break; - case 0x02: /* Not Ready */ - if(notready++ > USB_TRANSPORT_NOT_READY_RETRY) { - printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X (NOT READY)\n", - srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + case 0x02: + /* Not Ready */ + if (notready++ > USB_TRANSPORT_NOT_READY_RETRY) { + printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X" + " 0x%02X (NOT READY)\n", srb->cmd[0], + srb->sense_buf[0], srb->sense_buf[2], + srb->sense_buf[12], srb->sense_buf[13]); return USB_STOR_TRANSPORT_FAILED; } else { wait_ms(100); @@ -807,113 +857,116 @@ do_retry: } break; default: - if(retry++ > USB_TRANSPORT_UNKNOWN_RETRY) { - printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X\n", - srb->cmd[0],srb->sense_buf[0],srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + if (retry++ > USB_TRANSPORT_UNKNOWN_RETRY) { + printf("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X" + " 0x%02X\n", srb->cmd[0], srb->sense_buf[0], + srb->sense_buf[2], srb->sense_buf[12], + srb->sense_buf[13]); return USB_STOR_TRANSPORT_FAILED; - } else { + } else goto do_retry; - } break; } return USB_STOR_TRANSPORT_FAILED; } -static int usb_inquiry(ccb *srb,struct us_data *ss) +static int usb_inquiry(ccb *srb, struct us_data *ss) { - int retry,i; - retry=5; + int retry, i; + retry = 5; do { - memset(&srb->cmd[0],0,12); - srb->cmd[0]=SCSI_INQUIRY; - srb->cmd[1]=srb->lun<<5; - srb->cmd[4]=36; - srb->datalen=36; - srb->cmdlen=12; - i=ss->transport(srb,ss); - USB_STOR_PRINTF("inquiry returns %d\n",i); - if(i==0) + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_INQUIRY; + srb->cmd[1] = srb->lun<<5; + srb->cmd[4] = 36; + srb->datalen = 36; + srb->cmdlen = 12; + i = ss->transport(srb, ss); + USB_STOR_PRINTF("inquiry returns %d\n", i); + if (i == 0) break; - } while(retry--); + } while (retry--); - if(!retry) { + if (!retry) { printf("error in inquiry\n"); return -1; } return 0; } -static int usb_request_sense(ccb *srb,struct us_data *ss) +static int usb_request_sense(ccb *srb, struct us_data *ss) { char *ptr; - ptr=(char *)srb->pdata; - memset(&srb->cmd[0],0,12); - srb->cmd[0]=SCSI_REQ_SENSE; - srb->cmd[1]=srb->lun<<5; - srb->cmd[4]=18; - srb->datalen=18; + ptr = (char *)srb->pdata; + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_REQ_SENSE; + srb->cmd[1] = srb->lun << 5; + srb->cmd[4] = 18; + srb->datalen = 18; srb->pdata = &srb->sense_buf[0]; - srb->cmdlen=12; - ss->transport(srb,ss); - USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n",srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); - srb->pdata=(uchar *)ptr; + srb->cmdlen = 12; + ss->transport(srb, ss); + USB_STOR_PRINTF("Request Sense returned %02X %02X %02X\n", + srb->sense_buf[2], srb->sense_buf[12], + srb->sense_buf[13]); + srb->pdata = (uchar *)ptr; return 0; } -static int usb_test_unit_ready(ccb *srb,struct us_data *ss) +static int usb_test_unit_ready(ccb *srb, struct us_data *ss) { int retries = 10; do { - memset(&srb->cmd[0],0,12); - srb->cmd[0]=SCSI_TST_U_RDY; - srb->cmd[1]=srb->lun<<5; - srb->datalen=0; - srb->cmdlen=12; - if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_TST_U_RDY; + srb->cmd[1] = srb->lun << 5; + srb->datalen = 0; + srb->cmdlen = 12; + if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) return 0; - } - usb_request_sense (srb, ss); - wait_ms (100); - } while(retries--); + usb_request_sense(srb, ss); + wait_ms(100); + } while (retries--); return -1; } -static int usb_read_capacity(ccb *srb,struct us_data *ss) +static int usb_read_capacity(ccb *srb, struct us_data *ss) { int retry; - retry = 3; /* retries */ + /* XXX retries */ + retry = 3; do { - memset(&srb->cmd[0],0,12); - srb->cmd[0]=SCSI_RD_CAPAC; - srb->cmd[1]=srb->lun<<5; - srb->datalen=8; - srb->cmdlen=12; - if(ss->transport(srb,ss)==USB_STOR_TRANSPORT_GOOD) { + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_RD_CAPAC; + srb->cmd[1] = srb->lun << 5; + srb->datalen = 8; + srb->cmdlen = 12; + if (ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD) return 0; - } - } while(retry--); + } while (retry--); return -1; } -static int usb_read_10(ccb *srb,struct us_data *ss, unsigned long start, unsigned short blocks) +static int usb_read_10(ccb *srb, struct us_data *ss, unsigned long start, + unsigned short blocks) { - memset(&srb->cmd[0],0,12); - srb->cmd[0]=SCSI_READ10; - srb->cmd[1]=srb->lun<<5; - srb->cmd[2]=((unsigned char) (start>>24))&0xff; - srb->cmd[3]=((unsigned char) (start>>16))&0xff; - srb->cmd[4]=((unsigned char) (start>>8))&0xff; - srb->cmd[5]=((unsigned char) (start))&0xff; - srb->cmd[7]=((unsigned char) (blocks>>8))&0xff; - srb->cmd[8]=(unsigned char) blocks & 0xff; - srb->cmdlen=12; - USB_STOR_PRINTF("read10: start %lx blocks %x\n",start,blocks); - return ss->transport(srb,ss); + memset(&srb->cmd[0], 0, 12); + srb->cmd[0] = SCSI_READ10; + srb->cmd[1] = srb->lun << 5; + srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff; + srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff; + srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff; + srb->cmd[5] = ((unsigned char) (start)) & 0xff; + srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff; + srb->cmd[8] = (unsigned char) blocks & 0xff; + srb->cmdlen = 12; + USB_STOR_PRINTF("read10: start %lx blocks %x\n", start, blocks); + return ss->transport(srb, ss); } @@ -933,85 +986,94 @@ static void usb_bin_fixup(struct usb_device_descriptor descriptor, const unsigned char max_vendor_len = 40; const unsigned char max_product_len = 20; if (descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a) { - strncpy ((char *)vendor, "SMSC", max_vendor_len); - strncpy ((char *)product, "Flash Media Cntrller", max_product_len); + strncpy((char *)vendor, "SMSC", max_vendor_len); + strncpy((char *)product, "Flash Media Cntrller", + max_product_len); } } #endif /* CONFIG_USB_BIN_FIXUP */ #define USB_MAX_READ_BLK 20 -unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer) +unsigned long usb_stor_read(int device, unsigned long blknr, + unsigned long blkcnt, void *buffer) { - unsigned long start,blks, buf_addr; + unsigned long start, blks, buf_addr; unsigned short smallblks; struct usb_device *dev; - int retry,i; + int retry, i; ccb *srb = &usb_ccb; if (blkcnt == 0) return 0; device &= 0xff; - /* Setup device - */ - USB_STOR_PRINTF("\nusb_read: dev %d \n",device); - dev=NULL; - for(i=0;i<USB_MAX_DEVICE;i++) { - dev=usb_get_dev_index(i); - if(dev==NULL) { + /* Setup device */ + USB_STOR_PRINTF("\nusb_read: dev %d \n", device); + dev = NULL; + for (i = 0; i < USB_MAX_DEVICE; i++) { + dev = usb_get_dev_index(i); + if (dev == NULL) return 0; - } - if(dev->devnum==usb_dev_desc[device].target) + if (dev->devnum == usb_dev_desc[device].target) break; } usb_disable_asynch(1); /* asynch transfer not allowed */ - srb->lun=usb_dev_desc[device].lun; - buf_addr=(unsigned long)buffer; - start=blknr; - blks=blkcnt; - if(usb_test_unit_ready(srb,(struct us_data *)dev->privptr)) { - printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n", - srb->sense_buf[2],srb->sense_buf[12],srb->sense_buf[13]); + srb->lun = usb_dev_desc[device].lun; + buf_addr = (unsigned long)buffer; + start = blknr; + blks = blkcnt; + if (usb_test_unit_ready(srb, (struct us_data *)dev->privptr)) { + printf("Device NOT ready\n Request Sense returned %02X %02X" + " %02X\n", srb->sense_buf[2], srb->sense_buf[12], + srb->sense_buf[13]); return 0; } - USB_STOR_PRINTF("\nusb_read: dev %d startblk %lx, blccnt %lx buffer %lx\n",device,start,blks, buf_addr); + + USB_STOR_PRINTF("\nusb_read: dev %d startblk %lx, blccnt %lx" + " buffer %lx\n", device, start, blks, buf_addr); + do { - retry=2; - srb->pdata=(unsigned char *)buf_addr; - if(blks>USB_MAX_READ_BLK) { - smallblks=USB_MAX_READ_BLK; - } else { - smallblks=(unsigned short) blks; - } + /* XXX need some comment here */ + retry = 2; + srb->pdata = (unsigned char *)buf_addr; + if (blks > USB_MAX_READ_BLK) + smallblks = USB_MAX_READ_BLK; + else + smallblks = (unsigned short) blks; retry_it: - if(smallblks==USB_MAX_READ_BLK) + if (smallblks == USB_MAX_READ_BLK) usb_show_progress(); - srb->datalen=usb_dev_desc[device].blksz * smallblks; - srb->pdata=(unsigned char *)buf_addr; - if(usb_read_10(srb,(struct us_data *)dev->privptr, start, smallblks)) { + srb->datalen = usb_dev_desc[device].blksz * smallblks; + srb->pdata = (unsigned char *)buf_addr; + if (usb_read_10(srb, (struct us_data *)dev->privptr, start, + smallblks)) { USB_STOR_PRINTF("Read ERROR\n"); - usb_request_sense(srb,(struct us_data *)dev->privptr); - if(retry--) + usb_request_sense(srb, (struct us_data *)dev->privptr); + if (retry--) goto retry_it; - blkcnt-=blks; + blkcnt -= blks; break; } - start+=smallblks; - blks-=smallblks; - buf_addr+=srb->datalen; - } while(blks!=0); - USB_STOR_PRINTF("usb_read: end startblk %lx, blccnt %x buffer %lx\n",start,smallblks,buf_addr); + start += smallblks; + blks -= smallblks; + buf_addr += srb->datalen; + } while (blks != 0); + + USB_STOR_PRINTF("usb_read: end startblk %lx, blccnt %x buffer %lx\n", + start, smallblks, buf_addr); + usb_disable_asynch(0); /* asynch transfer allowed */ - if(blkcnt>=USB_MAX_READ_BLK) + if (blkcnt >= USB_MAX_READ_BLK) printf("\n"); - return(blkcnt); + return blkcnt; } /* Probe to see if a new device is actually a Storage device */ -int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data *ss) +int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, + struct us_data *ss) { struct usb_interface_descriptor *iface; int i; @@ -1025,8 +1087,11 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data #if 0 /* this is the place to patch some storage devices */ - USB_STOR_PRINTF("iVendor %X iProduct %X\n",dev->descriptor.idVendor,dev->descriptor.idProduct); - if ((dev->descriptor.idVendor) == 0x066b && (dev->descriptor.idProduct) == 0x0103) { + USB_STOR_PRINTF("iVendor %X iProduct %X\n", dev->descriptor.idVendor, + dev->descriptor.idProduct); + + if ((dev->descriptor.idVendor) == 0x066b && + (dev->descriptor.idProduct) == 0x0103) { USB_STOR_PRINTF("patched for E-USB\n"); protocol = US_PR_CB; subclass = US_SC_UFI; /* an assumption */ @@ -1095,19 +1160,20 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data */ for (i = 0; i < iface->bNumEndpoints; i++) { /* is it an BULK endpoint? */ - if ((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) - == USB_ENDPOINT_XFER_BULK) { + if ((iface->ep_desc[i].bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN) ss->ep_in = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; else - ss->ep_out = iface->ep_desc[i].bEndpointAddress & + ss->ep_out = + iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; } /* is it an interrupt endpoint? */ - if ((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) - == USB_ENDPOINT_XFER_INT) { + if ((iface->ep_desc[i].bmAttributes & + USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) { ss->ep_int = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; ss->irqinterval = iface->ep_desc[i].bInterval; @@ -1130,26 +1196,28 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,struct us_data */ if (ss->subclass != US_SC_UFI && ss->subclass != US_SC_SCSI && ss->subclass != US_SC_8070) { - printf("Sorry, protocol %d not yet supported.\n",ss->subclass); + printf("Sorry, protocol %d not yet supported.\n", ss->subclass); return 0; } - if(ss->ep_int) { /* we had found an interrupt endpoint, prepare irq pipe */ - /* set up the IRQ pipe and handler */ - + if (ss->ep_int) { + /* we had found an interrupt endpoint, prepare irq pipe + * set up the IRQ pipe and handler + */ ss->irqinterval = (ss->irqinterval > 0) ? ss->irqinterval : 255; ss->irqpipe = usb_rcvintpipe(ss->pusb_dev, ss->ep_int); ss->irqmaxp = usb_maxpacket(dev, ss->irqpipe); - dev->irq_handle=usb_stor_irq; + dev->irq_handle = usb_stor_irq; } - dev->privptr=(void *)ss; + dev->privptr = (void *)ss; return 1; } -int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t *dev_desc) +int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, + block_dev_desc_t *dev_desc) { - unsigned char perq,modi; + unsigned char perq, modi; unsigned long cap[2]; - unsigned long *capacity,*blksz; + unsigned long *capacity, *blksz; ccb *pccb = &usb_ccb; /* for some reasons a couple of devices would not survive this reset */ @@ -1157,7 +1225,6 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t /* Sony USM256E */ (dev->descriptor.idVendor == 0x054c && dev->descriptor.idProduct == 0x019e) - || /* USB007 Mini-USB2 Flash Drive */ (dev->descriptor.idVendor == 0x066f && @@ -1166,6 +1233,13 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t /* SanDisk Corporation Cruzer Micro 20044318410546613953 */ (dev->descriptor.idVendor == 0x0781 && dev->descriptor.idProduct == 0x5151) + || + /* + * SanDisk Corporation U3 Cruzer Micro 1/4GB + * Flash Drive 000016244373FFB4 + */ + (dev->descriptor.idVendor == 0x0781 && + dev->descriptor.idProduct == 0x5406) ) USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n"); else @@ -1175,17 +1249,20 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t dev_desc->target = dev->devnum; pccb->lun = dev_desc->lun; - USB_STOR_PRINTF(" address %d\n",dev_desc->target); + USB_STOR_PRINTF(" address %d\n", dev_desc->target); - if(usb_inquiry(pccb,ss)) + if (usb_inquiry(pccb, ss)) return -1; perq = usb_stor_buf[0]; modi = usb_stor_buf[1]; - if((perq & 0x1f) == 0x1f) { - return 0; /* skip unknown devices */ + + if ((perq & 0x1f) == 0x1f) { + /* skip unknown devices */ + return 0; } - if((modi&0x80) == 0x80) {/* drive is removable */ + if ((modi&0x80) == 0x80) { + /* drive is removable */ dev_desc->removable = 1; } memcpy(&dev_desc->vendor[0], &usb_stor_buf[8], 8); @@ -1195,29 +1272,34 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t dev_desc->product[16] = 0; dev_desc->revision[4] = 0; #ifdef CONFIG_USB_BIN_FIXUP - usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product); + usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, + (uchar *)dev_desc->product); #endif /* CONFIG_USB_BIN_FIXUP */ - USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n",usb_stor_buf[2],usb_stor_buf[3]); - if(usb_test_unit_ready(pccb,ss)) { - printf("Device NOT ready\n Request Sense returned %02X %02X %02X\n",pccb->sense_buf[2],pccb->sense_buf[12],pccb->sense_buf[13]); - if(dev_desc->removable == 1) { + USB_STOR_PRINTF("ISO Vers %X, Response Data %X\n", usb_stor_buf[2], + usb_stor_buf[3]); + if (usb_test_unit_ready(pccb, ss)) { + printf("Device NOT ready\n" + " Request Sense returned %02X %02X %02X\n", + pccb->sense_buf[2], pccb->sense_buf[12], + pccb->sense_buf[13]); + if (dev_desc->removable == 1) { dev_desc->type = perq; return 1; } - else - return 0; + return 0; } pccb->pdata = (unsigned char *)&cap[0]; - memset(pccb->pdata,0,8); - if(usb_read_capacity(pccb,ss) != 0) { + memset(pccb->pdata, 0, 8); + if (usb_read_capacity(pccb, ss) != 0) { printf("READ_CAP ERROR\n"); cap[0] = 2880; cap[1] = 0x200; } - USB_STOR_PRINTF("Read Capacity returns: 0x%lx, 0x%lx\n",cap[0],cap[1]); + USB_STOR_PRINTF("Read Capacity returns: 0x%lx, 0x%lx\n", cap[0], + cap[1]); #if 0 - if(cap[0]>(0x200000 * 10)) /* greater than 10 GByte */ - cap[0]>>=16; + if (cap[0] > (0x200000 * 10)) /* greater than 10 GByte */ + cap[0] >>= 16; #endif cap[0] = cpu_to_be32(cap[0]); cap[1] = cpu_to_be32(cap[1]); @@ -1226,15 +1308,16 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t cap[0] += 1; capacity = &cap[0]; blksz = &cap[1]; - USB_STOR_PRINTF("Capacity = 0x%lx, blocksz = 0x%lx\n",*capacity,*blksz); + USB_STOR_PRINTF("Capacity = 0x%lx, blocksz = 0x%lx\n", + *capacity, *blksz); dev_desc->lba = *capacity; dev_desc->blksz = *blksz; dev_desc->type = perq; - USB_STOR_PRINTF(" address %d\n",dev_desc->target); - USB_STOR_PRINTF("partype: %d\n",dev_desc->part_type); + USB_STOR_PRINTF(" address %d\n", dev_desc->target); + USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type); init_part(dev_desc); - USB_STOR_PRINTF("partype: %d\n",dev_desc->part_type); + USB_STOR_PRINTF("partype: %d\n", dev_desc->part_type); return 1; } diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 641f27049..9cbd47767 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -29,9 +29,7 @@ */ /* * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices + * 1 - this driver is intended for use with USB Mass Storage Devices * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! */ diff --git a/cpu/blackfin/Makefile b/cpu/blackfin/Makefile index 8fed4b422..b4049ff87 100644 --- a/cpu/blackfin/Makefile +++ b/cpu/blackfin/Makefile @@ -17,14 +17,15 @@ EXTRA := CEXTRA := initcode.o SEXTRA := start.o SOBJS := interrupt.o cache.o -COBJS := cpu.o traps.o interrupts.o reset.o serial.o i2c.o watchdog.o +COBJS-y := cpu.o traps.o interrupts.o reset.o serial.o watchdog.o +COBJS-$(CONFIG_JTAG_CONSOLE) += jtag-console.o ifeq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) -COBJS += initcode.o +COBJS-y += initcode.o endif -SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) EXTRA := $(addprefix $(obj),$(EXTRA)) CEXTRA := $(addprefix $(obj),$(CEXTRA)) SEXTRA := $(addprefix $(obj),$(SEXTRA)) diff --git a/cpu/blackfin/cache.S b/cpu/blackfin/cache.S index 51bdb30e3..9facadfd1 100644 --- a/cpu/blackfin/cache.S +++ b/cpu/blackfin/cache.S @@ -39,7 +39,7 @@ ENTRY(_blackfin_dcache_flush_range) RTS; ENDPROC(_blackfin_dcache_flush_range) -ENTRY(_blackfin_dcache_invalidate_range) +ENTRY(_blackfin_dcache_flush_invalidate_range) R2 = -32; R2 = R0 & R2; P0 = R2; @@ -58,4 +58,4 @@ ENTRY(_blackfin_dcache_invalidate_range) FLUSHINV[P0]; SSYNC; RTS; -ENDPROC(_blackfin_dcache_invalidate_range) +ENDPROC(_blackfin_dcache_flush_invalidate_range) diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c index 9efd88e7e..30c214be7 100644 --- a/cpu/blackfin/cpu.c +++ b/cpu/blackfin/cpu.c @@ -14,11 +14,14 @@ #include <asm/blackfin.h> #include <asm/cplb.h> #include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/ebiu.h> #include <asm/mach-common/bits/trace.h> #include "cpu.h" #include "serial.h" +ulong bfin_poweron_retx; + __attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { @@ -48,6 +51,9 @@ void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); #endif + /* Save RETX so we can pass it while booting Linux */ + bfin_poweron_retx = bootflag; + #ifdef CONFIG_DEBUG_DUMP /* Turn on hardware trace buffer */ bfin_write_TBUFCTL(TBUFPWR | TBUFEN); diff --git a/cpu/blackfin/i2c.c b/cpu/blackfin/i2c.c deleted file mode 100644 index 2a3e2238c..000000000 --- a/cpu/blackfin/i2c.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - * i2c.c - driver for Blackfin on-chip TWI/I2C - * - * Copyright (c) 2006-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include <common.h> - -#ifdef CONFIG_HARD_I2C - -#include <asm/blackfin.h> -#include <i2c.h> -#include <asm/io.h> -#include <asm/mach-common/bits/twi.h> - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#ifdef TWI0_CLKDIV -#define bfin_read_TWI_CLKDIV() bfin_read_TWI0_CLKDIV() -#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) -#define bfin_read_TWI_CONTROL() bfin_read_TWI0_CONTROL() -#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read_TWI0_SLAVE_CTL() -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write_TWI0_SLAVE_CTL(val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read_TWI0_SLAVE_STAT() -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write_TWI0_SLAVE_STAT(val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read_TWI0_SLAVE_ADDR() -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write_TWI0_SLAVE_ADDR(val) -#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL() -#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val) -#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT() -#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read_TWI0_MASTER_ADDR() -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) -#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT() -#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val) -#define bfin_read_TWI_INT_MASK() bfin_read_TWI0_INT_MASK() -#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val) -#define bfin_read_TWI_FIFO_CTL() bfin_read_TWI0_FIFO_CTL() -#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val) -#define bfin_read_TWI_FIFO_STAT() bfin_read_TWI0_FIFO_STAT() -#define bfin_write_TWI_FIFO_STAT(val) bfin_write_TWI0_FIFO_STAT(val) -#define bfin_read_TWI_XMT_DATA8() bfin_read_TWI0_XMT_DATA8() -#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val) -#define bfin_read_TWI_XMT_DATA_16() bfin_read_TWI0_XMT_DATA16() -#define bfin_write_TWI_XMT_DATA16(val) bfin_write_TWI0_XMT_DATA16(val) -#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8() -#define bfin_write_TWI_RCV_DATA8(val) bfin_write_TWI0_RCV_DATA8(val) -#define bfin_read_TWI_RCV_DATA16() bfin_read_TWI0_RCV_DATA16() -#define bfin_write_TWI_RCV_DATA16(val) bfin_write_TWI0_RCV_DATA16(val) -#endif - -#ifdef DEBUG_I2C -#define PRINTD(fmt,args...) do { \ - DECLARE_GLOBAL_DATA_PTR; \ - if (gd->have_console) \ - printf(fmt ,##args); \ - } while (0) -#else -#define PRINTD(fmt,args...) -#endif - -#ifndef CONFIG_TWICLK_KHZ -#define CONFIG_TWICLK_KHZ 50 -#endif - -/* All transfers are described by this data structure */ -struct i2c_msg { - u16 addr; /* slave address */ - u16 flags; -#define I2C_M_STOP 0x2 -#define I2C_M_RD 0x1 - u16 len; /* msg length */ - u8 *buf; /* pointer to msg data */ -}; - -/** - * i2c_reset: - reset the host controller - */ -static void i2c_reset(void) -{ - /* Disable TWI */ - bfin_write_TWI_CONTROL(0); - SSYNC(); - - /* Set TWI internal clock as 10MHz */ - bfin_write_TWI_CONTROL(((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F); - - /* Set Twi interface clock as specified */ - if (CONFIG_TWICLK_KHZ > 400) - bfin_write_TWI_CLKDIV(((5 * 1024 / 400) << 8) | ((5 * 1024 / - 400) & 0xFF)); - else - bfin_write_TWI_CLKDIV(((5 * 1024 / - CONFIG_TWICLK_KHZ) << 8) | ((5 * 1024 / - CONFIG_TWICLK_KHZ) - & 0xFF)); - - /* Enable TWI */ - bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); - SSYNC(); -} - -int wait_for_completion(struct i2c_msg *msg, int timeout_count) -{ - unsigned short twi_int_stat; - unsigned short mast_stat; - int i; - - for (i = 0; i < timeout_count; i++) { - twi_int_stat = bfin_read_TWI_INT_STAT(); - mast_stat = bfin_read_TWI_MASTER_STAT(); - - if (XMTSERV & twi_int_stat) { - /* Transmit next data */ - if (msg->len > 0) { - bfin_write_TWI_XMT_DATA8(*(msg->buf++)); - msg->len--; - } else if (msg->flags & I2C_M_STOP) - bfin_write_TWI_MASTER_CTL - (bfin_read_TWI_MASTER_CTL() | STOP); - SSYNC(); - /* Clear status */ - bfin_write_TWI_INT_STAT(XMTSERV); - SSYNC(); - i = 0; - } - if (RCVSERV & twi_int_stat) { - if (msg->len > 0) { - /* Receive next data */ - *(msg->buf++) = bfin_read_TWI_RCV_DATA8(); - msg->len--; - } else if (msg->flags & I2C_M_STOP) { - bfin_write_TWI_MASTER_CTL - (bfin_read_TWI_MASTER_CTL() | STOP); - SSYNC(); - } - /* Clear interrupt source */ - bfin_write_TWI_INT_STAT(RCVSERV); - SSYNC(); - i = 0; - } - if (MERR & twi_int_stat) { - bfin_write_TWI_INT_STAT(MERR); - bfin_write_TWI_INT_MASK(0); - bfin_write_TWI_MASTER_STAT(0x3e); - bfin_write_TWI_MASTER_CTL(0); - SSYNC(); - /* - * if both err and complete int stats are set, - * return proper results. - */ - if (MCOMP & twi_int_stat) { - bfin_write_TWI_INT_STAT(MCOMP); - bfin_write_TWI_INT_MASK(0); - bfin_write_TWI_MASTER_CTL(0); - SSYNC(); - /* - * If it is a quick transfer, - * only address bug no data, not an err. - */ - if (msg->len == 0 && mast_stat & BUFRDERR) - return 0; - /* - * If address not acknowledged return -3, - * else return 0. - */ - else if (!(mast_stat & ANAK)) - return 0; - else - return -3; - } - return -1; - } - if (MCOMP & twi_int_stat) { - bfin_write_TWI_INT_STAT(MCOMP); - SSYNC(); - bfin_write_TWI_INT_MASK(0); - bfin_write_TWI_MASTER_CTL(0); - SSYNC(); - return 0; - } - } - if (msg->flags & I2C_M_RD) - return -4; - else - return -2; -} - -/** - * i2c_transfer: - Transfer one byte over the i2c bus - * - * This function can tranfer a byte over the i2c bus in both directions. - * It is used by the public API functions. - * - * @return: 0: transfer successful - * -1: transfer fail - * -2: transmit timeout - * -3: ACK missing - * -4: receive timeout - * -5: controller not ready - */ -int i2c_transfer(struct i2c_msg *msg) -{ - int ret = 0; - int timeout_count = 10000; - int len = msg->len; - - if (!(bfin_read_TWI_CONTROL() & TWI_ENA)) { - ret = -5; - goto transfer_error; - } - - while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) - continue; - - /* Set Transmit device address */ - bfin_write_TWI_MASTER_ADDR(msg->addr); - - /* - * FIFO Initiation. - * Data in FIFO should be discarded before start a new operation. - */ - bfin_write_TWI_FIFO_CTL(0x3); - SSYNC(); - bfin_write_TWI_FIFO_CTL(0); - SSYNC(); - - if (!(msg->flags & I2C_M_RD)) { - /* Transmit first data */ - if (msg->len > 0) { - PRINTD("1 in i2c_transfer: buf=%d, len=%d\n", *msg->buf, - len); - bfin_write_TWI_XMT_DATA8(*(msg->buf++)); - msg->len--; - SSYNC(); - } - } - - /* clear int stat */ - bfin_write_TWI_INT_STAT(MERR | MCOMP | XMTSERV | RCVSERV); - - /* Interrupt mask . Enable XMT, RCV interrupt */ - bfin_write_TWI_INT_MASK(MCOMP | MERR | - ((msg->flags & I2C_M_RD) ? RCVSERV : XMTSERV)); - SSYNC(); - - if (len > 0 && len <= 255) - bfin_write_TWI_MASTER_CTL((len << 6)); - else if (msg->len > 255) { - bfin_write_TWI_MASTER_CTL((0xff << 6)); - msg->flags &= I2C_M_STOP; - } else - bfin_write_TWI_MASTER_CTL(0); - - /* Master enable */ - bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | MEN | - ((msg->flags & I2C_M_RD) - ? MDIR : 0) | ((CONFIG_TWICLK_KHZ > - 100) ? FAST : 0)); - SSYNC(); - - ret = wait_for_completion(msg, timeout_count); - PRINTD("3 in i2c_transfer: ret=%d\n", ret); - - transfer_error: - switch (ret) { - case 1: - PRINTD(("i2c_transfer: error: transfer fail\n")); - break; - case 2: - PRINTD(("i2c_transfer: error: transmit timeout\n")); - break; - case 3: - PRINTD(("i2c_transfer: error: ACK missing\n")); - break; - case 4: - PRINTD(("i2c_transfer: error: receive timeout\n")); - break; - case 5: - PRINTD(("i2c_transfer: error: controller not ready\n")); - i2c_reset(); - break; - default: - break; - } - return ret; - -} - -/* ---------------------------------------------------------------------*/ -/* API Functions */ -/* ---------------------------------------------------------------------*/ - -void i2c_init(int speed, int slaveaddr) -{ - i2c_reset(); -} - -/** - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ - -int i2c_probe(uchar chip) -{ - struct i2c_msg msg; - u8 probebuf; - - i2c_reset(); - - probebuf = 0; - msg.addr = chip; - msg.flags = 0; - msg.len = 1; - msg.buf = &probebuf; - if (i2c_transfer(&msg)) - return -1; - - msg.addr = chip; - msg.flags = I2C_M_RD; - msg.len = 1; - msg.buf = &probebuf; - if (i2c_transfer(&msg)) - return -1; - - return 0; -} - -/** - * i2c_read: - Read multiple bytes from an i2c device - * - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - - PRINTD("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x\n", chip, - addr, alen, len); - - if (alen > 0) { - addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF); - msg.addr = chip; - msg.flags = 0; - msg.len = alen; - msg.buf = addr_bytes; - if (i2c_transfer(&msg)) - return -1; - } - - /* start read sequence */ - PRINTD(("i2c_read: start read sequence\n")); - msg.addr = chip; - msg.flags = I2C_M_RD; - msg.len = len; - msg.buf = buffer; - if (i2c_transfer(&msg)) - return -1; - - return 0; -} - -/** - * i2c_write: - Write multiple bytes to an i2c device - * - * chip: I2C chip address, range 0..127 - * addr: Memory (register) address within the chip - * alen: Number of bytes to use for addr (typically 1, 2 for larger - * memories, 0 for register type devices with only one - * register) - * buffer: Where to read/write the data - * len: How many bytes to read/write - * - * Returns: 0 on success, not 0 on failure - */ - -int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - struct i2c_msg msg; - u8 addr_bytes[3]; /* lowest...highest byte of data address */ - - PRINTD - ("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x, len=0x%x, buf0=0x%x\n", - chip, addr, alen, len, buffer[0]); - - /* chip address write */ - if (alen > 0) { - addr_bytes[0] = (u8) ((addr >> 0) & 0x000000FF); - addr_bytes[1] = (u8) ((addr >> 8) & 0x000000FF); - addr_bytes[2] = (u8) ((addr >> 16) & 0x000000FF); - msg.addr = chip; - msg.flags = 0; - msg.len = alen; - msg.buf = addr_bytes; - if (i2c_transfer(&msg)) - return -1; - } - - /* start read sequence */ - PRINTD(("i2c_write: start write sequence\n")); - msg.addr = chip; - msg.flags = 0; - msg.len = len; - msg.buf = buffer; - if (i2c_transfer(&msg)) - return -1; - - return 0; - -} - -#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index ffc8420f1..e733dd20f 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -158,7 +158,7 @@ static inline void serial_putc(char c) #endif #ifndef CONFIG_PLL_CTL_VAL -# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9)) +# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF) #endif #ifndef CONFIG_EBIU_RSTCTL_VAL diff --git a/cpu/blackfin/jtag-console.c b/cpu/blackfin/jtag-console.c new file mode 100644 index 000000000..44c0a839e --- /dev/null +++ b/cpu/blackfin/jtag-console.c @@ -0,0 +1,125 @@ +/* + * jtag-console.c - console driver over Blackfin JTAG + * + * Copyright (c) 2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <devices.h> +#include <asm/blackfin.h> + +#ifndef CONFIG_JTAG_CONSOLE_TIMEOUT +# define CONFIG_JTAG_CONSOLE_TIMEOUT 100 +#endif + +/* The Blackfin tends to be much much faster than the JTAG hardware. */ +static void jtag_write_emudat(uint32_t emudat) +{ + static bool overflowed = false; + ulong timeout = get_timer(0) + CONFIG_JTAG_CONSOLE_TIMEOUT; + while (bfin_read_DBGSTAT() & 0x1) { + if (overflowed) + return; + if (timeout < get_timer(0)) + overflowed = true; + } + overflowed = false; + __asm__ __volatile__("emudat = %0;" : : "d"(emudat)); +} +/* Transmit a buffer. The format is: + * [32bit length][actual data] + */ +static void jtag_send(const char *c, uint32_t len) +{ + uint32_t i; + + if (len == 0) + return; + + /* First send the length */ + jtag_write_emudat(len); + + /* Then send the data */ + for (i = 0; i < len; i += 4) + jtag_write_emudat((c[i] << 0) | (c[i+1] << 8) | (c[i+2] << 16) | (c[i+3] << 24)); +} +static void jtag_putc(const char c) +{ + jtag_send(&c, 1); +} +static void jtag_puts(const char *s) +{ + jtag_send(s, strlen(s)); +} + +static int jtag_tstc(void) +{ + return (bfin_read_DBGSTAT() & 0x2); +} + +/* Receive a buffer. The format is: + * [32bit length][actual data] + */ +static size_t inbound_len; +static int leftovers_len; +static uint32_t leftovers; +static int jtag_getc(void) +{ + int ret; + uint32_t emudat; + + /* see if any data is left over */ + if (leftovers_len) { + --leftovers_len; + ret = leftovers & 0xff; + leftovers >>= 8; + return ret; + } + + /* wait for new data ! */ + while (!jtag_tstc()) + continue; + __asm__("%0 = emudat;" : "=d"(emudat)); + + if (inbound_len == 0) { + /* grab the length */ + inbound_len = emudat; + } else { + /* store the bytes */ + leftovers_len = min(4, inbound_len); + inbound_len -= leftovers_len; + leftovers = emudat; + } + + return jtag_getc(); +} + +int drv_jtag_console_init(void) +{ + device_t dev; + int ret; + + memset(&dev, 0x00, sizeof(dev)); + strcpy(dev.name, "jtag"); + dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + dev.putc = jtag_putc; + dev.puts = jtag_puts; + dev.tstc = jtag_tstc; + dev.getc = jtag_getc; + + ret = device_register(&dev); + return (ret == 0 ? 1 : ret); +} + +#ifdef CONFIG_UART_CONSOLE_IS_JTAG +/* Since the JTAG is always available (at power on), allow it to fake a UART */ +void serial_set_baud(uint32_t baud) {} +void serial_setbrg(void) {} +int serial_init(void) { return 0; } +void serial_putc(const char c) __attribute__((alias("jtag_putc"))); +void serial_puts(const char *s) __attribute__((alias("jtag_puts"))); +int serial_tstc(void) __attribute__((alias("jtag_tstc"))); +int serial_getc(void) __attribute__((alias("jtag_getc"))); +#endif diff --git a/cpu/blackfin/reset.c b/cpu/blackfin/reset.c index d1e34b3f9..284cea579 100644 --- a/cpu/blackfin/reset.c +++ b/cpu/blackfin/reset.c @@ -29,26 +29,35 @@ void bfin_reset(void) */ __builtin_bfin_ssync(); - while (1) { + /* The bootrom checks to see how it was reset and will + * automatically perform a software reset for us when + * it starts executing after the core reset. + */ + if (ANOMALY_05000353 || ANOMALY_05000386) { /* Initiate System software reset. */ bfin_write_SWRST(0x7); /* Due to the way reset is handled in the hardware, we need - * to delay for 7 SCLKS. The only reliable way to do this is - * to calculate the CCLK/SCLK ratio and multiply 7. For now, + * to delay for 10 SCLKS. The only reliable way to do this is + * to calculate the CCLK/SCLK ratio and multiply 10. For now, * we'll assume worse case which is a 1:15 ratio. */ asm( "LSETUP (1f, 1f) LC0 = %0\n" "1: nop;" : - : "a" (15 * 7) + : "a" (15 * 10) : "LC0", "LB0", "LT0" ); /* Clear System software reset */ bfin_write_SWRST(0); + /* The BF526 ROM will crash during reset */ +#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) + bfin_read_SWRST(); +#endif + /* Wait for the SWRST write to complete. Cannot rely on SSYNC * though as the System state is all reset now. */ @@ -59,10 +68,11 @@ void bfin_reset(void) : "a" (15 * 1) : "LC1", "LB1", "LT1" ); + } + while (1) /* Issue core reset */ asm("raise 1"); - } } /* We need to trampoline ourselves up into L1 since our linker diff --git a/cpu/blackfin/serial.c b/cpu/blackfin/serial.c index 0d6f377c0..42534bd9b 100644 --- a/cpu/blackfin/serial.c +++ b/cpu/blackfin/serial.c @@ -29,6 +29,8 @@ #include <asm/blackfin.h> #include <asm/mach-common/bits/uart.h> +#ifdef CONFIG_UART_CONSOLE + #if defined(UART_LSR) && (CONFIG_UART_CONSOLE != 0) # error CONFIG_UART_CONSOLE must be 0 on parts with only one UART #endif @@ -170,3 +172,5 @@ void serial_puts(const char *s) while (*s) serial_putc(*s++); } + +#endif diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h index ec40c266a..f67109676 100644 --- a/cpu/blackfin/serial.h +++ b/cpu/blackfin/serial.h @@ -14,6 +14,10 @@ #include <asm/blackfin.h> #include <asm/mach-common/bits/uart.h> +#ifndef CONFIG_UART_CONSOLE +# define CONFIG_UART_CONSOLE 0 +#endif + #ifdef CONFIG_DEBUG_EARLY_SERIAL # define BFIN_DEBUG_EARLY_SERIAL 1 #else @@ -95,7 +99,16 @@ __attribute__((always_inline)) static inline void serial_do_portmux(void) { -#ifdef __ADSPBF52x__ +#if defined(__ADSPBF51x__) +# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \ + bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \ + bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); + switch (CONFIG_UART_CONSOLE) { + case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */ + case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */ + } + SSYNC(); +#elif defined(__ADSPBF52x__) # define DO_MUX(port, mux, tx, rx) \ bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \ bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx); diff --git a/cpu/blackfin/start.S b/cpu/blackfin/start.S index 9975a0c62..6c8def481 100644 --- a/cpu/blackfin/start.S +++ b/cpu/blackfin/start.S @@ -125,8 +125,11 @@ ENTRY(_start) */ r6 = 1 (x); - /* Relocate from wherever are (FLASH/RAM/etc...) to the - * hardcoded monitor location in the end of RAM. + /* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded + * monitor location in the end of RAM. We know that memcpy() only + * uses registers, so it is safe to call here. Note that this only + * copies to external memory ... we do not start executing out of + * it yet (see "lower to 15" below). */ serial_early_puts("Relocate"); call _get_pc; @@ -135,27 +138,16 @@ ENTRY(_start) r2.h = .Loffset; r3.l = _start; r3.h = _start; - r1 = r2 - r3; - - r0 = r0 - r1; - - cc = r0 == r3; + r2 = r2 - r3; + r1 = r0 - r2; + cc = r1 == r3; if cc jump .Lnorelocate; - r6 = 0 (x); - p1 = r0; - - p2.l = LO(CONFIG_SYS_MONITOR_BASE); - p2.h = HI(CONFIG_SYS_MONITOR_BASE); - p3 = 0x04; - p4.l = LO(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN); - p4.h = HI(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN); -.Lloop1: - r1 = [p1 ++ p3]; - [p2 ++ p3] = r1; - cc=p2==p4; - if !cc jump .Lloop1; + r0 = r3; + r2.l = LO(CONFIG_SYS_MONITOR_LEN); + r2.h = HI(CONFIG_SYS_MONITOR_LEN); + call _memcpy_ASM; /* Initialize BSS section ... we know that memset() does not * use the BSS, so it is safe to call here. The bootrom LDR @@ -173,9 +165,8 @@ ENTRY(_start) .Lnorelocate: /* Setup the actual stack in external memory */ - r0.h = HI(CONFIG_STACKBASE); - r0.l = LO(CONFIG_STACKBASE); - sp = r0; + sp.h = HI(CONFIG_STACKBASE); + sp.l = LO(CONFIG_STACKBASE); fp = sp; /* Now lower ourselves from the highest interrupt level to @@ -183,7 +174,9 @@ ENTRY(_start) * setting the 15 handler to ".Lenable_nested", raising the 15 * interrupt, and then returning from the highest interrupt * level to the dummy "jump" until the interrupt controller - * services the pending 15 interrupt. + * services the pending 15 interrupt. If executing out of + * flash, these steps also changes the code flow from flash + * to external memory. */ serial_early_puts("Lower to 15"); r0 = r7; diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c index d17c0a195..a2c6f1ece 100644 --- a/cpu/blackfin/traps.c +++ b/cpu/blackfin/traps.c @@ -111,23 +111,12 @@ void trap_c(struct pt_regs *regs) } if (i == ARRAY_SIZE(bfin_memory_map)) { printf("%cCPLB exception outside of memory map at 0x%p\n", - (data ? 'D' : 'I'), new_cplb_addr); + (data ? 'D' : 'I'), (void *)new_cplb_addr); bfin_panic(regs); } else debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end); new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags); - /* Turn the cache off */ - SSYNC(); - if (data) { - asm(" .align 8; "); - *pDMEM_CONTROL &= ~ENDCPLB; - } else { - asm(" .align 8; "); - *pIMEM_CONTROL &= ~ENICPLB; - } - SSYNC(); - if (data) { CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0; CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0; @@ -149,8 +138,17 @@ void trap_c(struct pt_regs *regs) debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA); last_evicted = i + 1; + + /* need to turn off cplbs whenever we muck with the cplb table */ +#if ENDCPLB != ENICPLB +# error cplb enable bit violates my sanity +#endif + uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL); + bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB); *CPLB_ADDR = new_cplb_addr; *CPLB_DATA = new_cplb_data; + bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB); + SSYNC(); /* dump current table for debugging purposes */ CPLB_ADDR = CPLB_ADDR_BASE; @@ -158,17 +156,6 @@ void trap_c(struct pt_regs *regs) for (i = 0; i < 16; ++i) debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++); - /* Turn the cache back on */ - SSYNC(); - if (data) { - asm(" .align 8; "); - *pDMEM_CONTROL |= ENDCPLB; - } else { - asm(" .align 8; "); - *pIMEM_CONTROL |= ENICPLB; - } - SSYNC(); - break; } @@ -220,20 +207,21 @@ static const char *symbol_lookup(unsigned long addr, unsigned long *caddr) static void decode_address(char *buf, unsigned long address) { unsigned long sym_addr; + void *paddr = (void *)address; const char *sym = symbol_lookup(address, &sym_addr); if (sym) { - sprintf(buf, "<0x%p> { %s + 0x%x }", address, sym, address - sym_addr); + sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr); return; } if (!address) - sprintf(buf, "<0x%p> /* Maybe null pointer? */", address); + sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr); else if (address >= CONFIG_SYS_MONITOR_BASE && address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - sprintf(buf, "<0x%p> /* somewhere in u-boot */", address); + sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr); else - sprintf(buf, "<0x%p> /* unknown address */", address); + sprintf(buf, "<0x%p> /* unknown address */", paddr); } static char *strhwerrcause(uint16_t hwerrcause) @@ -273,7 +261,7 @@ static char *strexcause(uint16_t excause) void dump(struct pt_regs *fp) { char buf[150]; - size_t i; + int i; uint16_t hwerrcause, excause; if (!ENABLE_DUMP) @@ -288,8 +276,8 @@ void dump(struct pt_regs *fp) printf("SEQUENCER STATUS:\n"); printf(" SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n", fp->seqstat, fp->ipend, fp->syscfg); - printf(" HWERRCAUSE: 0x%lx: %s\n", hwerrcause, strhwerrcause(hwerrcause)); - printf(" EXCAUSE : 0x%lx: %s\n", excause, strexcause(excause)); + printf(" HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause)); + printf(" EXCAUSE : 0x%x: %s\n", excause, strexcause(excause)); for (i = 6; i <= 15; ++i) { if (fp->ipend & (1 << i)) { decode_address(buf, bfin_read32(EVT0 + 4*i)); @@ -323,7 +311,7 @@ void dump(struct pt_regs *fp) printf(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n", fp->p0, fp->p1, fp->p2, fp->p3); printf(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n", - fp->p4, fp->p5, fp->fp, fp); + fp->p4, fp->p5, fp->fp, (unsigned long)fp); printf(" LB0: %08lx LT0: %08lx LC0: %08lx\n", fp->lb0, fp->lt0, fp->lc0); printf(" LB1: %08lx LT1: %08lx LC1: %08lx\n", @@ -349,7 +337,7 @@ void dump_bfin_trace_buffer(void) { char buf[150]; unsigned long tflags; - size_t i = 0; + int i = 0; if (!ENABLE_DUMP) return; diff --git a/cpu/mips/au1x00_usb_ohci.c b/cpu/mips/au1x00_usb_ohci.c index 17489da8d..ea02efbb0 100644 --- a/cpu/mips/au1x00_usb_ohci.c +++ b/cpu/mips/au1x00_usb_ohci.c @@ -27,9 +27,7 @@ */ /* * IMPORTANT NOTES - * 1 - you MUST define LITTLEENDIAN in the configuration file for the - * board or this driver will NOT work! - * 2 - this driver is intended for use with USB Mass Storage Devices + * 1 - this driver is intended for use with USB Mass Storage Devices * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes! */ @@ -56,7 +54,7 @@ #define USBH_ENABLE_CE (1<<3) #define USBH_ENABLE_RD (1<<4) -#ifdef LITTLEENDIAN +#ifdef __LITTLE_ENDIAN #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C) #else #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE) diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index b7180b0c6..d5a16047d 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -65,6 +65,34 @@ void flush_cache(ulong start_addr, ulong size) } } +void flush_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + +void invalidate_dcache_range(ulong start_addr, ulong stop) +{ + unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (stop - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Invalidate_D, addr); + if (addr == aend) + break; + addr += lsize; + } +} + void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) { write_c0_entrylo0(low0); diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 542bf21c7..5992111c1 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -137,7 +137,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(clocks, 1, 0, do_clocks, - "clocks - print clock configuration\n", + "print clock configuration", " clocks\n" ); diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c index f1be485e8..c969ff65e 100644 --- a/cpu/mpc8260/bedbug_603e.c +++ b/cpu/mpc8260/bedbug_603e.c @@ -72,7 +72,7 @@ void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } @@ -119,7 +119,7 @@ void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc, (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) || (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' )))) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } diff --git a/cpu/mpc83xx/ecc.c b/cpu/mpc83xx/ecc.c index 5ab169fe3..f3942b411 100644 --- a/cpu/mpc83xx/ecc.c +++ b/cpu/mpc83xx/ecc.c @@ -119,7 +119,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) writeback[1] = 0x89abcdefUL; if (argc > 4) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -350,12 +350,12 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } } - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD(ecc, 4, 0, do_ecc, - "ecc - support for DDR ECC features\n", + "support for DDR ECC features", "status - print out status info\n" "ecc captureclear - clear capture regs data\n" "ecc sbecnt <val> - set Single-Bit Error counter\n" diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c index 4230099c0..9b7e7b576 100644 --- a/cpu/mpc83xx/speed.c +++ b/cpu/mpc83xx/speed.c @@ -544,6 +544,6 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(clocks, 1, 0, do_clocks, - "clocks - print clock configuration\n", + "print clock configuration", " clocks\n" ); diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c index 5d5236639..0308bbbf7 100644 --- a/cpu/mpc8xx/bedbug_860.c +++ b/cpu/mpc8xx/bedbug_860.c @@ -71,7 +71,7 @@ void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } @@ -122,7 +122,7 @@ void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc, if( !isdigit( argv[ 1 ][ 0 ])) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } diff --git a/cpu/nios2/sysid.c b/cpu/nios2/sysid.c index afd5d83d9..251204beb 100644 --- a/cpu/nios2/sysid.c +++ b/cpu/nios2/sysid.c @@ -52,7 +52,7 @@ int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sysid, 1, 1, do_sysid, - "sysid - display Nios-II system id\n\n", + "display Nios-II system id", "\n - display Nios-II system id\n" ); #endif /* CONFIG_SYS_NIOS_SYSID_BASE */ diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c index 5ef560791..ef11cb65e 100644 --- a/cpu/ppc4xx/bedbug_405.c +++ b/cpu/ppc4xx/bedbug_405.c @@ -71,7 +71,7 @@ void bedbug405_do_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* -------------------------------------------------- */ if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } @@ -125,7 +125,7 @@ void bedbug405_do_break (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* Set a breakpoint at the address */ if (!isdigit (argv[1][0])) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return; } diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 6d5f8d65d..4365df987 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -259,6 +259,7 @@ phys_size_t initdram(int board_type) #ifndef CONFIG_SYS_SDRAM_TABLE sdram_conf_t mb0cf[] = { {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4) */ + {(128 << 20), 13, 0x000A4001}, /* 128MB mode 3, 13x10(4) */ {(64 << 20), 12, 0x00082001} /* 64MB mode 2, 12x9(4) */ }; #else @@ -269,6 +270,18 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE; #define CONFIG_SYS_SDRAM0_TR0 0x41094012 #endif +#ifndef CONFIG_SYS_SDRAM0_WDDCTR +#define CONFIG_SYS_SDRAM0_WDDCTR 0x00000000 /* wrcp=0 dcd=0 */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_RTR +#define CONFIG_SYS_SDRAM0_RTR 0x04100000 /* 7.8us @ 133MHz PLB */ +#endif + +#ifndef CONFIG_SYS_SDRAM0_CFG0 +#define CONFIG_SYS_SDRAM0_CFG0 0x82000000 /* DCEN=1, PMUD=0, 64-bit */ +#endif + #define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) #define NUM_TRIES 64 @@ -378,7 +391,7 @@ phys_size_t initdram(int board_type) mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ - mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ + mtsdram(mem_wddctr, CONFIG_SYS_SDRAM0_WDDCTR); mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* @@ -387,31 +400,63 @@ phys_size_t initdram(int board_type) mtsdram(mem_b0cr, mb0cf[i].reg); mtsdram(mem_tr0, CONFIG_SYS_SDRAM0_TR0); mtsdram(mem_tr1, 0x80800800); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/ - mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */ + mtsdram(mem_rtr, CONFIG_SYS_SDRAM0_RTR); mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/ udelay(400); /* Delay 200 usecs (min) */ /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x82000000); /* DCEN=1, PMUD=0, 64-bit */ + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { + phys_size_t size = mb0cf[i].size; /* * Optimize TR1 to current hardware environment */ sdram_tr1_set(0x00000000, &tr1_bank1); mtsdram(mem_tr1, (tr1_bank1 | 0x80800800)); + + /* + * OK, size detected. Enable second bank if + * defined (assumes same type as bank 0) + */ +#ifdef CONFIG_SDRAM_BANK1 + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, mb0cf[i].size | mb0cf[i].reg); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + + /* + * Check if 2nd bank is really available. + * If the size not equal to the size of the first + * bank, then disable the 2nd bank completely. + */ + if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) + != mb0cf[i].size) { + mtsdram(mem_cfg0, 0); + mtsdram(mem_b1cr, 0); + mtsdram(mem_cfg0, CONFIG_SYS_SDRAM0_CFG0); + udelay(10000); + } else { + /* + * We have two identical banks, so the size + * is twice the bank size + */ + size = 2 * size; + } +#endif + #ifdef CONFIG_SDRAM_ECC - ecc_init(0, mb0cf[i].size); + ecc_init(0, size); #endif /* * OK, size detected -> all done */ - return mb0cf[i].size; + return size; } } diff --git a/disk/part_efi.c b/disk/part_efi.c index cc188ee89..d8a81115c 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -163,7 +163,9 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part, /* The ulong casting limits the maximum disk size to 2 TB */ info->start = (ulong) le64_to_int((*pgpt_pte)[part - 1].starting_lba); - info->size = (ulong) le64_to_int((*pgpt_pte)[part - 1].ending_lba) - info->start; + /* The ending LBA is inclusive, to calculate size, add 1 to it */ + info->size = ((ulong)le64_to_int((*pgpt_pte)[part - 1].ending_lba) + 1) + - info->start; info->blksz = GPT_BLOCK_SIZE; sprintf((char *)info->name, "%s%d\n", GPT_ENTRY_NAME, part); diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds index f9ffde445..5a6df7f6f 100644 --- a/doc/README.mpc8572ds +++ b/doc/README.mpc8572ds @@ -164,4 +164,3 @@ Implementing AMP(Asymmetric MultiProcessing) Please note only core0 will run u-boot, core1 starts kernel directly after "cpu release" command is issued. - diff --git a/drivers/gpio/pca953x.c b/drivers/gpio/pca953x.c index 390d99ad3..1c5e314d9 100644 --- a/drivers/gpio/pca953x.c +++ b/drivers/gpio/pca953x.c @@ -164,7 +164,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (!c || !((argc == (c->maxargs)) || (((int)c->cmd == PCA953X_CMD_DEVICE) && (argc == (c->maxargs - 1))))) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -209,7 +209,7 @@ int do_pca953x(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( pca953x, 5, 1, do_pca953x, - "pca953x - pca953x gpio access\n", + "pca953x gpio access", "device [dev]\n" " - show or set current device address\n" #ifdef CONFIG_CMD_PCA953X_INFO diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 6079c05ad..08cb91d60 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libi2c.a +COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c new file mode 100644 index 000000000..cfe55cd1d --- /dev/null +++ b/drivers/i2c/bfin-twi_i2c.c @@ -0,0 +1,285 @@ +/* + * i2c.c - driver for Blackfin on-chip TWI/I2C + * + * Copyright (c) 2006-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include <common.h> +#include <i2c.h> + +#include <asm/blackfin.h> +#include <asm/mach-common/bits/twi.h> + +#ifdef DEBUG +# define dmemset(s, c, n) memset(s, c, n) +#else +# define dmemset(s, c, n) +#endif +#define debugi(fmt, args...) \ + debug( \ + "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t" \ + "%-20s:%-3i: " fmt "\n", \ + bfin_read_TWI_MASTER_STAT(), bfin_read_TWI_FIFO_STAT(), bfin_read_TWI_INT_STAT(), \ + __func__, __LINE__, ## args) + +#ifdef TWI0_CLKDIV +#define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) +#define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) +#define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val) +#define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) +#define bfin_write_TWI_XMT_DATA8(val) bfin_write_TWI0_XMT_DATA8(val) +#define bfin_read_TWI_RCV_DATA8() bfin_read_TWI0_RCV_DATA8() +#define bfin_read_TWI_INT_STAT() bfin_read_TWI0_INT_STAT() +#define bfin_write_TWI_INT_STAT(val) bfin_write_TWI0_INT_STAT(val) +#define bfin_read_TWI_MASTER_STAT() bfin_read_TWI0_MASTER_STAT() +#define bfin_write_TWI_MASTER_STAT(val) bfin_write_TWI0_MASTER_STAT(val) +#define bfin_read_TWI_MASTER_CTL() bfin_read_TWI0_MASTER_CTL() +#define bfin_write_TWI_MASTER_CTL(val) bfin_write_TWI0_MASTER_CTL(val) +#define bfin_write_TWI_INT_MASK(val) bfin_write_TWI0_INT_MASK(val) +#define bfin_write_TWI_FIFO_CTL(val) bfin_write_TWI0_FIFO_CTL(val) +#endif + +#ifdef CONFIG_TWICLK_KHZ +# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED +#endif +#if CONFIG_SYS_I2C_SPEED > 400000 +# error The Blackfin I2C hardware can only operate at 400KHz max +#endif + +/* All transfers are described by this data structure */ +struct i2c_msg { + u8 flags; +#define I2C_M_COMBO 0x4 +#define I2C_M_STOP 0x2 +#define I2C_M_READ 0x1 + int len; /* msg length */ + u8 *buf; /* pointer to msg data */ + int alen; /* addr length */ + u8 *abuf; /* addr buffer */ +}; + +/** + * wait_for_completion - manage the actual i2c transfer + * @msg: the i2c msg + */ +static int wait_for_completion(struct i2c_msg *msg) +{ + uint16_t int_stat; + + while (!ctrlc()) { + int_stat = bfin_read_TWI_INT_STAT(); + + if (int_stat & XMTSERV) { + debugi("processing XMTSERV"); + bfin_write_TWI_INT_STAT(XMTSERV); + SSYNC(); + if (msg->alen) { + bfin_write_TWI_XMT_DATA8(*(msg->abuf++)); + --msg->alen; + } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { + bfin_write_TWI_XMT_DATA8(*(msg->buf++)); + --msg->len; + } else { + bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | + (msg->flags & I2C_M_COMBO ? RSTART | MDIR : STOP)); + SSYNC(); + } + } + if (int_stat & RCVSERV) { + debugi("processing RCVSERV"); + bfin_write_TWI_INT_STAT(RCVSERV); + SSYNC(); + if (msg->len) { + *(msg->buf++) = bfin_read_TWI_RCV_DATA8(); + --msg->len; + } else if (msg->flags & I2C_M_STOP) { + bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() | STOP); + SSYNC(); + } + } + if (int_stat & MERR) { + debugi("processing MERR"); + bfin_write_TWI_INT_STAT(MERR); + SSYNC(); + break; + } + if (int_stat & MCOMP) { + debugi("processing MCOMP"); + bfin_write_TWI_INT_STAT(MCOMP); + SSYNC(); + if (msg->flags & I2C_M_COMBO && msg->len) { + bfin_write_TWI_MASTER_CTL((bfin_read_TWI_MASTER_CTL() & ~RSTART) | + (min(msg->len, 0xff) << 6) | MEN | MDIR); + SSYNC(); + } else + break; + } + } + + return msg->len; +} + +/** + * i2c_transfer - setup an i2c transfer + * @return: 0 if things worked, non-0 if things failed + * + * Here we just get the i2c stuff all prepped and ready, and then tail off + * into wait_for_completion() for all the bits to go. + */ +static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags) +{ + uchar addr_buffer[] = { + (addr >> 0), + (addr >> 8), + (addr >> 16), + }; + struct i2c_msg msg = { + .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), + .buf = buffer, + .len = len, + .abuf = addr_buffer, + .alen = alen, + }; + int ret; + + dmemset(buffer, 0xff, len); + debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ", + chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr")); + + /* wait for things to settle */ + while (bfin_read_TWI_MASTER_STAT() & BUSBUSY) + if (ctrlc()) + return 1; + + /* Set Transmit device address */ + bfin_write_TWI_MASTER_ADDR(chip); + + /* Clear the FIFO before starting things */ + bfin_write_TWI_FIFO_CTL(XMTFLUSH | RCVFLUSH); + SSYNC(); + bfin_write_TWI_FIFO_CTL(0); + SSYNC(); + + /* prime the pump */ + if (msg.alen) { + len = msg.alen; + debugi("first byte=0x%02x", *msg.abuf); + bfin_write_TWI_XMT_DATA8(*(msg.abuf++)); + --msg.alen; + } else if (!(msg.flags & I2C_M_READ) && msg.len) { + debugi("first byte=0x%02x", *msg.buf); + bfin_write_TWI_XMT_DATA8(*(msg.buf++)); + --msg.len; + } + + /* clear int stat */ + bfin_write_TWI_MASTER_STAT(-1); + bfin_write_TWI_INT_STAT(-1); + bfin_write_TWI_INT_MASK(0); + SSYNC(); + + /* Master enable */ + bfin_write_TWI_MASTER_CTL( + (bfin_read_TWI_MASTER_CTL() & FAST) | + (min(len, 0xff) << 6) | MEN | + ((msg.flags & I2C_M_READ) ? MDIR : 0) + ); + SSYNC(); + debugi("CTL=0x%04x", bfin_read_TWI_MASTER_CTL()); + + /* process the rest */ + ret = wait_for_completion(&msg); + debugi("ret=%d", ret); + + if (ret) { + bfin_write_TWI_MASTER_CTL(bfin_read_TWI_MASTER_CTL() & ~MEN); + bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() & ~TWI_ENA); + SSYNC(); + bfin_write_TWI_CONTROL(bfin_read_TWI_CONTROL() | TWI_ENA); + SSYNC(); + } + + return ret; +} + +/* + * i2c_init - initialize the i2c bus + * @speed: bus speed (in HZ) + * @slaveaddr: address of device in slave mode (0 - not slave) + * + * Slave mode isn't actually implemented. It'll stay that way until + * we get a real request for it. + */ +void i2c_init(int speed, int slaveaddr) +{ + uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F; + + /* Set TWI internal clock as 10MHz */ + bfin_write_TWI_CONTROL(prescale); + + /* Set TWI interface clock as specified */ + bfin_write_TWI_CLKDIV( + ((5 * 1024 / (speed / 1000)) << 8) | + ((5 * 1024 / (speed / 1000)) & 0xFF) + ); + + /* Don't turn it on */ + bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + + /* But enable it */ + bfin_write_TWI_CONTROL(TWI_ENA | prescale); + SSYNC(); + + debugi("CONTROL:0x%04x CLKDIV:0x%04x", + bfin_read_TWI_CONTROL(), bfin_read_TWI_CLKDIV()); + +#if CONFIG_SYS_I2C_SLAVE +# error I2C slave support not tested/supported + /* If they want us as a slave, do it */ + if (slaveaddr) { + bfin_write_TWI_SLAVE_ADDR(slaveaddr); + bfin_write_TWI_SLAVE_CTL(SEN); + } +#endif +} + +/** + * i2c_probe - test if a chip exists at a given i2c address + * @chip: i2c chip addr to search for + * @return: 0 if found, non-0 if not found + */ +int i2c_probe(uchar chip) +{ + u8 byte; + return i2c_read(chip, 0, 0, &byte, 1); +} + +/** + * i2c_read - read data from an i2c device + * @chip: i2c chip addr + * @addr: memory (register) address in the chip + * @alen: byte size of address + * @buffer: buffer to store data read from chip + * @len: how many bytes to read + * @return: 0 on success, non-0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ)); +} + +/** + * i2c_write - write data to an i2c device + * @chip: i2c chip addr + * @addr: memory (register) address in the chip + * @alen: byte size of address + * @buffer: buffer to store data read from chip + * @len: how many bytes to write + * @return: 0 on success, non-0 on failure + */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + return i2c_transfer(chip, addr, alen, buffer, len, 0); +} diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index a27de5a7e..da6cec1fa 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -385,8 +385,18 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } shift -= 8; } - send_stop(); /* reportedly some chips need a full stop */ + + /* Some I2C chips need a stop/start sequence here, + * other chips don't work with a full stop and need + * only a start. Default behaviour is to send the + * stop/start sequence. + */ +#ifdef CONFIG_SOFT_I2C_READ_REPEATED_START send_start(); +#else + send_stop(); + send_start(); +#endif } /* * Send the chip address again, this time for a read cycle. diff --git a/drivers/misc/ds4510.c b/drivers/misc/ds4510.c index 4cd2fc224..8b5fbbc45 100644 --- a/drivers/misc/ds4510.c +++ b/drivers/misc/ds4510.c @@ -294,7 +294,7 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (!c || !((argc == (c->maxargs)) || (((int)c->cmd == DS4510_CMD_DEVICE) && (argc == (c->maxargs - 1))))) { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -371,7 +371,7 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else if (strcmp(argv[2], "write") == 0) { rw_func = ds4510_mem_write; } else { - printf("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -390,7 +390,7 @@ int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( ds4510, 6, 1, do_ds4510, - "ds4510 - ds4510 eeprom/seeprom/sram/gpio access\n", + "ds4510 eeprom/seeprom/sram/gpio access", "device [dev]\n" " - show or set current device address\n" #ifdef CONFIG_CMD_DS4510_INFO diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index e8afe9985..84ff7e809 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -774,17 +774,26 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) } } -/* loop through the sectors from the highest address when the passed - * address is greater or equal to the sector address we have a match +/* + * Loop through the sector table starting from the previously found sector. + * Searches forwards or backwards, dependent on the passed address. */ static flash_sect_t find_sector (flash_info_t * info, ulong addr) { - flash_sect_t sector; + static flash_sect_t saved_sector = 0; /* previously found sector */ + flash_sect_t sector = saved_sector; - for (sector = info->sector_count - 1; sector >= 0; sector--) { - if (addr >= info->start[sector]) - break; - } + while ((info->start[sector] < addr) + && (sector < info->sector_count - 1)) + sector++; + while ((info->start[sector] > addr) && (sector > 0)) + /* + * also decrements the sector in case of an overshot + * in the first loop + */ + sector--; + + saved_sector = sector; return sector; } @@ -795,7 +804,8 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, { void *dstaddr; int flag; - flash_sect_t sect; + flash_sect_t sect = 0; + char sect_found = 0; dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE); @@ -840,6 +850,7 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, sect = find_sector(info, dest); flash_unlock_seq (info, sect); flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE); + sect_found = 1; break; } @@ -864,8 +875,10 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, unmap_physmem(dstaddr, info->portwidth); - return flash_full_status_check (info, find_sector (info, dest), - info->write_tout, "write"); + if (!sect_found) + sect = find_sector (info, dest); + + return flash_full_status_check (info, sect, info->write_tout, "write"); } #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE @@ -1795,6 +1808,20 @@ static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) cfi_reverse_geometry(qry); } +static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) +{ + /* check if flash geometry needs reversal */ + if (qry->num_erase_regions > 1) { + /* reverse geometry if top boot part */ + if (info->cfi_version < 0x3131) { + /* CFI < 1.1, guess by device id (only M29W320ET now) */ + if (info->device_id == 0x2256) { + cfi_reverse_geometry(qry); + } + } + } +} + /* * The following code cannot be run from FLASH! * @@ -1868,6 +1895,9 @@ ulong flash_get_size (ulong base, int banknum) case 0x001f: flash_fixup_atmel(info, &qry); break; + case 0x0020: + flash_fixup_stm(info, &qry); + break; } debug ("manufacturer is %d\n", info->vendor); diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 504fd100a..dddbb78b1 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -331,20 +331,43 @@ static int SetupSystemRegs(int *opmode) *pVR_CTL |= CLKBUFOE; /* Set all the pins to peripheral mode */ -#ifndef CONFIG_BFIN_MAC_RMII - *pPORTH_FER = 0xFFFF; -#ifdef __ADSPBF52x__ - *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2; -#endif +#ifdef CONFIG_BFIN_MAC_RMII + /* grab RMII pins */ +# if defined(__ADSPBF51x__) + *pPORTF_MUX = (*pPORTF_MUX & \ + ~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \ + PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1; + *pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15; + *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1; + *pPORTG_FER |= PG0 | PG1 | PG2; +# elif defined(__ADSPBF52x__) + *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2; + *pPORTG_FER |= PG14 | PG15; + *pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \ + PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2; + *pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8; +# else + *pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15; +# endif #else -#if defined(__ADSPBF536__) || defined(__ADSPBF537__) - *pPORTH_FER = 0xC373; -#endif -#ifdef __ADSPBF52x__ - *pPORTH_FER = 0x01FF; - *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2; -#endif + /* grab MII & RMII pins */ +# if defined(__ADSPBF51x__) + *pPORTF_MUX = (*pPORTF_MUX & \ + ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \ + PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1; + *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15; + *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1; + *pPORTG_FER |= PG0 | PG1 | PG2; +# elif defined(__ADSPBF52x__) + *pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2; + *pPORTG_FER |= PG14 | PG15; + *pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2; + *pPORTH_FER = -1; /* all pins */ +# else + *pPORTH_FER = -1; /* all pins */ +# endif #endif + /* MDC = 2.5 MHz */ sysctl = SET_MDCDIV(24); /* Odd word alignment for Receive Frame DMA word */ diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 2dcaa2c91..a52749d78 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -82,6 +82,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, + {} }; /* Function forward declarations */ diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index e914d01d8..e90a4a5fe 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -425,7 +425,7 @@ static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong addr; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -455,13 +455,13 @@ static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return qe_upload_firmware((const struct qe_firmware *) addr); } - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } U_BOOT_CMD( qe, 4, 0, qe_cmd, - "qe - QUICC Engine commands\n", + "QUICC Engine commands", "fw <addr> [<length>] - Upload firmware binary at address <addr> to " "the QE,\n\twith optional length <length> verification.\n" ); diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 856f51a75..b306a65a9 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -28,11 +28,18 @@ LIB := $(obj)libusb.a # core COBJS-y += usbdcore.o COBJS-$(CONFIG_USB_OHCI_NEW) += usb_ohci.o +COBJS-$(CONFIG_USB_EHCI) += usb_ehci_core.o # host COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o COBJS-$(CONFIG_USB_SL811HS) += sl811_usb.o +COBJS-$(CONFIG_USB_EHCI_FSL) += usb_ehci_fsl.o +COBJS-$(CONFIG_USB_EHCI_PCI) += usb_ehci_pci.o +COBJS-$(CONFIG_USB_EHCI_IXP4XX) += usb_ehci_ixp.o +COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o +COBJS-$(CONFIG_USB_DAVINCI) += davinci_usb.o +COBJS-$(CONFIG_USB_EHCI_VCT) += usb_ehci_vct.o # device ifdef CONFIG_USB_DEVICE diff --git a/drivers/usb/davinci_usb.c b/drivers/usb/davinci_usb.c new file mode 100644 index 000000000..e66f660fe --- /dev/null +++ b/drivers/usb/davinci_usb.c @@ -0,0 +1,106 @@ +/* + * TI's Davinci platform specific USB wrapper functions. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + */ + +#include <common.h> +#include <asm/io.h> +#include "davinci_usb.h" + +/* MUSB platform configuration */ +struct musb_config musb_cfg = { + (struct musb_regs *)MENTOR_USB0_BASE, + DAVINCI_USB_TIMEOUT, + 0 +}; + +/* MUSB module register overlay */ +struct davinci_usb_regs *dregs; + +/* + * Enable the USB phy + */ +static u8 phy_on(void) +{ + u32 timeout; + + /* Wait until the USB phy is turned on */ + writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN, USBPHY_CTL_PADDR); + timeout = musb_cfg.timeout; + while (timeout--) + if (readl(USBPHY_CTL_PADDR) & USBPHY_PHYCLKGD) + return 1; + + /* USB phy was not turned on */ + return 0; +} + +/* + * Disable the USB phy + */ +static void phy_off(void) +{ + /* powerdown the on-chip PHY and its oscillator */ + writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, USBPHY_CTL_PADDR); +} + +/* + * This function performs Davinci platform specific initialization for usb0. + */ +int musb_platform_init(void) +{ + u32 revision; + + /* enable USB VBUS */ + enable_vbus(); + + /* start the on-chip USB phy and its pll */ + if (!phy_on()) + return -1; + + /* reset the controller */ + dregs = (struct davinci_usb_regs *)DAVINCI_USB0_BASE; + writel(1, &dregs->ctrlr); + udelay(5000); + + /* Returns zero if e.g. not clocked */ + revision = readl(&dregs->version); + if (!revision) + return -1; + + /* Disable all interrupts */ + writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_RXINT_MASK | + DAVINCI_USB_TXINT_MASK , &dregs->intmsksetr); + return 0; +} + +/* + * This function performs Davinci platform specific deinitialization for usb0. + */ +void musb_platform_deinit(void) +{ + /* Turn of the phy */ + phy_off(); + + /* flush any interrupts */ + writel(DAVINCI_USB_USBINT_MASK | DAVINCI_USB_TXINT_MASK | + DAVINCI_USB_RXINT_MASK , &dregs->intclrr); +} diff --git a/drivers/usb/davinci_usb.h b/drivers/usb/davinci_usb.h new file mode 100644 index 000000000..d270861af --- /dev/null +++ b/drivers/usb/davinci_usb.h @@ -0,0 +1,87 @@ +/* + * TI's Davinci platform specific USB wrapper functions. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + */ + +#ifndef __DAVINCI_USB_H__ +#define __DAVINCI_USB_H__ + +#include <asm/arch/hardware.h> +#include "musb_core.h" + +/* Base address of DAVINCI usb0 wrapper */ +#define DAVINCI_USB0_BASE 0x01C64000 + +/* Base address of DAVINCI musb core */ +#define MENTOR_USB0_BASE (DAVINCI_USB0_BASE+0x400) + +/* + * Davinci platform USB wrapper register overlay. Note: Only the required + * registers are included in this structure. It can be expanded as required. + */ +struct davinci_usb_regs { + u32 version; + u32 ctrlr; + u32 reserved[0x20]; + u32 intclrr; + u32 intmskr; + u32 intmsksetr; +}; + +#define DAVINCI_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */ +#define DAVINCI_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */ +#define DAVINCI_USB_USBINT_SHIFT 16 +#define DAVINCI_USB_TXINT_SHIFT 0 +#define DAVINCI_USB_RXINT_SHIFT 8 +#define DAVINCI_INTR_DRVVBUS 0x0100 + +#define DAVINCI_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */ +#define DAVINCI_USB_TXINT_MASK \ + (DAVINCI_USB_TX_ENDPTS_MASK << DAVINCI_USB_TXINT_SHIFT) +#define DAVINCI_USB_RXINT_MASK \ + (DAVINCI_USB_RX_ENDPTS_MASK << DAVINCI_USB_RXINT_SHIFT) +#define MGC_BUSCTL_OFFSET(_bEnd, _bOffset) \ + (0x80 + (8*(_bEnd)) + (_bOffset)) + +/* Integrated highspeed/otg PHY */ +#define USBPHY_CTL_PADDR (DAVINCI_SYSTEM_MODULE_BASE + 0x34) +#define USBPHY_PHYCLKGD (1 << 8) +#define USBPHY_SESNDEN (1 << 7) /* v(sess_end) comparator */ +#define USBPHY_VBDTCTEN (1 << 6) /* v(bus) comparator */ +#define USBPHY_PHYPLLON (1 << 4) /* override pll suspend */ +#define USBPHY_CLKO1SEL (1 << 3) +#define USBPHY_OSCPDWN (1 << 2) +#define USBPHY_PHYPDWN (1 << 0) + +/* Timeout for Davinci USB module */ +#define DAVINCI_USB_TIMEOUT 0x3FFFFFF + +/* IO Expander I2C address and VBUS enable mask */ +#define IOEXP_I2C_ADDR 0x3A +#define IOEXP_VBUSEN_MASK 1 + +/* extern functions */ +extern void lpsc_on(unsigned int id); +extern int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); +extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); +extern void enable_vbus(void); +#endif /* __DAVINCI_USB_H__ */ + diff --git a/drivers/usb/musb_core.c b/drivers/usb/musb_core.c new file mode 100644 index 000000000..ec57fc811 --- /dev/null +++ b/drivers/usb/musb_core.c @@ -0,0 +1,141 @@ +/* + * Mentor USB OTG Core functionality common for both Host and Device + * functionality. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + */ + +#include <common.h> + +#include "musb_core.h" +struct musb_regs *musbr; + +/* + * program the mentor core to start (enable interrupts, dma, etc.) + */ +void musb_start(void) +{ + u8 devctl; + + /* disable all interrupts */ + writew(0, &musbr->intrtxe); + writew(0, &musbr->intrrxe); + writeb(0, &musbr->intrusbe); + writeb(0, &musbr->testmode); + + /* put into basic highspeed mode and start session */ + writeb(MUSB_POWER_HSENAB, &musbr->power); +#if defined(CONFIG_MUSB_HCD) + devctl = readb(&musbr->devctl); + writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl); +#endif +} + +/* + * This function configures the endpoint configuration. The musb hcd or musb + * device implementation can use this function to configure the endpoints + * and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints + * should not be more than the available FIFO size. + * + * epinfo - Pointer to EP configuration table + * cnt - Number of entries in the EP conf table. + */ +void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) +{ + u16 csr; + u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */ + u32 fifosize; + u8 idx; + + while (cnt--) { + /* prepare fifosize to write to register */ + fifosize = epinfo->epsize >> 3; + idx = ffs(fifosize) - 1; + + writeb(epinfo->epnum, &musbr->index); + if (epinfo->epdir) { + /* Configure fifo size and fifo base address */ + writeb(idx, &musbr->txfifosz); + writew(fifoaddr >> 3, &musbr->txfifoadd); +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); +#endif + /* Flush fifo if required */ + if (csr & MUSB_TXCSR_TXPKTRDY) + writew(csr | MUSB_TXCSR_FLUSHFIFO, + &musbr->txcsr); + } else { + /* Configure fifo size and fifo base address */ + writeb(idx, &musbr->rxfifosz); + writew(fifoaddr >> 3, &musbr->rxfifoadd); +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = readw(&musbr->rxcsr); + writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); +#endif + /* Flush fifo if required */ + if (csr & MUSB_RXCSR_RXPKTRDY) + writew(csr | MUSB_RXCSR_FLUSHFIFO, + &musbr->rxcsr); + } + fifoaddr += epinfo->epsize; + epinfo++; + } +} + +/* + * This function writes data to endpoint fifo + * + * ep - endpoint number + * length - number of bytes to write to FIFO + * fifo_data - Pointer to data buffer that contains the data to write + */ +void write_fifo(u8 ep, u32 length, void *fifo_data) +{ + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + writeb(ep, &musbr->index); + + /* write the data to the fifo */ + while (length--) + writeb(*data++, &musbr->fifox[ep]); +} + +/* + * This function reads data from endpoint fifo + * + * ep - endpoint number + * length - number of bytes to read from FIFO + * fifo_data - pointer to data buffer into which data is read + */ +void read_fifo(u8 ep, u32 length, void *fifo_data) +{ + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + writeb(ep, &musbr->index); + + /* read the data to the fifo */ + while (length--) + *data++ = readb(&musbr->fifox[ep]); +} diff --git a/drivers/usb/musb_core.h b/drivers/usb/musb_core.h new file mode 100644 index 000000000..9f5ebe75e --- /dev/null +++ b/drivers/usb/musb_core.h @@ -0,0 +1,317 @@ +/****************************************************************** + * Copyright 2008 Mentor Graphics Corporation + * Copyright (C) 2008 by Texas Instruments + * + * This file is part of the Inventra Controller Driver for Linux. + * + * The Inventra Controller Driver for Linux is free software; you + * can redistribute it and/or modify it under the terms of the GNU + * General Public License version 2 as published by the Free Software + * Foundation. + * + * The Inventra Controller Driver for Linux is distributed in + * the hope that it will be useful, but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with The Inventra Controller Driver for Linux ; if not, + * write to the Free Software Foundation, Inc., 59 Temple Place, + * Suite 330, Boston, MA 02111-1307 USA + * + * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION + * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE + * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS + * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. + * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES + * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT + * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR + * GRAPHICS SUPPORT CUSTOMER. + ******************************************************************/ + +#ifndef __MUSB_HDRC_DEFS_H__ +#define __MUSB_HDRC_DEFS_H__ + +#include <usb.h> +#include <usb_defs.h> +#include <asm/io.h> + +#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ + +/* Mentor USB core register overlay structure */ +struct musb_regs { + /* common registers */ + u8 faddr; + u8 power; + u16 intrtx; + u16 intrrx; + u16 intrtxe; + u16 intrrxe; + u8 intrusb; + u8 intrusbe; + u16 frame; + u8 index; + u8 testmode; + /* indexed registers */ + u16 txmaxp; + u16 txcsr; + u16 rxmaxp; + u16 rxcsr; + u16 rxcount; + u8 txtype; + u8 txinterval; + u8 rxtype; + u8 rxinterval; + u8 reserved0; + u8 fifosize; + /* fifo */ + u32 fifox[16]; + /* OTG, dynamic FIFO, version & vendor registers */ + u8 devctl; + u8 reserved1; + u8 txfifosz; + u8 rxfifosz; + u16 txfifoadd; + u16 rxfifoadd; + u32 vcontrol; + u16 hwvers; + u16 reserved2[5]; + u8 epinfo; + u8 raminfo; + u8 linkinfo; + u8 vplen; + u8 hseof1; + u8 fseof1; + u8 lseof1; + u8 reserved3; + /* target address registers */ + struct musb_tar_regs { + u8 txfuncaddr; + u8 reserved0; + u8 txhubaddr; + u8 txhubport; + u8 rxfuncaddr; + u8 reserved1; + u8 rxhubaddr; + u8 rxhubport; + } tar[16]; +} __attribute((aligned(32))); + +/* + * MUSB Register bits + */ + +/* POWER */ +#define MUSB_POWER_ISOUPDATE 0x80 +#define MUSB_POWER_SOFTCONN 0x40 +#define MUSB_POWER_HSENAB 0x20 +#define MUSB_POWER_HSMODE 0x10 +#define MUSB_POWER_RESET 0x08 +#define MUSB_POWER_RESUME 0x04 +#define MUSB_POWER_SUSPENDM 0x02 +#define MUSB_POWER_ENSUSPEND 0x01 +#define MUSB_POWER_HSMODE_SHIFT 4 + +/* INTRUSB */ +#define MUSB_INTR_SUSPEND 0x01 +#define MUSB_INTR_RESUME 0x02 +#define MUSB_INTR_RESET 0x04 +#define MUSB_INTR_BABBLE 0x04 +#define MUSB_INTR_SOF 0x08 +#define MUSB_INTR_CONNECT 0x10 +#define MUSB_INTR_DISCONNECT 0x20 +#define MUSB_INTR_SESSREQ 0x40 +#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ + +/* DEVCTL */ +#define MUSB_DEVCTL_BDEVICE 0x80 +#define MUSB_DEVCTL_FSDEV 0x40 +#define MUSB_DEVCTL_LSDEV 0x20 +#define MUSB_DEVCTL_VBUS 0x18 +#define MUSB_DEVCTL_VBUS_SHIFT 3 +#define MUSB_DEVCTL_HM 0x04 +#define MUSB_DEVCTL_HR 0x02 +#define MUSB_DEVCTL_SESSION 0x01 + +/* TESTMODE */ +#define MUSB_TEST_FORCE_HOST 0x80 +#define MUSB_TEST_FIFO_ACCESS 0x40 +#define MUSB_TEST_FORCE_FS 0x20 +#define MUSB_TEST_FORCE_HS 0x10 +#define MUSB_TEST_PACKET 0x08 +#define MUSB_TEST_K 0x04 +#define MUSB_TEST_J 0x02 +#define MUSB_TEST_SE0_NAK 0x01 + +/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ +#define MUSB_FIFOSZ_DPB 0x10 +/* Allocation size (8, 16, 32, ... 4096) */ +#define MUSB_FIFOSZ_SIZE 0x0f + +/* CSR0 */ +#define MUSB_CSR0_FLUSHFIFO 0x0100 +#define MUSB_CSR0_TXPKTRDY 0x0002 +#define MUSB_CSR0_RXPKTRDY 0x0001 + +/* CSR0 in Peripheral mode */ +#define MUSB_CSR0_P_SVDSETUPEND 0x0080 +#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 +#define MUSB_CSR0_P_SENDSTALL 0x0020 +#define MUSB_CSR0_P_SETUPEND 0x0010 +#define MUSB_CSR0_P_DATAEND 0x0008 +#define MUSB_CSR0_P_SENTSTALL 0x0004 + +/* CSR0 in Host mode */ +#define MUSB_CSR0_H_DIS_PING 0x0800 +#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ +#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ +#define MUSB_CSR0_H_NAKTIMEOUT 0x0080 +#define MUSB_CSR0_H_STATUSPKT 0x0040 +#define MUSB_CSR0_H_REQPKT 0x0020 +#define MUSB_CSR0_H_ERROR 0x0010 +#define MUSB_CSR0_H_SETUPPKT 0x0008 +#define MUSB_CSR0_H_RXSTALL 0x0004 + +/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_CSR0_P_WZC_BITS \ + (MUSB_CSR0_P_SENTSTALL) +#define MUSB_CSR0_H_WZC_BITS \ + (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ + | MUSB_CSR0_RXPKTRDY) + +/* TxType/RxType */ +#define MUSB_TYPE_SPEED 0xc0 +#define MUSB_TYPE_SPEED_SHIFT 6 +#define MUSB_TYPE_SPEED_HIGH 1 +#define MUSB_TYPE_SPEED_FULL 2 +#define MUSB_TYPE_SPEED_LOW 3 +#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_SHIFT 4 +#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_BULK 2 +#define MUSB_TYPE_PROTO_INTR 3 + +/* CONFIGDATA */ +#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ +#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ +#define MUSB_CONFIGDATA_BIGENDIAN 0x20 +#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ +#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ +#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ +#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ +#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ + +/* TXCSR in Peripheral and Host mode */ +#define MUSB_TXCSR_AUTOSET 0x8000 +#define MUSB_TXCSR_MODE 0x2000 +#define MUSB_TXCSR_DMAENAB 0x1000 +#define MUSB_TXCSR_FRCDATATOG 0x0800 +#define MUSB_TXCSR_DMAMODE 0x0400 +#define MUSB_TXCSR_CLRDATATOG 0x0040 +#define MUSB_TXCSR_FLUSHFIFO 0x0008 +#define MUSB_TXCSR_FIFONOTEMPTY 0x0002 +#define MUSB_TXCSR_TXPKTRDY 0x0001 + +/* TXCSR in Peripheral mode */ +#define MUSB_TXCSR_P_ISO 0x4000 +#define MUSB_TXCSR_P_INCOMPTX 0x0080 +#define MUSB_TXCSR_P_SENTSTALL 0x0020 +#define MUSB_TXCSR_P_SENDSTALL 0x0010 +#define MUSB_TXCSR_P_UNDERRUN 0x0004 + +/* TXCSR in Host mode */ +#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 +#define MUSB_TXCSR_H_DATATOGGLE 0x0100 +#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 +#define MUSB_TXCSR_H_RXSTALL 0x0020 +#define MUSB_TXCSR_H_ERROR 0x0004 +#define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 + +/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_TXCSR_P_WZC_BITS \ + (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ + | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) +#define MUSB_TXCSR_H_WZC_BITS \ + (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ + | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) + +/* RXCSR in Peripheral and Host mode */ +#define MUSB_RXCSR_AUTOCLEAR 0x8000 +#define MUSB_RXCSR_DMAENAB 0x2000 +#define MUSB_RXCSR_DISNYET 0x1000 +#define MUSB_RXCSR_PID_ERR 0x1000 +#define MUSB_RXCSR_DMAMODE 0x0800 +#define MUSB_RXCSR_INCOMPRX 0x0100 +#define MUSB_RXCSR_CLRDATATOG 0x0080 +#define MUSB_RXCSR_FLUSHFIFO 0x0010 +#define MUSB_RXCSR_DATAERROR 0x0008 +#define MUSB_RXCSR_FIFOFULL 0x0002 +#define MUSB_RXCSR_RXPKTRDY 0x0001 + +/* RXCSR in Peripheral mode */ +#define MUSB_RXCSR_P_ISO 0x4000 +#define MUSB_RXCSR_P_SENTSTALL 0x0040 +#define MUSB_RXCSR_P_SENDSTALL 0x0020 +#define MUSB_RXCSR_P_OVERRUN 0x0004 + +/* RXCSR in Host mode */ +#define MUSB_RXCSR_H_AUTOREQ 0x4000 +#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 +#define MUSB_RXCSR_H_DATATOGGLE 0x0200 +#define MUSB_RXCSR_H_RXSTALL 0x0040 +#define MUSB_RXCSR_H_REQPKT 0x0020 +#define MUSB_RXCSR_H_ERROR 0x0004 +#define MUSB_S_RXCSR_H_DATATOGGLE 9 + +/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_RXCSR_P_WZC_BITS \ + (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ + | MUSB_RXCSR_RXPKTRDY) +#define MUSB_RXCSR_H_WZC_BITS \ + (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ + | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) + +/* HUBADDR */ +#define MUSB_HUBADDR_MULTI_TT 0x80 + +/* Endpoint configuration information. Note: The value of endpoint fifo size + * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other + * values are not supported + */ +struct musb_epinfo { + u8 epnum; /* endpoint number */ + u8 epdir; /* endpoint direction */ + u16 epsize; /* endpoint FIFO size */ +}; + +/* + * Platform specific MUSB configuration. Any platform using the musb + * functionality should create one instance of this structure in the + * platform specific file. + */ +struct musb_config { + struct musb_regs *regs; + u32 timeout; + u8 musb_speed; +}; + +/* externally defined data */ +extern struct musb_config musb_cfg; +extern struct musb_regs *musbr; + +/* exported functions */ +extern void musb_start(void); +extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); +extern void write_fifo(u8 ep, u32 length, void *fifo_data); +extern void read_fifo(u8 ep, u32 length, void *fifo_data); + +/* extern functions */ +extern inline void musb_writew(u32 offset, u16 value); +extern inline void musb_writeb(u32 offset, u8 value); +extern inline u16 musb_readw(u32 offset); +extern inline u8 musb_readb(u32 offset); + +#endif /* __MUSB_HDRC_DEFS_H__ */ + diff --git a/drivers/usb/musb_hcd.c b/drivers/usb/musb_hcd.c new file mode 100644 index 000000000..352a0d4eb --- /dev/null +++ b/drivers/usb/musb_hcd.c @@ -0,0 +1,792 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + */ + +#include <common.h> +#include "musb_hcd.h" + +/* MSC control transfers */ +#define USB_MSC_BBB_RESET 0xFF +#define USB_MSC_BBB_GET_MAX_LUN 0xFE + +/* Endpoint configuration information */ +static struct musb_epinfo epinfo[3] = { + {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ + {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */ + {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ +}; + +/* + * This function writes the data toggle value. + */ +static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) +{ + u16 toggle = usb_gettoggle(dev, ep, dir_out); + u16 csr; + + if (dir_out) { + if (!toggle) + writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); + else { + csr = readw(&musbr->txcsr); + csr |= MUSB_TXCSR_H_WR_DATATOGGLE; + writew(csr, &musbr->txcsr); + csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); + writew(csr, &musbr->txcsr); + } + } else { + if (!toggle) + writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); + else { + csr = readw(&musbr->rxcsr); + csr |= MUSB_RXCSR_H_WR_DATATOGGLE; + writew(csr, &musbr->rxcsr); + csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); + writew(csr, &musbr->rxcsr); + } + } +} + +/* + * This function checks if RxStall has occured on the endpoint. If a RxStall + * has occured, the RxStall is cleared and 1 is returned. If RxStall has + * not occured, 0 is returned. + */ +static u8 check_stall(u8 ep, u8 dir_out) +{ + u16 csr; + + /* For endpoint 0 */ + if (!ep) { + csr = readw(&musbr->txcsr); + if (csr & MUSB_CSR0_H_RXSTALL) { + csr &= ~MUSB_CSR0_H_RXSTALL; + writew(csr, &musbr->txcsr); + return 1; + } + } else { /* For non-ep0 */ + if (dir_out) { /* is it tx ep */ + csr = readw(&musbr->txcsr); + if (csr & MUSB_TXCSR_H_RXSTALL) { + csr &= ~MUSB_TXCSR_H_RXSTALL; + writew(csr, &musbr->txcsr); + return 1; + } + } else { /* is it rx ep */ + csr = readw(&musbr->rxcsr); + if (csr & MUSB_RXCSR_H_RXSTALL) { + csr &= ~MUSB_RXCSR_H_RXSTALL; + writew(csr, &musbr->rxcsr); + return 1; + } + } + } + return 0; +} + +/* + * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout + * error and -2 for stall. + */ +static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) +{ + u16 csr; + int result = 1; + + while (result > 0) { + csr = readw(&musbr->txcsr); + if (csr & MUSB_CSR0_H_ERROR) { + csr &= ~MUSB_CSR0_H_ERROR; + writew(csr, &musbr->txcsr); + dev->status = USB_ST_CRC_ERR; + result = -1; + break; + } + + switch (bit_mask) { + case MUSB_CSR0_TXPKTRDY: + if (!(csr & MUSB_CSR0_TXPKTRDY)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + + case MUSB_CSR0_RXPKTRDY: + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + if (csr & MUSB_CSR0_RXPKTRDY) + result = 0; + break; + + case MUSB_CSR0_H_REQPKT: + if (!(csr & MUSB_CSR0_H_REQPKT)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + } + } + return result; +} + +/* + * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 1)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = readw(&musbr->txcsr); + if (csr & MUSB_TXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (csr & MUSB_TXCSR_TXPKTRDY); + return 1; +} + +/* + * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 0)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = readw(&musbr->rxcsr); + if (csr & MUSB_RXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (!(csr & MUSB_RXCSR_RXPKTRDY)); + return 1; +} + +/* + * This function performs the setup phase of the control transfer + */ +static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) +{ + int result; + u16 csr; + + /* write the control request to ep0 fifo */ + write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); + + /* enable transfer of setup packet */ + csr = readw(&musbr->txcsr); + csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); + writew(csr, &musbr->txcsr); + + /* wait until the setup packet is transmitted */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + dev->act_len = 0; + return result; +} + +/* + * This function handles the control transfer in data phase + */ +static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 rxlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *rxbuff = (u8 *)buffer; + u8 rxedlength; + int result; + + while (rxlen < len) { + /* Determine the next read length */ + nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); + + /* Set the ReqPkt bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); + if (result < 0) + return result; + + /* Actual number of bytes received by usb */ + rxedlength = readb(&musbr->rxcount); + + /* Read the data from the RxFIFO */ + read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); + + /* Clear the RxPktRdy Bit */ + csr = readw(&musbr->txcsr); + csr &= ~MUSB_CSR0_RXPKTRDY; + writew(csr, &musbr->txcsr); + + /* short packet? */ + if (rxedlength != nextlen) { + dev->act_len += rxedlength; + break; + } + rxlen += nextlen; + dev->act_len = rxlen; + } + return 0; +} + +/* + * This function handles the control transfer out data phase + */ +static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *txbuff = (u8 *)buffer; + int result = 0; + + while (txlen < len) { + /* Determine the next write length */ + nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); + + /* Load the data to send in FIFO */ + write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); + + /* Set TXPKTRDY bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY, + &musbr->txcsr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + if (result < 0) + break; + + txlen += nextlen; + dev->act_len = txlen; + } + return result; +} + +/* + * This function handles the control transfer out status phase + */ +static int ctrlreq_out_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit */ + csr = readw(&musbr->txcsr); + csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | + MUSB_CSR0_H_STATUSPKT); + writew(csr, &musbr->txcsr); + + /* Wait until TXPKTRDY bit is cleared */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + return result; +} + +/* + * This function handles the control transfer in status phase + */ +static int ctrlreq_in_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit and ReqPkt bit */ + csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; + writew(csr, &musbr->txcsr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); + + /* clear StatusPkt bit and RxPktRdy bit */ + csr = readw(&musbr->txcsr); + csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); + writew(csr, &musbr->txcsr); + return result; +} + +/* + * determines the speed of the device (High/Full/Slow) + */ +static u8 get_dev_speed(struct usb_device *dev) +{ + return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH : + ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW : + MUSB_TYPE_SPEED_FULL); +} + +/* + * configure the hub address and the port address. + */ +static void config_hub_port(struct usb_device *dev, u8 ep) +{ + u8 chid; + u8 hub; + + /* Find out the nearest parent which is high speed */ + while (dev->parent->parent != NULL) + if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) + dev = dev->parent; + else + break; + + /* determine the port address at that hub */ + hub = dev->parent->devnum; + for (chid = 0; chid < USB_MAXCHILDREN; chid++) + if (dev->parent->children[chid] == dev) + break; + + /* configure the hub address and the port address */ + writeb(hub, &musbr->tar[ep].txhubaddr); + writeb((chid + 1), &musbr->tar[ep].txhubport); + writeb(hub, &musbr->tar[ep].rxhubaddr); + writeb((chid + 1), &musbr->tar[ep].rxhubport); +} + +/* + * do a control transfer + */ +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + int devnum = usb_pipedevice(pipe); + u16 csr; + u8 devspeed; + + /* select control endpoint */ + writeb(MUSB_CONTROL_EP, &musbr->index); + csr = readw(&musbr->txcsr); + + /* target addr and (for multipoint) hub addr/port */ + writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); + writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + config_hub_port(dev, MUSB_CONTROL_EP); + writeb(devspeed << 6, &musbr->txtype); + } else { + writeb(musb_cfg.musb_speed << 6, &musbr->txtype); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport); + } + + /* Control transfer setup phase */ + if (ctrlreq_setup_phase(dev, setup) < 0) + return 0; + + switch (setup->request) { + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + case USB_REQ_GET_INTERFACE: + case USB_REQ_GET_STATUS: + case USB_MSC_BBB_GET_MAX_LUN: + /* control transfer in-data-phase */ + if (ctrlreq_in_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer out-status-phase */ + if (ctrlreq_out_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_INTERFACE: + case USB_REQ_CLEAR_FEATURE: + case USB_MSC_BBB_RESET: + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_DESCRIPTOR: + /* control transfer out data phase */ + if (ctrlreq_out_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + default: + /* unhandled control transfer */ + return -1; + } + + dev->status = 0; + dev->act_len = len; + return len; +} + +/* + * do a bulk transfer + */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int devnum = usb_pipedevice(pipe); + u8 type; + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 devspeed; + + /* select bulk endpoint */ + writeb(MUSB_BULK_EP, &musbr->index); + + /* write the address of the device */ + if (dir_out) + writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr); + else + writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + /* + * MUSB is in high speed and the destination device is full + * speed device. So configure the hub address and port + * address registers. + */ + config_hub_port(dev, MUSB_BULK_EP); + } else { + if (dir_out) { + writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr); + writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport); + } else { + writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr); + writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport); + } + devspeed = musb_cfg.musb_speed; + } + + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + if (dir_out) { /* bulk-out transfer */ + /* Program the TxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + writeb(type, &musbr->txtype); + + /* Write maximum packet size to the TxMaxp register */ + writew(dev->epmaxpacketout[ep], &musbr->txmaxp); + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? + (len-txlen) : dev->epmaxpacketout[ep]; + + /* Write the data to the FIFO */ + write_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Set the TxPktRdy bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); + + /* Wait until the TxPktRdy bit is cleared */ + if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { + readw(&musbr->txcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + dev->act_len = txlen; + return 0; + } + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = readw(&musbr->txcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + } else { /* bulk-in transfer */ + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + /* Program the RxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + writeb(type, &musbr->rxtype); + + /* Write the maximum packet size to the RxMaxp register */ + writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? + (len-txlen) : dev->epmaxpacketin[ep]; + + /* Set the ReqPkt bit */ + writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); + + /* Wait until the RxPktRdy bit is set */ + if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + dev->act_len = txlen; + return 0; + } + + /* Read the data from the FIFO */ + read_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Clear the RxPktRdy bit */ + csr = readw(&musbr->rxcsr); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + } + + /* bulk transfer is complete */ + dev->status = 0; + dev->act_len = len; + return 0; +} + +/* + * This function initializes the usb controller module. + */ +int usb_lowlevel_init(void) +{ + u8 power; + u32 timeout; + + if (musb_platform_init() == -1) + return -1; + + /* Configure all the endpoint FIFO's and start usb controller */ + musbr = musb_cfg.regs; + musb_configure_ep(&epinfo[0], + sizeof(epinfo) / sizeof(struct musb_epinfo)); + musb_start(); + + /* + * Wait until musb is enabled in host mode with a timeout. There + * should be a usb device connected. + */ + timeout = musb_cfg.timeout; + while (timeout--) + if (readb(&musbr->devctl) & MUSB_DEVCTL_HM) + break; + + /* if musb core is not in host mode, then return */ + if (!timeout) + return -1; + + /* start usb bus reset */ + power = readb(&musbr->power); + writeb(power | MUSB_POWER_RESET, &musbr->power); + + /* After initiating a usb reset, wait for about 20ms to 30ms */ + udelay(30000); + + /* stop usb bus reset */ + power = readb(&musbr->power); + power &= ~MUSB_POWER_RESET; + writeb(power, &musbr->power); + + /* Determine if the connected device is a high/full/low speed device */ + musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ? + MUSB_TYPE_SPEED_HIGH : + ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ? + MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); + return 0; +} + +/* + * This function stops the operation of the davinci usb module. + */ +int usb_lowlevel_stop(void) +{ + /* Reset the USB module */ + musb_platform_deinit(); + writeb(0, &musbr->devctl); + return 0; +} + +/* + * This function supports usb interrupt transfers. Currently, usb interrupt + * transfers are not supported. + */ +int submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len, int interval) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int devnum = usb_pipedevice(pipe); + u8 type; + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 devspeed; + + /* select interrupt endpoint */ + writeb(MUSB_INTR_EP, &musbr->index); + + /* write the address of the device */ + if (dir_out) + writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr); + else + writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + /* + * MUSB is in high speed and the destination device is full + * speed device. So configure the hub address and port + * address registers. + */ + config_hub_port(dev, MUSB_INTR_EP); + } else { + if (dir_out) { + writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr); + writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport); + } else { + writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr); + writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport); + } + devspeed = musb_cfg.musb_speed; + } + + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + if (!dir_out) { /* intrrupt-in transfer */ + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + writeb(interval, &musbr->rxinterval); + + /* Program the RxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + writeb(type, &musbr->rxtype); + + /* Write the maximum packet size to the RxMaxp register */ + writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); + + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? + (len-txlen) : dev->epmaxpacketin[ep]; + + /* Set the ReqPkt bit */ + writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); + + /* Wait until the RxPktRdy bit is set */ + if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + dev->act_len = txlen; + return 0; + } + + /* Read the data from the FIFO */ + read_fifo(MUSB_INTR_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Clear the RxPktRdy bit */ + csr = readw(&musbr->rxcsr); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + } + + /* interrupt transfer is complete */ + dev->irq_status = 0; + dev->irq_act_len = len; + dev->irq_handle(dev); + dev->status = 0; + dev->act_len = len; + return 0; +} + + +#ifdef CONFIG_SYS_USB_EVENT_POLL +/* + * This function polls for USB keyboard data. + */ +void usb_event_poll() +{ + device_t *dev; + struct usb_device *usb_kbd_dev; + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int pipe; + int maxp; + + /* Get the pointer to USB Keyboard device pointer */ + dev = device_get_by_name("usbkbd"); + usb_kbd_dev = (struct usb_device *)dev->priv; + iface = &usb_kbd_dev->config.if_desc[0]; + ep = &iface->ep_desc[0]; + pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress); + + /* Submit a interrupt transfer request */ + maxp = usb_maxpacket(usb_kbd_dev, pipe); + usb_submit_int_msg(usb_kbd_dev, pipe, &new[0], + maxp > 8 ? 8 : maxp, ep->bInterval); +} +#endif /* CONFIG_SYS_USB_EVENT_POLL */ diff --git a/drivers/usb/musb_hcd.h b/drivers/usb/musb_hcd.h new file mode 100644 index 000000000..bb83311b0 --- /dev/null +++ b/drivers/usb/musb_hcd.h @@ -0,0 +1,51 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + */ + +#ifndef __MUSB_HCD_H__ +#define __MUSB_HCD_H__ + +#include "musb_core.h" +#ifdef CONFIG_USB_KEYBOARD +#include <devices.h> +extern unsigned char new[]; +#endif + +/* This defines the endpoint number used for control transfers */ +#define MUSB_CONTROL_EP 0 + +/* This defines the endpoint number used for bulk transfer */ +#define MUSB_BULK_EP 1 + +/* This defines the endpoint number used for interrupt transfer */ +#define MUSB_INTR_EP 2 + +/* Determine the operating speed of MUSB core */ +#define musb_ishighspeed() \ + ((readb(&musbr->power) & MUSB_POWER_HSMODE) \ + >> MUSB_POWER_HSMODE_SHIFT) + +/* extern functions */ +extern int musb_platform_init(void); +extern void musb_platform_deinit(void); + +#endif /* __MUSB_HCD_H__ */ diff --git a/drivers/usb/usb_ehci.h b/drivers/usb/usb_ehci.h new file mode 100644 index 000000000..b3c1d5d72 --- /dev/null +++ b/drivers/usb/usb_ehci.h @@ -0,0 +1,194 @@ +/*- + * Copyright (c) 2007-2008, Juniper Networks, Inc. + * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef USB_EHCI_H +#define USB_EHCI_H + +#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#endif + +/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */ +#define DeviceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define DeviceOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8) + +#define InterfaceRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointRequest \ + ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +#define EndpointOutRequest \ + ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8) + +/* + * Register Space. + */ +struct ehci_hccr { + uint32_t cr_capbase; +#define HC_LENGTH(p) (((p) >> 0) & 0x00ff) +#define HC_VERSION(p) (((p) >> 16) & 0xffff) + uint32_t cr_hcsparams; +#define HCS_PPC(p) ((p) & (1 << 4)) +#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */ +#define HCS_N_PORTS(p) (((p) >> 0) & 0xf) + uint32_t cr_hccparams; + uint8_t cr_hcsp_portrt[8]; +} __attribute__ ((packed)); + +struct ehci_hcor { + uint32_t or_usbcmd; +#define CMD_PARK (1 << 11) /* enable "park" */ +#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */ +#define CMD_ASE (1 << 5) /* async schedule enable */ +#define CMD_LRESET (1 << 7) /* partial reset */ +#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */ +#define CMD_PSE (1 << 4) /* periodic schedule enable */ +#define CMD_RESET (1 << 1) /* reset HC not bus */ +#define CMD_RUN (1 << 0) /* start/stop HC */ + uint32_t or_usbsts; +#define STD_ASS (1 << 15) +#define STS_HALT (1 << 12) + uint32_t or_usbintr; + uint32_t or_frindex; + uint32_t or_ctrldssegment; + uint32_t or_periodiclistbase; + uint32_t or_asynclistaddr; + uint32_t _reserved_[9]; + uint32_t or_configflag; +#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ + uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS]; + uint32_t or_systune; +} __attribute__ ((packed)); + +#define USBMODE 0x68 /* USB Device mode */ +#define USBMODE_SDIS (1 << 3) /* Stream disable */ +#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */ +#define USBMODE_CM_HC (3 << 0) /* host controller mode */ +#define USBMODE_CM_IDLE (0 << 0) /* idle state */ + +/* Interface descriptor */ +struct usb_linux_interface_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned char bInterfaceNumber; + unsigned char bAlternateSetting; + unsigned char bNumEndpoints; + unsigned char bInterfaceClass; + unsigned char bInterfaceSubClass; + unsigned char bInterfaceProtocol; + unsigned char iInterface; +} __attribute__ ((packed)); + +/* Configuration descriptor information.. */ +struct usb_linux_config_descriptor { + unsigned char bLength; + unsigned char bDescriptorType; + unsigned short wTotalLength; + unsigned char bNumInterfaces; + unsigned char bConfigurationValue; + unsigned char iConfiguration; + unsigned char bmAttributes; + unsigned char MaxPower; +} __attribute__ ((packed)); + +#if defined CONFIG_EHCI_DESC_BIG_ENDIAN +#define ehci_readl(x) (*((volatile u32 *)(x))) +#define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b)) +#else +#define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x)))) +#define ehci_writel(a, b) (*((volatile u32 *)(a)) = \ + cpu_to_le32(((volatile u32)b))) +#endif + +#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN +#define hc32_to_cpu(x) be32_to_cpu((x)) +#define cpu_to_hc32(x) cpu_to_be32((x)) +#else +#define hc32_to_cpu(x) le32_to_cpu((x)) +#define cpu_to_hc32(x) cpu_to_le32((x)) +#endif + +#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */ +#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */ +#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */ +#define EHCI_PS_PO (1 << 13) /* RW port owner */ +#define EHCI_PS_PP (1 << 12) /* RW,RO port power */ +#define EHCI_PS_LS (3 << 10) /* RO line status */ +#define EHCI_PS_PR (1 << 8) /* RW port reset */ +#define EHCI_PS_SUSP (1 << 7) /* RW suspend */ +#define EHCI_PS_FPR (1 << 6) /* RW force port resume */ +#define EHCI_PS_OCC (1 << 5) /* RWC over current change */ +#define EHCI_PS_OCA (1 << 4) /* RO over current active */ +#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */ +#define EHCI_PS_PE (1 << 2) /* RW port enable */ +#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */ +#define EHCI_PS_CS (1 << 0) /* RO connect status */ +#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) + +#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10)) + +/* + * Schedule Interface Space. + * + * IMPORTANT: Software must ensure that no interface data structure + * reachable by the EHCI host controller spans a 4K page boundary! + * + * Periodic transfers (i.e. isochronous and interrupt transfers) are + * not supported. + */ + +/* Queue Element Transfer Descriptor (qTD). */ +struct qTD { + uint32_t qt_next; +#define QT_NEXT_TERMINATE 1 + uint32_t qt_altnext; + uint32_t qt_token; + uint32_t qt_buffer[5]; +}; + +/* Queue Head (QH). */ +struct QH { + uint32_t qh_link; +#define QH_LINK_TERMINATE 1 +#define QH_LINK_TYPE_ITD 0 +#define QH_LINK_TYPE_QH 2 +#define QH_LINK_TYPE_SITD 4 +#define QH_LINK_TYPE_FSTN 6 + uint32_t qh_endpt1; + uint32_t qh_endpt2; + uint32_t qh_curtd; + struct qTD qh_overlay; + /* + * Add dummy fill value to make the size of this struct + * aligned to 32 bytes + */ + uint8_t fill[16]; +}; + +/* Low level init functions */ +int ehci_hcd_init(void); +int ehci_hcd_stop(void); + +#endif /* USB_EHCI_H */ diff --git a/drivers/usb/usb_ehci_core.c b/drivers/usb/usb_ehci_core.c new file mode 100644 index 000000000..813f64abd --- /dev/null +++ b/drivers/usb/usb_ehci_core.c @@ -0,0 +1,880 @@ +/*- + * Copyright (c) 2007-2008, Juniper Networks, Inc. + * Copyright (c) 2008, Excito Elektronik i SkÃ¥ne AB + * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it> + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/byteorder.h> +#include <usb.h> +#include <asm/io.h> +#include <malloc.h> +#include "usb_ehci.h" + +int rootdev; +struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ +volatile struct ehci_hcor *hcor; + +static uint16_t portreset; +static struct QH qh_list __attribute__((aligned(32))); + +static struct descriptor { + struct usb_hub_descriptor hub; + struct usb_device_descriptor device; + struct usb_linux_config_descriptor config; + struct usb_linux_interface_descriptor interface; + struct usb_endpoint_descriptor endpoint; +} __attribute__ ((packed)) descriptor = { + { + 0x8, /* bDescLength */ + 0x29, /* bDescriptorType: hub descriptor */ + 2, /* bNrPorts -- runtime modified */ + 0, /* wHubCharacteristics */ + 0xff, /* bPwrOn2PwrGood */ + 0, /* bHubCntrCurrent */ + {}, /* Device removable */ + {} /* at most 7 ports! XXX */ + }, + { + 0x12, /* bLength */ + 1, /* bDescriptorType: UDESC_DEVICE */ + 0x0002, /* bcdUSB: v2.0 */ + 9, /* bDeviceClass: UDCLASS_HUB */ + 0, /* bDeviceSubClass: UDSUBCLASS_HUB */ + 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */ + 64, /* bMaxPacketSize: 64 bytes */ + 0x0000, /* idVendor */ + 0x0000, /* idProduct */ + 0x0001, /* bcdDevice */ + 1, /* iManufacturer */ + 2, /* iProduct */ + 0, /* iSerialNumber */ + 1 /* bNumConfigurations: 1 */ + }, + { + 0x9, + 2, /* bDescriptorType: UDESC_CONFIG */ + cpu_to_le16(0x19), + 1, /* bNumInterface */ + 1, /* bConfigurationValue */ + 0, /* iConfiguration */ + 0x40, /* bmAttributes: UC_SELF_POWER */ + 0 /* bMaxPower */ + }, + { + 0x9, /* bLength */ + 4, /* bDescriptorType: UDESC_INTERFACE */ + 0, /* bInterfaceNumber */ + 0, /* bAlternateSetting */ + 1, /* bNumEndpoints */ + 9, /* bInterfaceClass: UICLASS_HUB */ + 0, /* bInterfaceSubClass: UISUBCLASS_HUB */ + 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */ + 0 /* iInterface */ + }, + { + 0x7, /* bLength */ + 5, /* bDescriptorType: UDESC_ENDPOINT */ + 0x81, /* bEndpointAddress: + * UE_DIR_IN | EHCI_INTR_ENDPT + */ + 3, /* bmAttributes: UE_INTERRUPT */ + 8, 0, /* wMaxPacketSize */ + 255 /* bInterval */ + }, +}; + +#if defined(CONFIG_EHCI_IS_TDI) +#define ehci_is_TDI() (1) +#else +#define ehci_is_TDI() (0) +#endif + +#if defined(CONFIG_EHCI_DCACHE) +/* + * Routines to handle (flush/invalidate) the dcache for the QH and qTD + * structures and data buffers. This is needed on platforms using this + * EHCI support with dcache enabled. + */ +static void flush_invalidate(u32 addr, int size, int flush) +{ + if (flush) + flush_dcache_range(addr, addr + size); + else + invalidate_dcache_range(addr, addr + size); +} + +static void cache_qtd(struct qTD *qtd, int flush) +{ + u32 *ptr = (u32 *)qtd->qt_buffer[0]; + int len = (qtd->qt_token & 0x7fff0000) >> 16; + + flush_invalidate((u32)qtd, sizeof(struct qTD), flush); + if (ptr && len) + flush_invalidate((u32)ptr, len, flush); +} + + +static inline struct QH *qh_addr(struct QH *qh) +{ + return (struct QH *)((u32)qh & 0xffffffe0); +} + +static void cache_qh(struct QH *qh, int flush) +{ + struct qTD *qtd; + struct qTD *next; + static struct qTD *first_qtd; + + /* + * Walk the QH list and flush/invalidate all entries + */ + while (1) { + flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush); + if ((u32)qh & QH_LINK_TYPE_QH) + break; + qh = qh_addr(qh); + qh = (struct QH *)qh->qh_link; + } + qh = qh_addr(qh); + + /* + * Save first qTD pointer, needed for invalidating pass on this QH + */ + if (flush) + first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay & + 0xffffffe0); + else + qtd = first_qtd; + + /* + * Walk the qTD list and flush/invalidate all entries + */ + while (1) { + if (qtd == NULL) + break; + cache_qtd(qtd, flush); + next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0); + if (next == qtd) + break; + qtd = next; + } +} + +static inline void ehci_flush_dcache(struct QH *qh) +{ + cache_qh(qh, 1); +} + +static inline void ehci_invalidate_dcache(struct QH *qh) +{ + cache_qh(qh, 0); +} +#else /* CONFIG_EHCI_DCACHE */ +/* + * + */ +static inline void ehci_flush_dcache(struct QH *qh) +{ +} + +static inline void ehci_invalidate_dcache(struct QH *qh) +{ +} +#endif /* CONFIG_EHCI_DCACHE */ + +static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec) +{ + uint32_t result; + do { + result = ehci_readl(ptr); + if (result == ~(uint32_t)0) + return -1; + result &= mask; + if (result == done) + return 0; + udelay(1); + usec--; + } while (usec > 0); + return -1; +} + +static void ehci_free(void *p, size_t sz) +{ + +} + +static int ehci_reset(void) +{ + uint32_t cmd; + uint32_t tmp; + uint32_t *reg_ptr; + int ret = 0; + + cmd = ehci_readl(&hcor->or_usbcmd); + cmd |= CMD_RESET; + ehci_writel(&hcor->or_usbcmd, cmd); + ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000); + if (ret < 0) { + printf("EHCI fail to reset\n"); + goto out; + } + + if (ehci_is_TDI()) { + reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE); + tmp = ehci_readl(reg_ptr); + tmp |= USBMODE_CM_HC; +#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN) + tmp |= USBMODE_BE; +#endif + ehci_writel(reg_ptr, tmp); + } +out: + return ret; +} + +static void *ehci_alloc(size_t sz, size_t align) +{ + static struct QH qh __attribute__((aligned(32))); + static struct qTD td[3] __attribute__((aligned (32))); + static int ntds; + void *p; + + switch (sz) { + case sizeof(struct QH): + p = &qh; + ntds = 0; + break; + case sizeof(struct qTD): + if (ntds == 3) { + debug("out of TDs\n"); + return NULL; + } + p = &td[ntds]; + ntds++; + break; + default: + debug("unknown allocation size\n"); + return NULL; + } + + memset(p, sz, 0); + return p; +} + +static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz) +{ + uint32_t addr, delta, next; + int idx; + + addr = (uint32_t) buf; + idx = 0; + while (idx < 5) { + td->qt_buffer[idx] = cpu_to_hc32(addr); + next = (addr + 4096) & ~4095; + delta = next - addr; + if (delta >= sz) + break; + sz -= delta; + addr = next; + idx++; + } + + if (idx == 5) { + debug("out of buffer pointers (%u bytes left)\n", sz); + return -1; + } + + return 0; +} + +static int +ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, struct devrequest *req) +{ + struct QH *qh; + struct qTD *td; + volatile struct qTD *vtd; + unsigned long ts; + uint32_t *tdp; + uint32_t endpt, token, usbsts; + uint32_t c, toggle; + uint32_t cmd; + int ret = 0; + + debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe, + buffer, length, req); + if (req != NULL) + debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", + req->request, req->request, + req->requesttype, req->requesttype, + le16_to_cpu(req->value), le16_to_cpu(req->value), + le16_to_cpu(req->index)); + + qh = ehci_alloc(sizeof(struct QH), 32); + if (qh == NULL) { + debug("unable to allocate QH\n"); + return -1; + } + qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); + c = (usb_pipespeed(pipe) != USB_SPEED_HIGH && + usb_pipeendpoint(pipe) == 0) ? 1 : 0; + endpt = (8 << 28) | + (c << 27) | + (usb_maxpacket(dev, pipe) << 16) | + (0 << 15) | + (1 << 14) | + (usb_pipespeed(pipe) << 12) | + (usb_pipeendpoint(pipe) << 8) | + (0 << 7) | (usb_pipedevice(pipe) << 0); + qh->qh_endpt1 = cpu_to_hc32(endpt); + endpt = (1 << 30) | + (dev->portnr << 23) | + (dev->parent->devnum << 16) | (0 << 8) | (0 << 0); + qh->qh_endpt2 = cpu_to_hc32(endpt); + qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + + td = NULL; + tdp = &qh->qh_overlay.qt_next; + + toggle = + usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)); + + if (req != NULL) { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) { + debug("unable to allocate SETUP td\n"); + goto fail; + } + td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + token = (0 << 31) | + (sizeof(*req) << 16) | + (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0); + td->qt_token = cpu_to_hc32(token); + if (ehci_td_buffer(td, req, sizeof(*req)) != 0) { + debug("unable construct SETUP td\n"); + ehci_free(td, sizeof(*td)); + goto fail; + } + *tdp = cpu_to_hc32((uint32_t) td); + tdp = &td->qt_next; + toggle = 1; + } + + if (length > 0 || req == NULL) { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) { + debug("unable to allocate DATA td\n"); + goto fail; + } + td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + token = (toggle << 31) | + (length << 16) | + ((req == NULL ? 1 : 0) << 15) | + (0 << 12) | + (3 << 10) | + ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0); + td->qt_token = cpu_to_hc32(token); + if (ehci_td_buffer(td, buffer, length) != 0) { + debug("unable construct DATA td\n"); + ehci_free(td, sizeof(*td)); + goto fail; + } + *tdp = cpu_to_hc32((uint32_t) td); + tdp = &td->qt_next; + } + + if (req != NULL) { + td = ehci_alloc(sizeof(struct qTD), 32); + if (td == NULL) { + debug("unable to allocate ACK td\n"); + goto fail; + } + td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + token = (toggle << 31) | + (0 << 16) | + (1 << 15) | + (0 << 12) | + (3 << 10) | + ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0); + td->qt_token = cpu_to_hc32(token); + *tdp = cpu_to_hc32((uint32_t) td); + tdp = &td->qt_next; + } + + qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH); + + /* Flush dcache */ + ehci_flush_dcache(&qh_list); + + usbsts = ehci_readl(&hcor->or_usbsts); + ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f)); + + /* Enable async. schedule. */ + cmd = ehci_readl(&hcor->or_usbcmd); + cmd |= CMD_ASE; + ehci_writel(&hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS, + 100 * 1000); + if (ret < 0) { + printf("EHCI fail timeout STD_ASS set\n"); + goto fail; + } + + /* Wait for TDs to be processed. */ + ts = get_timer(0); + vtd = td; + do { + /* Invalidate dcache */ + ehci_invalidate_dcache(&qh_list); + token = hc32_to_cpu(vtd->qt_token); + if (!(token & 0x80)) + break; + } while (get_timer(ts) < CONFIG_SYS_HZ); + + /* Disable async schedule. */ + cmd = ehci_readl(&hcor->or_usbcmd); + cmd &= ~CMD_ASE; + ehci_writel(&hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0, + 100 * 1000); + if (ret < 0) { + printf("EHCI fail timeout STD_ASS reset\n"); + goto fail; + } + + qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); + + token = hc32_to_cpu(qh->qh_overlay.qt_token); + if (!(token & 0x80)) { + debug("TOKEN=%#x\n", token); + switch (token & 0xfc) { + case 0: + toggle = token >> 31; + usb_settoggle(dev, usb_pipeendpoint(pipe), + usb_pipeout(pipe), toggle); + dev->status = 0; + break; + case 0x40: + dev->status = USB_ST_STALLED; + break; + case 0xa0: + case 0x20: + dev->status = USB_ST_BUF_ERR; + break; + case 0x50: + case 0x10: + dev->status = USB_ST_BABBLE_DET; + break; + default: + dev->status = USB_ST_CRC_ERR; + break; + } + dev->act_len = length - ((token >> 16) & 0x7fff); + } else { + dev->act_len = 0; + debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", + dev->devnum, ehci_readl(&hcor->or_usbsts), + ehci_readl(&hcor->or_portsc[0]), + ehci_readl(&hcor->or_portsc[1])); + } + + return (dev->status != USB_ST_NOT_PROC) ? 0 : -1; + +fail: + td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); + while (td != (void *)QT_NEXT_TERMINATE) { + qh->qh_overlay.qt_next = td->qt_next; + ehci_free(td, sizeof(*td)); + td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next); + } + ehci_free(qh, sizeof(*qh)); + return -1; +} + +static inline int min3(int a, int b, int c) +{ + + if (b < a) + a = b; + if (c < a) + a = c; + return a; +} + +int +ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, struct devrequest *req) +{ + uint8_t tmpbuf[4]; + u16 typeReq; + void *srcptr = NULL; + int len, srclen; + uint32_t reg; + uint32_t *status_reg; + + if (le16_to_cpu(req->index) >= CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) { + printf("The request port(%d) is not configured\n", + le16_to_cpu(req->index) - 1); + return -1; + } + status_reg = (uint32_t *)&hcor->or_portsc[ + le16_to_cpu(req->index) - 1]; + srclen = 0; + + debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n", + req->request, req->request, + req->requesttype, req->requesttype, + le16_to_cpu(req->value), le16_to_cpu(req->index)); + + typeReq = req->request << 8 | req->requesttype; + + switch (le16_to_cpu(typeReq)) { + case DeviceRequest | USB_REQ_GET_DESCRIPTOR: + switch (le16_to_cpu(req->value) >> 8) { + case USB_DT_DEVICE: + debug("USB_DT_DEVICE request\n"); + srcptr = &descriptor.device; + srclen = 0x12; + break; + case USB_DT_CONFIG: + debug("USB_DT_CONFIG config\n"); + srcptr = &descriptor.config; + srclen = 0x19; + break; + case USB_DT_STRING: + debug("USB_DT_STRING config\n"); + switch (le16_to_cpu(req->value) & 0xff) { + case 0: /* Language */ + srcptr = "\4\3\1\0"; + srclen = 4; + break; + case 1: /* Vendor */ + srcptr = "\16\3u\0-\0b\0o\0o\0t\0"; + srclen = 14; + break; + case 2: /* Product */ + srcptr = "\52\3E\0H\0C\0I\0 " + "\0H\0o\0s\0t\0 " + "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0"; + srclen = 42; + break; + default: + debug("unknown value DT_STRING %x\n", + le16_to_cpu(req->value)); + goto unknown; + } + break; + default: + debug("unknown value %x\n", le16_to_cpu(req->value)); + goto unknown; + } + break; + case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8): + switch (le16_to_cpu(req->value) >> 8) { + case USB_DT_HUB: + debug("USB_DT_HUB config\n"); + srcptr = &descriptor.hub; + srclen = 0x8; + break; + default: + debug("unknown value %x\n", le16_to_cpu(req->value)); + goto unknown; + } + break; + case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8): + debug("USB_REQ_SET_ADDRESS\n"); + rootdev = le16_to_cpu(req->value); + break; + case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: + debug("USB_REQ_SET_CONFIGURATION\n"); + /* Nothing to do */ + break; + case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8): + tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */ + tmpbuf[1] = 0; + srcptr = tmpbuf; + srclen = 2; + break; + case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8): + memset(tmpbuf, 0, 4); + reg = ehci_readl(status_reg); + if (reg & EHCI_PS_CS) + tmpbuf[0] |= USB_PORT_STAT_CONNECTION; + if (reg & EHCI_PS_PE) + tmpbuf[0] |= USB_PORT_STAT_ENABLE; + if (reg & EHCI_PS_SUSP) + tmpbuf[0] |= USB_PORT_STAT_SUSPEND; + if (reg & EHCI_PS_OCA) + tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT; + if (reg & EHCI_PS_PR && + (portreset & (1 << le16_to_cpu(req->index)))) { + int ret; + /* force reset to complete */ + reg = reg & ~(EHCI_PS_PR | EHCI_PS_CLEAR); + ehci_writel(status_reg, reg); + ret = handshake(status_reg, EHCI_PS_PR, 0, 2 * 1000); + if (!ret) + tmpbuf[0] |= USB_PORT_STAT_RESET; + else + printf("port(%d) reset error\n", + le16_to_cpu(req->index) - 1); + } + if (reg & EHCI_PS_PP) + tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; + + if (ehci_is_TDI()) { + switch ((reg >> 26) & 3) { + case 0: + break; + case 1: + tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; + break; + case 2: + default: + tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; + break; + } + } else { + tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; + } + + if (reg & EHCI_PS_CSC) + tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; + if (reg & EHCI_PS_PEC) + tmpbuf[2] |= USB_PORT_STAT_C_ENABLE; + if (reg & EHCI_PS_OCC) + tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT; + if (portreset & (1 << le16_to_cpu(req->index))) + tmpbuf[2] |= USB_PORT_STAT_C_RESET; + + srcptr = tmpbuf; + srclen = 4; + break; + case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = ehci_readl(status_reg); + reg &= ~EHCI_PS_CLEAR; + switch (le16_to_cpu(req->value)) { + case USB_PORT_FEAT_ENABLE: + reg |= EHCI_PS_PE; + ehci_writel(status_reg, reg); + break; + case USB_PORT_FEAT_POWER: + if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) { + reg |= EHCI_PS_PP; + ehci_writel(status_reg, reg); + } + break; + case USB_PORT_FEAT_RESET: + if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS && + !ehci_is_TDI() && + EHCI_PS_IS_LOWSPEED(reg)) { + /* Low speed device, give up ownership. */ + debug("port %d low speed --> companion\n", + req->index - 1); + reg |= EHCI_PS_PO; + ehci_writel(status_reg, reg); + break; + } else { + reg |= EHCI_PS_PR; + reg &= ~EHCI_PS_PE; + ehci_writel(status_reg, reg); + /* + * caller must wait, then call GetPortStatus + * usb 2.0 specification say 50 ms resets on + * root + */ + wait_ms(50); + portreset |= 1 << le16_to_cpu(req->index); + } + break; + default: + debug("unknown feature %x\n", le16_to_cpu(req->value)); + goto unknown; + } + /* unblock posted writes */ + ehci_readl(&hcor->or_usbcmd); + break; + case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8): + reg = ehci_readl(status_reg); + switch (le16_to_cpu(req->value)) { + case USB_PORT_FEAT_ENABLE: + reg &= ~EHCI_PS_PE; + break; + case USB_PORT_FEAT_C_ENABLE: + reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE; + break; + case USB_PORT_FEAT_POWER: + if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) + reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP); + case USB_PORT_FEAT_C_CONNECTION: + reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC; + break; + case USB_PORT_FEAT_OVER_CURRENT: + reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC; + break; + case USB_PORT_FEAT_C_RESET: + portreset &= ~(1 << le16_to_cpu(req->index)); + break; + default: + debug("unknown feature %x\n", le16_to_cpu(req->value)); + goto unknown; + } + ehci_writel(status_reg, reg); + /* unblock posted write */ + ehci_readl(&hcor->or_usbcmd); + break; + default: + debug("Unknown request\n"); + goto unknown; + } + + wait_ms(1); + len = min3(srclen, le16_to_cpu(req->length), length); + if (srcptr != NULL && len > 0) + memcpy(buffer, srcptr, len); + else + debug("Len is 0\n"); + + dev->act_len = len; + dev->status = 0; + return 0; + +unknown: + debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n", + req->requesttype, req->request, le16_to_cpu(req->value), + le16_to_cpu(req->index), le16_to_cpu(req->length)); + + dev->act_len = 0; + dev->status = USB_ST_STALLED; + return -1; +} + +int usb_lowlevel_stop(void) +{ + return ehci_hcd_stop(); +} + +int usb_lowlevel_init(void) +{ + uint32_t reg; + uint32_t cmd; + + if (ehci_hcd_init() != 0) + return -1; + + /* EHCI spec section 4.1 */ + if (ehci_reset() != 0) + return -1; + +#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) + if (ehci_hcd_init() != 0) + return -1; +#endif + + /* Set head of reclaim list */ + memset(&qh_list, 0, sizeof(qh_list)); + qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); + qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12)); + qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE); + qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40); + + /* Set async. queue head pointer. */ + ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list); + + reg = ehci_readl(&hccr->cr_hcsparams); + descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); + printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); + /* Port Indicators */ + if (HCS_INDICATOR(reg)) + descriptor.hub.wHubCharacteristics |= 0x80; + /* Port Power Control */ + if (HCS_PPC(reg)) + descriptor.hub.wHubCharacteristics |= 0x01; + + /* Start the host controller. */ + cmd = ehci_readl(&hcor->or_usbcmd); + /* Philips, Intel, and maybe others need CMD_RUN before the + * root hub will detect new devices (why?); NEC doesn't */ + cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); + cmd |= CMD_RUN; + ehci_writel(&hcor->or_usbcmd, cmd); + + /* take control over the ports */ + cmd = ehci_readl(&hcor->or_configflag); + cmd |= FLAG_CF; + ehci_writel(&hcor->or_configflag, cmd); + /* unblock posted write */ + cmd = ehci_readl(&hcor->or_usbcmd); + wait_ms(5); + reg = HC_VERSION(ehci_readl(&hccr->cr_capbase)); + printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff); + + rootdev = 0; + + return 0; +} + +int +submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int length) +{ + + if (usb_pipetype(pipe) != PIPE_BULK) { + debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe)); + return -1; + } + return ehci_submit_async(dev, pipe, buffer, length, NULL); +} + +int +submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, struct devrequest *setup) +{ + + if (usb_pipetype(pipe) != PIPE_CONTROL) { + debug("non-control pipe (type=%lu)", usb_pipetype(pipe)); + return -1; + } + + if (usb_pipedevice(pipe) == rootdev) { + if (rootdev == 0) + dev->speed = USB_SPEED_HIGH; + return ehci_submit_root(dev, pipe, buffer, length, setup); + } + return ehci_submit_async(dev, pipe, buffer, length, setup); +} + +int +submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int length, int interval) +{ + + debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", + dev, pipe, buffer, length, interval); + return -1; +} diff --git a/drivers/usb/usb_ehci_core.h b/drivers/usb/usb_ehci_core.h new file mode 100644 index 000000000..39e5c5e58 --- /dev/null +++ b/drivers/usb/usb_ehci_core.h @@ -0,0 +1,29 @@ +/*- + * Copyright (c) 2007-2008, Juniper Networks, Inc. + * Copyright (c) 2008, Excito Elektronik i SkÃ¥ne AB + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef USB_EHCI_CORE_H +#define USB_EHCI_CORE_H + +extern int rootdev; +extern struct ehci_hccr *hccr; +extern volatile struct ehci_hcor *hcor; + +#endif diff --git a/drivers/usb/usb_ehci_fsl.c b/drivers/usb/usb_ehci_fsl.c new file mode 100644 index 000000000..81d5d2165 --- /dev/null +++ b/drivers/usb/usb_ehci_fsl.c @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB + * + * Author: Tor Krill tor@excito.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <usb.h> +#include <mpc83xx.h> +#include <asm/io.h> +#include <asm/bitops.h> + +#include "usb_ehci.h" +#include "usb_ehci_fsl.h" +#include "usb_ehci_core.h" + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + * + * Excerpts from linux ehci fsl driver. + */ +int ehci_hcd_init(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + uint32_t addr, temp; + + addr = (uint32_t)&(im->usb[0]); + hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + /* Configure clock */ + clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK, + MPC83XX_SCCR_USB_DRCM_11); + + /* Confgure interface. */ + temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); + out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp + | REFSEL_16MHZ | UTMI_PHY_EN); + + /* Wait for clock to stabilize */ + do { + temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); + udelay(1000); + } while (!(temp & PHY_CLK_VALID)); + + /* Set to Host mode */ + temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE)); + out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST); + + out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB); + out_be32((void *)(addr + FSL_SOC_USB_SNOOP2), + 0x80000000 | SNOOP_SIZE_2GB); + + /* Init phy */ + /* TODO: handle different phys? */ + out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + + /* Enable interface. */ + temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); + out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN); + + out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c); + out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040); + out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001); + + /* Enable interface. */ + temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL)); + out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN); + + temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE)); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + return 0; +} diff --git a/drivers/usb/usb_ehci_fsl.h b/drivers/usb/usb_ehci_fsl.h new file mode 100644 index 000000000..c429af125 --- /dev/null +++ b/drivers/usb/usb_ehci_fsl.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2005 freescale semiconductor + * Copyright (c) 2005 MontaVista Software + * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _EHCI_FSL_H +#define _EHCI_FSL_H + +/* Global offsets */ +#define FSL_SKIP_PCI 0x100 + +/* offsets for the non-ehci registers in the FSL SOC USB controller */ +#define FSL_SOC_USB_ULPIVP 0x170 +#define FSL_SOC_USB_PORTSC1 0x184 +#define PORT_PTS_MSK (3 << 30) +#define PORT_PTS_UTMI (0 << 30) +#define PORT_PTS_ULPI (2 << 30) +#define PORT_PTS_SERIAL (3 << 30) +#define PORT_PTS_PTW (1 << 28) + +/* USBMODE Register bits */ +#define CM_IDLE (0 << 0) +#define CM_RESERVED (1 << 0) +#define CM_DEVICE (2 << 0) +#define CM_HOST (3 << 0) +#define USBMODE_RESERVED_2 (0 << 2) +#define SLOM (1 << 3) +#define SDIS (1 << 4) + +/* CONTROL Register bits */ +#define ULPI_INT_EN (1 << 0) +#define WU_INT_EN (1 << 1) +#define USB_EN (1 << 2) +#define LSF_EN (1 << 3) +#define KEEP_OTG_ON (1 << 4) +#define OTG_PORT (1 << 5) +#define REFSEL_12MHZ (0 << 6) +#define REFSEL_16MHZ (1 << 6) +#define REFSEL_48MHZ (2 << 6) +#define PLL_RESET (1 << 8) +#define UTMI_PHY_EN (1 << 9) +#define PHY_CLK_SEL_UTMI (0 << 10) +#define PHY_CLK_SEL_ULPI (1 << 10) +#define CLKIN_SEL_USB_CLK (0 << 11) +#define CLKIN_SEL_USB_CLK2 (1 << 11) +#define CLKIN_SEL_SYS_CLK (2 << 11) +#define CLKIN_SEL_SYS_CLK2 (3 << 11) +#define RESERVED_18 (0 << 13) +#define RESERVED_17 (0 << 14) +#define RESERVED_16 (0 << 15) +#define WU_INT (1 << 16) +#define PHY_CLK_VALID (1 << 17) + +#define FSL_SOC_USB_PORTSC2 0x188 +#define FSL_SOC_USB_USBMODE 0x1a8 +#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ +#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ +#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ +#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ +#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ +#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ +#define SNOOP_SIZE_2GB 0x1e + +/* System Clock Control Register */ +#define MPC83XX_SCCR_USB_MASK 0x00f00000 +#define MPC83XX_SCCR_USB_DRCM_11 0x00300000 +#define MPC83XX_SCCR_USB_DRCM_01 0x00100000 +#define MPC83XX_SCCR_USB_DRCM_10 0x00200000 + +#endif /* _EHCI_FSL_H */ diff --git a/drivers/usb/usb_ehci_ixp.c b/drivers/usb/usb_ehci_ixp.c new file mode 100644 index 000000000..25c18c104 --- /dev/null +++ b/drivers/usb/usb_ehci_ixp.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2008, Michael Trimarchi <trimarchimichael@yahoo.it> + * + * Author: Michael Trimarchi <trimarchimichael@yahoo.it> + * This code is based on ehci freescale driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <usb.h> +#include "usb_ehci.h" +#include "usb_ehci_core.h" +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(void) +{ + hccr = (struct ehci_hccr *)(0xcd000100); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + printf("IXP4XX init hccr %x and hcor %x hc_length %d\n", + (uint32_t)hccr, (uint32_t)hcor, + (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + return 0; +} diff --git a/drivers/usb/usb_ehci_pci.c b/drivers/usb/usb_ehci_pci.c new file mode 100644 index 000000000..3e7143cd9 --- /dev/null +++ b/drivers/usb/usb_ehci_pci.c @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 2007-2008, Juniper Networks, Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> +#include <usb.h> +#include "usb_ehci.h" +#include "usb_ehci_core.h" + +#ifdef CONFIG_PCI_EHCI_DEVICE +static struct pci_device_id ehci_pci_ids[] = { + /* Please add supported PCI EHCI controller ids here */ + {0, 0} +}; +#endif + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(void) +{ + pci_dev_t pdev; + uint32_t addr; + + pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE); + if (pdev == -1) { + printf("EHCI host controller not found\n"); + return -1; + } + + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr); + hccr = (struct ehci_hccr *)addr; + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + return 0; +} diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 28c7805d0..8081ee7a8 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -672,6 +672,7 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) { __u8 block[FS_BLOCK_SIZE]; volume_info *vistart; + char *fstype; if (disk_read(0, 1, block) < 0) { FAT_DPRINT("Error: reading block\n"); @@ -704,9 +705,12 @@ read_bootsectandvi(boot_sector *bs, volume_info *volinfo, int *fatsize) } memcpy(volinfo, vistart, sizeof(volume_info)); - /* Terminate fs_type string. Writing past the end of vistart - is ok - it's just the buffer. */ - vistart->fs_type[8] = '\0'; + /* + * Terminate fs_type string. Writing past the end of vistart + * is ok - it's just the buffer. + */ + fstype = vistart->fs_type; + fstype[8] = '\0'; if (*fatsize == 32) { if (compare_sign(FAT32_SIGN, vistart->fs_type) == 0) { diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h index 0ab68ace7..21abd724f 100644 --- a/include/asm-blackfin/blackfin-config-post.h +++ b/include/asm-blackfin/blackfin-config-post.h @@ -1,7 +1,7 @@ /* * blackfin-config-post.h - setup common defines for Blackfin boards based on config.h * - * Copyright (c) 2007 Analog Devices Inc. + * Copyright (c) 2007-2008 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -9,11 +9,6 @@ #ifndef __ASM_BLACKFIN_CONFIG_POST_H__ #define __ASM_BLACKFIN_CONFIG_POST_H__ -/* Check to make sure everything fits in external RAM */ -#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) -# error Memory Map does not fit into configuration -#endif - /* Sanity check CONFIG_BFIN_CPU */ #ifndef CONFIG_BFIN_CPU # error CONFIG_BFIN_CPU: your board config needs to define this @@ -65,8 +60,81 @@ #endif /* Using L1 scratch pad makes sense for everyone by default. */ -#ifndef CMD_LINE_ADDR -# define CMD_LINE_ADDR L1_SRAM_SCRATCH +#ifndef CONFIG_LINUX_CMDLINE_ADDR +# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH +#endif +#ifndef CONFIG_LINUX_CMDLINE_SIZE +# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE +#endif + +/* Default/common Blackfin memory layout */ +#ifndef CONFIG_SYS_SDRAM_BASE +# define CONFIG_SYS_SDRAM_BASE 0 +#endif +#ifndef CONFIG_SYS_MAX_RAM_SIZE +# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) +#endif +#ifndef CONFIG_SYS_MONITOR_BASE +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) +#endif +#ifndef CONFIG_SYS_MALLOC_BASE +# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#endif +#ifndef CONFIG_SYS_GBL_DATA_SIZE +# define CONFIG_SYS_GBL_DATA_SIZE (128) +#endif +#ifndef CONFIG_SYS_GBL_DATA_ADDR +# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) +#endif +#ifndef CONFIG_STACKBASE +# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4) +#endif +#ifndef CONFIG_SYS_MEMTEST_START +# define CONFIG_SYS_MEMTEST_START 0 +#endif +#ifndef CONFIG_SYS_MEMTEST_END +# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4) +#endif + +/* Check to make sure everything fits in external RAM */ +#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) +# error Memory Map does not fit into configuration +#endif + +/* Default/common Blackfin environment settings */ +#ifndef CONFIG_LOADADDR +# define CONFIG_LOADADDR 0x1000000 +#endif +#ifndef CONFIG_SYS_LOAD_ADDR +# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#endif +#ifndef CONFIG_SYS_BOOTM_LEN +# define CONFIG_SYS_BOOTM_LEN 0x4000000 +#endif +#ifndef CONFIG_SYS_PROMPT +# define CONFIG_SYS_PROMPT "bfin> " +#endif +#ifndef CONFIG_SYS_CBSIZE +# ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 +# else +# define CONFIG_SYS_CBSIZE 256 +# endif +#endif +#ifndef CONFIG_SYS_BARGSIZE +# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#endif +#ifndef CONFIG_SYS_PBSIZE +# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#endif +#ifndef CONFIG_SYS_MAXARGS +# define CONFIG_SYS_MAXARGS 16 +#endif +#ifndef CONFIG_SYS_HZ +# define CONFIG_SYS_HZ 1000 +#endif +#ifndef CONFIG_SYS_BAUDRATE_TABLE +# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif #endif diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h index 6f0e662a9..c9ee91a43 100644 --- a/include/asm-blackfin/blackfin_local.h +++ b/include/asm-blackfin/blackfin_local.h @@ -58,7 +58,7 @@ extern u_long get_sclk(void); extern void blackfin_icache_flush_range(const void *, const void *); extern void blackfin_dcache_flush_range(const void *, const void *); -extern void blackfin_dcache_invalidate_range(const void *, const void *); +extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); /* Use DMA to move data from on chip to external memory. While this is * required for only L1 instruction (it is not directly readable by the diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h index 6cdaa4f89..fb97ff81b 100644 --- a/include/asm-blackfin/mach-common/bits/bootrom.h +++ b/include/asm-blackfin/mach-common/bits/bootrom.h @@ -88,27 +88,42 @@ #define _BOOTROM_REV 0xEF000040 #define _BOOTROM_SESR 0xEF001000 +#define BOOTROM_FOLLOWS_C_ABI 1 + #define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1 -/* Not available on initial BF54x or BF52x */ -#if (defined(__ADSPBF54x__) && __SILICON_REVISION__ < 1) || \ - (defined(__ADSPBF52x__) && __SILICON_REVISION__ < 2) -#define BOOTROM_CAPS_SYSCONTROL 0 -#else -#define BOOTROM_CAPS_SYSCONTROL 1 #endif +#ifndef BOOTROM_FOLLOWS_C_ABI +#define BOOTROM_FOLLOWS_C_ABI 0 #endif - #ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS #define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0 #endif -#ifndef BOOTROM_CAPS_SYSCONTROL -#define BOOTROM_CAPS_SYSCONTROL 0 -#endif + +/* Possible syscontrol action flags */ +#define SYSCTRL_READ 0x00000000 /* read registers */ +#define SYSCTRL_WRITE 0x00000001 /* write registers */ +#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ +#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */ +#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */ +#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ +#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ +#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ +#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ +#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ +#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ +#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ +#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ #ifndef __ASSEMBLY__ +#if BOOTROM_FOLLOWS_C_ABI +# define BOOTROM_CALLED_FUNC_ATTR +#else +# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall)) +#endif + /* Structures for the syscontrol() function */ typedef struct ADI_SYSCTRL_VALUES { uint16_t uwVrCtl; @@ -121,25 +136,26 @@ typedef struct ADI_SYSCTRL_VALUES { #ifndef _BOOTROM_SYSCONTROL #define _BOOTROM_SYSCONTROL 0 #endif -static uint32_t (* const syscontrol)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL; - -#endif /* __ASSEMBLY__ */ - -/* Possible syscontrol action flags */ -#define SYSCTRL_READ 0x00000000 /* read registers */ -#define SYSCTRL_WRITE 0x00000001 /* write registers */ -#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ -#define SYSCTRL_SOFTRESET 0x00000004 /* perform core and system reset */ -#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ -#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ -#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ -#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ -#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ -#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ -#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ -#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ +static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL; -#ifndef __ASSEMBLY__ +/* We need a dedicated function since we need to screw with the stack pointer + * when resetting. The on-chip ROM will save/restore registers on the stack + * when doing a system reset, so the stack cannot be outside of the chip. + */ +__attribute__((__noreturn__)) +static inline void bfrom_SoftReset(void *new_stack) +{ + while (1) + __asm__ __volatile__( + "sp = %[stack];" + "jump (%[bfrom_syscontrol]);" + : : [bfrom_syscontrol] "p"(bfrom_SysControl), + "q0"(SYSCTRL_SOFTRESET), + "q1"(0), + "q2"(NULL), + [stack] "p"(new_stack) + ); +} /* Structures for working with LDRs and boot rom callbacks */ typedef struct ADI_BOOT_HEADER { diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/include/asm-blackfin/mach-common/bits/ebiu.h index ab530ad86..af456fbe9 100644 --- a/include/asm-blackfin/mach-common/bits/ebiu.h +++ b/include/asm-blackfin/mach-common/bits/ebiu.h @@ -410,12 +410,31 @@ /* EBIU_SDSTAT Masks */ #define SDCI 0x0001 /* SDRAM controller is idle */ -#define SDSRA 0x0002 /* SDRAM SDRAM self refresh is active */ +#define SDSRA 0x0002 /* SDRAM self refresh is active */ #define SDPUA 0x0004 /* SDRAM power up active */ #define SDRS 0x0008 /* SDRAM is in reset state */ #define SDEASE 0x0010 /* SDRAM EAB sticky error status - W1C */ #define BGSTAT 0x0020 /* Bus granted */ +/* Only available on DDR based-parts */ +#else + +/* EBIU_ERRMST Masks */ +#define DEB0_ERROR 0x0001 /* DEB0 access on reserved memory */ +#define DEB1_ERROR 0x0002 /* DEB1 access on reserved memory */ +#define DEB2_ERROR 0x0004 /* DEB2 (USB) access on reserved memory */ +#define CORE_ERROR 0x0008 /* Core access on reserved memory */ +#define DEB0_MERROR 0x0010 /* DEB0 access on reserved memory and DEB0_ERROR is set */ +#define DEB1_MERROR 0x0020 /* DEB1 access on reserved memory and DEB1_ERROR is set */ +#define DEB2_MERROR 0x0040 /* DEB2 access on reserved memory and DEB2_ERROR is set */ +#define CORE_MERROR 0x0080 /* Core access on reserved memory and CORE_ERROR is set */ + +/* EBIU_RSTCTL Masks */ +#define DDR_SRESET 0x0001 /* Reset Control to DDR Controller */ +#define SRREQ 0x0008 /* Self Refresh Request */ +#define SRACK 0x0010 /* Self Refresh Request Acknowledgement */ +#define MDDRENABLE 0x0020 /* Mobile DDR Enable */ + #endif /* EBIU_SDGCTL */ #endif diff --git a/include/asm-blackfin/mach-common/bits/otp.h b/include/asm-blackfin/mach-common/bits/otp.h index d529a0a98..4e3f1afcf 100644 --- a/include/asm-blackfin/mach-common/bits/otp.h +++ b/include/asm-blackfin/mach-common/bits/otp.h @@ -9,23 +9,22 @@ #include "bootrom.h" -static uint32_t (* const otp_command)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND; -static uint32_t (* const otp_read)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ; -static uint32_t (* const otp_write)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE; +static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND; +static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ; +static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE; #endif /* otp_command(): defines for "command" */ -#define OTP_INIT 0x00000001 -#define OTP_CLOSE 0x00000002 +#define OTP_INIT 0x00000001 +#define OTP_CLOSE 0x00000002 /* otp_{read,write}(): defines for "flags" */ -#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ -#define OTP_UPPER_HALF 0x00000001 -#define OTP_NO_ECC 0x00000010 /* do not use ECC */ -#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ -#define OTP_ACCESS_READ 0x00001000 -#define OTP_ACCESS_READWRITE 0x00002000 +#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ +#define OTP_UPPER_HALF 0x00000001 +#define OTP_NO_ECC 0x00000010 /* do not use ECC */ +#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ +#define OTP_CHECK_FOR_PREV_WRITE 0x00000080 /* Return values for all functions */ #define OTP_SUCCESS 0x00000000 diff --git a/include/command.h b/include/command.h index a8a153cb0..d7321af92 100644 --- a/include/command.h +++ b/include/command.h @@ -33,6 +33,11 @@ #define NULL 0 #endif +/* Default to a width of 8 characters for help message command width */ +#ifndef CONFIG_SYS_HELP_CMD_WIDTH +#define CONFIG_SYS_HELP_CMD_WIDTH 8 +#endif + #ifndef __ASSEMBLY__ /* * Monitor Command Table @@ -64,6 +69,8 @@ extern cmd_tbl_t __u_boot_cmd_end; cmd_tbl_t *find_cmd(const char *cmd); cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len); +extern void cmd_usage(cmd_tbl_t *cmdtp); + #ifdef CONFIG_AUTO_COMPLETE extern void install_auto_complete(void); extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); diff --git a/include/common.h b/include/common.h index 5968036a0..afee1889a 100644 --- a/include/common.h +++ b/include/common.h @@ -597,6 +597,8 @@ ulong video_setmem (ulong); /* lib_$(ARCH)/cache.c */ void flush_cache (unsigned long, unsigned long); +void flush_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_range(unsigned long start, unsigned long stop); /* lib_$(ARCH)/ticks.S */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index a11a9b8db..2ee4f809d 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 1e3666077..fa9fc2382 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -184,7 +184,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index eebce38e7..40fef88f9 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 328773430..5c88c47b5 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -112,7 +112,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 89ba139af..f032a8d7a 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d0b4d1133..2677cfb27 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 69c8c6eee..aae0d7372 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -133,7 +133,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index be8c238a0..233320878 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -135,7 +135,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 884f3fe88..187547d2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index b445faecb..bf9fd8275 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -152,7 +152,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index e5de8ef01..ed9a235f6 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -177,7 +177,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 1106b0dcf..0e7d2c010 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 32814d49f..2591f1ded 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 58e9328e4..13d6e0496 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index d0a37d7bc..4e397990c 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index e9f16461e..7f2337bac 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -138,7 +138,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 8d07d7705..43e95320c 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -132,7 +132,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index d4322b6ba..d2eae1d7f 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -192,7 +192,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index 920134699..d4154d205 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -67,6 +67,7 @@ #define CONFIG_CMD_IDE +#undef CONFIG_CMD_ENV #undef CONFIG_CMD_FLASH diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 83d0d56c1..d9bcf6b7a 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -36,7 +36,6 @@ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index f173bcc9b..38a1d0dec 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 90efc6d81..db00c652f 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -121,7 +121,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index de6e12f51..99188bc34 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index e996bbd32..9eed3423c 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -114,7 +114,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index f1c5526d6..01da99b82 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -131,7 +131,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91_BASE_UHP */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 4501cae3c..2f1a41f64 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -116,7 +116,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 668fe3b08..ebecfa409 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -129,7 +129,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index c6603ff1f..09b871a5e 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -136,7 +136,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index e87173717..48c0252e4 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -198,7 +198,7 @@ #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SLAVE 0 #define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 5ad99a2fd..ee41c7e78 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -300,7 +300,7 @@ #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SLAVE 0 #endif /* CONFIG_SOFT_I2C */ /* diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index ac5aaa59a..27567faab 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -305,13 +305,11 @@ /* * I2C settings - * By default PF1 is used as SDA and PF0 as SCL on the Stamp board */ -/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */ -#define CONFIG_HARD_I2C 1 /* I2C TWI */ -#if defined CONFIG_HARD_I2C -#define CONFIG_TWICLK_KHZ 50 -#endif +#define CONFIG_HARD_I2C 1 +#define CONFIG_BFIN_TWI_I2C 1 +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0 #define CONFIG_EBIU_SDRRC_VAL 0x306 #define CONFIG_EBIU_SDGCTL_VAL 0x91114d @@ -321,39 +319,6 @@ #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#if defined CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF0 -#define PF_SDA PF1 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xFE - /* 0xFF, 0x7BB07BB0, 0x22547BB0 */ /* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) #define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 874f2c0b3..5d3b09aa3 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -162,7 +162,6 @@ * */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ -#undef CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #undef CONFIG_SYS_BASE_BAUD #define CONFIG_BAUDRATE 38400 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 2e30e6964..a33efde9f 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -161,7 +161,6 @@ * */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */ -#undef CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 38400 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index a727f5625..667c0d882 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -171,6 +171,8 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC +#define CONFIG_MUSB_HCD +#define CONFIG_USB_DAVINCI /*===================*/ /* Linux Information */ /*===================*/ @@ -203,6 +205,22 @@ #else #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" #endif +/*==========================*/ +/* USB MSC support (if any) */ +/*==========================*/ +#ifdef CONFIG_USB_DAVINCI +#define CONFIG_CMD_USB +#ifdef CONFIG_MUSB_HCD +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_PREBOOT "usb start" +#endif +#endif /*=======================*/ /* KGDB support (if any) */ /*=======================*/ diff --git a/include/configs/delta.h b/include/configs/delta.h index fd97b746f..abb2676bc 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -131,8 +131,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ - #define CONFIG_BOOTDELAY -1 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.0.0 diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h new file mode 100644 index 000000000..d193919dc --- /dev/null +++ b/include/configs/gdppc440etx.h @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * Based on include/configs/yosemite.h + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME gdppc440etx +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CONFIG_SYS_USB_DEVICE 0x50000000 +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 + +/* + * Initial RAM & stack pointer (placed in SDRAM) + */ +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes init data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE + +/* + * Environment + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* + * DDR SDRAM + */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ +#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CONFIG_SYS_SDRAM_BANKS (2) + +#define CONFIG_SDRAM_BANK0 +#define CONFIG_SDRAM_BANK1 + +#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 +#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 +#define CONFIG_SYS_SDRAM0_RTR 0x04080000 +#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 + +#undef CONFIG_SDRAM_ECC + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "" + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY1_ADDR 3 + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#endif + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_EEPROM + +/* + * PCI stuff + */ + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ + CONFIG_SYS_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT +#define CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) + +#endif /* __CONFIG_H */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index fb10616c3..9ac7e9afb 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -216,7 +216,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index c156820ac..7197aaf79 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -147,7 +147,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 1b5905945..ebca448ea 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -123,7 +123,6 @@ #undef CONFIG_SYS_DIRECT_FLASH_TFTP /* R8A66597 */ -#define LITTLEENDIAN /* for include/usb.h */ #define CONFIG_USB_R8A66597_HCD #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 57c82d1a1..c61667fd0 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -293,7 +293,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ #define CONFIG_USB_STORAGE 1 #endif diff --git a/include/configs/trab.h b/include/configs/trab.h index 562cd6093..0a7a73d30 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -44,7 +44,6 @@ #define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ #define CONFIG_TRAB 1 /* on a TRAB Board */ #undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ /* automatic software updates (see board/trab/auto_update.c) */ #define CONFIG_AUTO_UPDATE 1 diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index b2065ee48..0a8e99412 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -42,8 +42,6 @@ */ #define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ - #define CONFIG_MMC 1 #define BOARD_LATE_INIT 1 diff --git a/include/configs/vct.h b/include/configs/vct.h new file mode 100644 index 000000000..391535ed2 --- /dev/null +++ b/include/configs/vct.h @@ -0,0 +1,340 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the VCT board + * family: + * + * vct_premium + * vct_premium_small + * vct_premium_onenand + * vct_premium_onenand_small + * vct_platinum + * vct_platinum_small + * vct_platinum_onenand + * vct_platinum_onenand_small + * vct_platinumavc + * vct_platinumavc_small + * vct_platinumavc_onenand + * vct_platinumavc_onenand_small + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */ +#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_STACKSIZE (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND) +#define CONFIG_VCT_NOR +#else +#define CONFIG_SYS_NO_FLASH +#endif + +/* + * UART + */ +#define CONFIG_VCT_SERIAL +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * SDRAM + */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_MBYTES_SDRAM 128 +#define CONFIG_SYS_MEMTEST_START 0x80200000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 +#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ + +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) +/* + * SMSC91C11x Network Card + */ +#define CONFIG_DRIVER_SMC911X +#define CONFIG_DRIVER_SMC911X_BASE 0x00000000 +#define CONFIG_DRIVER_SMC911X_32_BIT +#define CONFIG_NET_RETRY_COUNT 20 +#endif + +/* + * Commands + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C + +/* + * Only Premium/Platinum have ethernet support right now + */ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP +#else +#undef CONFIG_CMD_NET +#endif + +/* + * Only Premium/Platinum have USB-EHCI support right now + */ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#endif + +#if defined(CONFIG_CMD_USB) +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_SUPPORT_VFAT + +/* + * USB/EHCI + */ +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_VCT /* on VCT platform */ +#define CONFIG_EHCI_DCACHE /* with dcache handling support */ +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_IS_TDI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ +#endif /* CONFIG_CMD_USB */ + +#if !defined(CONFIG_VCT_NOR) +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#endif + +#if defined(CONFIG_VCT_NAND) +#define CONFIG_CMD_NAND +#endif + +#if defined(CONFIG_VCT_ONENAND) +#define CONFIG_CMD_ONENAND +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCT# " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ + +/* + * FLASH and environment organization + */ +#if defined(CONFIG_VCT_NOR) +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_NOT_MEM_MAPPED + +/* + * We need special accessor functions for the CFI FLASH driver. This + * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option. + */ +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* + * For the non-memory-mapped NOR FLASH, we need to define the + * NOR FLASH area. This can't be detected via the addr2info() + * function, since we check for flash access in the very early + * U-Boot code, before the NOR FLASH is detected. + */ +#define CONFIG_FLASH_BASE 0xb0000000 +#define CONFIG_FLASH_END 0xbfffffff + +/* + * CFI driver settings + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ + +#define CONFIG_SYS_FLASH_BASE 0xb0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ +#endif /* CONFIG_VCT_NOR */ + +#if defined(CONFIG_VCT_ONENAND) +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_ENV_IS_IN_ONENAND +#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */ +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */ +#define CONFIG_ENV_SIZE (128 << 10) /* erase size */ +#endif /* CONFIG_VCT_ONENAND */ + +/* + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * I2C/EEPROM + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ + +#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */ +#define CONFIG_SYS_I2C_SLAVE 0x7f + +/* + * Software (bit-bang) I2C driver configuration + */ +#define CONFIG_SYS_GPIO_I2C_SCL 11 +#define CONFIG_SYS_GPIO_I2C_SDA 10 + +#ifndef __ASSEMBLY__ +int vct_gpio_dir(int pin, int dir); +void vct_gpio_set(int pin, int val); +int vct_gpio_get(int pin); +#endif + +#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1) +#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1) +#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0) +#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA) +#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit) +#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +/* CAT24WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CONFIG_BOOTCOMMAND "run test3" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* + * Needed for 64bit printf format + */ +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * UBI configuration + */ +#if defined(CONFIG_VCT_ONENAND) +#define CONFIG_SYS_USE_UBI +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_JFFS2_CMDLINE + +#define MTDIDS_DEFAULT "onenand0=onenand" +#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(u-boot)," \ + "128k(env)," \ + "20m(kernel)," \ + "-(rootfs)" +#endif + +/* + * We need a small, stripped down image to fit into the first 128k OneNAND + * erase block (gzipped). This image only needs basic commands for FLASH + * (NOR/OneNAND) usage and Linux kernel booting. + */ +#if defined(CONFIG_VCT_SMALL_IMAGE) +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_SNTP +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_REGINFO +#undef CONFIG_CMD_STRINGS +#undef CONFIG_CMD_TERMINAL +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_CRC32 +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADY +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_FAT + +#undef CONFIG_DRIVER_SMC911X +#undef CONFIG_SOFT_I2C +#undef CONFIG_AUTOSCRIPT +#undef CONFIG_SYS_LONGHELP +#undef CONFIG_TIMESTAMP +#endif /* CONFIG_VCT_SMALL_IMAGE */ + +#endif /* __CONFIG_H */ diff --git a/include/devices.h b/include/devices.h index 20ddfc434..84c451488 100644 --- a/include/devices.h +++ b/include/devices.h @@ -116,5 +116,8 @@ int drv_usbtty_init (void); #ifdef CONFIG_NETCONSOLE int drv_nc_init (void); #endif +#ifdef CONFIG_JTAG_CONSOLE +int drv_jtag_console_init (void); +#endif #endif /* _DEVICES_H_ */ diff --git a/include/sata.h b/include/sata.h index 57ee9ac86..37573cfee 100644 --- a/include/sata.h +++ b/include/sata.h @@ -7,5 +7,6 @@ ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer); ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer); int sata_initialize(void); +int __sata_initialize(void); #endif diff --git a/include/status_led.h b/include/status_led.h index 79be69885..175972a05 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -346,6 +346,9 @@ void status_led_set (int led, int state); #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ /************************************************************************/ +#elif defined(CONFIG_BLACKFIN) +/* XXX empty just to avoid the error */ +/************************************************************************/ #elif defined(CONFIG_V38B) # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ diff --git a/include/usb.h b/include/usb.h index 510df95d6..7c47098d8 100644 --- a/include/usb.h +++ b/include/usb.h @@ -138,7 +138,7 @@ enum { struct usb_device { int devnum; /* Device number on USB bus */ - int slow; /* Slow device? */ + int speed; /* full/low/high */ char mf[32]; /* manufacturer */ char prod[32]; /* product */ char serial[32]; /* serial number */ @@ -171,6 +171,7 @@ struct usb_device { unsigned long status; int act_len; /* transfered bytes */ int maxchild; /* Number of ports if hub */ + int portnr; struct usb_device *parent; struct usb_device *children[USB_MAXCHILDREN]; }; @@ -180,8 +181,9 @@ struct usb_device { */ #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ - defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_SL811HS) || \ - defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_R8A66597_HCD) + defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ + defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ + defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); @@ -263,13 +265,13 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); ((x_ & 0xFF000000UL) >> 24)); \ }) -#ifdef LITTLEENDIAN +#ifdef __LITTLE_ENDIAN # define swap_16(x) (x) # define swap_32(x) (x) #else # define swap_16(x) __swap_16(x) # define swap_32(x) __swap_32(x) -#endif /* LITTLEENDIAN */ +#endif /* * Calling this entity a "pipe" is glorifying it. A USB pipe @@ -279,7 +281,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); * - endpoint number (4 bits) * - current Data0/1 state (1 bit) * - direction (1 bit) - * - speed (1 bit) + * - speed (2 bits) * - max packet size (2 bits: 8, 16, 32 or 64) * - pipe type (2 bits: control, interrupt, bulk, isochronous) * @@ -296,7 +298,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); * - device: bits 8-14 * - endpoint: bits 15-18 * - Data0/1: bit 19 - * - speed: bit 26 (0 = Full, 1 = Low Speed) + * - speed: bit 26 (0 = Full, 1 = Low Speed, 2 = High) * - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt, * 10 = control, 11 = bulk) * @@ -308,8 +310,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); /* Create various pipes... */ #define create_pipe(dev,endpoint) \ (((dev)->devnum << 8) | (endpoint << 15) | \ - ((dev)->slow << 26) | (dev)->maxpacketsize) -#define default_pipe(dev) ((dev)->slow << 26) + ((dev)->speed << 26) | (dev)->maxpacketsize) +#define default_pipe(dev) ((dev)->speed << 26) #define usb_sndctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \ create_pipe(dev, endpoint)) @@ -359,7 +361,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); #define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff) #define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf) #define usb_pipedata(pipe) (((pipe) >> 19) & 1) -#define usb_pipeslow(pipe) (((pipe) >> 26) & 1) +#define usb_pipespeed(pipe) (((pipe) >> 26) & 3) +#define usb_pipeslow(pipe) (usb_pipespeed(pipe) == USB_SPEED_LOW) #define usb_pipetype(pipe) (((pipe) >> 30) & 3) #define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS) #define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT) diff --git a/include/usb_defs.h b/include/usb_defs.h index 353019fc1..8032e5712 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -80,6 +80,12 @@ #define USB_DIR_OUT 0 #define USB_DIR_IN 0x80 +/* USB device speeds */ +#define USB_SPEED_FULL 0x0 /* 12Mbps */ +#define USB_SPEED_LOW 0x1 /* 1.5Mbps */ +#define USB_SPEED_HIGH 0x2 /* 480Mbps */ +#define USB_SPEED_RESERVED 0x3 + /* Descriptor types */ #define USB_DT_DEVICE 0x01 #define USB_DT_CONFIG 0x02 @@ -202,6 +208,7 @@ #define USB_PORT_FEAT_RESET 4 #define USB_PORT_FEAT_POWER 8 #define USB_PORT_FEAT_LOWSPEED 9 +#define USB_PORT_FEAT_HIGHSPEED 10 #define USB_PORT_FEAT_C_CONNECTION 16 #define USB_PORT_FEAT_C_ENABLE 17 #define USB_PORT_FEAT_C_SUSPEND 18 @@ -216,6 +223,9 @@ #define USB_PORT_STAT_RESET 0x0010 #define USB_PORT_STAT_POWER 0x0100 #define USB_PORT_STAT_LOW_SPEED 0x0200 +#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */ +#define USB_PORT_STAT_SPEED \ + (USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED) /* wPortChange bits */ #define USB_PORT_STAT_C_CONNECTION 0x0001 diff --git a/lib_blackfin/Makefile b/lib_blackfin/Makefile index 3f69770d6..fee0fdaca 100644 --- a/lib_blackfin/Makefile +++ b/lib_blackfin/Makefile @@ -37,7 +37,7 @@ SOBJS-y += memmove.o SOBJS-y += memset.o COBJS-y += board.o -COBJS-y += bootm.o +COBJS-y += boot.o COBJS-y += cache.o COBJS-y += muldi3.o COBJS-y += post.o diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index ddf814428..01b71d448 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -13,10 +13,10 @@ #include <command.h> #include <devices.h> #include <environment.h> -#include <i2c.h> #include <malloc.h> #include <net.h> #include <timestamp.h> +#include <status_led.h> #include <version.h> #include <asm/cplb.h> @@ -279,9 +279,13 @@ void board_init_f(ulong bootflag) dcache_enable(); #endif +#ifdef DEBUG + if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd)) + hang(); +#endif serial_early_puts("Init global data\n"); gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR); - memset((void *)gd, 0, sizeof(gd_t)); + memset((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE); /* Board data initialization */ addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t)); @@ -331,16 +335,6 @@ void board_init_f(ulong bootflag) board_init_r((gd_t *) gd, 0x20000010); } -#if defined(CONFIG_SOFT_I2C) || defined(CONFIG_HARD_I2C) -static int init_func_i2c(void) -{ - puts("I2C: "); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - puts("ready\n"); - return (0); -} -#endif - void board_init_r(gd_t * id, ulong dest_addr) { extern void malloc_bin_reloc(void); @@ -356,14 +350,14 @@ void board_init_r(gd_t * id, ulong dest_addr) #endif #if !defined(CONFIG_SYS_NO_FLASH) - /* There are some other pointer constants we must deal with */ - /* configure available FLASH banks */ + /* Initialize the flash and protect u-boot by default */ extern flash_info_t flash_info[]; ulong size = flash_init(); puts("Flash: "); print_size(size, "\n"); flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0x1ffff, &flash_info[0]); + CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - 1, + &flash_info[0]); bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; bd->bi_flashsize = size; bd->bi_flashoffset = 0; @@ -420,6 +414,11 @@ void board_init_r(gd_t * id, ulong dest_addr) /* Initialize the console (after the relocation and devices init) */ console_init_r(); +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); + status_led_set(STATUS_LED_CRASH, STATUS_LED_OFF); +#endif + /* Initialize from environment */ if ((s = getenv("loadaddr")) != NULL) load_addr = simple_strtoul(s, NULL, 16); @@ -442,10 +441,6 @@ void board_init_r(gd_t * id, ulong dest_addr) bd->bi_enetaddr[3], bd->bi_enetaddr[4], bd->bi_enetaddr[5]); #endif -#if defined(CONFIG_SOFT_I2C) || defined(CONFIG_HARD_I2C) - init_func_i2c(); -#endif - display_global_data(); #if defined(CONFIG_POST) @@ -460,6 +455,10 @@ void board_init_r(gd_t * id, ulong dest_addr) void hang(void) { +#ifdef CONFIG_STATUS_LED + status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF); + status_led_set(STATUS_LED_CRASH, STATUS_LED_BLINKING); +#endif puts("### ERROR ### Please RESET the board ###\n"); while (1) /* If a JTAG emulator is hooked up, we'll automatically trigger diff --git a/lib_blackfin/bootm.c b/lib_blackfin/boot.c index 195eb9c00..951d5b0d0 100644 --- a/lib_blackfin/bootm.c +++ b/lib_blackfin/boot.c @@ -1,5 +1,5 @@ /* - * U-boot - bootm.c - misc boot helper functions + * U-boot - boot.c - misc boot helper functions * * Copyright (c) 2005-2008 Analog Devices Inc. * @@ -20,17 +20,19 @@ extern void swap_to(int device_id); static char *make_command_line(void) { - char *dest = (char *)CMD_LINE_ADDR; + char *dest = (char *)CONFIG_LINUX_CMDLINE_ADDR; char *bootargs = getenv("bootargs"); if (bootargs == NULL) return NULL; - strncpy(dest, bootargs, 0x1000); - dest[0xfff] = 0; + strncpy(dest, bootargs, CONFIG_LINUX_CMDLINE_SIZE); + dest[CONFIG_LINUX_CMDLINE_SIZE - 1] = 0; return dest; } +extern ulong bfin_poweron_retx; + int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { int (*appl) (char *cmdline); @@ -45,11 +47,16 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) appl = (int (*)(char *))images->ep; - printf("Starting Kernel at = %x\n", appl); + printf("Starting Kernel at = %p\n", appl); cmdline = make_command_line(); icache_disable(); dcache_disable(); - (*appl) (cmdline); + asm __volatile__( + "RETX = %[retx];" + "CALL (%0);" + : + : "p"(appl), "q0"(cmdline), [retx] "d"(bfin_poweron_retx) + ); /* does not return */ return 1; diff --git a/lib_blackfin/string.c b/lib_blackfin/string.c index 6887c93de..36eecdff4 100644 --- a/lib_blackfin/string.c +++ b/lib_blackfin/string.c @@ -1,7 +1,7 @@ /* * U-boot - string.c Contains library routines. * - * Copyright (c) 2005-2007 Analog Devices Inc. + * Copyright (c) 2005-2008 Analog Devices Inc. * * (C) Copyright 2000-2004 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -130,12 +130,22 @@ int strncmp(const char *cs, const char *ct, size_t count) # define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS # define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA1_D0_IRQ_STATUS #endif -static void *dma_memcpy(void *dst, const void *src, size_t count) +/* This version misbehaves for count values of 0 and 2^16+. + * Perhaps we should detect that ? Nowhere do we actually + * use dma memcpy for those types of lengths though ... + */ +void dma_memcpy_nocache(void *dst, const void *src, size_t count) { - if (dcache_status()) - blackfin_dcache_flush_range(src, src + count); + /* Scratchpad cannot be a DMA source or destination */ + if (((unsigned long)src >= L1_SRAM_SCRATCH && + (unsigned long)src < L1_SRAM_SCRATCH_END) || + ((unsigned long)dst >= L1_SRAM_SCRATCH && + (unsigned long)dst < L1_SRAM_SCRATCH_END)) + hang(); - bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); + bfin_write_MDMA_S0_CONFIG(0); + bfin_write_MDMA_D0_CONFIG(0); + bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR); /* Copy sram functions from sdram to sram */ /* Setup destination start address */ @@ -154,20 +164,33 @@ static void *dma_memcpy(void *dst, const void *src, size_t count) /* Enable source DMA */ bfin_write_MDMA_S0_CONFIG(DMAEN); - SSYNC(); bfin_write_MDMA_D0_CONFIG(WNR | DMAEN); + SSYNC(); while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) - bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); - bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); + continue; + + bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_RUN | DMA_DONE | DMA_ERR); + bfin_write_MDMA_D0_CONFIG(0); + bfin_write_MDMA_S0_CONFIG(0); +} +/* We should do a dcache invalidate on the destination after the dma, but since + * we lack such hardware capability, we'll flush/invalidate the destination + * before the dma and bank on the idea that u-boot is single threaded. + */ +void *dma_memcpy(void *dst, const void *src, size_t count) +{ + if (dcache_status()) { + blackfin_dcache_flush_range(src, src + count); + blackfin_dcache_flush_invalidate_range(dst, dst + count); + } + + dma_memcpy_nocache(dst, src, count); if (icache_status()) blackfin_icache_flush_range(dst, dst + count); - if (dcache_status()) - blackfin_dcache_invalidate_range(dst, dst + count); - return dst; } diff --git a/lib_generic/gunzip.c b/lib_generic/gunzip.c index 74f0bf9f3..5bcf5b7b2 100644 --- a/lib_generic/gunzip.c +++ b/lib_generic/gunzip.c @@ -102,8 +102,9 @@ int gunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp) s.next_out = dst; s.avail_out = dstlen; r = inflate(&s, Z_FINISH); - if (r != Z_OK && r != Z_STREAM_END) { + if (r != Z_STREAM_END) { printf ("Error: inflate() returned %d\n", r); + inflateEnd(&s); return (-1); } *lenp = s.next_out - (unsigned char *) dst; diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 61c29b563..df1cf13b5 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -38,9 +38,6 @@ #if defined(CONFIG_CMD_IDE) #include <ide.h> #endif -#if defined(CONFIG_CMD_SATA) -#include <sata.h> -#endif #if defined(CONFIG_CMD_SCSI) #include <scsi.h> #endif @@ -639,16 +636,6 @@ void board_init_f (ulong bootflag) /* NOTREACHED - relocate_code() does not return */ } -int __is_sata_supported(void) -{ - /* For some boards, when sata disabled by the switch, and the - * driver still access the sata registers, the cpu will hangup. - * please define platform specific is_sata_supported() if your - * board have such issue.*/ - return 1; -} -int is_sata_supported(void) __attribute__((weak, alias("__is_sata_supported"))); - /************************************************************************ * * This is the next part if the initialization sequence: we are now @@ -1152,13 +1139,6 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif #endif -#if defined(CONFIG_CMD_SATA) - if (is_sata_supported()) { - puts("SATA: "); - sata_initialize(); - } -#endif - #ifdef CONFIG_LAST_STAGE_INIT WATCHDOG_RESET (); /* diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile index b0967a30b..416e176d4 100644 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -34,7 +34,8 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o -COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o time.o +COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \ + time.o cache.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -78,6 +79,9 @@ $(obj)ns16550.c: $(obj)nand_init.c: ln -sf $(SRCTREE)/cpu/mpc83xx/nand_init.c $< +$(obj)cache.c: + ln -sf $(SRCTREE)/lib_ppc/cache.c $< + $(obj)time.c: ln -sf $(SRCTREE)/lib_ppc/time.c $< diff --git a/tools/updater/cmd_flash.c b/tools/updater/cmd_flash.c index 5ff733659..5ce45baeb 100644 --- a/tools/updater/cmd_flash.c +++ b/tools/updater/cmd_flash.c @@ -122,7 +122,7 @@ int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) int rcode = 0; if (argc < 2) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -147,7 +147,7 @@ int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) } if (argc != 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -168,7 +168,7 @@ int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) addr_last = simple_strtoul(argv[2], NULL, 16); if (addr_first >= addr_last) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -244,7 +244,7 @@ int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) int rcode = 0; if (argc < 3) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -253,7 +253,7 @@ int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) else if (strcmp(argv[1], "on") == 0) p = 1; else { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -310,7 +310,7 @@ int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) } if (argc != 4) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } @@ -350,7 +350,7 @@ int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) addr_last = simple_strtoul(argv[3], NULL, 16); if (addr_first >= addr_last) { - printf ("Usage:\n%s\n", cmdtp->usage); + cmd_usage(cmdtp); return 1; } rcode = flash_sect_protect (p, addr_first, addr_last); |