1 files changed, 106 insertions, 199 deletions

diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e5b21b555..194f6ab96 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -1,5 +1,6 @@
 /*
- * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
+ * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
+ *
  * Copyright 2007 Embedded Specialties, Inc.
  *
  * Copyright 2004, 2007 Freescale Semiconductor.
@@ -32,6 +33,8 @@
 #include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <spd_sdram.h>
+#include <netdev.h>
+#include <tsec.h>
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
@@ -49,25 +52,19 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
 
 	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
-			(*rev) >> 4);
+			in_8(rev) >> 4);
 
 	/*
 	 * Initialize local bus.
 	 */
 	local_bus_init ();
 
-	/*
-	 * Hack TSEC 3 and 4 IO voltages.
-	 */
-	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
-
-	ecm->eedr = 0xffffffff;		/* clear ecm errors */
-	ecm->eeer = 0xffffffff;		/* enable ecm errors */
+	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
 	return 0;
 }
 
@@ -89,7 +86,7 @@ initdram(int board_type)
 
 		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
-		gur->ddrdllcr = 0x81000000;
+		out_be32(&gur->ddrdllcr, 0x81000000);
 		asm("sync;isync;msync");
 		udelay(200);
 	}
@@ -126,24 +123,24 @@ local_bus_init(void)
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
-	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+	clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
-	gur->lbiuiplldcr1 = 0x00078080;
+	out_be32(&gur->lbiuiplldcr1, 0x00078080);
 	if (clkdiv == 16) {
-		gur->lbiuiplldcr0 = 0x7c0f1bf0;
+		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
 	} else if (clkdiv == 8) {
-		gur->lbiuiplldcr0 = 0x6c0f1bf0;
+		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
 	} else if (clkdiv == 4) {
-		gur->lbiuiplldcr0 = 0x5c0f1bf0;
+		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
 	}
 
-	lbc->lcrr |= 0x00030000;
+	setbits_be32(&lbc->lcrr, 0x00030000);
 
 	asm("sync;isync;msync");
 
-	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
-	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
+	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
+	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
 }
 
 /*
@@ -152,7 +149,7 @@ local_bus_init(void)
 void
 sdram_init(void)
 {
-#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
 
 	uint idx;
 	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -166,18 +163,24 @@ sdram_init(void)
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or3 = CONFIG_SYS_OR3_PRELIM;
+	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
 	asm("msync");
 
-	lbc->br3 = CONFIG_SYS_BR3_PRELIM;
+	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
 	asm("msync");
 
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
 	asm("msync");
 
+	out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
+	asm("msync");
 
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+	asm("msync");
+
+
+	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
+	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
 	asm("msync");
 
 	/*
@@ -189,7 +192,7 @@ sdram_init(void)
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -199,7 +202,7 @@ sdram_init(void)
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
+		out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH);
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -209,7 +212,7 @@ sdram_init(void)
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -218,7 +221,7 @@ sdram_init(void)
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+	out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL);
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -266,228 +269,132 @@ testdram(void)
 }
 #endif
 
-#if	!defined(CONFIG_SPD_EEPROM)
+#if !defined(CONFIG_SPD_EEPROM)
+#define CONFIG_SYS_DDR_CONTROL 0xc300c000
 /*************************************************************************
  *  fixed_sdram init -- doesn't use serial presence detect.
  *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
  ************************************************************************/
 long int fixed_sdram (void)
 {
-    #define CONFIG_SYS_DDR_CONTROL 0xc300c000
-
 	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds		= 0x0000007f;
-	ddr->cs1_bnds		= 0x008000ff;
-	ddr->cs2_bnds		= 0x00000000;
-	ddr->cs3_bnds		= 0x00000000;
-	ddr->cs0_config		= 0x80010101;
-	ddr->cs1_config		= 0x80010101;
-	ddr->cs2_config		= 0x00000000;
-	ddr->cs3_config		= 0x00000000;
-	ddr->timing_cfg_3		= 0x00000000;
-	ddr->timing_cfg_0	= 0x00220802;
-	ddr->timing_cfg_1	= 0x38377322;
-	ddr->timing_cfg_2	= 0x0fa044C7;
-	ddr->sdram_cfg		= 0x4300C000;
-	ddr->sdram_cfg_2	= 0x24401000;
-	ddr->sdram_mode		= 0x23C00542;
-	ddr->sdram_mode_2	= 0x00000000;
-	ddr->sdram_interval	= 0x05080100;
-	ddr->sdram_md_cntl	= 0x00000000;
-	ddr->sdram_data_init	= 0x00000000;
-	ddr->sdram_clk_cntl	= 0x03800000;
+	out_be32(&ddr->cs0_bnds, 0x0000007f);
+	out_be32(&ddr->cs1_bnds, 0x008000ff);
+	out_be32(&ddr->cs2_bnds, 0x00000000);
+	out_be32(&ddr->cs3_bnds, 0x00000000);
+	out_be32(&ddr->cs0_config, 0x80010101);
+	out_be32(&ddr->cs1_config, 0x80010101);
+	out_be32(&ddr->cs2_config, 0x00000000);
+	out_be32(&ddr->cs3_config, 0x00000000);
+	out_be32(&ddr->timing_cfg_3, 0x00000000);
+	out_be32(&ddr->timing_cfg_0, 0x00220802);
+	out_be32(&ddr->timing_cfg_1, 0x38377322);
+	out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
+	out_be32(&ddr->sdram_cfg, 0x4300C000);
+	out_be32(&ddr->sdram_cfg_2, 0x24401000);
+	out_be32(&ddr->sdram_mode, 0x23C00542);
+	out_be32(&ddr->sdram_mode_2, 0x00000000);
+	out_be32(&ddr->sdram_interval, 0x05080100);
+	out_be32(&ddr->sdram_md_cntl, 0x00000000);
+	out_be32(&ddr->sdram_data_init, 0x00000000);
+	out_be32(&ddr->sdram_clk_cntl, 0x03800000);
 	asm("sync;isync;msync");
 	udelay(500);
 
 	#if defined (CONFIG_DDR_ECC)
 	  /* Enable ECC checking */
-	  ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
 	#else
-	  ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
 	#endif
 
 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif
 
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device.  Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_sbc8548_config_table[] = {
-	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
-		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
-		mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
-		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
-		mpc85xx_config_via_ac97, {0,0,0}},
-	{},
-};
-
-static struct pci_controller pci1_hose = {
-	config_table: pci_sbc8548_config_table};
-#endif	/* CONFIG_PCI */
-
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif	/* CONFIG_PCI2 */
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif	/* CONFIG_PCI1 */
 
 #ifdef CONFIG_PCIE1
 static struct pci_controller pcie1_hose;
 #endif	/* CONFIG_PCIE1 */
 
-int first_free_busno=0;
 
+#ifdef CONFIG_PCI
 void
 pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info[2];
+	u32 devdisr, pordevsr, porpllsr, io_sel;
+	int first_free_busno = 0;
+	int num = 0;
 
-#ifdef CONFIG_PCI1
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
-	struct pci_controller *hose = &pci1_hose;
-	struct pci_config_table *table;
-	struct pci_region *r = hose->regions;
+#ifdef CONFIG_PCIE1
+	int pcie_configured;
+#endif
 
-	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
-	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
-	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	porpllsr = in_be32(&gur->porpllsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 
-	uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
+	debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
-	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+#ifdef CONFIG_PCI1
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
+		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */
 
-	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
-		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
+		printf ("    PCI host: %d bit, %s MHz, %s, %s\n",
 			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
+			(pci_speed == 33000000) ? "33" :
+			(pci_speed == 66000000) ? "66" : "unknown",
 			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter"
-			);
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_MEM_BASE,
-			       CONFIG_SYS_PCI1_MEM_PHYS,
-			       CONFIG_SYS_PCI1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCI1_IO_BASE,
-			       CONFIG_SYS_PCI1_IO_PHYS,
-			       CONFIG_SYS_PCI1_IO_SIZE,
-			       PCI_REGION_IO);
-		hose->region_count = r - hose->regions;
-
-		/* relocate config table pointers */
-		hose->config_table = \
-			(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
-		for (table = hose->config_table; table && table->vendor; table++)
-			table->config_device += gd->reloc_off;
-
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		first_free_busno=hose->last_busno+1;
-		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
-#ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
-			/* PCI-X init */
-			if (CONFIG_SYS_CLK_FREQ < 66000000)
-				printf("PCI-X will only work at 66 MHz\n");
-
-			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
-				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
-			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
-		}
-#endif
+			pci_arb ? "arbiter" : "external-arbiter");
+
+		SET_STD_PCI_INFO(pci_info[num], 1);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pci1_hose, first_free_busno);
 	} else {
 		printf ("    PCI: disabled\n");
 	}
-}
+
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
 #endif
 
-#ifdef CONFIG_PCI2
-{
-	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
-	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
-	if (pci_dual) {
-		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
-			pci2_clk_sel ? "sync" : "async");
-	} else {
-		printf ("    PCI2: disabled\n");
-	}
-}
-#else
-	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
-#endif /* CONFIG_PCI2 */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
 
 #ifdef CONFIG_PCIE1
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pcie1_hose;
-	int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
-	struct pci_region *r = hose->regions;
-
-	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
-	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
-		printf ("\n    PCIE connected to slot as %s (base address %x)",
-			pcie_ep ? "End Point" : "Root Complex",
-			(uint)pci);
-
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
-		}
-		printf ("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BASE,
-			       CONFIG_SYS_PCIE1_MEM_PHYS,
-			       CONFIG_SYS_PCIE1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BASE,
-			       CONFIG_SYS_PCIE1_IO_PHYS,
-			       CONFIG_SYS_PCIE1_IO_SIZE,
-			       PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
-
-		first_free_busno=hose->last_busno+1;
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		printf ("    PCIE at base address %lx\n", pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
 	} else {
 		printf ("    PCIE: disabled\n");
 	}
- }
+
+	puts("\n");
 #else
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+}
 #endif
 
+int board_eth_init(bd_t *bis)
+{
+	tsec_standard_init(bis);
+	pci_eth_init(bis);
+	return 0;	/* otherwise cpu_eth_init gets run */
 }
 
 int last_stage_init(void)