diff options
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/Makefile | 1 | ||||
| -rw-r--r-- | drivers/i2c/bfin-twi_i2c.c | 74 | ||||
| -rw-r--r-- | drivers/i2c/omap24xx_i2c.c | 166 | ||||
| -rw-r--r-- | drivers/i2c/pca9564_i2c.c | 189 | ||||
| -rw-r--r-- | drivers/i2c/s3c24x0_i2c.c | 6 | ||||
| -rw-r--r-- | drivers/i2c/soft_i2c.c | 5 |
6 files changed, 355 insertions, 86 deletions
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 4a12976e3..b860e89f8 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o +COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index e79063407..73a78d223 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -26,6 +26,7 @@ #ifdef TWI0_CLKDIV #define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) +#define bfin_read_TWI_CLKDIV(val) bfin_read_TWI0_CLKDIV(val) #define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) #define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val) #define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) @@ -44,8 +45,21 @@ #ifdef CONFIG_TWICLK_KHZ # error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED #endif -#if CONFIG_SYS_I2C_SPEED > 400000 -# error The Blackfin I2C hardware can only operate at 400KHz max + +/* + * The way speed is changed into duty often results in integer truncation + * with 50% duty, so we'll force rounding up to the next duty by adding 1 + * to the max. In practice this will get us a speed of something like + * 385 KHz. The other limit is easy to handle as it is only 8 bits. + */ +#define I2C_SPEED_MAX 400000 +#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) +#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) +#define I2C_DUTY_MIN 0xff /* 8 bit limited */ +#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) +/* Note: duty is inverse of speed, so the comparisons below are correct */ +#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN +# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" #endif /* All transfers are described by this data structure */ @@ -60,6 +74,9 @@ struct i2c_msg { u8 *abuf; /* addr buffer */ }; +/* Allow msec timeout per ~byte transfer */ +#define I2C_TIMEOUT 10 + /** * wait_for_completion - manage the actual i2c transfer * @msg: the i2c msg @@ -67,8 +84,9 @@ struct i2c_msg { static int wait_for_completion(struct i2c_msg *msg) { uint16_t int_stat; + ulong timebase = get_timer(0); - while (!ctrlc()) { + do { int_stat = bfin_read_TWI_INT_STAT(); if (int_stat & XMTSERV) { @@ -103,7 +121,7 @@ static int wait_for_completion(struct i2c_msg *msg) debugi("processing MERR"); bfin_write_TWI_INT_STAT(MERR); SSYNC(); - break; + return msg->len; } if (int_stat & MCOMP) { debugi("processing MCOMP"); @@ -116,7 +134,12 @@ static int wait_for_completion(struct i2c_msg *msg) } else break; } - } + + /* If we were able to do something, reset timeout */ + if (int_stat) + timebase = get_timer(0); + + } while (get_timer(timebase) < I2C_TIMEOUT); return msg->len; } @@ -204,7 +227,36 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, return ret; } -/* +/** + * i2c_set_bus_speed - set i2c bus speed + * @speed: bus speed (in HZ) + */ +int i2c_set_bus_speed(unsigned int speed) +{ + u16 clkdiv = I2C_SPEED_TO_DUTY(speed); + + /* Set TWI interface clock */ + if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) + return -1; + bfin_write_TWI_CLKDIV((clkdiv << 8) | (clkdiv & 0xff)); + + /* Don't turn it on */ + bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + + return 0; +} + +/** + * i2c_get_bus_speed - get i2c bus speed + * @speed: bus speed (in HZ) + */ +unsigned int i2c_get_bus_speed(void) +{ + /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ + return 5000000 / (bfin_read_TWI_CLKDIV() & 0xff); +} + +/** * i2c_init - initialize the i2c bus * @speed: bus speed (in HZ) * @slaveaddr: address of device in slave mode (0 - not slave) @@ -220,15 +272,9 @@ void i2c_init(int speed, int slaveaddr) bfin_write_TWI_CONTROL(prescale); /* Set TWI interface clock as specified */ - bfin_write_TWI_CLKDIV( - ((5 * 1024 / (speed / 1000)) << 8) | - ((5 * 1024 / (speed / 1000)) & 0xFF) - ); - - /* Don't turn it on */ - bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + i2c_set_bus_speed(speed); - /* But enable it */ + /* Enable it */ bfin_write_TWI_CONTROL(TWI_ENA | prescale); SSYNC(); diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 1a4c8c9ad..ff18991f0 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -29,6 +29,11 @@ static void wait_for_bb (void); static u16 wait_for_pin (void); static void flush_fifo(void); +static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE; + +static unsigned int bus_initialized[I2C_BUS_MAX]; +static unsigned int current_bus; + void i2c_init (int speed, int slaveadd) { int psc, fsscll, fssclh; @@ -95,30 +100,32 @@ void i2c_init (int speed, int slaveadd) sclh = (unsigned int)fssclh; } - writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ udelay(1000); - writew(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, &i2c_base->sysc); /* will probably self clear but */ - if (readw (I2C_CON) & I2C_CON_EN) { - writew (0, I2C_CON); + if (readw (&i2c_base->con) & I2C_CON_EN) { + writew (0, &i2c_base->con); udelay (50000); } - writew(psc, I2C_PSC); - writew(scll, I2C_SCLL); - writew(sclh, I2C_SCLH); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); /* own address */ - writew (slaveadd, I2C_OA); - writew (I2C_CON_EN, I2C_CON); + writew (slaveadd, &i2c_base->oa); + writew (I2C_CON_EN, &i2c_base->con); /* have to enable intrrupts or OMAP i2c module doesn't work */ writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); udelay (1000); flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); + + bus_initialized[current_bus] = 1; } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -130,19 +137,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) wait_for_bb (); /* one byte only */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* no stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - writeb (regoffset, I2C_DATA); + writeb (regoffset, &i2c_base->data); udelay (20000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c_base->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -151,28 +158,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - writew (0, I2C_CON); - while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (0, &i2c_base->con); + while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); } wait_for_bb (); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* read one byte from slave */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* need stop bit here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + &i2c_base->con); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = readb (I2C_DATA); + *value = readb (&i2c_base->data); #else - *value = readw (I2C_DATA); + *value = readw (&i2c_base->data); #endif udelay (20000); } else { @@ -180,17 +187,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) } if (!i2c_error) { - writew (I2C_CON_EN, I2C_CON); - while (readw (I2C_STAT) - || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c_base->con); + while (readw (&i2c_base->stat) + || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (10000); - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); } } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); return i2c_error; } @@ -203,12 +210,12 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) wait_for_bb (); /* two bytes */ - writew (2, I2C_CNT); + writew (2, &i2c_base->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + I2C_CON_STP, &i2c_base->con); /* wait until state change */ status = wait_for_pin (); @@ -216,24 +223,24 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* send out 1 byte */ - writeb (regoffset, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (regoffset, &i2c_base->data); + writew (I2C_STAT_XRDY, &i2c_base->stat); status = wait_for_pin (); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ - writeb (value, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (value, &i2c_base->data); + writew (I2C_STAT_XRDY, &i2c_base->stat); } else { i2c_error = 1; } #else /* send out two bytes */ - writew ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, &i2c_base->data); #endif /* must have enough delay to allow BB bit to go low */ udelay (50000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c_base->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -243,18 +250,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (!i2c_error) { int eout = 200; - writew (I2C_CON_EN, I2C_CON); - while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c_base->con); + while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); return i2c_error; } @@ -265,14 +272,14 @@ static void flush_fifo(void) * you get a bus error */ while(1){ - stat = readw(I2C_STAT); + stat = readw(&i2c_base->stat); if(stat == I2C_STAT_RRDY){ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - readb(I2C_DATA); + readb(&i2c_base->data); #else - readw(I2C_DATA); + readw(&i2c_base->data); #endif - writew(I2C_STAT_RRDY,I2C_STAT); + writew(I2C_STAT_RRDY,&i2c_base->stat); udelay(1000); }else break; @@ -283,7 +290,7 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == readw (I2C_OA)) { + if (chip == readw (&i2c_base->oa)) { return res; } @@ -291,27 +298,27 @@ int i2c_probe (uchar chip) wait_for_bb (); /* try to read one byte */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* set slave address */ - writew (chip, I2C_SA); + writew (chip, &i2c_base->sa); /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); /* enough delay for the NACK bit set */ udelay (50000); - if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); - writew(0xFFFF, I2C_STAT); + writew(0xFFFF, &i2c_base->stat); } else { - writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ - writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/ + writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - writew(0xFFFF, I2C_STAT); + writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, &i2c_base->stat); return res; } @@ -370,17 +377,17 @@ static void wait_for_bb (void) int timeout = 10; u16 stat; - writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - writew (stat, I2C_STAT); + writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/ + while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) { + writew (stat, &i2c_base->stat); udelay (50000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - readw (I2C_STAT)); + readw (&i2c_base->stat)); } - writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ } static u16 wait_for_pin (void) @@ -390,7 +397,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = readw (I2C_STAT); + status = readw (&i2c_base->stat); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -398,8 +405,33 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - readw (I2C_STAT)); - writew(0xFFFF, I2C_STAT); + readw (&i2c_base->stat)); + writew(0xFFFF, &i2c_base->stat); } return status; } + +int i2c_set_bus_num(unsigned int bus) +{ + if ((bus < 0) || (bus >= I2C_BUS_MAX)) { + printf("Bad bus: %d\n", bus); + return -1; + } + +#if I2C_BUS_MAX==3 + if (bus == 2) + i2c_base = (struct i2c *)I2C_BASE3; + else +#endif + if (bus == 1) + i2c_base = (struct i2c *)I2C_BASE2; + else + i2c_base = (struct i2c *)I2C_BASE1; + + current_bus = bus; + + if(!bus_initialized[current_bus]) + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return 0; +} diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c new file mode 100644 index 000000000..199a9ee39 --- /dev/null +++ b/drivers/i2c/pca9564_i2c.c @@ -0,0 +1,189 @@ +/* + * File: drivers/i2c/pca9564.c + * Based on: drivers/i2c/s3c44b0_i2c.c + * Author: + * + * Created: 2009-06-23 + * Description: PCA9564 i2c bridge driver + * + * Modified: + * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ + * + * Bugs: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <pca9564.h> +#include <asm/io.h> + +#define PCA_STA (CONFIG_PCA9564_BASE + 0) +#define PCA_TO (CONFIG_PCA9564_BASE + 0) +#define PCA_DAT (CONFIG_PCA9564_BASE + (1 << 2)) +#define PCA_ADR (CONFIG_PCA9564_BASE + (2 << 2)) +#define PCA_CON (CONFIG_PCA9564_BASE + (3 << 2)) + +static unsigned char pca_read_reg(unsigned int reg) +{ + return readb((void *)reg); +} + +static void pca_write_reg(unsigned int reg, unsigned char value) +{ + writeb(value, (void *)reg); +} + +static int pca_wait_busy(void) +{ + unsigned int timeout = 10000; + + while (!(pca_read_reg(PCA_CON) & PCA_CON_SI) && --timeout) + udelay(1); + + if (timeout == 0) + debug("I2C timeout!\n"); + + debug("CON = 0x%02x, STA = 0x%02x\n", pca_read_reg(PCA_CON), + pca_read_reg(PCA_STA)); + + return timeout ? 0 : 1; +} + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Initialization + */ +void i2c_init(int speed, int slaveaddr) +{ + pca_write_reg(PCA_CON, PCA_CON_ENSIO | speed); +} + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ + +int i2c_probe(uchar chip) +{ + unsigned char res; + + pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO); + pca_wait_busy(); + + pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1) | 1); + res = pca_wait_busy(); + + if ((res == 0) && (pca_read_reg(PCA_STA) == 0x48)) + res = 1; + + pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO); + + return res; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1)); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + if (alen > 0) { + pca_write_reg(PCA_DAT, addr); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO); + + udelay(500); + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1) | 1); + pca_wait_busy(); + + for (i = 0; i < len; ++i) { + if (i == len - 1) + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + else + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_AA); + + pca_wait_busy(); + buffer[i] = pca_read_reg(PCA_DAT); + + } + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO); + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, chip << 1); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + if (alen > 0) { + pca_write_reg(PCA_DAT, addr); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + for (i = 0; i < len; ++i) { + pca_write_reg(PCA_DAT, buffer[i]); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO); + + return 0; +} diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 55c6a12aa..c8371cf73 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -27,11 +27,7 @@ */ #include <common.h> -#if defined(CONFIG_S3C2400) -#include <s3c2400.h> -#elif defined(CONFIG_S3C2410) -#include <s3c2410.h> -#endif +#include <asm/arch/s3c24x0_cpu.h> #include <asm/io.h> #include <i2c.h> diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 59883a58f..9a4878391 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -34,6 +34,11 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #endif +#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include <asm/arch/ixp425.h> #endif |