diff options
Diffstat (limited to 'include/asm-ppc/immap_85xx.h')
| -rw-r--r-- | include/asm-ppc/immap_85xx.h | 85 |
1 files changed, 11 insertions, 74 deletions
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index d3c6b86d2..db2bdf0af 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007 Freescale Semiconductor. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) @@ -12,6 +12,7 @@ #define __IMMAP_85xx__ #include <asm/types.h> +#include <asm/fsl_dma.h> #include <asm/fsl_i2c.h> #include <asm/fsl_lbc.h> @@ -406,80 +407,9 @@ typedef struct ccsr_l2cache { */ typedef struct ccsr_dma { char res1[256]; - uint mr0; /* 0x21100 - DMA 0 Mode Register */ - uint sr0; /* 0x21104 - DMA 0 Status Register */ - char res2[4]; - uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ - uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ - uint sar0; /* 0x21114 - DMA 0 Source Address Register */ - uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ - uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ - uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ - char res3[4]; - uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ - char res4[8]; - uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ - char res5[4]; - uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ - uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ - uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ - char res6[56]; - uint mr1; /* 0x21180 - DMA 1 Mode Register */ - uint sr1; /* 0x21184 - DMA 1 Status Register */ - char res7[4]; - uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ - uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ - uint sar1; /* 0x21194 - DMA 1 Source Address Register */ - uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ - uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ - uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ - char res8[4]; - uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ - char res9[8]; - uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ - char res10[4]; - uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ - uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ - uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ - char res11[56]; - uint mr2; /* 0x21200 - DMA 2 Mode Register */ - uint sr2; /* 0x21204 - DMA 2 Status Register */ - char res12[4]; - uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ - uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ - uint sar2; /* 0x21214 - DMA 2 Source Address Register */ - uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ - uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ - uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ - char res13[4]; - uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ - char res14[8]; - uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ - char res15[4]; - uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ - uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ - uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ - char res16[56]; - uint mr3; /* 0x21280 - DMA 3 Mode Register */ - uint sr3; /* 0x21284 - DMA 3 Status Register */ - char res17[4]; - uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ - uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ - uint sar3; /* 0x21294 - DMA 3 Source Address Register */ - uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ - uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ - uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ - char res18[4]; - uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ - char res19[8]; - uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ - char res20[4]; - uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ - uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ - uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ - char res21[56]; + struct fsl_dma dma[4]; uint dgsr; /* 0x21300 - DMA General Status Register */ - char res22[11516]; + char res2[11516]; } ccsr_dma_t; /* @@ -1596,8 +1526,11 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 #endif +#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 +#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 +#define MPC85xx_PORBMSR_HA_SHIFT 16 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 @@ -1607,6 +1540,7 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 @@ -1732,5 +1666,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#define CONFIG_SYS_MPC85xx_USB_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) #endif /*__IMMAP_85xx__*/ |