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This will be needed for MPC8360E-MDS boards with rev. 2.1 CPUs.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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Fixed a misunderstanding in the original implementation, 'devnum' that
was used in the cpu/ppc4xx/4xx_enet.c implementation was NOT the
PHY's SMI address, rather it was the number of the MAC interface on
the CPU. The equivalent of this for uec_phy will be the UEC number
stored in mii_info->dev->name. Usage example is updated for uec.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Copied over the fixed PHY driver as used in pp4xx/4xx_enet.c.
This adds support for PHY-less MAC connections to the UEC.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Change UEC phy interface from GMII to RGMII on MPC8568MDS board
Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed,
but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more stable.
Now both UEC1 and UEC2 can work properly under u-boot.
It is also in consistent with the kernel setting for 8568 UEC phy interface.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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This patch adds basic support for Broadcom BCM5481 PHY.
RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is
Peter Barada <peterb@logicpd.com>.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
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Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
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allow u-boot to recover (and, e.g., switch to another interface) in the
case where a PHY does not report autonegotiation is complete within its
two second timeout value.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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erratum 5.6 states the autoneg completion bit is functional only if the
autoneg bit is asserted.
This fixes any secondarily-issued networking commands on non-gigabit
links on the mpc8360 mds board.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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PHY less board prints out lots of "read wrong ...":
read wrong value : mii_id 3,mii_reg 2, base e0102320
read wrong value : mii_id 3,mii_reg 3, base e0102320
UEC: PHY is Generic MII (ffffffff)
read wrong value : mii_id 3,mii_reg 4, base e0102320
read wrong value : mii_id 3,mii_reg 0, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 5, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 1, base e0102320
read wrong value : mii_id 3,mii_reg 5, base e0102320
FSL UEC0: Full Duplex
FSL UEC0: Speed 100BT
FSL UEC0: Link is up
Using FSL UEC0 device
Make this printout depend on UEC_VERBOSE_DEBUG and
remove its definition in uec_phy.c
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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actually polling for PHY autonegotiation to finish enables us to remove the
5 second boot prompt latency present on QE based boards.
call to qe_set_mii_clk_src in init_phy, and mv call to init_phy from
uec_initialize to uec_init by Joakim Tjernlund; autonegotiation wait
code shamelessly stolen from tsec driver.
also rm unused CONFIG_RMII_MODE code.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
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