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There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
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A bunch of the 85xx boards have this cruft in them - it's not used
anywhere. Delete it.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
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For some reason the MPC8544 enabled BEDBUG if PCI was enabled and that
got copied int the MPC8536, MPC8572 and P2020 DS boards. The BEDBUG
support has never been made to work completely on e500/85xx so we
just disable it to save space and match the other FSL 85xx boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks. This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".
The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We have always mapped at least 16M in the kernel and we have seen cases
with new kernel features that a kernel image needs more than 8M of
memory.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The KSEG1ADDR macro used to be necessary for the RTL8139 Ethernet
driver, but the code that used that macro was removed over a year
ago, so board configuration files no longer need to define it.
The _IO_BASE macro is also automatically defined to 0 if it isn't
already set, so there's no need to define that macro either in the
board configuration files.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
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Introduce a new define to seperate out the virtual address that PCI
IO space is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
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Introduce a new define to seperate out the virtual address that PCI
memory is at from the physical address. In most situations these are
mapped 1:1. However any code accessing the bus should use VIRT.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
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Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead
of _IO_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead
of _MEM_BASE so we are more explicit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
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Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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Prevent further viral propogation of the unused
symbol CONFIG_L1_INIT_RAM by just removing it.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
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The DDR controller of 8548/8544/8568/8572/8536 processors
have the ECC data init feature, and the new DDR code is
using the feature, and we don't need the way with DMA to
init memory any more.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
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Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS,
MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows()
and ft_fsl_pci_setup().
With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
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The pixis sgmii command depend on the FPGA support on the board, some 85xx
boards support SGMII riser card but did not support this command, define
CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command.
Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits
are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and
PIXIS_VCFGEN1_MASK in header file for both boards.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The 8544DS and 8572DS platforms support an optional SGMII riser card to
expose ethernet over an SGMII interface. Once the card is in, it is also
necessary to configure the board such that it uses the card, rather than
the on-board ethernet ports. This can either be done by flipping dip switches
on the motherboard, or by modifying registers in the pixis. Either way
requires a reboot.
This adds a command to allow users to choose which ports are routed through
the SGMII card, and which through the onboard ports. It also allows users
to revert to the current switch settings.
This code does not work on the 8572, as the PIXIS is different.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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The 8544DS and 8572DS systems have an optional SGMII riser card which
exposes new ethernet ports which are connected to the eTSECs via an
SGMII interface. The SGMII PHYs for this board are offset from the standard
PHY addresses, so this code modifies the passed in tsec_info structure to
use the SGMII PHYs on the card, instead.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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The L2_INIT_RAM option was unused, and recent changes to the TLB code
meant that the INIT_RAM TLBs weren't being cleared out. In order to reduce
the amount of mapped space attached to nothing, we change things so the TLBs
get cleared.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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The fake flash bank was generating errors for anyone who didn't have a
PromJET hooked up to the board. As that constitutes the vast majority of
users, we remove it.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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Add support for using a PCIe ATI Video card on PCIe2.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping
space for some anyway, we were allowing speculative loads into unmapped space,
which would cause an exception (annoying, even if ultimately harmless).
Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the
problem.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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A number of board ports have empty version of board_early_init_f
for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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* Enable flash progress
* remove CLEAR_LAW0 since we dont really use it
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Remove unused and unconfigured DDR test code from FSL 85xx boards.
Besides, other common code exists.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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This patch removes the unknown flash message information:
'## Unknown FLASH on Bank 1 - Size = 0xdeadbeef = -286261248 MB'
This unknown flash message is caused by PromJet.
Some of the board user is unhappy with this information.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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When we go to 36-bit physical addresses we need to keep the concept of
the physical CCSRBAR address seperate from the virtual one.
For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Now that all boards have been converted, remove old config code and the
config option for the new style.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.
Also, minor cleanup in cache.h to make the code a bit more readable.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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* Enabled CONFIG_CMD_ELF
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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* Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2
* Removed some misc environment setup
* Moved to using fdtfile & fdtaddr as fdt env var names
* Enabled CONFIG_CMDLINE_EDITING
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Updated the MPC8544DS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Basically, refactor the CFG_PIXIS_VBOOT_MASK values
into the separate board config files.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
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The RTC on the M1575 ULI chipset requires a dummy read before
we are able to talk to the RTC. We accomplish this by adding a
second memory region to the PHB the ULI is on and read from it.
The second region is added to maintain compatiabilty with Linux's
view of the PCI memory map.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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if a board/$(VENDOR)/common/Makefile exists, build it.
also add the first such case, board/freescale/common/Makefile, to
handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
dictated by board configuration.
thusly get rid of alternate build dir errors such as:
FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory
by putting the common/ mkdir command in its proper place (the common
Makefile). Common bits from existing individual board Makefiles have
been removed.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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and make some minor corrections to the FDT part of the README.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.
So make it use far less IO & memory space and have it use the shared LAW. This
free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed
by each bus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The tsec_info structure and array has a "flags" field for each
ethernet controller. This field is the only reason there are
settings. Switch to defining TSECn_FLAGS for each controller
in the config header, and we can greatly simplify the array, and
also simplify the addition of future boards.
Signed-off-by: Andy Fleming <afleming@freescale.com>
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PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.
Enable LBC and ECM errors and clear error registers.
Add tftpflash env var to get uboot from tftp server and flash it.
Add pci/pcie convenience env vars to display register space:
"run pcie3regs" to see all pcie3 ccsr registers
"run pcie3cfg" to see all cfg registers
Whitespace cleanup and MPC8544DS.h
Enable CONFIG_INTERRUPTS.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
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