From 18f5edacccb7ae2247e8cbe53c168bdd0a193f81 Mon Sep 17 00:00:00 2001 From: Joakim Axelsson Date: Fri, 22 Oct 2010 15:38:45 +0200 Subject: db8500: cpu-arch rename stw8500 to db8500 Started work with splitting the files in board/st/u8500 into proper SoC (system on a chip), drivers, commands and board code. ST-Ericsson ID: None Signed-off-by: Joakim Axelsson Change-Id: I33300b1990f377bc049785102f1c87fbe579e86d Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/7089 Reviewed-by: Robert ROSENGREN Reviewed-by: Markus HELGESSON Reviewed-by: Michael BRANDT Tested-by: Michael BRANDT Reviewed-by: Mikael LARSSON1 --- Makefile | 2 +- cpu/arm_cortexa9/db8500/Makefile | 48 +++ cpu/arm_cortexa9/db8500/clock.c | 56 +++ cpu/arm_cortexa9/db8500/interrupts.c | 181 +++++++++ cpu/arm_cortexa9/db8500/prcmu-fw-defs_v1.h | 586 ++++++++++++++++++++++++++++ cpu/arm_cortexa9/db8500/prcmu.c | 205 ++++++++++ cpu/arm_cortexa9/db8500/timer.c | 127 ++++++ cpu/arm_cortexa9/stw8500/Makefile | 48 --- cpu/arm_cortexa9/stw8500/clock.c | 56 --- cpu/arm_cortexa9/stw8500/interrupts.c | 181 --------- cpu/arm_cortexa9/stw8500/prcmu-fw-defs_v1.h | 586 ---------------------------- cpu/arm_cortexa9/stw8500/prcmu.c | 205 ---------- cpu/arm_cortexa9/stw8500/timer.c | 127 ------ include/asm-arm/arch-db8500/ab8500.h | 510 ++++++++++++++++++++++++ include/asm-arm/arch-db8500/bits.h | 58 +++ include/asm-arm/arch-db8500/clock.h | 72 ++++ include/asm-arm/arch-db8500/common.h | 138 +++++++ include/asm-arm/arch-db8500/gpio.h | 526 +++++++++++++++++++++++++ include/asm-arm/arch-db8500/hardware.h | 90 +++++ include/asm-arm/arch-db8500/mtu.h | 66 ++++ include/asm-arm/arch-stw8500/ab8500.h | 510 ------------------------ include/asm-arm/arch-stw8500/bits.h | 58 --- include/asm-arm/arch-stw8500/clock.h | 72 ---- include/asm-arm/arch-stw8500/common.h | 138 ------- include/asm-arm/arch-stw8500/gpio.h | 526 ------------------------- include/asm-arm/arch-stw8500/hardware.h | 90 ----- include/asm-arm/arch-stw8500/mtu.h | 66 ---- 27 files changed, 2664 insertions(+), 2664 deletions(-) create mode 100644 cpu/arm_cortexa9/db8500/Makefile create mode 100755 cpu/arm_cortexa9/db8500/clock.c create mode 100644 cpu/arm_cortexa9/db8500/interrupts.c create mode 100644 cpu/arm_cortexa9/db8500/prcmu-fw-defs_v1.h create mode 100644 cpu/arm_cortexa9/db8500/prcmu.c create mode 100644 cpu/arm_cortexa9/db8500/timer.c delete mode 100755 cpu/arm_cortexa9/stw8500/Makefile delete mode 100755 cpu/arm_cortexa9/stw8500/clock.c delete mode 100755 cpu/arm_cortexa9/stw8500/interrupts.c delete mode 100644 cpu/arm_cortexa9/stw8500/prcmu-fw-defs_v1.h delete mode 100644 cpu/arm_cortexa9/stw8500/prcmu.c delete mode 100644 cpu/arm_cortexa9/stw8500/timer.c create mode 100644 include/asm-arm/arch-db8500/ab8500.h create mode 100644 include/asm-arm/arch-db8500/bits.h create mode 100644 include/asm-arm/arch-db8500/clock.h create mode 100644 include/asm-arm/arch-db8500/common.h create mode 100644 include/asm-arm/arch-db8500/gpio.h create mode 100644 include/asm-arm/arch-db8500/hardware.h create mode 100644 include/asm-arm/arch-db8500/mtu.h delete mode 100644 include/asm-arm/arch-stw8500/ab8500.h delete mode 100755 include/asm-arm/arch-stw8500/bits.h delete mode 100644 include/asm-arm/arch-stw8500/clock.h delete mode 100644 include/asm-arm/arch-stw8500/common.h delete mode 100755 include/asm-arm/arch-stw8500/gpio.h delete mode 100644 include/asm-arm/arch-stw8500/hardware.h delete mode 100755 include/asm-arm/arch-stw8500/mtu.h diff --git a/Makefile b/Makefile index f0f865c11..994f76316 100644 --- a/Makefile +++ b/Makefile @@ -3180,7 +3180,7 @@ u8500_auto_config: echo "#define CONFIG_BOOT_SRAM" >> $(obj)include/config.h ; \ echo "TEXT_BASE = 0x40030000" >$(obj)board/st/u8500/config.tmp ; \ fi ; \ - $(MKCONFIG) -a u8500 arm arm_cortexa9 u8500 st stw8500 ; \ + $(MKCONFIG) -a u8500 arm arm_cortexa9 u8500 st db8500 ; \ fi ######################################################################### diff --git a/cpu/arm_cortexa9/db8500/Makefile b/cpu/arm_cortexa9/db8500/Makefile new file mode 100644 index 000000000..180da3026 --- /dev/null +++ b/cpu/arm_cortexa9/db8500/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o interrupts.o +COBJS += clock.o +COBJS += prcmu.o + +SRCS := $(START:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa9/db8500/clock.c b/cpu/arm_cortexa9/db8500/clock.c new file mode 100755 index 000000000..41f1bb254 --- /dev/null +++ b/cpu/arm_cortexa9/db8500/clock.c @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2009 ST-Ericsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct clkrst { + unsigned int pcken; + unsigned int pckdis; + unsigned int kcken; + unsigned int kckdis; +}; + +static unsigned int clkrst_base[] = { + U8500_CLKRST1_BASE, + U8500_CLKRST2_BASE, + U8500_CLKRST3_BASE, + NULL, + U8500_CLKRST5_BASE, + U8500_CLKRST6_BASE, + U8500_CLKRST7_BASE, /* ED only */ +}; + +/* Turn on peripheral clock at PRCC level */ +void u8500_clock_enable(int periph, int cluster, int kern) +{ + struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1]; + + if (kern != -1) + writel(1 << kern, &clkrst->kcken); + + if (cluster != -1) + writel(1 << cluster, &clkrst->pcken); +} diff --git a/cpu/arm_cortexa9/db8500/interrupts.c b/cpu/arm_cortexa9/db8500/interrupts.c new file mode 100644 index 000000000..4357ede39 --- /dev/null +++ b/cpu/arm_cortexa9/db8500/interrupts.c @@ -0,0 +1,181 @@ +/* + * (C) Copyright 2006, NXP BV + * Jean-Paul Saman + * + * (C) Copyright 2004 + * Texas Instruments + * Richard Woodruff + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +extern void reset_cpu(ulong addr); + +#ifdef CONFIG_USE_IRQ +/* enable IRQ interrupts */ +void enable_interrupts (void) +{ + unsigned long temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "bic %0, %0, #0x80\n" + "msr cpsr_c, %0" + : "=r" (temp) + : + : "memory"); +} + +/* + * disable IRQ/FIQ interrupts + * returns true if interrupts had been enabled before we disabled them + */ +int disable_interrupts (void) +{ + unsigned long old,temp; + __asm__ __volatile__("mrs %0, cpsr\n" + "orr %1, %0, #0xc0\n" + "msr cpsr_c, %1" + : "=r" (old), "=r" (temp) + : + : "memory"); + return(old & 0x80) == 0; +} +#else +void enable_interrupts (void) +{ + return; +} +int disable_interrupts (void) +{ + return 0; +} +#endif + + +void bad_mode (void) +{ + panic ("Resetting CPU ...\n"); + reset_cpu (0); +} + +void show_regs (struct pt_regs *regs) +{ + unsigned long flags; + const char *processor_modes[] = { + "USER_26", "FIQ_26", "IRQ_26", "SVC_26", + "UK4_26", "UK5_26", "UK6_26", "UK7_26", + "UK8_26", "UK9_26", "UK10_26", "UK11_26", + "UK12_26", "UK13_26", "UK14_26", "UK15_26", + "USER_32", "FIQ_32", "IRQ_32", "SVC_32", + "UK4_32", "UK5_32", "UK6_32", "ABT_32", + "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK12_32", "UK13_32", "UK14_32", "SYS_32", + }; + + flags = condition_codes (regs); + + printf ("pc : [<%08lx>] lr : [<%08lx>]\n" + "sp : %08lx ip : %08lx fp : %08lx\n", + instruction_pointer (regs), + regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); + printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", + regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); + printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", + regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); + printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", + regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); + printf ("Flags: %c%c%c%c", + flags & CC_N_BIT ? 'N' : 'n', + flags & CC_Z_BIT ? 'Z' : 'z', + flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); + printf (" IRQs %s FIQs %s Mode %s%s\n", + interrupts_enabled (regs) ? "on" : "off", + fast_interrupts_enabled (regs) ? "on" : "off", + processor_modes[processor_mode (regs)], + thumb_mode (regs) ? " (T)" : ""); +} + +void do_undefined_instruction (struct pt_regs *pt_regs) +{ + printf ("undefined instruction\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_software_interrupt (struct pt_regs *pt_regs) +{ + printf ("software interrupt\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_prefetch_abort (struct pt_regs *pt_regs) +{ + printf ("prefetch abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_data_abort (struct pt_regs *pt_regs) +{ + printf ("data abort\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_not_used (struct pt_regs *pt_regs) +{ + printf ("not used\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_fiq (struct pt_regs *pt_regs) +{ + printf ("fast interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +void do_irq (struct pt_regs *pt_regs) +{ + printf ("interrupt request\n"); + show_regs (pt_regs); + bad_mode (); +} + +/* nothing really to do with interrupts, just starts up a counter. */ +int interrupt_init (void) +{ + + (void) timer_init(); + + return(0); +} diff --git a/cpu/arm_cortexa9/db8500/prcmu-fw-defs_v1.h b/cpu/arm_cortexa9/db8500/prcmu-fw-defs_v1.h new file mode 100644 index 000000000..046f89e21 --- /dev/null +++ b/cpu/arm_cortexa9/db8500/prcmu-fw-defs_v1.h @@ -0,0 +1,586 @@ +/* + * Copyright (c) 2009 ST-Ericsson SA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * Copied from the Linux version: + * Author: Kumar Sanghvi + */ + +#ifndef __MACH_PRCMU_FW_DEFS_V1_H +#define __MACH_PRCMU_FW_DEFS_V1_H + +/** + * enum state_t - ON/OFF state definition + * @OFF: State is ON + * @ON: State is OFF + * + */ +enum state_t { + OFF = 0x0, + ON = 0x1, +}; + +/** + * enum ret_state_t - general purpose On/Off/Retention states + * + */ +enum ret_state_t { + OFFST = 0, + ONST = 1, + RETST = 2 +}; + + +/** + * enum clk_arm_t - ARM Cortex A9 clock schemes + * @A9_OFF: + * @A9_BOOT: + * @A9_OPPT1: + * @A9_OPPT2: + * @A9_EXTCLK: + */ +enum clk_arm_t { + A9_OFF, + A9_BOOT, + A9_OPPT1, + A9_OPPT2, + A9_EXTCLK +}; + +/** + * enum clk_gen_t - GEN#0/GEN#1 clock schemes + * @GEN_OFF: + * @GEN_BOOT: + * @GEN_OPPT1: + */ +enum clk_gen_t { + GEN_OFF, + GEN_BOOT, + GEN_OPPT1, +}; + +/* some information between arm and xp70 */ + +/** + * enum romcode_write_t - Romcode message written by A9 AND read by XP70 + * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70 + * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the + * romcode. The xp70 will go into self-reset + */ +enum romcode_write_t { + RDY_2_DS = 0x09, + RDY_2_XP70_RST = 0x10 +}; + +/** + * enum romcode_read_t - Romcode message written by XP70 and read by A9 + * @INIT: Init value when romcode field is not used + * @FS_2_DS: Value set when power state is going from ApExecute to + * ApDeepSleep + * @END_DS: Value set when ApDeepSleep power state is reached coming from + * ApExecute state + * @DS_TO_FS: Value set when power state is going from ApDeepSleep to + * ApExecute + * @END_FS: Value set when ApExecute power state is reached coming from + * ApDeepSleep state + * @SWR: Value set when power state is going to ApReset + * @END_SWR: Value set when the xp70 finished executing ApReset actions and + * waits for romcode acknowledgment to go to self-reset + */ +enum romcode_read_t { + INIT = 0x00, + FS_2_DS = 0x0A, + END_DS = 0x0B, + DS_TO_FS = 0x0C, + END_FS = 0x0D, + SWR = 0x0E, + END_SWR = 0x0F +}; + + +/** + * enum pingpong_t + * @PING: value is 0 + * @PONG: value is 1 + * + * implementation issue: the values are chosen the way that + * we can change from ping to pong (resp. pong to ping) by + * simply using the 'not' operator in C, e.g. toggling operation: + * t_PingPong p = ping; p = ~p; + */ +enum pingpong_t { + PING = 0x00, + PONG = 0xFF +}; + +/** + * enum wkup_reason_fdst_t + * @EVTWR: event has been read by ARM + * @EVTST: event has been sent by PRCMU FW + * @EVTRD: event has been written by PRCMU FW + */ +enum wkup_reason_fdst_t { + /* WRF has been written but neither sent nor read by the arm */ + EVTWR = 1, + /* WRF has been written and sent, but not yet read by the arm */ + EVTST = 2, + /* WRF has been written, sent and read by the arm */ + EVTRD = 0 +}; /* Wake-up reason Field State */ + + + +/** + * enum ap_pwrst_t - current power states defined in PRCMU firmware + * @NO_PWRST: Current power state init + * @AP_BOOT: Current power state is apBoot + * @AP_EXECUTE: Current power state is apExecute + * @AP_DEEP_SLEEP: Current power state is apDeepSleep + * @AP_SLEEP: Current power state is apSleep + * @AP_IDLE: Current power state is apIdle + * @AP_RESET: Current power state is apReset + */ +enum ap_pwrst_t { + NO_PWRST = 0x00, + AP_BOOT = 0x01, + AP_EXECUTE = 0x02, + AP_DEEP_SLEEP = 0x03, + AP_SLEEP = 0x04, + AP_IDLE = 0x05, + AP_RESET = 0x06 +}; + +/** + * enum ap_pwrst_trans_t - Transition states defined in PRCMU firmware + * @NO_TRANSITION: No power state transition + * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep + * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep + * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute + * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to + * ApDeepSleep + * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle + */ +enum ap_pwrst_trans_t { + NO_TRANSITION = 0x00, + APEXECUTE_TO_APSLEEP = 0x01, + APIDLE_TO_APSLEEP = 0x02, + APBOOT_TO_APEXECUTE = 0x03, + APEXECUTE_TO_APDEEPSLEEP = 0x04, + APEXECUTE_TO_APIDLE = 0x05 +}; + +/** + * enum ddr_pwrst_t - DDR power states definition + * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged + * @DDR_PWR_STATE_ON: + * @DDR_PWR_STATE_OFFLOWLAT: + * @DDR_PWR_STATE_OFFHIGHLAT: + */ +enum ddr_pwrst_t { + DDR_PWR_STATE_UNCHANGED = 0x00, + DDR_PWR_STATE_ON = 0x01, + DDR_PWR_STATE_OFFLOWLAT = 0x02, + DDR_PWR_STATE_OFFHIGHLAT = 0x03 +}; + +/** + * enum arm_opp_t - ARM OPP states definition + * @ARM_NO_CHANGE: The ARM operating point is unchanged + * @ARM_100_OPP: The new ARM operating point is arm100opp + * @ARM_50_OPP: The new ARM operating point is arm100opp + * @ARM_EXTCLK: The new ARM operating point is armExtClk + */ +enum arm_opp_t { + ARM_NO_CHANGE = 0x00, + ARM_100_OPP = 0x02, + ARM_50_OPP = 0x03, + ARM_EXTCLK = 0x07 +}; + +/** + * enum ape_opp_t - APE OPP states definition + * @APE_NO_CHANGE: The APE operating point is unchanged + * @APE_100_OPP: The new APE operating point is ape100opp + */ +enum ape_opp_t { + APE_NO_CHANGE = 0x00, + APE_100_OPP = 0x02, + APE_50_OPP = 0x03 +}; + +/** + * enum hw_accst_t - State definition for hardware accelerator + * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged + * @HW_OFF: The hardware accelerator must be switched off + * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its + * internal RAM in retention + * @HW_ON: The hwa hadware accelerator hwa must be switched on + */ +enum hw_accst_t { + HW_NO_CHANGE = 0x00, + HW_OFF = 0x01, + HW_OFF_RAMRET = 0x02, + HW_ON = 0x03 +}; + +/** + * enum mbox_2_arm_stat_t - Status messages definition for mbox_arm + * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been + * completed + * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been + * completed + * @SLEEPOK: The apExecute to apSleep state transition has been completed + * @IDLEOK: The apExecute to apIdle state transition has been completed + * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed + * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going + * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going + * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on + * going + * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on + * going + * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has + * been completed + * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going + * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going + * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been + * completed + * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going + * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going + * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been + * completed + * @INIT_STATUS: Status init + */ +enum ap_pwrsttr_status_t { + BOOT_TO_EXECUTEOK = 0xFF, + DEEPSLEEPOK = 0xFE, + SLEEPOK = 0xFD, + IDLEOK = 0xFC, + SOFTRESETOK = 0xFB, + SOFTRESETGO = 0xFA, + BOOT_TO_EXECUTE = 0xF9, + EXECUTE_TO_DEEPSLEEP = 0xF8, + DEEPSLEEP_TO_EXECUTE = 0xF7, + DEEPSLEEP_TO_EXECUTEOK = 0xF6, + EXECUTE_TO_SLEEP = 0xF5, + SLEEP_TO_EXECUTE = 0xF4, + SLEEP_TO_EXECUTEOK = 0xF3, + EXECUTE_TO_IDLE = 0xF2, + IDLE_TO_EXECUTE = 0xF1, + IDLE_TO_EXECUTEOK = 0xF0, + RDYTODS_RETURNTOEXE = 0xEF, + NORDYTODS_RETURNTOEXE = 0xEE, + EXETOSLEEP_RETURNTOEXE = 0xED, + EXETOIDLE_RETURNTOEXE = 0xEC, + INIT_STATUS = 0xEB, + + /*error messages */ + INITERROR = 0x00, + PLLARMLOCKP_ER = 0x01, + PLLDDRLOCKP_ER = 0x02, + PLLSOCLOCKP_ER = 0x03, + PLLSOCK1LOCKP_ER = 0x04, + ARMWFI_ER = 0x05, + SYSCLKOK_ER = 0x06, + I2C_NACK_DATA_ER = 0x07, + BOOT_ER = 0x08, + I2C_STATUS_ALWAYS_1 = 0x0A, + I2C_NACK_REG_ADDR_ER = 0x0B, + I2C_NACK_DATA0123_ER = 0x1B, + I2C_NACK_ADDR_ER = 0x1F, + CURAPPWRSTISNOT_BOOT = 0x20, + CURAPPWRSTISNOT_EXECUTE = 0x21, + CURAPPWRSTISNOT_SLEEPMODE = 0x22, + CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23, + FIFO4500WUISNOT_WUPEVENT = 0x24, + PLL32KLOCKP_ER = 0x29, + DDRDEEPSLEEPOK_ER = 0x2A, + ROMCODEREADY_ER = 0x50, + WUPBEFOREDS = 0x51, + DDRCONFIG_ER = 0x52, + WUPBEFORESLEEP = 0x53, + WUPBEFOREIDLE = 0x54 +}; /* earlier called as mbox_2_arm_stat_t */ + + +/** + * enum dvfs_stat_t - DVFS status messages definition + * @DVFS_GO: A state transition DVFS is on going + * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP + * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP + * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK + * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for + * NOCHGCLK + * @DVFS_INITSTATUS: Value init + */ +enum dvfs_stat_t { + DVFS_GO = 0xFF, + DVFS_ARM100OPPOK = 0xFE, + DVFS_ARM50OPPOK = 0xFD, + DVFS_ARMEXTCLKOK = 0xFC, + DVFS_NOCHGTCLKOK = 0xFB, + DVFS_INITSTATUS = 0x00 +}; + +/** + * enum mbox_2_arm_hwacc_pwr_stat_t - Hardware Accelarator status message + * @HWACC_PWRST_GO: A state transition on hardware accelerator is on going + * @HWACC_PWRST_OK: The state transition on hardware accelerator has been + * completed + * @HWACC_PWRSTATUS_INIT: Value init + */ +enum mbox_2_arm_hwacc_pwr_stat_t { + HWACC_PWRST_GO = 0xFF, + HWACC_PWRST_OK = 0xFE, + HWACC_PWRSTATUS_INIT = 0x00 +}; + +/** + * enum sva_mmdsp_stat_t - SVA MMDSP status messages + * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened + * @SVA_MMDSP_INIT: Status init + */ +enum sva_mmdsp_stat_t { + SVA_MMDSP_GO = 0xFF, + SVA_MMDSP_INIT = 0x00 +}; + +/** + * enum sia_mmdsp_stat_t - SIA MMDSP status messages + * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened + * @SIA_MMDSP_INIT: Status init + */ +enum sia_mmdsp_stat_t { + SIA_MMDSP_GO = 0xFF, + SIA_MMDSP_INIT = 0x00 +}; + +/** + * enum intr_wakeup_t - Configure STW4500 FIFO interrupt as wake-up + * @NTR_NOT_AS_WAKEUP: The 4500 fifo interrupt is not configured as a + * wake-up event + * @INTR_AS_WAKEUP: The 4500 fifo interrupt is configured as a wake-up event + */ +enum intr_wakeup_t { + INTR_NOT_AS_WAKEUP = 0x0, + INTR_AS_WAKEUP = 0x1 +}; + +/** + * enum mbox_to_arm_err_t - Error messages definition + * @INIT_ERR: Init value + * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time + * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time + * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time + * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time + * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time + * @SYSCLKOK_ERR: The SYSCLK is not available in the given time + * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time + * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context + * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered + * through I2C has not been correctly executed in the given time + * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered + * through I2C has not been correctly executed in the given time + * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through + * I2C has not been correctly executed in the given time + * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered + * through I2C has not been correctly executed in the given time + * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through + * I2C has not been correctly executed in the given time + * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered + * through I2C has not been correctly executed in the given time + * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through + * I2C has not been correctly executed in the given time + * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C + * has not been correctly executed in the given time + * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has + * not been correctly executed in the given time + * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has + * not been correctly executed in the given time + * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through + * I2C has not been correctly executed in the given time + * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through + * I2C has not been correctly executed in the given time + * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered + * through I2C has not been correctly executed in the given time + * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition + * ApBoot to ApExecute but the power current state is not Apboot + * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state + * transition from ApExecute to others power state but the + * power current state is not ApExecute + * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted + * but the power current state is not ApDeepSleep/ApSleep/ApIdle + * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted + * but the power current state is not correct + * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not + * been correctly executed in the given time + * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not + * been correctly executed in the given time + * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not + * been correctly executed in the given time + * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not + * been correctly executed in the given time + * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not + * been correctly executed in the given time + */ +enum mbox_to_arm_err_t { + INIT_ERR = 0x00, + PLLARMLOCKP_ERR = 0x01, + PLLDDRLOCKP_ERR = 0x02, + PLLSOC0LOCKP_ERR = 0x03, + PLLSOC1LOCKP_ERR = 0x04, + ARMWFI_ERR = 0x05, + SYSCLKOK_ERR = 0x06, + BOOT_ERR = 0x07, + ROMCODESAVECONTEXT = 0x08, + VARMHIGHSPEEDVALTO_ERR = 0x10, + VARMHIGHSPEEDACCESS_ERR = 0x11, + VARMLOWSPEEDVALTO_ERR = 0x12, + VARMLOWSPEEDACCESS_ERR = 0x13, + VARMRETENTIONVALTO_ERR = 0x14, + VARMRETENTIONACCESS_ERR = 0x15, + VAPEHIGHSPEEDVALTO_ERR = 0x16, + VSAFEHPVALTO_ERR = 0x17, + VMODSEL1VALTO_ERR = 0x18, + VMODSEL2VALTO_ERR = 0x19, + VARMOFFACCESS_ERR = 0x1A, + VAPEOFFACCESS_ERR = 0x1B, + VARMRETACCES_ERR = 0x1C, + CURAPPWRSTISNOTBOOT = 0x20, + CURAPPWRSTISNOTEXECUTE = 0x21, + CURAPPWRSTISNOTSLEEPMODE = 0x22, + CURAPPWRSTISNOTCORRECTDBG = 0x23, + ARMREGU1VALTO_ERR = 0x24, + ARMREGU2VALTO_ERR = 0x25, + VAPEREGUVALTO_ERR = 0x26, + VSMPS3REGUVALTO_ERR = 0x27, + VMODREGUVALTO_ERR = 0x28 +}; + +enum hw_acc_t { + SVAMMDSP = 0, + SVAPIPE = 1, + SIAMMDSP = 2, + SIAPIPE = 3, + SGA = 4, + B2R2MCDE = 5, + ESRAM1 = 6, + ESRAM2 = 7, + ESRAM3 = 8, + ESRAM4 = 9 +}; + +enum reqmb0_header_t { + PWRSTTRH = 0, + WKUPCFG_EXEH = 1, + WKUP_EXEH = 2, + RDWKUPACKH = 3, + WKUPCFG_SLEEPH = 4, + WKUP_SLEEPH = 5, +}; + +enum cs_pwrmgt_t { + PWRDNCS0 = 0, + WKUPCS0 = 1, + PWRDNCS1 = 2, + WKUPCS1 = 3 +}; + +enum reqmb2_header_t { + DPS_H = 0, + HW_ACCT_AUTO_PWR_H = 1, +}; + + +/* Defs related to autonomous power management */ + +/** + * enum sia_sva_pwr_policy_t - Power policy + * @NO_CHGT: No change + * @DSPOFF_HWPOFF: + * @DSPOFFRAMRET_HWPOFF: + * @DSPCLKOFF_HWPOFF: + * @DSPCLKOFF_HWPCLKOFF: + * + */ +enum sia_sva_pwr_policy_t { + NO_CHGT = 0x0, + DSPOFF_HWPOFF = 0x1, + DSPOFFRAMRET_HWPOFF = 0x2, + DSPCLKOFF_HWPOFF = 0x3, + DSPCLKOFF_HWPCLKOFF = 0x4, +}; + +/** + * enum auto_enable_t - Auto Power enable + * @AUTO_OFF: + * @AUTO_ON: + * + */ +enum auto_enable_t { + AUTO_OFF = 0x0, + AUTO_ON = 0x1, +}; + + +/** + * enum reqmb4_header_t -Header type for mail box 4 + * @MEMSTH: The ARM can set what are the expected memory states depending on + * the AP power states. + * @PARTIALREFRESHH: ARM has to update MR16 & MR17 of SDRAM register, for + * partial-refresh of SDRAM, via this mailbox + * @AUTOREFRESHH: Enable to change cycle count before enabling automatic + * DDR self-refresh + * @CSPWRDNH: Enables to lock/unlock one of SDRAM memory cut in self-refresh + * In V2,this service will enable to put CS in pwrdn + * @SYSCLKH: Enables to switch SYSCLK ON/OFF on the AP side + * @USBWKUPH: Used to enable USB wakeup event of PRCMU + */ +enum reqmb4_header_t { + MEM_ST_H = 0, + PARTIAL_S_REFRESH_H = 1, + AUTO_REFRESH_H = 2, + CS_PWRDN_H = 3, + SYSCLK_H = 5, + AUTO_PWR_H = 6, + USB_WKUP_H = 7 +}; + +enum ack_mb4_status_t { + ACKMB4_INIT = 0, + SYSCLKON_OK = 1, + DDRON_OK = 2 +}; + +enum I2C_op_t { + I2CWRITE = 0, + I2CREAD = 1 +}; + +enum ack_mb5_status_t { + ACKMB5_INIT = 0x00, + I2C_WR_OK = 0x01, + I2C_RD_OK = 0x02, + SYSCLK_OK = 0x03, + I2C_TIMEOUT = 0x11, + SYSCLK_ER = 0x12, + /*Error Status resent by PRCM_HWI2C_SR*/ + I2CWR_NACK_DATA_ER = 0x07, + I2CWR_NACK_REG_ADDR_ER = 0x0B, + I2CRDWR_NACK_DATA0123_ER = 0x1B, + I2CWR_NACK_ADDR_ER = 0x1F, + I2CRD_NACK_ADDR_INIT_ER = 0x0F, + I2CRD_NACK_REG_ADDR_INIT_ER = 0x13, + I2CRD_NACK_ADDR_ER = 0x17 +}; + +enum ack_mb7_status_t { + MOD_SW_RESET_REQ = 0x03, + CA_SLEEP_REQ = 0x02, + HOST_PORT_ACK = 0x01, + ACKMB7_INIT = 0x00 +}; + +#endif /* __MACH_PRCMU_FW_DEFS_V1_H */ diff --git a/cpu/arm_cortexa9/db8500/prcmu.c b/cpu/arm_cortexa9/db8500/prcmu.c new file mode 100644 index 000000000..e411d1a1c --- /dev/null +++ b/cpu/arm_cortexa9/db8500/prcmu.c @@ -0,0 +1,205 @@ +/* + * Copyright (C) 2009 ST-Ericsson SA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * Adapted from the Linux version: + * Author: Kumar Sanghvi + */ + +/* + * NOTE: This currently does not support the I2C workaround access method. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include "prcmu-fw-defs_v1.h" + +#define DEBUG 0 +#define dbg_printk(format, arg...) \ + if (DEBUG) \ + printf("prcmu: " format, ##arg) \ + +#define PRCMU_BASE U8500_PRCMU_BASE + +#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0fc) +#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100) + +#define PRCM_XP70_CUR_PWR_STATE (tcdm_base + 0xFFC) + +#define PRCM_REQ_MB5 (tcdm_base + 0xE44) +#define PRCM_ACK_MB5 (tcdm_base + 0xDF4) + +/* Mailbox 5 Requests */ +#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) +#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) +#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) +#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) + +/* Mailbox 5 ACKs */ +#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) +#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) +#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) + +#define PRCMU_I2C_WRITE(slave) \ + (((slave) << 1) | I2CWRITE | (cpu_is_u8500v2() ? (1 << 6) : 0)) + +#define PRCMU_I2C_READ(slave) \ + (((slave) << 1) | I2CREAD | (cpu_is_u8500v2() ? (1 << 6) : 0)) + +enum mailbox_t { + REQ_MB0 = 0, /* Uses XP70_IT_EVENT_10 */ + REQ_MB1 = 1, /* Uses XP70_IT_EVENT_11 */ + REQ_MB2 = 2, /* Uses XP70_IT_EVENT_12 */ + REQ_MB5 = 5, /* Uses XP70_IT_EVENT_17 */ +}; + +static void *tcdm_base; + +static int prcmu_is_ready(void) +{ + int ready; + + if (!tcdm_base) { + if (cpu_is_u8500v1()) + tcdm_base = (void *) U8500_PRCMU_TCDM_BASE_V1; + else if (cpu_is_u8500v2()) + tcdm_base = (void *) U8500_PRCMU_TCDM_BASE; + else { + printf("PRCMU: Unsupported chip version\n"); + return 0; + } + } + + ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; + if (!ready) + printf("PRCMU firmware not ready\n"); + + return ready; +} + +static int _wait_for_req_complete(enum mailbox_t num) +{ + int timeout = 1000; + + /* checking any already on-going transaction */ + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) + ; + + timeout = 1000; + + /* Set an interrupt to XP70 */ + writel(1 << num, PRCM_MBOX_CPU_SET); + + while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) + ; + + if (!timeout) { + printf("PRCMU operation timed out\n"); + return -1; + } + + return 0; +} + +/** + * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db8500 register to be accessed + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_read(u8 reg, u16 slave) +{ + uint8_t i2c_status; + uint8_t i2c_val; + + if (!prcmu_is_ready()) + return -1; + + dbg_printk("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", + reg, slave); + + /* prepare the data for mailbox 5 */ + writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG); + writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(0, PRCM_REQ_MB5_I2CVAL); + + _wait_for_req_complete(REQ_MB5); + + /* retrieve values */ + dbg_printk("ack-mb5:transfer status = %x\n", + readb(PRCM_ACK_MB5_STATUS)); + dbg_printk("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); + dbg_printk("ack-mb5:slave_add = %x\n", + readb(PRCM_ACK_MB5_SLAVE)); + dbg_printk("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); + + i2c_status = readb(PRCM_ACK_MB5_STATUS); + i2c_val = readb(PRCM_ACK_MB5_VAL); + + if (i2c_status == I2C_RD_OK) + return i2c_val; + else { + + printf("prcmu_i2c_read:read return status= %d\n", + i2c_status); + return -1; + } + +} + +/** + * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C + * @reg: - db8500 register bank to be accessed + * @slave: - db800 register to be written to + * @reg_data: - the data to write + * Returns: ACK_MB5 value containing the status + */ +int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) +{ + uint8_t i2c_status; + + if (!prcmu_is_ready()) + return -1; + + dbg_printk("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", + reg, slave); + + /* prepare the data for mailbox 5 */ + writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG); + writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); + writeb(slave, PRCM_REQ_MB5_I2CSLAVE); + writeb(reg_data, PRCM_REQ_MB5_I2CVAL); + + dbg_printk("\ncpu_is_u8500v11\n"); + _wait_for_req_complete(REQ_MB5); + + /* retrieve values */ + dbg_printk("ack-mb5:transfer status = %x\n", + readb(PRCM_ACK_MB5_STATUS)); + dbg_printk("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); + dbg_printk("ack-mb5:slave_add = %x\n", + readb(PRCM_ACK_MB5_SLAVE)); + dbg_printk("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); + + i2c_status = readb(PRCM_ACK_MB5_STATUS); + dbg_printk("\ni2c_status = %x\n", i2c_status); + if (i2c_status == I2C_WR_OK) + return 0; + else { + printf("ape-i2c: i2c_status : 0x%x\n", i2c_status); + return -1; + } +} diff --git a/cpu/arm_cortexa9/db8500/timer.c b/cpu/arm_cortexa9/db8500/timer.c new file mode 100644 index 000000000..bc27755b1 --- /dev/null +++ b/cpu/arm_cortexa9/db8500/timer.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. + */ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +/* + * The MTU is clocked at 133 MHz by default. (V1 and later) + */ +#define TIMER_CLOCK (133 * 1000 * 1000 / 16) +#define COUNT_TO_USEC(x) ((x) * 16 / 133) +#define USEC_TO_COUNT(x) ((x) * 133 / 16) +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) + +/* + * MTU timer to use (from 0 to 3). + * Linux ux500 timer0 on MTU0 and timer0 on MTU1 + */ +#define MTU_TIMER 2 + +static unsigned int timerbase; + +/* macro to read the 32 bit timer: since it decrements, we invert read value */ +#define READ_TIMER() (~readl(timerbase + MTU_VAL(MTU_TIMER))) + +/* Configure a free-running, auto-wrap counter with /16 prescaler */ +int timer_init(void) +{ + timerbase = u8500_is_earlydrop() ? U8500_MTU0_BASE_ED + : U8500_MTU0_BASE_V1; + + writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_16 | MTU_CRn_32BITS, + timerbase + MTU_CR(MTU_TIMER)); + reset_timer(); + return 0; +} + +/* Restart counting from 0 */ +void reset_timer(void) +{ + writel(0, timerbase + MTU_LR(MTU_TIMER)); /* Immediate effect */ +} + +/* Return how many HZ passed since "base" */ +ulong get_timer(ulong base) +{ + return TICKS_TO_HZ(READ_TIMER()) - base; +} + +u64 get_timer_us(void) +{ + return COUNT_TO_USEC(READ_TIMER()); +} + +/* Delay x useconds */ +void udelay(unsigned long usec) +{ + ulong ini, end; + + ini = READ_TIMER(); + end = ini + USEC_TO_COUNT(usec); + while ((signed)(end - READ_TIMER()) > 0) + ; + boottime_idle_add(usec); +} diff --git a/cpu/arm_cortexa9/stw8500/Makefile b/cpu/arm_cortexa9/stw8500/Makefile deleted file mode 100755 index 180da3026..000000000 --- a/cpu/arm_cortexa9/stw8500/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = timer.o interrupts.o -COBJS += clock.o -COBJS += prcmu.o - -SRCS := $(START:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -START := $(addprefix $(obj),$(START)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/cpu/arm_cortexa9/stw8500/clock.c b/cpu/arm_cortexa9/stw8500/clock.c deleted file mode 100755 index 41f1bb254..000000000 --- a/cpu/arm_cortexa9/stw8500/clock.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * (C) Copyright 2009 ST-Ericsson - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct clkrst { - unsigned int pcken; - unsigned int pckdis; - unsigned int kcken; - unsigned int kckdis; -}; - -static unsigned int clkrst_base[] = { - U8500_CLKRST1_BASE, - U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, - NULL, - U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE, - U8500_CLKRST7_BASE, /* ED only */ -}; - -/* Turn on peripheral clock at PRCC level */ -void u8500_clock_enable(int periph, int cluster, int kern) -{ - struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1]; - - if (kern != -1) - writel(1 << kern, &clkrst->kcken); - - if (cluster != -1) - writel(1 << cluster, &clkrst->pcken); -} diff --git a/cpu/arm_cortexa9/stw8500/interrupts.c b/cpu/arm_cortexa9/stw8500/interrupts.c deleted file mode 100755 index 4357ede39..000000000 --- a/cpu/arm_cortexa9/stw8500/interrupts.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * (C) Copyright 2006, NXP BV - * Jean-Paul Saman - * - * (C) Copyright 2004 - * Texas Instruments - * Richard Woodruff - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * Alex Zuepke - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -extern void reset_cpu(ulong addr); - -#ifdef CONFIG_USE_IRQ -/* enable IRQ interrupts */ -void enable_interrupts (void) -{ - unsigned long temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "bic %0, %0, #0x80\n" - "msr cpsr_c, %0" - : "=r" (temp) - : - : "memory"); -} - -/* - * disable IRQ/FIQ interrupts - * returns true if interrupts had been enabled before we disabled them - */ -int disable_interrupts (void) -{ - unsigned long old,temp; - __asm__ __volatile__("mrs %0, cpsr\n" - "orr %1, %0, #0xc0\n" - "msr cpsr_c, %1" - : "=r" (old), "=r" (temp) - : - : "memory"); - return(old & 0x80) == 0; -} -#else -void enable_interrupts (void) -{ - return; -} -int disable_interrupts (void) -{ - return 0; -} -#endif - - -void bad_mode (void) -{ - panic ("Resetting CPU ...\n"); - reset_cpu (0); -} - -void show_regs (struct pt_regs *regs) -{ - unsigned long flags; - const char *processor_modes[] = { - "USER_26", "FIQ_26", "IRQ_26", "SVC_26", - "UK4_26", "UK5_26", "UK6_26", "UK7_26", - "UK8_26", "UK9_26", "UK10_26", "UK11_26", - "UK12_26", "UK13_26", "UK14_26", "UK15_26", - "USER_32", "FIQ_32", "IRQ_32", "SVC_32", - "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", - "UK12_32", "UK13_32", "UK14_32", "SYS_32", - }; - - flags = condition_codes (regs); - - printf ("pc : [<%08lx>] lr : [<%08lx>]\n" - "sp : %08lx ip : %08lx fp : %08lx\n", - instruction_pointer (regs), - regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); - printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); - printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); - printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); - printf ("Flags: %c%c%c%c", - flags & CC_N_BIT ? 'N' : 'n', - flags & CC_Z_BIT ? 'Z' : 'z', - flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); - printf (" IRQs %s FIQs %s Mode %s%s\n", - interrupts_enabled (regs) ? "on" : "off", - fast_interrupts_enabled (regs) ? "on" : "off", - processor_modes[processor_mode (regs)], - thumb_mode (regs) ? " (T)" : ""); -} - -void do_undefined_instruction (struct pt_regs *pt_regs) -{ - printf ("undefined instruction\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_software_interrupt (struct pt_regs *pt_regs) -{ - printf ("software interrupt\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_prefetch_abort (struct pt_regs *pt_regs) -{ - printf ("prefetch abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_data_abort (struct pt_regs *pt_regs) -{ - printf ("data abort\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_not_used (struct pt_regs *pt_regs) -{ - printf ("not used\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_fiq (struct pt_regs *pt_regs) -{ - printf ("fast interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -void do_irq (struct pt_regs *pt_regs) -{ - printf ("interrupt request\n"); - show_regs (pt_regs); - bad_mode (); -} - -/* nothing really to do with interrupts, just starts up a counter. */ -int interrupt_init (void) -{ - - (void) timer_init(); - - return(0); -} diff --git a/cpu/arm_cortexa9/stw8500/prcmu-fw-defs_v1.h b/cpu/arm_cortexa9/stw8500/prcmu-fw-defs_v1.h deleted file mode 100644 index 046f89e21..000000000 --- a/cpu/arm_cortexa9/stw8500/prcmu-fw-defs_v1.h +++ /dev/null @@ -1,586 +0,0 @@ -/* - * Copyright (c) 2009 ST-Ericsson SA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * Copied from the Linux version: - * Author: Kumar Sanghvi - */ - -#ifndef __MACH_PRCMU_FW_DEFS_V1_H -#define __MACH_PRCMU_FW_DEFS_V1_H - -/** - * enum state_t - ON/OFF state definition - * @OFF: State is ON - * @ON: State is OFF - * - */ -enum state_t { - OFF = 0x0, - ON = 0x1, -}; - -/** - * enum ret_state_t - general purpose On/Off/Retention states - * - */ -enum ret_state_t { - OFFST = 0, - ONST = 1, - RETST = 2 -}; - - -/** - * enum clk_arm_t - ARM Cortex A9 clock schemes - * @A9_OFF: - * @A9_BOOT: - * @A9_OPPT1: - * @A9_OPPT2: - * @A9_EXTCLK: - */ -enum clk_arm_t { - A9_OFF, - A9_BOOT, - A9_OPPT1, - A9_OPPT2, - A9_EXTCLK -}; - -/** - * enum clk_gen_t - GEN#0/GEN#1 clock schemes - * @GEN_OFF: - * @GEN_BOOT: - * @GEN_OPPT1: - */ -enum clk_gen_t { - GEN_OFF, - GEN_BOOT, - GEN_OPPT1, -}; - -/* some information between arm and xp70 */ - -/** - * enum romcode_write_t - Romcode message written by A9 AND read by XP70 - * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70 - * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the - * romcode. The xp70 will go into self-reset - */ -enum romcode_write_t { - RDY_2_DS = 0x09, - RDY_2_XP70_RST = 0x10 -}; - -/** - * enum romcode_read_t - Romcode message written by XP70 and read by A9 - * @INIT: Init value when romcode field is not used - * @FS_2_DS: Value set when power state is going from ApExecute to - * ApDeepSleep - * @END_DS: Value set when ApDeepSleep power state is reached coming from - * ApExecute state - * @DS_TO_FS: Value set when power state is going from ApDeepSleep to - * ApExecute - * @END_FS: Value set when ApExecute power state is reached coming from - * ApDeepSleep state - * @SWR: Value set when power state is going to ApReset - * @END_SWR: Value set when the xp70 finished executing ApReset actions and - * waits for romcode acknowledgment to go to self-reset - */ -enum romcode_read_t { - INIT = 0x00, - FS_2_DS = 0x0A, - END_DS = 0x0B, - DS_TO_FS = 0x0C, - END_FS = 0x0D, - SWR = 0x0E, - END_SWR = 0x0F -}; - - -/** - * enum pingpong_t - * @PING: value is 0 - * @PONG: value is 1 - * - * implementation issue: the values are chosen the way that - * we can change from ping to pong (resp. pong to ping) by - * simply using the 'not' operator in C, e.g. toggling operation: - * t_PingPong p = ping; p = ~p; - */ -enum pingpong_t { - PING = 0x00, - PONG = 0xFF -}; - -/** - * enum wkup_reason_fdst_t - * @EVTWR: event has been read by ARM - * @EVTST: event has been sent by PRCMU FW - * @EVTRD: event has been written by PRCMU FW - */ -enum wkup_reason_fdst_t { - /* WRF has been written but neither sent nor read by the arm */ - EVTWR = 1, - /* WRF has been written and sent, but not yet read by the arm */ - EVTST = 2, - /* WRF has been written, sent and read by the arm */ - EVTRD = 0 -}; /* Wake-up reason Field State */ - - - -/** - * enum ap_pwrst_t - current power states defined in PRCMU firmware - * @NO_PWRST: Current power state init - * @AP_BOOT: Current power state is apBoot - * @AP_EXECUTE: Current power state is apExecute - * @AP_DEEP_SLEEP: Current power state is apDeepSleep - * @AP_SLEEP: Current power state is apSleep - * @AP_IDLE: Current power state is apIdle - * @AP_RESET: Current power state is apReset - */ -enum ap_pwrst_t { - NO_PWRST = 0x00, - AP_BOOT = 0x01, - AP_EXECUTE = 0x02, - AP_DEEP_SLEEP = 0x03, - AP_SLEEP = 0x04, - AP_IDLE = 0x05, - AP_RESET = 0x06 -}; - -/** - * enum ap_pwrst_trans_t - Transition states defined in PRCMU firmware - * @NO_TRANSITION: No power state transition - * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep - * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep - * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute - * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to - * ApDeepSleep - * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle - */ -enum ap_pwrst_trans_t { - NO_TRANSITION = 0x00, - APEXECUTE_TO_APSLEEP = 0x01, - APIDLE_TO_APSLEEP = 0x02, - APBOOT_TO_APEXECUTE = 0x03, - APEXECUTE_TO_APDEEPSLEEP = 0x04, - APEXECUTE_TO_APIDLE = 0x05 -}; - -/** - * enum ddr_pwrst_t - DDR power states definition - * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged - * @DDR_PWR_STATE_ON: - * @DDR_PWR_STATE_OFFLOWLAT: - * @DDR_PWR_STATE_OFFHIGHLAT: - */ -enum ddr_pwrst_t { - DDR_PWR_STATE_UNCHANGED = 0x00, - DDR_PWR_STATE_ON = 0x01, - DDR_PWR_STATE_OFFLOWLAT = 0x02, - DDR_PWR_STATE_OFFHIGHLAT = 0x03 -}; - -/** - * enum arm_opp_t - ARM OPP states definition - * @ARM_NO_CHANGE: The ARM operating point is unchanged - * @ARM_100_OPP: The new ARM operating point is arm100opp - * @ARM_50_OPP: The new ARM operating point is arm100opp - * @ARM_EXTCLK: The new ARM operating point is armExtClk - */ -enum arm_opp_t { - ARM_NO_CHANGE = 0x00, - ARM_100_OPP = 0x02, - ARM_50_OPP = 0x03, - ARM_EXTCLK = 0x07 -}; - -/** - * enum ape_opp_t - APE OPP states definition - * @APE_NO_CHANGE: The APE operating point is unchanged - * @APE_100_OPP: The new APE operating point is ape100opp - */ -enum ape_opp_t { - APE_NO_CHANGE = 0x00, - APE_100_OPP = 0x02, - APE_50_OPP = 0x03 -}; - -/** - * enum hw_accst_t - State definition for hardware accelerator - * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged - * @HW_OFF: The hardware accelerator must be switched off - * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its - * internal RAM in retention - * @HW_ON: The hwa hadware accelerator hwa must be switched on - */ -enum hw_accst_t { - HW_NO_CHANGE = 0x00, - HW_OFF = 0x01, - HW_OFF_RAMRET = 0x02, - HW_ON = 0x03 -}; - -/** - * enum mbox_2_arm_stat_t - Status messages definition for mbox_arm - * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been - * completed - * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been - * completed - * @SLEEPOK: The apExecute to apSleep state transition has been completed - * @IDLEOK: The apExecute to apIdle state transition has been completed - * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed - * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going - * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going - * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on - * going - * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on - * going - * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has - * been completed - * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going - * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going - * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been - * completed - * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going - * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going - * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been - * completed - * @INIT_STATUS: Status init - */ -enum ap_pwrsttr_status_t { - BOOT_TO_EXECUTEOK = 0xFF, - DEEPSLEEPOK = 0xFE, - SLEEPOK = 0xFD, - IDLEOK = 0xFC, - SOFTRESETOK = 0xFB, - SOFTRESETGO = 0xFA, - BOOT_TO_EXECUTE = 0xF9, - EXECUTE_TO_DEEPSLEEP = 0xF8, - DEEPSLEEP_TO_EXECUTE = 0xF7, - DEEPSLEEP_TO_EXECUTEOK = 0xF6, - EXECUTE_TO_SLEEP = 0xF5, - SLEEP_TO_EXECUTE = 0xF4, - SLEEP_TO_EXECUTEOK = 0xF3, - EXECUTE_TO_IDLE = 0xF2, - IDLE_TO_EXECUTE = 0xF1, - IDLE_TO_EXECUTEOK = 0xF0, - RDYTODS_RETURNTOEXE = 0xEF, - NORDYTODS_RETURNTOEXE = 0xEE, - EXETOSLEEP_RETURNTOEXE = 0xED, - EXETOIDLE_RETURNTOEXE = 0xEC, - INIT_STATUS = 0xEB, - - /*error messages */ - INITERROR = 0x00, - PLLARMLOCKP_ER = 0x01, - PLLDDRLOCKP_ER = 0x02, - PLLSOCLOCKP_ER = 0x03, - PLLSOCK1LOCKP_ER = 0x04, - ARMWFI_ER = 0x05, - SYSCLKOK_ER = 0x06, - I2C_NACK_DATA_ER = 0x07, - BOOT_ER = 0x08, - I2C_STATUS_ALWAYS_1 = 0x0A, - I2C_NACK_REG_ADDR_ER = 0x0B, - I2C_NACK_DATA0123_ER = 0x1B, - I2C_NACK_ADDR_ER = 0x1F, - CURAPPWRSTISNOT_BOOT = 0x20, - CURAPPWRSTISNOT_EXECUTE = 0x21, - CURAPPWRSTISNOT_SLEEPMODE = 0x22, - CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23, - FIFO4500WUISNOT_WUPEVENT = 0x24, - PLL32KLOCKP_ER = 0x29, - DDRDEEPSLEEPOK_ER = 0x2A, - ROMCODEREADY_ER = 0x50, - WUPBEFOREDS = 0x51, - DDRCONFIG_ER = 0x52, - WUPBEFORESLEEP = 0x53, - WUPBEFOREIDLE = 0x54 -}; /* earlier called as mbox_2_arm_stat_t */ - - -/** - * enum dvfs_stat_t - DVFS status messages definition - * @DVFS_GO: A state transition DVFS is on going - * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP - * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP - * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK - * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for - * NOCHGCLK - * @DVFS_INITSTATUS: Value init - */ -enum dvfs_stat_t { - DVFS_GO = 0xFF, - DVFS_ARM100OPPOK = 0xFE, - DVFS_ARM50OPPOK = 0xFD, - DVFS_ARMEXTCLKOK = 0xFC, - DVFS_NOCHGTCLKOK = 0xFB, - DVFS_INITSTATUS = 0x00 -}; - -/** - * enum mbox_2_arm_hwacc_pwr_stat_t - Hardware Accelarator status message - * @HWACC_PWRST_GO: A state transition on hardware accelerator is on going - * @HWACC_PWRST_OK: The state transition on hardware accelerator has been - * completed - * @HWACC_PWRSTATUS_INIT: Value init - */ -enum mbox_2_arm_hwacc_pwr_stat_t { - HWACC_PWRST_GO = 0xFF, - HWACC_PWRST_OK = 0xFE, - HWACC_PWRSTATUS_INIT = 0x00 -}; - -/** - * enum sva_mmdsp_stat_t - SVA MMDSP status messages - * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened - * @SVA_MMDSP_INIT: Status init - */ -enum sva_mmdsp_stat_t { - SVA_MMDSP_GO = 0xFF, - SVA_MMDSP_INIT = 0x00 -}; - -/** - * enum sia_mmdsp_stat_t - SIA MMDSP status messages - * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened - * @SIA_MMDSP_INIT: Status init - */ -enum sia_mmdsp_stat_t { - SIA_MMDSP_GO = 0xFF, - SIA_MMDSP_INIT = 0x00 -}; - -/** - * enum intr_wakeup_t - Configure STW4500 FIFO interrupt as wake-up - * @NTR_NOT_AS_WAKEUP: The 4500 fifo interrupt is not configured as a - * wake-up event - * @INTR_AS_WAKEUP: The 4500 fifo interrupt is configured as a wake-up event - */ -enum intr_wakeup_t { - INTR_NOT_AS_WAKEUP = 0x0, - INTR_AS_WAKEUP = 0x1 -}; - -/** - * enum mbox_to_arm_err_t - Error messages definition - * @INIT_ERR: Init value - * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time - * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time - * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time - * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time - * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time - * @SYSCLKOK_ERR: The SYSCLK is not available in the given time - * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time - * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context - * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered - * through I2C has not been correctly executed in the given time - * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered - * through I2C has not been correctly executed in the given time - * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through - * I2C has not been correctly executed in the given time - * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered - * through I2C has not been correctly executed in the given time - * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through - * I2C has not been correctly executed in the given time - * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered - * through I2C has not been correctly executed in the given time - * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through - * I2C has not been correctly executed in the given time - * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C - * has not been correctly executed in the given time - * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has - * not been correctly executed in the given time - * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has - * not been correctly executed in the given time - * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through - * I2C has not been correctly executed in the given time - * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through - * I2C has not been correctly executed in the given time - * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered - * through I2C has not been correctly executed in the given time - * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition - * ApBoot to ApExecute but the power current state is not Apboot - * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state - * transition from ApExecute to others power state but the - * power current state is not ApExecute - * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted - * but the power current state is not ApDeepSleep/ApSleep/ApIdle - * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted - * but the power current state is not correct - * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not - * been correctly executed in the given time - * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not - * been correctly executed in the given time - * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not - * been correctly executed in the given time - * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not - * been correctly executed in the given time - * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not - * been correctly executed in the given time - */ -enum mbox_to_arm_err_t { - INIT_ERR = 0x00, - PLLARMLOCKP_ERR = 0x01, - PLLDDRLOCKP_ERR = 0x02, - PLLSOC0LOCKP_ERR = 0x03, - PLLSOC1LOCKP_ERR = 0x04, - ARMWFI_ERR = 0x05, - SYSCLKOK_ERR = 0x06, - BOOT_ERR = 0x07, - ROMCODESAVECONTEXT = 0x08, - VARMHIGHSPEEDVALTO_ERR = 0x10, - VARMHIGHSPEEDACCESS_ERR = 0x11, - VARMLOWSPEEDVALTO_ERR = 0x12, - VARMLOWSPEEDACCESS_ERR = 0x13, - VARMRETENTIONVALTO_ERR = 0x14, - VARMRETENTIONACCESS_ERR = 0x15, - VAPEHIGHSPEEDVALTO_ERR = 0x16, - VSAFEHPVALTO_ERR = 0x17, - VMODSEL1VALTO_ERR = 0x18, - VMODSEL2VALTO_ERR = 0x19, - VARMOFFACCESS_ERR = 0x1A, - VAPEOFFACCESS_ERR = 0x1B, - VARMRETACCES_ERR = 0x1C, - CURAPPWRSTISNOTBOOT = 0x20, - CURAPPWRSTISNOTEXECUTE = 0x21, - CURAPPWRSTISNOTSLEEPMODE = 0x22, - CURAPPWRSTISNOTCORRECTDBG = 0x23, - ARMREGU1VALTO_ERR = 0x24, - ARMREGU2VALTO_ERR = 0x25, - VAPEREGUVALTO_ERR = 0x26, - VSMPS3REGUVALTO_ERR = 0x27, - VMODREGUVALTO_ERR = 0x28 -}; - -enum hw_acc_t { - SVAMMDSP = 0, - SVAPIPE = 1, - SIAMMDSP = 2, - SIAPIPE = 3, - SGA = 4, - B2R2MCDE = 5, - ESRAM1 = 6, - ESRAM2 = 7, - ESRAM3 = 8, - ESRAM4 = 9 -}; - -enum reqmb0_header_t { - PWRSTTRH = 0, - WKUPCFG_EXEH = 1, - WKUP_EXEH = 2, - RDWKUPACKH = 3, - WKUPCFG_SLEEPH = 4, - WKUP_SLEEPH = 5, -}; - -enum cs_pwrmgt_t { - PWRDNCS0 = 0, - WKUPCS0 = 1, - PWRDNCS1 = 2, - WKUPCS1 = 3 -}; - -enum reqmb2_header_t { - DPS_H = 0, - HW_ACCT_AUTO_PWR_H = 1, -}; - - -/* Defs related to autonomous power management */ - -/** - * enum sia_sva_pwr_policy_t - Power policy - * @NO_CHGT: No change - * @DSPOFF_HWPOFF: - * @DSPOFFRAMRET_HWPOFF: - * @DSPCLKOFF_HWPOFF: - * @DSPCLKOFF_HWPCLKOFF: - * - */ -enum sia_sva_pwr_policy_t { - NO_CHGT = 0x0, - DSPOFF_HWPOFF = 0x1, - DSPOFFRAMRET_HWPOFF = 0x2, - DSPCLKOFF_HWPOFF = 0x3, - DSPCLKOFF_HWPCLKOFF = 0x4, -}; - -/** - * enum auto_enable_t - Auto Power enable - * @AUTO_OFF: - * @AUTO_ON: - * - */ -enum auto_enable_t { - AUTO_OFF = 0x0, - AUTO_ON = 0x1, -}; - - -/** - * enum reqmb4_header_t -Header type for mail box 4 - * @MEMSTH: The ARM can set what are the expected memory states depending on - * the AP power states. - * @PARTIALREFRESHH: ARM has to update MR16 & MR17 of SDRAM register, for - * partial-refresh of SDRAM, via this mailbox - * @AUTOREFRESHH: Enable to change cycle count before enabling automatic - * DDR self-refresh - * @CSPWRDNH: Enables to lock/unlock one of SDRAM memory cut in self-refresh - * In V2,this service will enable to put CS in pwrdn - * @SYSCLKH: Enables to switch SYSCLK ON/OFF on the AP side - * @USBWKUPH: Used to enable USB wakeup event of PRCMU - */ -enum reqmb4_header_t { - MEM_ST_H = 0, - PARTIAL_S_REFRESH_H = 1, - AUTO_REFRESH_H = 2, - CS_PWRDN_H = 3, - SYSCLK_H = 5, - AUTO_PWR_H = 6, - USB_WKUP_H = 7 -}; - -enum ack_mb4_status_t { - ACKMB4_INIT = 0, - SYSCLKON_OK = 1, - DDRON_OK = 2 -}; - -enum I2C_op_t { - I2CWRITE = 0, - I2CREAD = 1 -}; - -enum ack_mb5_status_t { - ACKMB5_INIT = 0x00, - I2C_WR_OK = 0x01, - I2C_RD_OK = 0x02, - SYSCLK_OK = 0x03, - I2C_TIMEOUT = 0x11, - SYSCLK_ER = 0x12, - /*Error Status resent by PRCM_HWI2C_SR*/ - I2CWR_NACK_DATA_ER = 0x07, - I2CWR_NACK_REG_ADDR_ER = 0x0B, - I2CRDWR_NACK_DATA0123_ER = 0x1B, - I2CWR_NACK_ADDR_ER = 0x1F, - I2CRD_NACK_ADDR_INIT_ER = 0x0F, - I2CRD_NACK_REG_ADDR_INIT_ER = 0x13, - I2CRD_NACK_ADDR_ER = 0x17 -}; - -enum ack_mb7_status_t { - MOD_SW_RESET_REQ = 0x03, - CA_SLEEP_REQ = 0x02, - HOST_PORT_ACK = 0x01, - ACKMB7_INIT = 0x00 -}; - -#endif /* __MACH_PRCMU_FW_DEFS_V1_H */ diff --git a/cpu/arm_cortexa9/stw8500/prcmu.c b/cpu/arm_cortexa9/stw8500/prcmu.c deleted file mode 100644 index e411d1a1c..000000000 --- a/cpu/arm_cortexa9/stw8500/prcmu.c +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation. - * - * Adapted from the Linux version: - * Author: Kumar Sanghvi - */ - -/* - * NOTE: This currently does not support the I2C workaround access method. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include "prcmu-fw-defs_v1.h" - -#define DEBUG 0 -#define dbg_printk(format, arg...) \ - if (DEBUG) \ - printf("prcmu: " format, ##arg) \ - -#define PRCMU_BASE U8500_PRCMU_BASE - -#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0fc) -#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100) - -#define PRCM_XP70_CUR_PWR_STATE (tcdm_base + 0xFFC) - -#define PRCM_REQ_MB5 (tcdm_base + 0xE44) -#define PRCM_ACK_MB5 (tcdm_base + 0xDF4) - -/* Mailbox 5 Requests */ -#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) -#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) -#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) -#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) - -/* Mailbox 5 ACKs */ -#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) -#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) -#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) - -#define PRCMU_I2C_WRITE(slave) \ - (((slave) << 1) | I2CWRITE | (cpu_is_u8500v2() ? (1 << 6) : 0)) - -#define PRCMU_I2C_READ(slave) \ - (((slave) << 1) | I2CREAD | (cpu_is_u8500v2() ? (1 << 6) : 0)) - -enum mailbox_t { - REQ_MB0 = 0, /* Uses XP70_IT_EVENT_10 */ - REQ_MB1 = 1, /* Uses XP70_IT_EVENT_11 */ - REQ_MB2 = 2, /* Uses XP70_IT_EVENT_12 */ - REQ_MB5 = 5, /* Uses XP70_IT_EVENT_17 */ -}; - -static void *tcdm_base; - -static int prcmu_is_ready(void) -{ - int ready; - - if (!tcdm_base) { - if (cpu_is_u8500v1()) - tcdm_base = (void *) U8500_PRCMU_TCDM_BASE_V1; - else if (cpu_is_u8500v2()) - tcdm_base = (void *) U8500_PRCMU_TCDM_BASE; - else { - printf("PRCMU: Unsupported chip version\n"); - return 0; - } - } - - ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; - if (!ready) - printf("PRCMU firmware not ready\n"); - - return ready; -} - -static int _wait_for_req_complete(enum mailbox_t num) -{ - int timeout = 1000; - - /* checking any already on-going transaction */ - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) - ; - - timeout = 1000; - - /* Set an interrupt to XP70 */ - writel(1 << num, PRCM_MBOX_CPU_SET); - - while ((readl(PRCM_MBOX_CPU_VAL) & (1 << num)) && timeout--) - ; - - if (!timeout) { - printf("PRCMU operation timed out\n"); - return -1; - } - - return 0; -} - -/** - * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db8500 register to be accessed - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_read(u8 reg, u16 slave) -{ - uint8_t i2c_status; - uint8_t i2c_val; - - if (!prcmu_is_ready()) - return -1; - - dbg_printk("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", - reg, slave); - - /* prepare the data for mailbox 5 */ - writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(0, PRCM_REQ_MB5_I2CVAL); - - _wait_for_req_complete(REQ_MB5); - - /* retrieve values */ - dbg_printk("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - dbg_printk("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - dbg_printk("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - dbg_printk("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - i2c_val = readb(PRCM_ACK_MB5_VAL); - - if (i2c_status == I2C_RD_OK) - return i2c_val; - else { - - printf("prcmu_i2c_read:read return status= %d\n", - i2c_status); - return -1; - } - -} - -/** - * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db800 register to be written to - * @reg_data: - the data to write - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) -{ - uint8_t i2c_status; - - if (!prcmu_is_ready()) - return -1; - - dbg_printk("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", - reg, slave); - - /* prepare the data for mailbox 5 */ - writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(reg_data, PRCM_REQ_MB5_I2CVAL); - - dbg_printk("\ncpu_is_u8500v11\n"); - _wait_for_req_complete(REQ_MB5); - - /* retrieve values */ - dbg_printk("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - dbg_printk("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - dbg_printk("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - dbg_printk("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - dbg_printk("\ni2c_status = %x\n", i2c_status); - if (i2c_status == I2C_WR_OK) - return 0; - else { - printf("ape-i2c: i2c_status : 0x%x\n", i2c_status); - return -1; - } -} diff --git a/cpu/arm_cortexa9/stw8500/timer.c b/cpu/arm_cortexa9/stw8500/timer.c deleted file mode 100644 index bc27755b1..000000000 --- a/cpu/arm_cortexa9/stw8500/timer.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -/* - * The MTU device hosts four different counters, with 4 set of - * registers. These are register names. - */ - -#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ -#define MTU_RIS 0x04 /* Raw interrupt status */ -#define MTU_MIS 0x08 /* Masked interrupt status */ -#define MTU_ICR 0x0C /* Interrupt clear register */ - -/* per-timer registers take 0..3 as argument */ -#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ -#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ -#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ -#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ - -/* bits for the control register */ -#define MTU_CRn_ENA 0x80 -#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CRn_PRESCALE_MASK 0x0c -#define MTU_CRn_PRESCALE_1 0x00 -#define MTU_CRn_PRESCALE_16 0x04 -#define MTU_CRn_PRESCALE_256 0x08 -#define MTU_CRn_32BITS 0x02 -#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ - -/* Other registers are usual amba/primecell registers, currently not used */ -#define MTU_ITCR 0xff0 -#define MTU_ITOP 0xff4 - -#define MTU_PERIPH_ID0 0xfe0 -#define MTU_PERIPH_ID1 0xfe4 -#define MTU_PERIPH_ID2 0xfe8 -#define MTU_PERIPH_ID3 0xfeC - -#define MTU_PCELL0 0xff0 -#define MTU_PCELL1 0xff4 -#define MTU_PCELL2 0xff8 -#define MTU_PCELL3 0xffC - -/* - * The MTU is clocked at 133 MHz by default. (V1 and later) - */ -#define TIMER_CLOCK (133 * 1000 * 1000 / 16) -#define COUNT_TO_USEC(x) ((x) * 16 / 133) -#define USEC_TO_COUNT(x) ((x) * 133 / 16) -#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) -#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) - -/* - * MTU timer to use (from 0 to 3). - * Linux ux500 timer0 on MTU0 and timer0 on MTU1 - */ -#define MTU_TIMER 2 - -static unsigned int timerbase; - -/* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(timerbase + MTU_VAL(MTU_TIMER))) - -/* Configure a free-running, auto-wrap counter with /16 prescaler */ -int timer_init(void) -{ - timerbase = u8500_is_earlydrop() ? U8500_MTU0_BASE_ED - : U8500_MTU0_BASE_V1; - - writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_16 | MTU_CRn_32BITS, - timerbase + MTU_CR(MTU_TIMER)); - reset_timer(); - return 0; -} - -/* Restart counting from 0 */ -void reset_timer(void) -{ - writel(0, timerbase + MTU_LR(MTU_TIMER)); /* Immediate effect */ -} - -/* Return how many HZ passed since "base" */ -ulong get_timer(ulong base) -{ - return TICKS_TO_HZ(READ_TIMER()) - base; -} - -u64 get_timer_us(void) -{ - return COUNT_TO_USEC(READ_TIMER()); -} - -/* Delay x useconds */ -void udelay(unsigned long usec) -{ - ulong ini, end; - - ini = READ_TIMER(); - end = ini + USEC_TO_COUNT(usec); - while ((signed)(end - READ_TIMER()) > 0) - ; - boottime_idle_add(usec); -} diff --git a/include/asm-arm/arch-db8500/ab8500.h b/include/asm-arm/arch-db8500/ab8500.h new file mode 100644 index 000000000..5db047979 --- /dev/null +++ b/include/asm-arm/arch-db8500/ab8500.h @@ -0,0 +1,510 @@ +/* + * Copyright (C) ST-Ericsson 2009. + * + * Author: Srinidhi Kasagar + * Licensed under GPLv2. + */ +#ifndef _AB8500_H +#define _AB8500_H + +/* + * AB8500 bank addresses + */ +#define AB8500_SYS_CTRL1_BLOCK 0x1 +#define AB8500_SYS_CTRL2_BLOCK 0x2 +#define AB8500_REGU_CTRL1 0x3 +#define AB8500_REGU_CTRL2 0x4 +#define AB8500_USB 0x5 +#define AB8500_TVOUT 0x6 +#define AB8500_DBI 0x7 +#define AB8500_ECI_AV_ACC 0x8 +#define AB8500_RESERVED 0x9 +#define STw4550_GPADC 0xA +#define AB8500_GPADC 0xA +#define AB8500_CHARGER 0xB +#define AB8500_GAS_GAUGE 0xC +#define AB8500_AUDIO 0xD +#define AB8500_INTERRUPT 0xE +#define AB8500_RTC 0xF +#define AB8500_MISC 0x10 +#define AB8500_DEBUG 0x12 +#define AB8500_PROD_TEST 0x13 +#define AB8500_OTP_EMUL 0x15 + +/* + * System control 1 register offsets. + * Bank = 0x01 + */ +#define AB8500_TURNON_STAT_REG 0x0100 +#define AB8500_RESET_STAT_REG 0x0101 +#define AB8500_PONKEY1_PRESS_STAT_REG 0x0102 + +#define AB8500_FSM_STAT1_REG 0x0140 +#define AB8500_FSM_STAT2_REG 0x0141 +#define AB8500_SYSCLK_REQ_STAT_REG 0x0142 +#define AB8500_USB_STAT1_REG 0x0143 +#define AB8500_USB_STAT2_REG 0x0144 +#define AB8500_STATUS_SPARE1_REG 0x0145 +#define AB8500_STATUS_SPARE2_REG 0x0146 + +#define AB8500_CTRL1_REG 0x0180 +#define AB8500_CTRL2_REG 0x0181 + +/* + * System control 2 register offsets. + * bank = 0x02 + */ +#define AB8500_CTRL3_REG 0x0200 +#define AB8500_CTRL3_RST_DENC_MASK 0x4 +#define AB8500_CTRL3_RST_DENC_SHIFT 2 +#define AB8500_CTRL3_RST_AUD_MASK 0x2 +#define AB8500_CTRL3_RST_AUD_SHIFT 1 +#define AB8500_MAIN_WDOG_CTRL_REG 0x0201 +#define AB8500_MAIN_WDOG_TIMER_REG 0x0202 +#define AB8500_LOW_BAT_REG 0x0203 +#define AB8500_BATT_OK_REG 0x0204 +#define AB8500_SYSCLK_TIMER_REG 0x0205 +#define AB8500_SMPSCLK_CTRL_REG 0x0206 +#define AB8500_SMPSCLK_SEL1_REG 0x0207 +#define AB8500_SMPSCLK_SEL2_REG 0x0208 +#define AB8500_SMPSCLK_SEL3_REG 0x0209 +#define AB8500_SYSULPCLK_CONF_REG 0x020A +#define AB8500_SYSULPCLK_CTRL1_REG 0x020B +#define AB8500_SYSCLK_CTRL_REG 0x020C +#define AB8500_SYSCLK_REQ1_VALID_REG 0x020D +#define AB8500_SYSCLK_REQ_VALID_REG 0x020E +#define AB8500_SYSCTRL_SPARE_REG 0x020F +#define AB8500_PAD_CONF_REG 0x0210 + +/* + * Regu control1 register offsets (SPI) + * Bank = 0x03 + */ +#define AB8500_REGU_SERIAL_CTRL1_REG 0x0300 +#define AB8500_REGU_SERIAL_CTRL2_REG 0x0301 +#define AB8500_REGU_SERIAL_CTRL3_REG 0x0302 +#define AB8500_REGU_REQ_CTRL1_REG 0x0303 +#define AB8500_REGU_REQ_CTRL2_REG 0x0304 +#define AB8500_REGU_REQ_CTRL3_REG 0x0305 +#define AB8500_REGU_REQ_CTRL4_REG 0x0306 +#define AB8500_REGU_SYSCLK_REQ1HP_VALID1_REG 0x0307 +#define AB8500_REGU_SYSCLK_REQ1HP_VALID2_REG 0x0308 +#define AB8500_REGU_HWHPREQ1_VALID1_REG 0x0309 +#define AB8500_REGU_HWHPREQ1_VALID2_REG 0x030A +#define AB8500_REGU_HWHPREQ2_VALID1_REG 0x030B +#define AB8500_REGU_HWHPREQ2_VALID2_REG 0x030C +#define AB8500_REGU_SWHPREQ_VALID1_REG 0x030D +#define AB8500_REGU_SWHPREQ_VALID2_REG 0x030E + +#define AB8500_REGU_SYSCLK_REQ1_VALID_REG 0x030F /* only for ED*/ +#define AB8500_REGU_SYSCLK_REQ2_VALID_REG 0x0310 /*only for ED*/ + +#define AB8500_REGU_MISC1_REG 0x0380 +#define AB8500_REGU_OTGSUPPLY_CTRL_REG 0x0381 +#define AB8500_REGU_VUSB_CTRL_REG 0x0382 /* see reg manaul*/ +#define AB8500_REGU_VAUDIO_SUPPLY_REG 0x0383 +#define AB8500_REGU_CTRL1_SPARE_REG 0x0384 + + /* + * Regu control2 register offsets (SPI/APE I2C) + * Bank = 0x04 + */ +#define AB8500_REGU_ARM_REGU1_REG 0x0400 +#define AB8500_REGU_ARM_REGU2_REG 0x0401 +#define AB8500_REGU_VAPE_REGU_REG 0x0402 +#define AB8500_REGU_VSMPS1_REGU_REG 0x0403 +#define AB8500_REGU_VSMPS2_REGU_REG 0x0404 +#define AB8500_REGU_VSMPS3_REGU_REG 0x0405 +#define AB8500_REGU_VPLLVANA_REGU_REG 0x0406 +#define AB8500_REGU_VREF_DDR_REG 0x0407 +#define AB8500_REGU_EXTSUPPLY_REGU_REG 0x0408 +#define AB8500_REGU_VAUX12_REGU_REG 0x0409 +#define AB8500_REGU_VAUX12_REGU_VAUX1_MASK 0x3 +#define AB8500_REGU_VAUX12_REGU_VAUX1_SHIFT 0 +#define AB8500_REGU_VAUX12_REGU_VAUX1_FORCE_HP 0x1 +#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A +#define AB8500_REGU_VARM_SEL1_REG 0x040B +#define AB8500_REGU_VARM_SEL2_REG 0x040C +#define AB8500_REGU_VARM_SEL3_REG 0x040D +#define AB8500_REGU_VAPE_SEL1_REG 0x040E +#define AB8500_REGU_VAPE_SEL2_REG 0x040F +#define AB8500_REGU_VAPE_SEL3_REG 0x0410 +#define AB8500_REGU_VBB_SEL2_REG 0x0412 +#define AB8500_REGU_VSMPS1_SEL1_REG 0x0413 +#define AB8500_REGU_VSMPS1_SEL2_REG 0x0414 +#define AB8500_REGU_VSMPS1_SEL3_REG 0x0415 +#define AB8500_REGU_VSMPS2_SEL1_REG 0x0417 +#define AB8500_REGU_VSMPS2_SEL2_REG 0x0418 +#define AB8500_REGU_VSMPS2_SEL3_REG 0x0419 +#define AB8500_REGU_VSMPS3_SEL1_REG 0x041B +#define AB8500_REGU_VSMPS3_SEL2_REG 0x041C +#define AB8500_REGU_VSMPS3_SEL3_REG 0x041D +#define AB8500_REGU_VAUX1_SEL_REG 0x041F +#define AB8500_REGU_VAUX1_SEL_MASK 0xf +#define AB8500_REGU_VAUX1_SEL_SHIFT 0 +#define AB8500_REGU_VAUX1_SEL_1_5V 0x4 +#define AB8500_REGU_VAUX1_SEL_2_5V 0x8 +#define AB8500_REGU_VAUX2_SEL_REG 0x0420 +#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 +#define AB8500_REGU_CTRL2_SPARE_REG 0x0422 + +/* + * Regu control2 Vmod register offsets + */ +#define AB8500_REGU_VMOD_REGU_REG 0x0440 +#define AB8500_REGU_VMOD_SEL1_REG 0x0441 +#define AB8500_REGU_VMOD_SEL2_REG 0x0442 +#define AB8500_REGU_CTRL_DISCH_REG 0x0443 +#define AB8500_REGU_CTRL_DISCH2_REG 0x0444 + +/* + * Sim control register offsets + * Bank:0x4 + */ +#define AB8500_SIM_REG1_SGR1L_REG 0x0480 +#define AB8500_SIM_REG1_SGR1U_REG 0x0481 +#define AB8500_SIM_REG2_SCR1L_REG 0x0482 +#define AB8500_SIM_REG2_SCR1U_REG 0x0483 +#define AB8500_SIM_REG3_SCTRLRL_REG 0x0484 +#define AB8500_SIM_REG3_SCTRLRU_REG 0x0485 +#define AB8500_SIM_ISOUICCINT_SRC_REG 0x0486 +#define AB8500_SIM_ISOUICCINT_LATCH_REG 0x0487 +#define AB8500_SIM_ISOUICCINT_MASK_REG 0x0488 +#define AB8500_SIM_REG4_USBUICC_REG 0x0489 +#define AB8500_SIM_SDELAYSEL_REG 0x048A +#define AB8500_SIM_USBUICC_CTRL 0x048B /* bit 3 only for ED */ + +/* + * USB/ULPI register offsets + * Bank : 0x5 + */ +#define AB8500_USB_LINE_STAT_REG 0x0580 +#define AB8500_USB_LINE_CTRL1_REG 0x0581 +#define AB8500_USB_LINE_CTRL2_REG 0x0582 +#define AB8500_USB_LINE_CTRL3_REG 0x0583 +#define AB8500_USB_LINE_CTRL4_REG 0x0584 +#define AB8500_USB_LINE_CTRL5_REG 0x0585 +#define AB8500_USB_OTG_CTRL_REG 0x0587 +#define AB8500_USB_OTG_STAT_REG 0x0588 +#define AB8500_USB_OTG_STAT_REG 0x0588 +#define AB8500_USB_CTRL_SPARE_REG 0x0589 +#define AB8500_USB_PHY_CTRL_REG 0x058A /*only in Cut1.0*/ + +/* + * TVOUT / CTRL register offsets + * Bank : 0x06 + */ +#define AB8500_DENC_CONF0_REG 0x0600 +#define AB8500_DENC_CONF1_REG 0x0601 +#define AB8500_DENC_CONF2_REG 0x0602 +#define AB8500_DENC_CONF3_REG 0x0603 +#define AB8500_DENC_CONF4_REG 0x0604 +#define AB8500_DENC_CONF5_REG 0x0605 +#define AB8500_DENC_CONF6_REG 0x0606 +#define AB8500_DENC_CONF6_SOFT_RST_MASK 0x80 +#define AB8500_DENC_CONF6_SOFT_RST_SHIFT 7 +#define AB8500_DENC_CONF6_SOFT_RST_OFF 0x0 +#define AB8500_DENC_CONF6_SOFT_RST_ON 0x1 +#define AB8500_DENC_CONF7_REG 0x0607 +#define AB8500_DENC_CONF8_REG 0x0608 +#define AB8500_TVOUT_CTRL_REG 0x0680 +#define AB8500_TVOUT_CTRL2_REG 0x0681 +/* + * DBI register offsets + * Bank : 0x07 + */ +#define AB8500_DBI_REG1_REG 0x0700 +#define AB8500_DBI_REG2_REG 0x0701 +/* + * ECI regsiter offsets + * Bank : 0x08 + */ +#define AB8500_ECI_CTRL_REG 0x0800 +#define AB8500_ECI_HOOKLEVEL_REG 0x0801 +#define AB8500_ECI_DATAOUT_REG 0x0802 +#define AB8500_ECI_DATAIN_REG 0x0803 +/* + * AV Connector register offsets + * Bank : 0x08 + */ +#define AB8500_AV_CONN_REG 0x0840 +/* + * Accessory detection register offsets + * Bank : 0x08 + */ +#define AB8500_ACC_DET_DB1_REG 0x0880 +#define AB8500_ACC_DET_DB2_REG 0x0881 +/* + * GPADC register offsets + * Bank : 0x0A + */ +#define AB8500_GPADC_CTRL1_REG 0x0A00 +#define AB8500_GPADC_CTRL2_REG 0x0A01 +#define AB8500_GPADC_CTRL3_REG 0x0A02 +#define AB8500_GPADC_AUTO_TIMER_REG 0x0A03 +#define AB8500_GPADC_STAT_REG 0x0A04 +#define AB8500_GPADC_MANDATAL_REG 0x0A05 +#define AB8500_GPADC_MANDATAH_REG 0x0A06 +#define AB8500_GPADC_AUTODATAL_REG 0x0A07 +#define AB8500_GPADC_AUTODATAH_REG 0x0A08 +#define AB8500_GPADC_MUX_CTRL_REG 0x0A09 +/* + * Charger / status register offfsets + * Bank : 0x0B + */ +#define AB8500_CH_STATUS1_REG 0x0B00 +#define AB8500_CH_STATUS2_REG 0x0B01 +#define AB8500_CH_USBCH_STAT1_REG 0x0B02 +#define AB8500_CH_USBCH_STAT2_REG 0x0B03 +#define AB8500_CH_FSM_STAT_REG 0x0B04 +#define AB8500_CH_STAT_REG 0x0B05 +/* + * Charger / control register offfsets + * Bank : 0x0B + */ +#define AB8500_CH_VOLT_LVL_REG 0x0B40 +#define AB8500_CH_VOLT_LVL_MAX_REG 0x0B41 /*Only in Cut1.0*/ +#define AB8500_CH_OPT_CRNTLVL_REG 0x0B42 /*Only in Cut1.0*/ +#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x0B43 /*Only in Cut1.0*/ +#define AB8500_CH_WD_TIMER_REG 0x0B44 /*Only in Cut1.0*/ +#define AB8500_CH_WD_CTRL_REG 0x0B45 /*Only in Cut1.0*/ +#define AB8500_CHARG_WD_CTRL 0x0B51 +#define AB8500_LED_INDICATOR_PWM_CTRL 0x0B53 +#define AB8500_LED_INDICATOR_PWM_DUTY 0x0B54 +#define AB8500_BATT_OVV 0x0B55 +/* + * Charger / main control register offfsets + * Bank : 0x0B + */ +#define AB8500_MCH_CTRL1 0x0B80 +#define AB8500_MCH_CTRL2 0x0B81 +#define AB8500_MCH_IPT_CURLVL_REG 0x0B82 +#define AB8500_CH_WD_REG 0x0B83 +/* + * Charger / USB control register offsets + * Bank : 0x0B + */ +#define AB8500_USBCH_CTRL1_REG 0x0BC0 +#define AB8500_USBCH_CTRL2_REG 0x0BC1 +#define AB8500_USBCH_IPT_CRNTLVL_REG 0x0BC2 +/* + * Gas Gauge register offsets + * Bank : 0x0C + */ +#define AB8500_GASG_CC_CTRL_REG 0x0C00 +#define AB8500_GASG_CC_ACCU1_REG 0x0C01 +#define AB8500_GASG_CC_ACCU2_REG 0x0C02 +#define AB8500_GASG_CC_ACCU3_REG 0x0C03 +#define AB8500_GASG_CC_ACCU4_REG 0x0C04 +#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x0C05 +#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x0C06 +#define AB8500_GASG_CC_SMPL_CNVL_REG 0x0C07 +#define AB8500_GASG_CC_SMPL_CNVH_REG 0x0C08 +#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x0C09 +#define AB8500_GASG_CC_OFFSET_REG 0x0C0A +#define AB8500_GASG_CC_NCOV_ACCU 0x0C10 +#define AB8500_GASG_CC_NCOV_ACCU_CTRL 0x0C11 +#define AB8500_GASG_CC_NCOV_ACCU_LOW 0x0C12 +#define AB8500_GASG_CC_NCOV_ACCU_MED 0x0C13 +#define AB8500_GASG_CC_NCOV_ACCU_HIGH 0x0C14 + + + +/* + * Audio + * Bank : 0x0D + * Should be part of Audio codec driver + */ +#define AB8500_AUDIO_POWER_UP 0x0D00 +#define AB8500_AUDIO_ANA_CONF4 0x0D08 +#define AB8500_AUDIO_DA_PATH_CONF 0x0D09 +#define AB8500_AUDIO_PWM_GEN_CONF1 0x0D0F +#define AB8500_AUDIO_PWM_GEN_CONF2 0x0D10 +#define AB8500_AUDIO_PWM_GEN_CONF3 0x0D11 +#define AB8500_AUDIO_PWM_GEN_CONF4 0x0D12 +#define AB8500_AUDIO_PWM_GEN_CONF5 0x0D13 + +/* + * Interrupt register offsets + * Bank : 0x0E + */ +#define AB8500_IT_SOURCE1_REG 0x0E00 +#define AB8500_IT_SOURCE2_REG 0x0E01 +#define AB8500_IT_SOURCE3_REG 0x0E02 +#define AB8500_IT_SOURCE4_REG 0x0E03 +#define AB8500_IT_SOURCE5_REG 0x0E04 +#define AB8500_IT_SOURCE6_REG 0x0E05 + +/* available only in 1.0 */ +#define AB8500_IT_SOURCE7_REG 0x0E06 +#define AB8500_IT_SOURCE8_REG 0x0E07 +#define AB8500_IT_SOURCE19_REG 0x0E12 + +#define AB8500_IT_SOURCE20_REG 0x0E13 +#define AB8500_IT_SOURCE21_REG 0x0E14 +#define AB8500_IT_SOURCE22_REG 0x0E15 +#define AB8500_IT_SOURCE23_REG 0x0E16 +#define AB8500_IT_SOURCE24_REG 0x0E17 + +/* + * latch registers + */ +#define AB8500_IT_LATCH1_REG 0x0E20 +#define AB8500_IT_LATCH2_REG 0x0E21 +#define AB8500_IT_LATCH3_REG 0x0E22 +#define AB8500_IT_LATCH4_REG 0x0E23 +#define AB8500_IT_LATCH5_REG 0x0E24 +#define AB8500_IT_LATCH6_REG 0x0E25 + +/* available only in 1.0 */ +#define AB8500_IT_LATCH7_REG 0x0E26 +#define AB8500_IT_LATCH8_REG 0x0E27 +#define AB8500_IT_LATCH9_REG 0x0E28 +#define AB8500_IT_LATCH10_REG 0x0E29 +#define AB8500_IT_LATCH19_REG 0x0E32 + +#define AB8500_IT_LATCH20_REG 0x0E33 +#define AB8500_IT_LATCH21_REG 0x0E34 +#define AB8500_IT_LATCH22_REG 0x0E35 +#define AB8500_IT_LATCH23_REG 0x0E36 +#define AB8500_IT_LATCH24_REG 0x0E37 + +/* + * mask registers + */ + +#define AB8500_IT_MASK1_REG 0x0E40 +#define AB8500_IT_MASK2_REG 0x0E41 +#define AB8500_IT_MASK3_REG 0x0E42 +#define AB8500_IT_MASK4_REG 0x0E43 +#define AB8500_IT_MASK5_REG 0x0E44 +#define AB8500_IT_MASK6_REG 0x0E45 + + +/* available only in 1.0 */ +#define AB8500_IT_MASK7_REG 0x0E46 +#define AB8500_IT_MASK8_REG 0x0E47 +#define AB8500_IT_MASK9_REG 0x0E48 +#define AB8500_IT_MASK10_REG 0x0E49 +#define AB8500_IT_MASK11_REG 0x0E4A +#define AB8500_IT_MASK12_REG 0x0E4B +#define AB8500_IT_MASK13_REG 0x0E4C +#define AB8500_IT_MASK14_REG 0x0E4D +#define AB8500_IT_MASK15_REG 0x0E4E +#define AB8500_IT_MASK16_REG 0x0E4F +#define AB8500_IT_MASK17_REG 0x0E50 +#define AB8500_IT_MASK18_REG 0x0E51 +#define AB8500_IT_MASK19_REG 0x0E52 + +#define AB8500_IT_MASK20_REG 0x0E53 +#define AB8500_IT_MASK21_REG 0x0E54 +#define AB8500_IT_MASK22_REG 0x0E55 +#define AB8500_IT_MASK23_REG 0x0E56 +#define AB8500_IT_MASK24_REG 0x0E57 + +/* + * RTC bank register offsets + * Bank : 0xF + */ +#define AB8500_RTC_SWITCHOFF_STAT_REG 0x0F00 +#define AB8500_RTC_CC_CONF_REG 0x0F01 +#define AB8500_RTC_READ_REQ_REG 0x0F02 +#define AB8500_RTC_WATCH_TSECMID_REG 0x0F03 +#define AB8500_RTC_WATCH_TSECHI_REG 0x0F04 +#define AB8500_RTC_WATCH_TMIN_LOW_REG 0x0F05 +#define AB8500_RTC_WATCH_TMIN_MID_REG 0x0F06 +#define AB8500_RTC_WATCH_TMIN_HI_REG 0x0F07 +#define AB8500_RTC_ALRM_MIN_LOW_REG 0x0F08 +#define AB8500_RTC_ALRM_MIN_MID_REG 0x0F09 +#define AB8500_RTC_ALRM_MIN_HI_REG 0x0F0A +#define AB8500_RTC_STAT_REG 0x0F0B +#define AB8500_RTC_BKUP_CHG_REG 0x0F0C +#define AB8500_RTC_FORCE_BKUP_REG 0x0F0D +#define AB8500_RTC_CALIB_REG 0x0F0E +#define AB8500_RTC_SWITCH_STAT_REG 0x0F0F + +/* + * Misc block GPIO register offsets - Not for ED + * Bank : 0x10 + */ +/* available only in 1.0 */ +#define AB8500_GPIO_SEL1_REG 0x01000 +#define AB8500_GPIO_SEL2_REG 0x01001 +#define AB8500_GPIO_SEL3_REG 0x01002 +#define AB8500_GPIO_SEL4_REG 0x01003 +#define AB8500_GPIO_SEL5_REG 0x01004 +#define AB8500_GPIO_SEL6_REG 0x01005 +#define AB8500_GPIO_DIR1_REG 0x01010 +#define AB8500_GPIO_DIR2_REG 0x01011 +#define AB8500_GPIO_DIR3_REG 0x01012 +#define AB8500_GPIO_DIR4_REG 0x01013 +#define AB8500_GPIO_DIR5_REG 0x01014 +#define AB8500_GPIO_DIR6_REG 0x01015 + +#define AB8500_GPIO_OUT1_REG 0x01020 +#define AB8500_GPIO_OUT2_REG 0x01021 +#define AB8500_GPIO_OUT3_REG 0x01022 +#define AB8500_GPIO_OUT4_REG 0x01023 +#define AB8500_GPIO_OUT5_REG 0x01024 +#define AB8500_GPIO_OUT6_REG 0x01025 + +#define AB8500_GPIO_PUD1_REG 0x01030 +#define AB8500_GPIO_PUD2_REG 0x01031 +#define AB8500_GPIO_PUD3_REG 0x01032 +#define AB8500_GPIO_PUD4_REG 0x01033 +#define AB8500_GPIO_PUD5_REG 0x01034 +#define AB8500_GPIO_PUD6_REG 0x01035 + +#define AB8500_GPIO_IN1_REG 0x01040 +#define AB8500_GPIO_IN2_REG 0x01041 +#define AB8500_GPIO_IN3_REG 0x01042 +#define AB8500_GPIO_IN4_REG 0x01043 +#define AB8500_GPIO_IN5_REG 0x01044 +#define AB8500_GPIO_IN6_REG 0x01045 +#define AB8500_GPIO_ALT_FUNC 0x01050 + +/* + * PWM Out generators + * Bank: 0x10 + */ +#define AB8500_PWM_OUT_CTRL1_REG 0x1060 +#define AB8500_PWM_OUT_CTRL2_REG 0x1061 +#define AB8500_PWM_OUT_CTRL3_REG 0x1062 +#define AB8500_PWM_OUT_CTRL4_REG 0x1063 +#define AB8500_PWM_OUT_CTRL5_REG 0x1064 +#define AB8500_PWM_OUT_CTRL6_REG 0x1065 +#define AB8500_PWM_OUT_CTRL7_REG 0x1066 + +#define AB8500_I2C_PAD_CTRL_REG 0x1067 +#define AB8500_REV_REG 0x1080 + +/* + * Misc, Debug Test Configuration register + * Bank : 0x11 + */ +#define AB8500_DEBUG_TESTMODE_REG 0x01100 + +/* only in 1.0 */ +#define AB8500_I2C_TRIG1_ADR_REG 0x1101 +#define AB8500_I2C_TRIG1_ID_REG 0x1102 +#define AB8500_I2C_TRIG2_ADR_REG 0x1103 +#define AB8500_I2C_TRIG3_ID_REG 0x1104 +#define AB8500_I2C_NOACCESS_SUP_REG 0x1105 + +/* Offsets in TurnOnstatus register + */ + +#define AB8500_MAX_INT 192 +#define AB8500_MAX_FUTURE_USE 105 + +#define AB8500_MAX_INT_SOURCE 11 +#define AB8500_MAX_INT_LATCH 13 +#define AB8500_MAX_INT_MASK 21 + +#define ab8500_read prcmu_i2c_read +#define ab8500_write prcmu_i2c_write + +extern int prcmu_i2c_read(u8 reg, u16 slave); +extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); + +#endif /* AB8500_H_ */ diff --git a/include/asm-arm/arch-db8500/bits.h b/include/asm-arm/arch-db8500/bits.h new file mode 100644 index 000000000..17e2f09a4 --- /dev/null +++ b/include/asm-arm/arch-db8500/bits.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __bits_h +#define __bits_h 1 + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/include/asm-arm/arch-db8500/clock.h b/include/asm-arm/arch-db8500/clock.h new file mode 100644 index 000000000..b00ab0d21 --- /dev/null +++ b/include/asm-arm/arch-db8500/clock.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK +#define __ASM_ARCH_CLOCK + +struct prcmu { + unsigned int armclkfix_mgt; + unsigned int armclk_mgt; + unsigned int svammdspclk_mgt; + unsigned int siammdspclk_mgt; + unsigned int reserved; + unsigned int sgaclk_mgt; + unsigned int uartclk_mgt; + unsigned int msp02clk_mgt; + unsigned int i2cclk_mgt; + unsigned int sdmmcclk_mgt; + unsigned int slimclk_mgt; + unsigned int per1clk_mgt; + unsigned int per2clk_mgt; + unsigned int per3clk_mgt; + unsigned int per5clk_mgt; + unsigned int per6clk_mgt; + unsigned int per7clk_mgt; + unsigned int lcdclk_mgt; + unsigned int reserved1; + unsigned int bmlclk_mgt; + unsigned int hsitxclk_mgt; + unsigned int hsirxclk_mgt; + unsigned int hdmiclk_mgt; + unsigned int apeatclk_mgt; + unsigned int apetraceclk_mgt; + unsigned int mcdeclk_mgt; + unsigned int ipi2cclk_mgt; + unsigned int dsialtclk_mgt; + unsigned int spare2clk_mgt; + unsigned int dmaclk_mgt; + unsigned int b2r2clk_mgt; + unsigned int tvclk_mgt; + unsigned int unused[82]; + unsigned int tcr; + unsigned int unused1[23]; + unsigned int ape_softrst; +}; + +extern void u8500_clock_enable(int periph, int kern, int cluster); + +static inline void u8500_prcmu_enable(unsigned int *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +#endif /* __ASM_ARCH_CLOCK */ diff --git a/include/asm-arm/arch-db8500/common.h b/include/asm-arm/arch-db8500/common.h new file mode 100644 index 000000000..38079b79c --- /dev/null +++ b/include/asm-arm/arch-db8500/common.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _DB8500_COMMON_H_ +#define _DB8500_COMMON_H_ +#include + +#define PASS (1) +#define FAIL (0) + +#define IO(addr) (*((u32*) (addr))) +#define HIO(addr) (*((u16*) (addr))) +#define BIO(addr) (*((u8*) (addr))) + +/* + * macro to get at IO space + */ +#define IO_ADDRESS(x) (x) + +#define REG_WRITE_BITS(reg,val,mask,sb) (writel(((readl(reg) & ~(mask)) | (((val)<<(sb)) & (mask))), reg)) + +#define nmdk_error(format, arg...) printf(": " format "\n" , ## arg) + +#if !defined(FALSE) && !defined(TRUE) +typedef enum {FALSE, TRUE} t_bool; +#else /* FALSE & TRUE already defined */ +typedef enum {BOOL_FALSE, BOOL_TRUE} t_bool; +#endif /* !defined(FALSE) && !defined(TRUE) */ + +/*----------------------------------------------------------------------------- + * Bit mask definition + *---------------------------------------------------------------------------*/ +#define MASK_NULL8 0x00 +#define MASK_NULL16 0x0000 +#define MASK_NULL32 0x00000000 +#define MASK_ALL8 0xFF +#define MASK_ALL16 0xFFFF +#define MASK_ALL32 0xFFFFFFFF + +#define MASK_BIT0 (1UL<<0) +#define MASK_BIT1 (1UL<<1) +#define MASK_BIT2 (1UL<<2) +#define MASK_BIT3 (1UL<<3) +#define MASK_BIT4 (1UL<<4) +#define MASK_BIT5 (1UL<<5) +#define MASK_BIT6 (1UL<<6) +#define MASK_BIT7 (1UL<<7) +#define MASK_BIT8 (1UL<<8) +#define MASK_BIT9 (1UL<<9) +#define MASK_BIT10 (1UL<<10) +#define MASK_BIT11 (1UL<<11) +#define MASK_BIT12 (1UL<<12) +#define MASK_BIT13 (1UL<<13) +#define MASK_BIT14 (1UL<<14) +#define MASK_BIT15 (1UL<<15) +#define MASK_BIT16 (1UL<<16) +#define MASK_BIT17 (1UL<<17) +#define MASK_BIT18 (1UL<<18) +#define MASK_BIT19 (1UL<<19) +#define MASK_BIT20 (1UL<<20) +#define MASK_BIT21 (1UL<<21) +#define MASK_BIT22 (1UL<<22) +#define MASK_BIT23 (1UL<<23) +#define MASK_BIT24 (1UL<<24) +#define MASK_BIT25 (1UL<<25) +#define MASK_BIT26 (1UL<<26) +#define MASK_BIT27 (1UL<<27) +#define MASK_BIT28 (1UL<<28) +#define MASK_BIT29 (1UL<<29) +#define MASK_BIT30 (1UL<<30) +#define MASK_BIT31 (1UL<<31) + +#define NOMADIK_INTERNAL_ERROR (-8) +#define NOMADIK_NOT_CONFIGURED (-7) +#define NOMADIK_REQUEST_PENDING (-6) +#define NOMADIK_REQUEST_NOT_APPLICABLE (-5) +#define NOMADIK_INVALID_PARAMETER (-4) +#define NOMADIK_UNSUPPORTED_FEATURE (-3) +#define NOMADIK_UNSUPPORTED_HW (-2) +#define NOMADIK_ERROR (-1) +#define NOMADIK_OK ( 0) +#define NOMADIK_INTERNAL_EVENT ( 1) +#define NOMADIK_REMAINING_PENDING_EVENTS ( 2) +#define NOMADIK_REMAINING_FILTER_PENDING_EVENTS ( 3) +#define NOMADIK_NO_MORE_PENDING_EVENT ( 4) +#define NOMADIK_NO_MORE_FILTER_PENDING_EVENT ( 5) +#define NOMADIK_NO_PENDING_EVENT_ERROR ( 7) + + +#define NOMADIK_MAX_ERROR_VALUE (-65) /* HW specific error codes + * should start from this offset + */ +/*----------------------------------------------------------------------------- + * Bit setting or clearing + *---------------------------------------------------------------------------*/ +#define NOMADIK_SET_BITS(reg,mask) ((reg) |= (mask)) +#define NOMADIK_CLEAR_BITS(reg,mask) ((reg) &= ~(mask)) +#define NOMADIK_READ_BITS(reg,mask) ((reg) & (mask)) +#define NOMADIK_WRITE_BITS(reg,val,mask) ((reg) = (((reg) & ~(mask)) | ((val) & (mask)))) +#define NOMADIK_READ_REG(reg) (reg) +#define NOMADIK_WRITE_REG(reg,val) ((reg) = (val)) + +/* + * Definition of the different kind of addresses manipulated into a system with MMU + * (handle physical AND logical addresses) + */ + +typedef u32 t_physical_address; +typedef u32 t_logical_address; + +/*function prototypes*/ +void gpio_init(void); + +int u8500_is_earlydrop(void); +int cpu_is_u8500v11(void); +int cpu_is_u8500v1(void); +int cpu_is_u8500v2(void); + +int board_early_access(block_dev_desc_t *block_dev); +#endif /* _DB8500_COMMON_H_ */ diff --git a/include/asm-arm/arch-db8500/gpio.h b/include/asm-arm/arch-db8500/gpio.h new file mode 100644 index 000000000..fbff7fcb6 --- /dev/null +++ b/include/asm-arm/arch-db8500/gpio.h @@ -0,0 +1,526 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MOP500_GPIO_h +#define _MOP500_GPIO_h + +#include +#include +#include + +#include + +#define GPIO_TOTAL_PINS 268 + +#define GPIO_PINS_PER_BLOCK 32 +#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK +1) +#define GPIO_BLOCK(pin) ( ( ( pin + GPIO_PINS_PER_BLOCK ) >> 5) - 1 ) + + +struct gpio_register { + u32 gpio_dat; /* GPIO data register *//*0x000 */ + u32 gpio_dats; /* GPIO data Set register *//*0x004 */ + u32 gpio_datc; /* GPIO data Clear register *//*0x008 */ + u32 gpio_pdis; /* GPIO Pull disable register *//*0x00C */ + u32 gpio_dir; /* GPIO data direction register *//*0x010 */ + u32 gpio_dirs; /* GPIO data dir Set register *//*0x014 */ + u32 gpio_dirc; /* GPIO data dir Clear register *//*0x018 */ + u32 gpio_slpm; /* GPIO Sleep mode register *//*0x01C */ + u32 gpio_afsa; /* GPIO AltFun A Select reg *//*0x020 */ + u32 gpio_afsb; /* GPIO AltFun B Select reg *//*0x024 */ + u32 gpio_lowemi; /* GPIO low EMI Select reg *//*0x028 */ + u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/ + u32 gpio_rimsc; /* GPIO rising edge intr set/clear *//*0x040 */ + u32 gpio_fimsc; /* GPIO falling edge interrupt set/clear register *//*0x044 */ + u32 gpio_mis; /* GPIO masked interrupt status register *//*0x048 */ + u32 gpio_ic; /* GPIO Interrupt Clear register *//*0x04C */ + u32 gpio_rwimsc; /* GPIO Rising-edge Wakeup IMSC register *//*0x050 */ + u32 gpio_fwimsc; /* GPIO Falling-edge Wakeup IMSC register *//*0x054 */ + u32 gpio_wks; /* GPIO Wakeup Status register *//*0x058 */ +}; + +/* Error values returned by functions */ +typedef enum { + GPIO_OK = 0, /* (0) */ + GPIO_UNSUPPORTED_HW = -2, /* NOMADIK_UNSUPPORTED_HW, (-2) */ + GPIO_UNSUPPORTED_FEATURE = -3, /* NOMADIK_UNSUPPORTED_FEATURE, (-3) */ + GPIO_INVALID_PARAMETER = -4, /* NOMADIK_INVALID_PARAMETER, (-4) */ + GPIO_REQUEST_NOT_APPLICABLE = -5, /* NOMADIK_REQUEST_NOT_APPLICABLE, (-5) */ + GPIO_REQUEST_PENDING = -6, /* NOMADIK_REQUEST_PENDING, (-6) */ + GPIO_NOT_CONFIGURED = -7, /* NOMADIK_NOT_CONFIGURED, (-7) */ + GPIO_INTERNAL_ERROR = -8, /* NOMADIK_INTERNAL_ERROR, (-8) */ + GPIO_INTERNAL_EVENT = 1, /* NOMADIK_INTERNAL_EVENT,*/ + GPIO_REMAINING_EVENT = 2, /* NOMADIK_REMAINING_PENDING_EVENTS,*/ + GPIO_NO_MORE_PENDING_EVENT = 3, /* NOMADIK_NO_MORE_PENDING_EVENT,*/ + GPIO_INVALID_CLIENT = -25, + GPIO_INVALID_PIN = -26, + GPIO_PIN_BUSY = -27, + GPIO_PIN_NOT_ALLOCATED = -28, + GPIO_WRONG_CLIENT = -29, + GPIO_UNSUPPORTED_ALTFUNC = -30, + +} gpio_error; + +/*GPIO DEVICE ID */ +typedef enum { + GPIO_DEVICE_ID_0, + GPIO_DEVICE_ID_1, + GPIO_DEVICE_ID_2, + GPIO_DEVICE_ID_3, + GPIO_DEVICE_ID_INVALID +} gpio_device_id; + +/* + * Pin description To be used in SOFTWARE mode: refers to a pin. + */ +typedef enum { + GPIO_PIN_0, + GPIO_PIN_1, + GPIO_PIN_2, + GPIO_PIN_3, + GPIO_PIN_4, + GPIO_PIN_5, + GPIO_PIN_6, + GPIO_PIN_7, + GPIO_PIN_8, + GPIO_PIN_9, + GPIO_PIN_10, + GPIO_PIN_11, + GPIO_PIN_12, + GPIO_PIN_13, + GPIO_PIN_14, + GPIO_PIN_15, + GPIO_PIN_16, + GPIO_PIN_17, + GPIO_PIN_18, + GPIO_PIN_19, + GPIO_PIN_20, + GPIO_PIN_21, + GPIO_PIN_22, + GPIO_PIN_23, + GPIO_PIN_24, + GPIO_PIN_25, + GPIO_PIN_26, + GPIO_PIN_27, + GPIO_PIN_28, + GPIO_PIN_29, + GPIO_PIN_30, + GPIO_PIN_31, + GPIO_PIN_32, + GPIO_PIN_33, + GPIO_PIN_34, + GPIO_PIN_35, + GPIO_PIN_36, + GPIO_PIN_37, + GPIO_PIN_38, + GPIO_PIN_39, + GPIO_PIN_40, + GPIO_PIN_41, + GPIO_PIN_42, + GPIO_PIN_43, + GPIO_PIN_44, + GPIO_PIN_45, + GPIO_PIN_46, + GPIO_PIN_47, + GPIO_PIN_48, + GPIO_PIN_49, + GPIO_PIN_50, + GPIO_PIN_51, + GPIO_PIN_52, + GPIO_PIN_53, + GPIO_PIN_54, + GPIO_PIN_55, + GPIO_PIN_56, + GPIO_PIN_57, + GPIO_PIN_58, + GPIO_PIN_59, + GPIO_PIN_60, + GPIO_PIN_61, + GPIO_PIN_62, + GPIO_PIN_63, + GPIO_PIN_64, + GPIO_PIN_65, + GPIO_PIN_66, + GPIO_PIN_67, + GPIO_PIN_68, + GPIO_PIN_69, + GPIO_PIN_70, + GPIO_PIN_71, + GPIO_PIN_72, + GPIO_PIN_73, + GPIO_PIN_74, + GPIO_PIN_75, + GPIO_PIN_76, + GPIO_PIN_77, + GPIO_PIN_78, + GPIO_PIN_79, + GPIO_PIN_80, + GPIO_PIN_81, + GPIO_PIN_82, + GPIO_PIN_83, + GPIO_PIN_84, + GPIO_PIN_85, + GPIO_PIN_86, + GPIO_PIN_87, + GPIO_PIN_88, + GPIO_PIN_89, + GPIO_PIN_90, + GPIO_PIN_91, + GPIO_PIN_92, + GPIO_PIN_93, + GPIO_PIN_94, + GPIO_PIN_95, + GPIO_PIN_96, + GPIO_PIN_97, + GPIO_PIN_98, + GPIO_PIN_99, + GPIO_PIN_100, + GPIO_PIN_101, + GPIO_PIN_102, + GPIO_PIN_103, + GPIO_PIN_104, + GPIO_PIN_105, + GPIO_PIN_106, + GPIO_PIN_107, + GPIO_PIN_108, + GPIO_PIN_109, + GPIO_PIN_110, + GPIO_PIN_111, + GPIO_PIN_112, + GPIO_PIN_113, + GPIO_PIN_114, + GPIO_PIN_115, + GPIO_PIN_116, + GPIO_PIN_117, + GPIO_PIN_118, + GPIO_PIN_119, + GPIO_PIN_120, + GPIO_PIN_121, + GPIO_PIN_122, + GPIO_PIN_123, + GPIO_PIN_124, + GPIO_PIN_125, + GPIO_PIN_126, + GPIO_PIN_127, + GPIO_PIN_128, + GPIO_PIN_129, + GPIO_PIN_130, + GPIO_PIN_131, + GPIO_PIN_132, + GPIO_PIN_133, + GPIO_PIN_134, + GPIO_PIN_135, + GPIO_PIN_136, + GPIO_PIN_137, + GPIO_PIN_138, + GPIO_PIN_139, + GPIO_PIN_140, + GPIO_PIN_141, + GPIO_PIN_142, + GPIO_PIN_143, + GPIO_PIN_144, + GPIO_PIN_145, + GPIO_PIN_146, + GPIO_PIN_147, + GPIO_PIN_148, + GPIO_PIN_149, + GPIO_PIN_150, + GPIO_PIN_151, + GPIO_PIN_152, + GPIO_PIN_153, + GPIO_PIN_154, + GPIO_PIN_155, + GPIO_PIN_156, + GPIO_PIN_157, + GPIO_PIN_158, + GPIO_PIN_159, + GPIO_PIN_160, + GPIO_PIN_161, + GPIO_PIN_162, + GPIO_PIN_163, + GPIO_PIN_164, + GPIO_PIN_165, + GPIO_PIN_166, + GPIO_PIN_167, + GPIO_PIN_168, + GPIO_PIN_169, + GPIO_PIN_170, + GPIO_PIN_171, + GPIO_PIN_172, + GPIO_PIN_173, + GPIO_PIN_174, + GPIO_PIN_175, + GPIO_PIN_176, + GPIO_PIN_177, + GPIO_PIN_178, + GPIO_PIN_179, + GPIO_PIN_180, + GPIO_PIN_181, + GPIO_PIN_182, + GPIO_PIN_183, + GPIO_PIN_184, + GPIO_PIN_185, + GPIO_PIN_186, + GPIO_PIN_187, + GPIO_PIN_188, + GPIO_PIN_189, + GPIO_PIN_190, + GPIO_PIN_191, + GPIO_PIN_192, + GPIO_PIN_193, + GPIO_PIN_194, + GPIO_PIN_195, + GPIO_PIN_196, + GPIO_PIN_197, + GPIO_PIN_198, + GPIO_PIN_199, + GPIO_PIN_200, + GPIO_PIN_201, + GPIO_PIN_202, + GPIO_PIN_203, + GPIO_PIN_204, + GPIO_PIN_205, + GPIO_PIN_206, + GPIO_PIN_207, + GPIO_PIN_208, + GPIO_PIN_209, + GPIO_PIN_210, + GPIO_PIN_211, + GPIO_PIN_212, + GPIO_PIN_213, + GPIO_PIN_214, + GPIO_PIN_215, + GPIO_PIN_216, + GPIO_PIN_217, + GPIO_PIN_218, + GPIO_PIN_219, + GPIO_PIN_220, + GPIO_PIN_221, + GPIO_PIN_222, + GPIO_PIN_223, + GPIO_PIN_224, + GPIO_PIN_225, + GPIO_PIN_226, + GPIO_PIN_227, + GPIO_PIN_228, + GPIO_PIN_229, + GPIO_PIN_230, + GPIO_PIN_231, + GPIO_PIN_232, + GPIO_PIN_233, + GPIO_PIN_234, + GPIO_PIN_235, + GPIO_PIN_236, + GPIO_PIN_237, + GPIO_PIN_238, + GPIO_PIN_239, + GPIO_PIN_240, + GPIO_PIN_241, + GPIO_PIN_242, + GPIO_PIN_243, + GPIO_PIN_244, + GPIO_PIN_245, + GPIO_PIN_246, + GPIO_PIN_247, + GPIO_PIN_248, + GPIO_PIN_249, + GPIO_PIN_250, + GPIO_PIN_251, + GPIO_PIN_252, + GPIO_PIN_253, + GPIO_PIN_254, + GPIO_PIN_255, + GPIO_PIN_256, + GPIO_PIN_257, + GPIO_PIN_258, + GPIO_PIN_259, + GPIO_PIN_260, + GPIO_PIN_261, + GPIO_PIN_262, + GPIO_PIN_263, + GPIO_PIN_264, + GPIO_PIN_265, + GPIO_PIN_266, + GPIO_PIN_267 +} gpio_pin; + +/* + * Alternate Function: + * refered in altfun_table to pointout particular altfun to be enabled + * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation + */ +typedef enum { + GPIO_ALT_UART_0_MODEM, + GPIO_ALT_UART_0_NO_MODEM, + GPIO_ALT_UART_1, + GPIO_ALT_UART_2, + GPIO_ALT_I2C_0, + GPIO_ALT_I2C_1, + GPIO_ALT_I2C_2, + GPIO_ALT_I2C_3, + GPIO_ALT_MSP_0, + GPIO_ALT_MSP_1, + GPIO_ALT_MSP_2, + GPIO_ALT_MSP_3, + GPIO_ALT_MSP_4, + GPIO_ALT_MSP_5, + GPIO_ALT_SSP_0, + GPIO_ALT_SSP_1, + GPIO_ALT_MM_CARD0, + GPIO_ALT_SD_CARD0, + GPIO_ALT_DMA_0, + GPIO_ALT_DMA_1, + GPIO_ALT_HSI0, + GPIO_ALT_CCIR656_INPUT, + GPIO_ALT_CCIR656_OUTPUT, + GPIO_ALT_LCD_PANEL, + GPIO_ALT_MDIF, + GPIO_ALT_SDRAM, + GPIO_ALT_HAMAC_AUDIO_DBG, + GPIO_ALT_HAMAC_VIDEO_DBG, + GPIO_ALT_CLOCK_RESET, + GPIO_ALT_TSP, + GPIO_ALT_IRDA, + GPIO_ALT_USB_MINIMUM, + GPIO_ALT_USB_I2C, + GPIO_ALT_OWM, + GPIO_ALT_PWL, + GPIO_ALT_FSMC, + GPIO_ALT_COMP_FLASH, + GPIO_ALT_SRAM_NOR_FLASH, + GPIO_ALT_FSMC_ADDLINE_0_TO_15, + GPIO_ALT_SCROLL_KEY, + GPIO_ALT_MSHC, + GPIO_ALT_HPI, + GPIO_ALT_USB_OTG, + GPIO_ALT_SDIO, + GPIO_ALT_HSMMC, + GPIO_ALT_FSMC_ADD_DATA_0_TO_25, + GPIO_ALT_HSI1, + GPIO_ALT_NOR, + GPIO_ALT_NAND, + GPIO_ALT_KEYPAD, + GPIO_ALT_VPIP, + GPIO_ALT_CAM, + GPIO_ALT_CCP1, + GPIO_ALT_EMMC, + GPIO_ALT_POP_EMMC, + GPIO_ALT_SPI_0, + GPIO_ALT_SPI_1, + GPIO_ALT_SPI_2, + GPIO_ALT_SPI_3, + GPIO_ALT_FUNMAX /* Add new alt func before this */ +} gpio_alt_function; + +/* Defines pin assignment(Software mode or Alternate mode) */ +typedef enum { + GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */ + GPIO_ALTF_A, /* Pin connected to alternate function 1 (HW periph 1) */ + GPIO_ALTF_B, /* Pin connected to alternate function 2 (HW periph 2) */ + GPIO_ALTF_C, /* Pin connected to alternate function 3 (HW periph 3) */ + GPIO_ALTF_FIND, /* Pin connected to alternate function 3 (HW periph 3) */ + GPIO_ALTF_DISABLE /* Pin connected to alternate function 3 (HW periph 3) */ +} gpio_mode; + +/* Defines GPIO pin direction */ +typedef enum { + GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_DIR_INPUT, /* GPIO set as input */ + GPIO_DIR_OUTPUT /* GPIO set as output */ +} gpio_direction; + +/* Interrupt trigger mode */ +typedef enum { + GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored by the function */ + GPIO_TRIG_DISABLE, /* Triggers no IT */ + GPIO_TRIG_RISING_EDGE, /* Triggers an IT on a rising edge */ + GPIO_TRIG_FALLING_EDGE, /* Triggers an IT on a falling edge */ + GPIO_TRIG_BOTH_EDGES, /* Triggers an IT on a rising and a falling edge */ + GPIO_TRIG_HIGH_LEVEL, /* Triggers an IT on a high level */ + GPIO_TRIG_LOW_LEVEL /* Triggers an IT on a low level */ +} gpio_trig; /* Interrupt trigger mode, or disable */ + +/* Configuration parameters for one GPIO pin.*/ +typedef struct { + gpio_mode mode; /* Defines mode (SOFTWARE or Alternate). */ + gpio_direction direction; /* Define pin direction (in SOFTWARE mode only). */ + gpio_trig trig; /* Interrupt trigger (in SOFTWARE mode only) */ + char *dev_name; /* Name of client driver who owns the gpio pin */ +} gpio_config; + +/* GPIO pin data*/ +typedef enum { + GPIO_DATA_LOW, /* GPIO pin status is low. */ + GPIO_DATA_HIGH /* GPIO pin status is high. */ +} gpio_data; + +/* GPIO behaviour in sleep mode */ +typedef enum { + GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull up/down enabled + when in sleep mode. */ + GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by GPIO IP. So mode, + direction and data values for GPIO pin in + sleep mode are determined by configuration + set to GPIO pin before entering to sleep mode. */ +} gpio_sleep_mode; + +/* GPIO ability to wake the system up from sleep mode.*/ +typedef enum { + GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ + GPIO_WAKE_DISABLE, /* GPIO will not wake the system from sleep mode. */ + GPIO_WAKE_LOW_LEVEL, /* GPIO will wake the system up on a LOW level. */ + GPIO_WAKE_HIGH_LEVEL, /* GPIO will wake the system up on a HIGH level. */ + GPIO_WAKE_RISING_EDGE, /* GPIO will wake the system up on a RISING edge. */ + GPIO_WAKE_FALLING_EDGE, /* GPIO will wake the system up on a FALLING edge. */ + GPIO_WAKE_BOTH_EDGES /* GPIO will wake the system up on both RISING and FALLING edge. */ +} gpio_wake; + +/* Configuration parameters for one GPIO pin in sleep mode.*/ +typedef struct { + gpio_sleep_mode sleep_mode; /* GPIO behaviour in sleep mode. */ + gpio_wake wake; /* GPIO ability to wake up the system. */ +} gpio_sleep_config; + +/*------------------------------------------------------------------------ + * Functions declaration + * refer ./Documentation/arm/STM-Nomadik/gpio_user_guide.txt + *----------------------------------------------------------------------*/ + +extern gpio_error gpio_setpinconfig(gpio_pin pin_id, gpio_config * pin_config); +extern gpio_error gpio_resetpinconfig(gpio_pin pin_id, char *dev_name); +extern int gpio_writepin(gpio_pin pin_id, gpio_data value, char *dev_name); +extern int gpio_readpin(gpio_pin pin_id, gpio_data * value); +extern int gpio_altfuncenable(gpio_alt_function altfunc, + char *dev_name); +extern int gpio_altfuncdisable(gpio_alt_function altfunc, + char *dev_name); + +struct gpio_altfun_data { + u16 altfun; + u16 start; + u16 end; + t_bool cont; + u8 type; +}; + +#endif /* __INC_GPIO_H */ diff --git a/include/asm-arm/arch-db8500/hardware.h b/include/asm-arm/arch-db8500/hardware.h new file mode 100644 index 000000000..df55a841d --- /dev/null +++ b/include/asm-arm/arch-db8500/hardware.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* Peripheral clusters */ + +#define U8500_PER3_BASE 0x80000000 +#define U8500_PER2_BASE 0x80110000 +#define U8500_PER1_BASE 0x80120000 +#define U8500_PER4_BASE 0x80150000 + +#define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER7_BASE 0xa03d0000 +#define U8500_PER5_BASE 0xa03e0000 + +/* GPIO */ + +#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) +#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80) + +#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000) +#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80) +#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100) +#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180) + +#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000) +#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80) + +#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000) + +/* Per7 */ +#define U8500_MTU0_BASE_ED (U8500_PER7_BASE + 0xa000) +#define U8500_MTU1_BASE_ED (U8500_PER7_BASE + 0xb000) +#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) + +/* Per6 */ +#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000) +#define U8500_MTU1_BASE_v1 (U8500_PER6_BASE + 0x7000) +#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) + +/* Per5 */ +#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) + +/* Per4 */ +#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) + +/* Per3 */ +#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) +#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) + +/* Per2 */ +#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) +#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) +#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) +#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) + +/* Per1 */ +#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) +#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) +#define U8500_SPI3_BASE (U8500_PER2_BASE + 0x9000) +#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) + +#define U8500_BOOTROM_BASE 0x90000000 +#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4) +#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-db8500/mtu.h b/include/asm-arm/arch-db8500/mtu.h new file mode 100644 index 000000000..a87be9ef4 --- /dev/null +++ b/include/asm-arm/arch-db8500/mtu.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MTU_H +#define __ASM_ARCH_MTU_H + +/* + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. + */ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +#endif /* __ASM_ARCH_MTU_H */ diff --git a/include/asm-arm/arch-stw8500/ab8500.h b/include/asm-arm/arch-stw8500/ab8500.h deleted file mode 100644 index 5db047979..000000000 --- a/include/asm-arm/arch-stw8500/ab8500.h +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright (C) ST-Ericsson 2009. - * - * Author: Srinidhi Kasagar - * Licensed under GPLv2. - */ -#ifndef _AB8500_H -#define _AB8500_H - -/* - * AB8500 bank addresses - */ -#define AB8500_SYS_CTRL1_BLOCK 0x1 -#define AB8500_SYS_CTRL2_BLOCK 0x2 -#define AB8500_REGU_CTRL1 0x3 -#define AB8500_REGU_CTRL2 0x4 -#define AB8500_USB 0x5 -#define AB8500_TVOUT 0x6 -#define AB8500_DBI 0x7 -#define AB8500_ECI_AV_ACC 0x8 -#define AB8500_RESERVED 0x9 -#define STw4550_GPADC 0xA -#define AB8500_GPADC 0xA -#define AB8500_CHARGER 0xB -#define AB8500_GAS_GAUGE 0xC -#define AB8500_AUDIO 0xD -#define AB8500_INTERRUPT 0xE -#define AB8500_RTC 0xF -#define AB8500_MISC 0x10 -#define AB8500_DEBUG 0x12 -#define AB8500_PROD_TEST 0x13 -#define AB8500_OTP_EMUL 0x15 - -/* - * System control 1 register offsets. - * Bank = 0x01 - */ -#define AB8500_TURNON_STAT_REG 0x0100 -#define AB8500_RESET_STAT_REG 0x0101 -#define AB8500_PONKEY1_PRESS_STAT_REG 0x0102 - -#define AB8500_FSM_STAT1_REG 0x0140 -#define AB8500_FSM_STAT2_REG 0x0141 -#define AB8500_SYSCLK_REQ_STAT_REG 0x0142 -#define AB8500_USB_STAT1_REG 0x0143 -#define AB8500_USB_STAT2_REG 0x0144 -#define AB8500_STATUS_SPARE1_REG 0x0145 -#define AB8500_STATUS_SPARE2_REG 0x0146 - -#define AB8500_CTRL1_REG 0x0180 -#define AB8500_CTRL2_REG 0x0181 - -/* - * System control 2 register offsets. - * bank = 0x02 - */ -#define AB8500_CTRL3_REG 0x0200 -#define AB8500_CTRL3_RST_DENC_MASK 0x4 -#define AB8500_CTRL3_RST_DENC_SHIFT 2 -#define AB8500_CTRL3_RST_AUD_MASK 0x2 -#define AB8500_CTRL3_RST_AUD_SHIFT 1 -#define AB8500_MAIN_WDOG_CTRL_REG 0x0201 -#define AB8500_MAIN_WDOG_TIMER_REG 0x0202 -#define AB8500_LOW_BAT_REG 0x0203 -#define AB8500_BATT_OK_REG 0x0204 -#define AB8500_SYSCLK_TIMER_REG 0x0205 -#define AB8500_SMPSCLK_CTRL_REG 0x0206 -#define AB8500_SMPSCLK_SEL1_REG 0x0207 -#define AB8500_SMPSCLK_SEL2_REG 0x0208 -#define AB8500_SMPSCLK_SEL3_REG 0x0209 -#define AB8500_SYSULPCLK_CONF_REG 0x020A -#define AB8500_SYSULPCLK_CTRL1_REG 0x020B -#define AB8500_SYSCLK_CTRL_REG 0x020C -#define AB8500_SYSCLK_REQ1_VALID_REG 0x020D -#define AB8500_SYSCLK_REQ_VALID_REG 0x020E -#define AB8500_SYSCTRL_SPARE_REG 0x020F -#define AB8500_PAD_CONF_REG 0x0210 - -/* - * Regu control1 register offsets (SPI) - * Bank = 0x03 - */ -#define AB8500_REGU_SERIAL_CTRL1_REG 0x0300 -#define AB8500_REGU_SERIAL_CTRL2_REG 0x0301 -#define AB8500_REGU_SERIAL_CTRL3_REG 0x0302 -#define AB8500_REGU_REQ_CTRL1_REG 0x0303 -#define AB8500_REGU_REQ_CTRL2_REG 0x0304 -#define AB8500_REGU_REQ_CTRL3_REG 0x0305 -#define AB8500_REGU_REQ_CTRL4_REG 0x0306 -#define AB8500_REGU_SYSCLK_REQ1HP_VALID1_REG 0x0307 -#define AB8500_REGU_SYSCLK_REQ1HP_VALID2_REG 0x0308 -#define AB8500_REGU_HWHPREQ1_VALID1_REG 0x0309 -#define AB8500_REGU_HWHPREQ1_VALID2_REG 0x030A -#define AB8500_REGU_HWHPREQ2_VALID1_REG 0x030B -#define AB8500_REGU_HWHPREQ2_VALID2_REG 0x030C -#define AB8500_REGU_SWHPREQ_VALID1_REG 0x030D -#define AB8500_REGU_SWHPREQ_VALID2_REG 0x030E - -#define AB8500_REGU_SYSCLK_REQ1_VALID_REG 0x030F /* only for ED*/ -#define AB8500_REGU_SYSCLK_REQ2_VALID_REG 0x0310 /*only for ED*/ - -#define AB8500_REGU_MISC1_REG 0x0380 -#define AB8500_REGU_OTGSUPPLY_CTRL_REG 0x0381 -#define AB8500_REGU_VUSB_CTRL_REG 0x0382 /* see reg manaul*/ -#define AB8500_REGU_VAUDIO_SUPPLY_REG 0x0383 -#define AB8500_REGU_CTRL1_SPARE_REG 0x0384 - - /* - * Regu control2 register offsets (SPI/APE I2C) - * Bank = 0x04 - */ -#define AB8500_REGU_ARM_REGU1_REG 0x0400 -#define AB8500_REGU_ARM_REGU2_REG 0x0401 -#define AB8500_REGU_VAPE_REGU_REG 0x0402 -#define AB8500_REGU_VSMPS1_REGU_REG 0x0403 -#define AB8500_REGU_VSMPS2_REGU_REG 0x0404 -#define AB8500_REGU_VSMPS3_REGU_REG 0x0405 -#define AB8500_REGU_VPLLVANA_REGU_REG 0x0406 -#define AB8500_REGU_VREF_DDR_REG 0x0407 -#define AB8500_REGU_EXTSUPPLY_REGU_REG 0x0408 -#define AB8500_REGU_VAUX12_REGU_REG 0x0409 -#define AB8500_REGU_VAUX12_REGU_VAUX1_MASK 0x3 -#define AB8500_REGU_VAUX12_REGU_VAUX1_SHIFT 0 -#define AB8500_REGU_VAUX12_REGU_VAUX1_FORCE_HP 0x1 -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VARM_SEL1_REG 0x040B -#define AB8500_REGU_VARM_SEL2_REG 0x040C -#define AB8500_REGU_VARM_SEL3_REG 0x040D -#define AB8500_REGU_VAPE_SEL1_REG 0x040E -#define AB8500_REGU_VAPE_SEL2_REG 0x040F -#define AB8500_REGU_VAPE_SEL3_REG 0x0410 -#define AB8500_REGU_VBB_SEL2_REG 0x0412 -#define AB8500_REGU_VSMPS1_SEL1_REG 0x0413 -#define AB8500_REGU_VSMPS1_SEL2_REG 0x0414 -#define AB8500_REGU_VSMPS1_SEL3_REG 0x0415 -#define AB8500_REGU_VSMPS2_SEL1_REG 0x0417 -#define AB8500_REGU_VSMPS2_SEL2_REG 0x0418 -#define AB8500_REGU_VSMPS2_SEL3_REG 0x0419 -#define AB8500_REGU_VSMPS3_SEL1_REG 0x041B -#define AB8500_REGU_VSMPS3_SEL2_REG 0x041C -#define AB8500_REGU_VSMPS3_SEL3_REG 0x041D -#define AB8500_REGU_VAUX1_SEL_REG 0x041F -#define AB8500_REGU_VAUX1_SEL_MASK 0xf -#define AB8500_REGU_VAUX1_SEL_SHIFT 0 -#define AB8500_REGU_VAUX1_SEL_1_5V 0x4 -#define AB8500_REGU_VAUX1_SEL_2_5V 0x8 -#define AB8500_REGU_VAUX2_SEL_REG 0x0420 -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 -#define AB8500_REGU_CTRL2_SPARE_REG 0x0422 - -/* - * Regu control2 Vmod register offsets - */ -#define AB8500_REGU_VMOD_REGU_REG 0x0440 -#define AB8500_REGU_VMOD_SEL1_REG 0x0441 -#define AB8500_REGU_VMOD_SEL2_REG 0x0442 -#define AB8500_REGU_CTRL_DISCH_REG 0x0443 -#define AB8500_REGU_CTRL_DISCH2_REG 0x0444 - -/* - * Sim control register offsets - * Bank:0x4 - */ -#define AB8500_SIM_REG1_SGR1L_REG 0x0480 -#define AB8500_SIM_REG1_SGR1U_REG 0x0481 -#define AB8500_SIM_REG2_SCR1L_REG 0x0482 -#define AB8500_SIM_REG2_SCR1U_REG 0x0483 -#define AB8500_SIM_REG3_SCTRLRL_REG 0x0484 -#define AB8500_SIM_REG3_SCTRLRU_REG 0x0485 -#define AB8500_SIM_ISOUICCINT_SRC_REG 0x0486 -#define AB8500_SIM_ISOUICCINT_LATCH_REG 0x0487 -#define AB8500_SIM_ISOUICCINT_MASK_REG 0x0488 -#define AB8500_SIM_REG4_USBUICC_REG 0x0489 -#define AB8500_SIM_SDELAYSEL_REG 0x048A -#define AB8500_SIM_USBUICC_CTRL 0x048B /* bit 3 only for ED */ - -/* - * USB/ULPI register offsets - * Bank : 0x5 - */ -#define AB8500_USB_LINE_STAT_REG 0x0580 -#define AB8500_USB_LINE_CTRL1_REG 0x0581 -#define AB8500_USB_LINE_CTRL2_REG 0x0582 -#define AB8500_USB_LINE_CTRL3_REG 0x0583 -#define AB8500_USB_LINE_CTRL4_REG 0x0584 -#define AB8500_USB_LINE_CTRL5_REG 0x0585 -#define AB8500_USB_OTG_CTRL_REG 0x0587 -#define AB8500_USB_OTG_STAT_REG 0x0588 -#define AB8500_USB_OTG_STAT_REG 0x0588 -#define AB8500_USB_CTRL_SPARE_REG 0x0589 -#define AB8500_USB_PHY_CTRL_REG 0x058A /*only in Cut1.0*/ - -/* - * TVOUT / CTRL register offsets - * Bank : 0x06 - */ -#define AB8500_DENC_CONF0_REG 0x0600 -#define AB8500_DENC_CONF1_REG 0x0601 -#define AB8500_DENC_CONF2_REG 0x0602 -#define AB8500_DENC_CONF3_REG 0x0603 -#define AB8500_DENC_CONF4_REG 0x0604 -#define AB8500_DENC_CONF5_REG 0x0605 -#define AB8500_DENC_CONF6_REG 0x0606 -#define AB8500_DENC_CONF6_SOFT_RST_MASK 0x80 -#define AB8500_DENC_CONF6_SOFT_RST_SHIFT 7 -#define AB8500_DENC_CONF6_SOFT_RST_OFF 0x0 -#define AB8500_DENC_CONF6_SOFT_RST_ON 0x1 -#define AB8500_DENC_CONF7_REG 0x0607 -#define AB8500_DENC_CONF8_REG 0x0608 -#define AB8500_TVOUT_CTRL_REG 0x0680 -#define AB8500_TVOUT_CTRL2_REG 0x0681 -/* - * DBI register offsets - * Bank : 0x07 - */ -#define AB8500_DBI_REG1_REG 0x0700 -#define AB8500_DBI_REG2_REG 0x0701 -/* - * ECI regsiter offsets - * Bank : 0x08 - */ -#define AB8500_ECI_CTRL_REG 0x0800 -#define AB8500_ECI_HOOKLEVEL_REG 0x0801 -#define AB8500_ECI_DATAOUT_REG 0x0802 -#define AB8500_ECI_DATAIN_REG 0x0803 -/* - * AV Connector register offsets - * Bank : 0x08 - */ -#define AB8500_AV_CONN_REG 0x0840 -/* - * Accessory detection register offsets - * Bank : 0x08 - */ -#define AB8500_ACC_DET_DB1_REG 0x0880 -#define AB8500_ACC_DET_DB2_REG 0x0881 -/* - * GPADC register offsets - * Bank : 0x0A - */ -#define AB8500_GPADC_CTRL1_REG 0x0A00 -#define AB8500_GPADC_CTRL2_REG 0x0A01 -#define AB8500_GPADC_CTRL3_REG 0x0A02 -#define AB8500_GPADC_AUTO_TIMER_REG 0x0A03 -#define AB8500_GPADC_STAT_REG 0x0A04 -#define AB8500_GPADC_MANDATAL_REG 0x0A05 -#define AB8500_GPADC_MANDATAH_REG 0x0A06 -#define AB8500_GPADC_AUTODATAL_REG 0x0A07 -#define AB8500_GPADC_AUTODATAH_REG 0x0A08 -#define AB8500_GPADC_MUX_CTRL_REG 0x0A09 -/* - * Charger / status register offfsets - * Bank : 0x0B - */ -#define AB8500_CH_STATUS1_REG 0x0B00 -#define AB8500_CH_STATUS2_REG 0x0B01 -#define AB8500_CH_USBCH_STAT1_REG 0x0B02 -#define AB8500_CH_USBCH_STAT2_REG 0x0B03 -#define AB8500_CH_FSM_STAT_REG 0x0B04 -#define AB8500_CH_STAT_REG 0x0B05 -/* - * Charger / control register offfsets - * Bank : 0x0B - */ -#define AB8500_CH_VOLT_LVL_REG 0x0B40 -#define AB8500_CH_VOLT_LVL_MAX_REG 0x0B41 /*Only in Cut1.0*/ -#define AB8500_CH_OPT_CRNTLVL_REG 0x0B42 /*Only in Cut1.0*/ -#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x0B43 /*Only in Cut1.0*/ -#define AB8500_CH_WD_TIMER_REG 0x0B44 /*Only in Cut1.0*/ -#define AB8500_CH_WD_CTRL_REG 0x0B45 /*Only in Cut1.0*/ -#define AB8500_CHARG_WD_CTRL 0x0B51 -#define AB8500_LED_INDICATOR_PWM_CTRL 0x0B53 -#define AB8500_LED_INDICATOR_PWM_DUTY 0x0B54 -#define AB8500_BATT_OVV 0x0B55 -/* - * Charger / main control register offfsets - * Bank : 0x0B - */ -#define AB8500_MCH_CTRL1 0x0B80 -#define AB8500_MCH_CTRL2 0x0B81 -#define AB8500_MCH_IPT_CURLVL_REG 0x0B82 -#define AB8500_CH_WD_REG 0x0B83 -/* - * Charger / USB control register offsets - * Bank : 0x0B - */ -#define AB8500_USBCH_CTRL1_REG 0x0BC0 -#define AB8500_USBCH_CTRL2_REG 0x0BC1 -#define AB8500_USBCH_IPT_CRNTLVL_REG 0x0BC2 -/* - * Gas Gauge register offsets - * Bank : 0x0C - */ -#define AB8500_GASG_CC_CTRL_REG 0x0C00 -#define AB8500_GASG_CC_ACCU1_REG 0x0C01 -#define AB8500_GASG_CC_ACCU2_REG 0x0C02 -#define AB8500_GASG_CC_ACCU3_REG 0x0C03 -#define AB8500_GASG_CC_ACCU4_REG 0x0C04 -#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x0C05 -#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x0C06 -#define AB8500_GASG_CC_SMPL_CNVL_REG 0x0C07 -#define AB8500_GASG_CC_SMPL_CNVH_REG 0x0C08 -#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x0C09 -#define AB8500_GASG_CC_OFFSET_REG 0x0C0A -#define AB8500_GASG_CC_NCOV_ACCU 0x0C10 -#define AB8500_GASG_CC_NCOV_ACCU_CTRL 0x0C11 -#define AB8500_GASG_CC_NCOV_ACCU_LOW 0x0C12 -#define AB8500_GASG_CC_NCOV_ACCU_MED 0x0C13 -#define AB8500_GASG_CC_NCOV_ACCU_HIGH 0x0C14 - - - -/* - * Audio - * Bank : 0x0D - * Should be part of Audio codec driver - */ -#define AB8500_AUDIO_POWER_UP 0x0D00 -#define AB8500_AUDIO_ANA_CONF4 0x0D08 -#define AB8500_AUDIO_DA_PATH_CONF 0x0D09 -#define AB8500_AUDIO_PWM_GEN_CONF1 0x0D0F -#define AB8500_AUDIO_PWM_GEN_CONF2 0x0D10 -#define AB8500_AUDIO_PWM_GEN_CONF3 0x0D11 -#define AB8500_AUDIO_PWM_GEN_CONF4 0x0D12 -#define AB8500_AUDIO_PWM_GEN_CONF5 0x0D13 - -/* - * Interrupt register offsets - * Bank : 0x0E - */ -#define AB8500_IT_SOURCE1_REG 0x0E00 -#define AB8500_IT_SOURCE2_REG 0x0E01 -#define AB8500_IT_SOURCE3_REG 0x0E02 -#define AB8500_IT_SOURCE4_REG 0x0E03 -#define AB8500_IT_SOURCE5_REG 0x0E04 -#define AB8500_IT_SOURCE6_REG 0x0E05 - -/* available only in 1.0 */ -#define AB8500_IT_SOURCE7_REG 0x0E06 -#define AB8500_IT_SOURCE8_REG 0x0E07 -#define AB8500_IT_SOURCE19_REG 0x0E12 - -#define AB8500_IT_SOURCE20_REG 0x0E13 -#define AB8500_IT_SOURCE21_REG 0x0E14 -#define AB8500_IT_SOURCE22_REG 0x0E15 -#define AB8500_IT_SOURCE23_REG 0x0E16 -#define AB8500_IT_SOURCE24_REG 0x0E17 - -/* - * latch registers - */ -#define AB8500_IT_LATCH1_REG 0x0E20 -#define AB8500_IT_LATCH2_REG 0x0E21 -#define AB8500_IT_LATCH3_REG 0x0E22 -#define AB8500_IT_LATCH4_REG 0x0E23 -#define AB8500_IT_LATCH5_REG 0x0E24 -#define AB8500_IT_LATCH6_REG 0x0E25 - -/* available only in 1.0 */ -#define AB8500_IT_LATCH7_REG 0x0E26 -#define AB8500_IT_LATCH8_REG 0x0E27 -#define AB8500_IT_LATCH9_REG 0x0E28 -#define AB8500_IT_LATCH10_REG 0x0E29 -#define AB8500_IT_LATCH19_REG 0x0E32 - -#define AB8500_IT_LATCH20_REG 0x0E33 -#define AB8500_IT_LATCH21_REG 0x0E34 -#define AB8500_IT_LATCH22_REG 0x0E35 -#define AB8500_IT_LATCH23_REG 0x0E36 -#define AB8500_IT_LATCH24_REG 0x0E37 - -/* - * mask registers - */ - -#define AB8500_IT_MASK1_REG 0x0E40 -#define AB8500_IT_MASK2_REG 0x0E41 -#define AB8500_IT_MASK3_REG 0x0E42 -#define AB8500_IT_MASK4_REG 0x0E43 -#define AB8500_IT_MASK5_REG 0x0E44 -#define AB8500_IT_MASK6_REG 0x0E45 - - -/* available only in 1.0 */ -#define AB8500_IT_MASK7_REG 0x0E46 -#define AB8500_IT_MASK8_REG 0x0E47 -#define AB8500_IT_MASK9_REG 0x0E48 -#define AB8500_IT_MASK10_REG 0x0E49 -#define AB8500_IT_MASK11_REG 0x0E4A -#define AB8500_IT_MASK12_REG 0x0E4B -#define AB8500_IT_MASK13_REG 0x0E4C -#define AB8500_IT_MASK14_REG 0x0E4D -#define AB8500_IT_MASK15_REG 0x0E4E -#define AB8500_IT_MASK16_REG 0x0E4F -#define AB8500_IT_MASK17_REG 0x0E50 -#define AB8500_IT_MASK18_REG 0x0E51 -#define AB8500_IT_MASK19_REG 0x0E52 - -#define AB8500_IT_MASK20_REG 0x0E53 -#define AB8500_IT_MASK21_REG 0x0E54 -#define AB8500_IT_MASK22_REG 0x0E55 -#define AB8500_IT_MASK23_REG 0x0E56 -#define AB8500_IT_MASK24_REG 0x0E57 - -/* - * RTC bank register offsets - * Bank : 0xF - */ -#define AB8500_RTC_SWITCHOFF_STAT_REG 0x0F00 -#define AB8500_RTC_CC_CONF_REG 0x0F01 -#define AB8500_RTC_READ_REQ_REG 0x0F02 -#define AB8500_RTC_WATCH_TSECMID_REG 0x0F03 -#define AB8500_RTC_WATCH_TSECHI_REG 0x0F04 -#define AB8500_RTC_WATCH_TMIN_LOW_REG 0x0F05 -#define AB8500_RTC_WATCH_TMIN_MID_REG 0x0F06 -#define AB8500_RTC_WATCH_TMIN_HI_REG 0x0F07 -#define AB8500_RTC_ALRM_MIN_LOW_REG 0x0F08 -#define AB8500_RTC_ALRM_MIN_MID_REG 0x0F09 -#define AB8500_RTC_ALRM_MIN_HI_REG 0x0F0A -#define AB8500_RTC_STAT_REG 0x0F0B -#define AB8500_RTC_BKUP_CHG_REG 0x0F0C -#define AB8500_RTC_FORCE_BKUP_REG 0x0F0D -#define AB8500_RTC_CALIB_REG 0x0F0E -#define AB8500_RTC_SWITCH_STAT_REG 0x0F0F - -/* - * Misc block GPIO register offsets - Not for ED - * Bank : 0x10 - */ -/* available only in 1.0 */ -#define AB8500_GPIO_SEL1_REG 0x01000 -#define AB8500_GPIO_SEL2_REG 0x01001 -#define AB8500_GPIO_SEL3_REG 0x01002 -#define AB8500_GPIO_SEL4_REG 0x01003 -#define AB8500_GPIO_SEL5_REG 0x01004 -#define AB8500_GPIO_SEL6_REG 0x01005 -#define AB8500_GPIO_DIR1_REG 0x01010 -#define AB8500_GPIO_DIR2_REG 0x01011 -#define AB8500_GPIO_DIR3_REG 0x01012 -#define AB8500_GPIO_DIR4_REG 0x01013 -#define AB8500_GPIO_DIR5_REG 0x01014 -#define AB8500_GPIO_DIR6_REG 0x01015 - -#define AB8500_GPIO_OUT1_REG 0x01020 -#define AB8500_GPIO_OUT2_REG 0x01021 -#define AB8500_GPIO_OUT3_REG 0x01022 -#define AB8500_GPIO_OUT4_REG 0x01023 -#define AB8500_GPIO_OUT5_REG 0x01024 -#define AB8500_GPIO_OUT6_REG 0x01025 - -#define AB8500_GPIO_PUD1_REG 0x01030 -#define AB8500_GPIO_PUD2_REG 0x01031 -#define AB8500_GPIO_PUD3_REG 0x01032 -#define AB8500_GPIO_PUD4_REG 0x01033 -#define AB8500_GPIO_PUD5_REG 0x01034 -#define AB8500_GPIO_PUD6_REG 0x01035 - -#define AB8500_GPIO_IN1_REG 0x01040 -#define AB8500_GPIO_IN2_REG 0x01041 -#define AB8500_GPIO_IN3_REG 0x01042 -#define AB8500_GPIO_IN4_REG 0x01043 -#define AB8500_GPIO_IN5_REG 0x01044 -#define AB8500_GPIO_IN6_REG 0x01045 -#define AB8500_GPIO_ALT_FUNC 0x01050 - -/* - * PWM Out generators - * Bank: 0x10 - */ -#define AB8500_PWM_OUT_CTRL1_REG 0x1060 -#define AB8500_PWM_OUT_CTRL2_REG 0x1061 -#define AB8500_PWM_OUT_CTRL3_REG 0x1062 -#define AB8500_PWM_OUT_CTRL4_REG 0x1063 -#define AB8500_PWM_OUT_CTRL5_REG 0x1064 -#define AB8500_PWM_OUT_CTRL6_REG 0x1065 -#define AB8500_PWM_OUT_CTRL7_REG 0x1066 - -#define AB8500_I2C_PAD_CTRL_REG 0x1067 -#define AB8500_REV_REG 0x1080 - -/* - * Misc, Debug Test Configuration register - * Bank : 0x11 - */ -#define AB8500_DEBUG_TESTMODE_REG 0x01100 - -/* only in 1.0 */ -#define AB8500_I2C_TRIG1_ADR_REG 0x1101 -#define AB8500_I2C_TRIG1_ID_REG 0x1102 -#define AB8500_I2C_TRIG2_ADR_REG 0x1103 -#define AB8500_I2C_TRIG3_ID_REG 0x1104 -#define AB8500_I2C_NOACCESS_SUP_REG 0x1105 - -/* Offsets in TurnOnstatus register - */ - -#define AB8500_MAX_INT 192 -#define AB8500_MAX_FUTURE_USE 105 - -#define AB8500_MAX_INT_SOURCE 11 -#define AB8500_MAX_INT_LATCH 13 -#define AB8500_MAX_INT_MASK 21 - -#define ab8500_read prcmu_i2c_read -#define ab8500_write prcmu_i2c_write - -extern int prcmu_i2c_read(u8 reg, u16 slave); -extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); - -#endif /* AB8500_H_ */ diff --git a/include/asm-arm/arch-stw8500/bits.h b/include/asm-arm/arch-stw8500/bits.h deleted file mode 100755 index 17e2f09a4..000000000 --- a/include/asm-arm/arch-stw8500/bits.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __bits_h -#define __bits_h 1 - -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -#endif diff --git a/include/asm-arm/arch-stw8500/clock.h b/include/asm-arm/arch-stw8500/clock.h deleted file mode 100644 index b00ab0d21..000000000 --- a/include/asm-arm/arch-stw8500/clock.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_CLOCK -#define __ASM_ARCH_CLOCK - -struct prcmu { - unsigned int armclkfix_mgt; - unsigned int armclk_mgt; - unsigned int svammdspclk_mgt; - unsigned int siammdspclk_mgt; - unsigned int reserved; - unsigned int sgaclk_mgt; - unsigned int uartclk_mgt; - unsigned int msp02clk_mgt; - unsigned int i2cclk_mgt; - unsigned int sdmmcclk_mgt; - unsigned int slimclk_mgt; - unsigned int per1clk_mgt; - unsigned int per2clk_mgt; - unsigned int per3clk_mgt; - unsigned int per5clk_mgt; - unsigned int per6clk_mgt; - unsigned int per7clk_mgt; - unsigned int lcdclk_mgt; - unsigned int reserved1; - unsigned int bmlclk_mgt; - unsigned int hsitxclk_mgt; - unsigned int hsirxclk_mgt; - unsigned int hdmiclk_mgt; - unsigned int apeatclk_mgt; - unsigned int apetraceclk_mgt; - unsigned int mcdeclk_mgt; - unsigned int ipi2cclk_mgt; - unsigned int dsialtclk_mgt; - unsigned int spare2clk_mgt; - unsigned int dmaclk_mgt; - unsigned int b2r2clk_mgt; - unsigned int tvclk_mgt; - unsigned int unused[82]; - unsigned int tcr; - unsigned int unused1[23]; - unsigned int ape_softrst; -}; - -extern void u8500_clock_enable(int periph, int kern, int cluster); - -static inline void u8500_prcmu_enable(unsigned int *reg) -{ - writel(readl(reg) | (1 << 8), reg); -} - -#endif /* __ASM_ARCH_CLOCK */ diff --git a/include/asm-arm/arch-stw8500/common.h b/include/asm-arm/arch-stw8500/common.h deleted file mode 100644 index 38079b79c..000000000 --- a/include/asm-arm/arch-stw8500/common.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _DB8500_COMMON_H_ -#define _DB8500_COMMON_H_ -#include - -#define PASS (1) -#define FAIL (0) - -#define IO(addr) (*((u32*) (addr))) -#define HIO(addr) (*((u16*) (addr))) -#define BIO(addr) (*((u8*) (addr))) - -/* - * macro to get at IO space - */ -#define IO_ADDRESS(x) (x) - -#define REG_WRITE_BITS(reg,val,mask,sb) (writel(((readl(reg) & ~(mask)) | (((val)<<(sb)) & (mask))), reg)) - -#define nmdk_error(format, arg...) printf(": " format "\n" , ## arg) - -#if !defined(FALSE) && !defined(TRUE) -typedef enum {FALSE, TRUE} t_bool; -#else /* FALSE & TRUE already defined */ -typedef enum {BOOL_FALSE, BOOL_TRUE} t_bool; -#endif /* !defined(FALSE) && !defined(TRUE) */ - -/*----------------------------------------------------------------------------- - * Bit mask definition - *---------------------------------------------------------------------------*/ -#define MASK_NULL8 0x00 -#define MASK_NULL16 0x0000 -#define MASK_NULL32 0x00000000 -#define MASK_ALL8 0xFF -#define MASK_ALL16 0xFFFF -#define MASK_ALL32 0xFFFFFFFF - -#define MASK_BIT0 (1UL<<0) -#define MASK_BIT1 (1UL<<1) -#define MASK_BIT2 (1UL<<2) -#define MASK_BIT3 (1UL<<3) -#define MASK_BIT4 (1UL<<4) -#define MASK_BIT5 (1UL<<5) -#define MASK_BIT6 (1UL<<6) -#define MASK_BIT7 (1UL<<7) -#define MASK_BIT8 (1UL<<8) -#define MASK_BIT9 (1UL<<9) -#define MASK_BIT10 (1UL<<10) -#define MASK_BIT11 (1UL<<11) -#define MASK_BIT12 (1UL<<12) -#define MASK_BIT13 (1UL<<13) -#define MASK_BIT14 (1UL<<14) -#define MASK_BIT15 (1UL<<15) -#define MASK_BIT16 (1UL<<16) -#define MASK_BIT17 (1UL<<17) -#define MASK_BIT18 (1UL<<18) -#define MASK_BIT19 (1UL<<19) -#define MASK_BIT20 (1UL<<20) -#define MASK_BIT21 (1UL<<21) -#define MASK_BIT22 (1UL<<22) -#define MASK_BIT23 (1UL<<23) -#define MASK_BIT24 (1UL<<24) -#define MASK_BIT25 (1UL<<25) -#define MASK_BIT26 (1UL<<26) -#define MASK_BIT27 (1UL<<27) -#define MASK_BIT28 (1UL<<28) -#define MASK_BIT29 (1UL<<29) -#define MASK_BIT30 (1UL<<30) -#define MASK_BIT31 (1UL<<31) - -#define NOMADIK_INTERNAL_ERROR (-8) -#define NOMADIK_NOT_CONFIGURED (-7) -#define NOMADIK_REQUEST_PENDING (-6) -#define NOMADIK_REQUEST_NOT_APPLICABLE (-5) -#define NOMADIK_INVALID_PARAMETER (-4) -#define NOMADIK_UNSUPPORTED_FEATURE (-3) -#define NOMADIK_UNSUPPORTED_HW (-2) -#define NOMADIK_ERROR (-1) -#define NOMADIK_OK ( 0) -#define NOMADIK_INTERNAL_EVENT ( 1) -#define NOMADIK_REMAINING_PENDING_EVENTS ( 2) -#define NOMADIK_REMAINING_FILTER_PENDING_EVENTS ( 3) -#define NOMADIK_NO_MORE_PENDING_EVENT ( 4) -#define NOMADIK_NO_MORE_FILTER_PENDING_EVENT ( 5) -#define NOMADIK_NO_PENDING_EVENT_ERROR ( 7) - - -#define NOMADIK_MAX_ERROR_VALUE (-65) /* HW specific error codes - * should start from this offset - */ -/*----------------------------------------------------------------------------- - * Bit setting or clearing - *---------------------------------------------------------------------------*/ -#define NOMADIK_SET_BITS(reg,mask) ((reg) |= (mask)) -#define NOMADIK_CLEAR_BITS(reg,mask) ((reg) &= ~(mask)) -#define NOMADIK_READ_BITS(reg,mask) ((reg) & (mask)) -#define NOMADIK_WRITE_BITS(reg,val,mask) ((reg) = (((reg) & ~(mask)) | ((val) & (mask)))) -#define NOMADIK_READ_REG(reg) (reg) -#define NOMADIK_WRITE_REG(reg,val) ((reg) = (val)) - -/* - * Definition of the different kind of addresses manipulated into a system with MMU - * (handle physical AND logical addresses) - */ - -typedef u32 t_physical_address; -typedef u32 t_logical_address; - -/*function prototypes*/ -void gpio_init(void); - -int u8500_is_earlydrop(void); -int cpu_is_u8500v11(void); -int cpu_is_u8500v1(void); -int cpu_is_u8500v2(void); - -int board_early_access(block_dev_desc_t *block_dev); -#endif /* _DB8500_COMMON_H_ */ diff --git a/include/asm-arm/arch-stw8500/gpio.h b/include/asm-arm/arch-stw8500/gpio.h deleted file mode 100755 index fbff7fcb6..000000000 --- a/include/asm-arm/arch-stw8500/gpio.h +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _MOP500_GPIO_h -#define _MOP500_GPIO_h - -#include -#include -#include - -#include - -#define GPIO_TOTAL_PINS 268 - -#define GPIO_PINS_PER_BLOCK 32 -#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK +1) -#define GPIO_BLOCK(pin) ( ( ( pin + GPIO_PINS_PER_BLOCK ) >> 5) - 1 ) - - -struct gpio_register { - u32 gpio_dat; /* GPIO data register *//*0x000 */ - u32 gpio_dats; /* GPIO data Set register *//*0x004 */ - u32 gpio_datc; /* GPIO data Clear register *//*0x008 */ - u32 gpio_pdis; /* GPIO Pull disable register *//*0x00C */ - u32 gpio_dir; /* GPIO data direction register *//*0x010 */ - u32 gpio_dirs; /* GPIO data dir Set register *//*0x014 */ - u32 gpio_dirc; /* GPIO data dir Clear register *//*0x018 */ - u32 gpio_slpm; /* GPIO Sleep mode register *//*0x01C */ - u32 gpio_afsa; /* GPIO AltFun A Select reg *//*0x020 */ - u32 gpio_afsb; /* GPIO AltFun B Select reg *//*0x024 */ - u32 gpio_lowemi; /* GPIO low EMI Select reg *//*0x028 */ - u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/ - u32 gpio_rimsc; /* GPIO rising edge intr set/clear *//*0x040 */ - u32 gpio_fimsc; /* GPIO falling edge interrupt set/clear register *//*0x044 */ - u32 gpio_mis; /* GPIO masked interrupt status register *//*0x048 */ - u32 gpio_ic; /* GPIO Interrupt Clear register *//*0x04C */ - u32 gpio_rwimsc; /* GPIO Rising-edge Wakeup IMSC register *//*0x050 */ - u32 gpio_fwimsc; /* GPIO Falling-edge Wakeup IMSC register *//*0x054 */ - u32 gpio_wks; /* GPIO Wakeup Status register *//*0x058 */ -}; - -/* Error values returned by functions */ -typedef enum { - GPIO_OK = 0, /* (0) */ - GPIO_UNSUPPORTED_HW = -2, /* NOMADIK_UNSUPPORTED_HW, (-2) */ - GPIO_UNSUPPORTED_FEATURE = -3, /* NOMADIK_UNSUPPORTED_FEATURE, (-3) */ - GPIO_INVALID_PARAMETER = -4, /* NOMADIK_INVALID_PARAMETER, (-4) */ - GPIO_REQUEST_NOT_APPLICABLE = -5, /* NOMADIK_REQUEST_NOT_APPLICABLE, (-5) */ - GPIO_REQUEST_PENDING = -6, /* NOMADIK_REQUEST_PENDING, (-6) */ - GPIO_NOT_CONFIGURED = -7, /* NOMADIK_NOT_CONFIGURED, (-7) */ - GPIO_INTERNAL_ERROR = -8, /* NOMADIK_INTERNAL_ERROR, (-8) */ - GPIO_INTERNAL_EVENT = 1, /* NOMADIK_INTERNAL_EVENT,*/ - GPIO_REMAINING_EVENT = 2, /* NOMADIK_REMAINING_PENDING_EVENTS,*/ - GPIO_NO_MORE_PENDING_EVENT = 3, /* NOMADIK_NO_MORE_PENDING_EVENT,*/ - GPIO_INVALID_CLIENT = -25, - GPIO_INVALID_PIN = -26, - GPIO_PIN_BUSY = -27, - GPIO_PIN_NOT_ALLOCATED = -28, - GPIO_WRONG_CLIENT = -29, - GPIO_UNSUPPORTED_ALTFUNC = -30, - -} gpio_error; - -/*GPIO DEVICE ID */ -typedef enum { - GPIO_DEVICE_ID_0, - GPIO_DEVICE_ID_1, - GPIO_DEVICE_ID_2, - GPIO_DEVICE_ID_3, - GPIO_DEVICE_ID_INVALID -} gpio_device_id; - -/* - * Pin description To be used in SOFTWARE mode: refers to a pin. - */ -typedef enum { - GPIO_PIN_0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, - GPIO_PIN_8, - GPIO_PIN_9, - GPIO_PIN_10, - GPIO_PIN_11, - GPIO_PIN_12, - GPIO_PIN_13, - GPIO_PIN_14, - GPIO_PIN_15, - GPIO_PIN_16, - GPIO_PIN_17, - GPIO_PIN_18, - GPIO_PIN_19, - GPIO_PIN_20, - GPIO_PIN_21, - GPIO_PIN_22, - GPIO_PIN_23, - GPIO_PIN_24, - GPIO_PIN_25, - GPIO_PIN_26, - GPIO_PIN_27, - GPIO_PIN_28, - GPIO_PIN_29, - GPIO_PIN_30, - GPIO_PIN_31, - GPIO_PIN_32, - GPIO_PIN_33, - GPIO_PIN_34, - GPIO_PIN_35, - GPIO_PIN_36, - GPIO_PIN_37, - GPIO_PIN_38, - GPIO_PIN_39, - GPIO_PIN_40, - GPIO_PIN_41, - GPIO_PIN_42, - GPIO_PIN_43, - GPIO_PIN_44, - GPIO_PIN_45, - GPIO_PIN_46, - GPIO_PIN_47, - GPIO_PIN_48, - GPIO_PIN_49, - GPIO_PIN_50, - GPIO_PIN_51, - GPIO_PIN_52, - GPIO_PIN_53, - GPIO_PIN_54, - GPIO_PIN_55, - GPIO_PIN_56, - GPIO_PIN_57, - GPIO_PIN_58, - GPIO_PIN_59, - GPIO_PIN_60, - GPIO_PIN_61, - GPIO_PIN_62, - GPIO_PIN_63, - GPIO_PIN_64, - GPIO_PIN_65, - GPIO_PIN_66, - GPIO_PIN_67, - GPIO_PIN_68, - GPIO_PIN_69, - GPIO_PIN_70, - GPIO_PIN_71, - GPIO_PIN_72, - GPIO_PIN_73, - GPIO_PIN_74, - GPIO_PIN_75, - GPIO_PIN_76, - GPIO_PIN_77, - GPIO_PIN_78, - GPIO_PIN_79, - GPIO_PIN_80, - GPIO_PIN_81, - GPIO_PIN_82, - GPIO_PIN_83, - GPIO_PIN_84, - GPIO_PIN_85, - GPIO_PIN_86, - GPIO_PIN_87, - GPIO_PIN_88, - GPIO_PIN_89, - GPIO_PIN_90, - GPIO_PIN_91, - GPIO_PIN_92, - GPIO_PIN_93, - GPIO_PIN_94, - GPIO_PIN_95, - GPIO_PIN_96, - GPIO_PIN_97, - GPIO_PIN_98, - GPIO_PIN_99, - GPIO_PIN_100, - GPIO_PIN_101, - GPIO_PIN_102, - GPIO_PIN_103, - GPIO_PIN_104, - GPIO_PIN_105, - GPIO_PIN_106, - GPIO_PIN_107, - GPIO_PIN_108, - GPIO_PIN_109, - GPIO_PIN_110, - GPIO_PIN_111, - GPIO_PIN_112, - GPIO_PIN_113, - GPIO_PIN_114, - GPIO_PIN_115, - GPIO_PIN_116, - GPIO_PIN_117, - GPIO_PIN_118, - GPIO_PIN_119, - GPIO_PIN_120, - GPIO_PIN_121, - GPIO_PIN_122, - GPIO_PIN_123, - GPIO_PIN_124, - GPIO_PIN_125, - GPIO_PIN_126, - GPIO_PIN_127, - GPIO_PIN_128, - GPIO_PIN_129, - GPIO_PIN_130, - GPIO_PIN_131, - GPIO_PIN_132, - GPIO_PIN_133, - GPIO_PIN_134, - GPIO_PIN_135, - GPIO_PIN_136, - GPIO_PIN_137, - GPIO_PIN_138, - GPIO_PIN_139, - GPIO_PIN_140, - GPIO_PIN_141, - GPIO_PIN_142, - GPIO_PIN_143, - GPIO_PIN_144, - GPIO_PIN_145, - GPIO_PIN_146, - GPIO_PIN_147, - GPIO_PIN_148, - GPIO_PIN_149, - GPIO_PIN_150, - GPIO_PIN_151, - GPIO_PIN_152, - GPIO_PIN_153, - GPIO_PIN_154, - GPIO_PIN_155, - GPIO_PIN_156, - GPIO_PIN_157, - GPIO_PIN_158, - GPIO_PIN_159, - GPIO_PIN_160, - GPIO_PIN_161, - GPIO_PIN_162, - GPIO_PIN_163, - GPIO_PIN_164, - GPIO_PIN_165, - GPIO_PIN_166, - GPIO_PIN_167, - GPIO_PIN_168, - GPIO_PIN_169, - GPIO_PIN_170, - GPIO_PIN_171, - GPIO_PIN_172, - GPIO_PIN_173, - GPIO_PIN_174, - GPIO_PIN_175, - GPIO_PIN_176, - GPIO_PIN_177, - GPIO_PIN_178, - GPIO_PIN_179, - GPIO_PIN_180, - GPIO_PIN_181, - GPIO_PIN_182, - GPIO_PIN_183, - GPIO_PIN_184, - GPIO_PIN_185, - GPIO_PIN_186, - GPIO_PIN_187, - GPIO_PIN_188, - GPIO_PIN_189, - GPIO_PIN_190, - GPIO_PIN_191, - GPIO_PIN_192, - GPIO_PIN_193, - GPIO_PIN_194, - GPIO_PIN_195, - GPIO_PIN_196, - GPIO_PIN_197, - GPIO_PIN_198, - GPIO_PIN_199, - GPIO_PIN_200, - GPIO_PIN_201, - GPIO_PIN_202, - GPIO_PIN_203, - GPIO_PIN_204, - GPIO_PIN_205, - GPIO_PIN_206, - GPIO_PIN_207, - GPIO_PIN_208, - GPIO_PIN_209, - GPIO_PIN_210, - GPIO_PIN_211, - GPIO_PIN_212, - GPIO_PIN_213, - GPIO_PIN_214, - GPIO_PIN_215, - GPIO_PIN_216, - GPIO_PIN_217, - GPIO_PIN_218, - GPIO_PIN_219, - GPIO_PIN_220, - GPIO_PIN_221, - GPIO_PIN_222, - GPIO_PIN_223, - GPIO_PIN_224, - GPIO_PIN_225, - GPIO_PIN_226, - GPIO_PIN_227, - GPIO_PIN_228, - GPIO_PIN_229, - GPIO_PIN_230, - GPIO_PIN_231, - GPIO_PIN_232, - GPIO_PIN_233, - GPIO_PIN_234, - GPIO_PIN_235, - GPIO_PIN_236, - GPIO_PIN_237, - GPIO_PIN_238, - GPIO_PIN_239, - GPIO_PIN_240, - GPIO_PIN_241, - GPIO_PIN_242, - GPIO_PIN_243, - GPIO_PIN_244, - GPIO_PIN_245, - GPIO_PIN_246, - GPIO_PIN_247, - GPIO_PIN_248, - GPIO_PIN_249, - GPIO_PIN_250, - GPIO_PIN_251, - GPIO_PIN_252, - GPIO_PIN_253, - GPIO_PIN_254, - GPIO_PIN_255, - GPIO_PIN_256, - GPIO_PIN_257, - GPIO_PIN_258, - GPIO_PIN_259, - GPIO_PIN_260, - GPIO_PIN_261, - GPIO_PIN_262, - GPIO_PIN_263, - GPIO_PIN_264, - GPIO_PIN_265, - GPIO_PIN_266, - GPIO_PIN_267 -} gpio_pin; - -/* - * Alternate Function: - * refered in altfun_table to pointout particular altfun to be enabled - * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation - */ -typedef enum { - GPIO_ALT_UART_0_MODEM, - GPIO_ALT_UART_0_NO_MODEM, - GPIO_ALT_UART_1, - GPIO_ALT_UART_2, - GPIO_ALT_I2C_0, - GPIO_ALT_I2C_1, - GPIO_ALT_I2C_2, - GPIO_ALT_I2C_3, - GPIO_ALT_MSP_0, - GPIO_ALT_MSP_1, - GPIO_ALT_MSP_2, - GPIO_ALT_MSP_3, - GPIO_ALT_MSP_4, - GPIO_ALT_MSP_5, - GPIO_ALT_SSP_0, - GPIO_ALT_SSP_1, - GPIO_ALT_MM_CARD0, - GPIO_ALT_SD_CARD0, - GPIO_ALT_DMA_0, - GPIO_ALT_DMA_1, - GPIO_ALT_HSI0, - GPIO_ALT_CCIR656_INPUT, - GPIO_ALT_CCIR656_OUTPUT, - GPIO_ALT_LCD_PANEL, - GPIO_ALT_MDIF, - GPIO_ALT_SDRAM, - GPIO_ALT_HAMAC_AUDIO_DBG, - GPIO_ALT_HAMAC_VIDEO_DBG, - GPIO_ALT_CLOCK_RESET, - GPIO_ALT_TSP, - GPIO_ALT_IRDA, - GPIO_ALT_USB_MINIMUM, - GPIO_ALT_USB_I2C, - GPIO_ALT_OWM, - GPIO_ALT_PWL, - GPIO_ALT_FSMC, - GPIO_ALT_COMP_FLASH, - GPIO_ALT_SRAM_NOR_FLASH, - GPIO_ALT_FSMC_ADDLINE_0_TO_15, - GPIO_ALT_SCROLL_KEY, - GPIO_ALT_MSHC, - GPIO_ALT_HPI, - GPIO_ALT_USB_OTG, - GPIO_ALT_SDIO, - GPIO_ALT_HSMMC, - GPIO_ALT_FSMC_ADD_DATA_0_TO_25, - GPIO_ALT_HSI1, - GPIO_ALT_NOR, - GPIO_ALT_NAND, - GPIO_ALT_KEYPAD, - GPIO_ALT_VPIP, - GPIO_ALT_CAM, - GPIO_ALT_CCP1, - GPIO_ALT_EMMC, - GPIO_ALT_POP_EMMC, - GPIO_ALT_SPI_0, - GPIO_ALT_SPI_1, - GPIO_ALT_SPI_2, - GPIO_ALT_SPI_3, - GPIO_ALT_FUNMAX /* Add new alt func before this */ -} gpio_alt_function; - -/* Defines pin assignment(Software mode or Alternate mode) */ -typedef enum { - GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */ - GPIO_ALTF_A, /* Pin connected to alternate function 1 (HW periph 1) */ - GPIO_ALTF_B, /* Pin connected to alternate function 2 (HW periph 2) */ - GPIO_ALTF_C, /* Pin connected to alternate function 3 (HW periph 3) */ - GPIO_ALTF_FIND, /* Pin connected to alternate function 3 (HW periph 3) */ - GPIO_ALTF_DISABLE /* Pin connected to alternate function 3 (HW periph 3) */ -} gpio_mode; - -/* Defines GPIO pin direction */ -typedef enum { - GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_DIR_INPUT, /* GPIO set as input */ - GPIO_DIR_OUTPUT /* GPIO set as output */ -} gpio_direction; - -/* Interrupt trigger mode */ -typedef enum { - GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored by the function */ - GPIO_TRIG_DISABLE, /* Triggers no IT */ - GPIO_TRIG_RISING_EDGE, /* Triggers an IT on a rising edge */ - GPIO_TRIG_FALLING_EDGE, /* Triggers an IT on a falling edge */ - GPIO_TRIG_BOTH_EDGES, /* Triggers an IT on a rising and a falling edge */ - GPIO_TRIG_HIGH_LEVEL, /* Triggers an IT on a high level */ - GPIO_TRIG_LOW_LEVEL /* Triggers an IT on a low level */ -} gpio_trig; /* Interrupt trigger mode, or disable */ - -/* Configuration parameters for one GPIO pin.*/ -typedef struct { - gpio_mode mode; /* Defines mode (SOFTWARE or Alternate). */ - gpio_direction direction; /* Define pin direction (in SOFTWARE mode only). */ - gpio_trig trig; /* Interrupt trigger (in SOFTWARE mode only) */ - char *dev_name; /* Name of client driver who owns the gpio pin */ -} gpio_config; - -/* GPIO pin data*/ -typedef enum { - GPIO_DATA_LOW, /* GPIO pin status is low. */ - GPIO_DATA_HIGH /* GPIO pin status is high. */ -} gpio_data; - -/* GPIO behaviour in sleep mode */ -typedef enum { - GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull up/down enabled - when in sleep mode. */ - GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by GPIO IP. So mode, - direction and data values for GPIO pin in - sleep mode are determined by configuration - set to GPIO pin before entering to sleep mode. */ -} gpio_sleep_mode; - -/* GPIO ability to wake the system up from sleep mode.*/ -typedef enum { - GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored by the function. */ - GPIO_WAKE_DISABLE, /* GPIO will not wake the system from sleep mode. */ - GPIO_WAKE_LOW_LEVEL, /* GPIO will wake the system up on a LOW level. */ - GPIO_WAKE_HIGH_LEVEL, /* GPIO will wake the system up on a HIGH level. */ - GPIO_WAKE_RISING_EDGE, /* GPIO will wake the system up on a RISING edge. */ - GPIO_WAKE_FALLING_EDGE, /* GPIO will wake the system up on a FALLING edge. */ - GPIO_WAKE_BOTH_EDGES /* GPIO will wake the system up on both RISING and FALLING edge. */ -} gpio_wake; - -/* Configuration parameters for one GPIO pin in sleep mode.*/ -typedef struct { - gpio_sleep_mode sleep_mode; /* GPIO behaviour in sleep mode. */ - gpio_wake wake; /* GPIO ability to wake up the system. */ -} gpio_sleep_config; - -/*------------------------------------------------------------------------ - * Functions declaration - * refer ./Documentation/arm/STM-Nomadik/gpio_user_guide.txt - *----------------------------------------------------------------------*/ - -extern gpio_error gpio_setpinconfig(gpio_pin pin_id, gpio_config * pin_config); -extern gpio_error gpio_resetpinconfig(gpio_pin pin_id, char *dev_name); -extern int gpio_writepin(gpio_pin pin_id, gpio_data value, char *dev_name); -extern int gpio_readpin(gpio_pin pin_id, gpio_data * value); -extern int gpio_altfuncenable(gpio_alt_function altfunc, - char *dev_name); -extern int gpio_altfuncdisable(gpio_alt_function altfunc, - char *dev_name); - -struct gpio_altfun_data { - u16 altfun; - u16 start; - u16 end; - t_bool cont; - u8 type; -}; - -#endif /* __INC_GPIO_H */ diff --git a/include/asm-arm/arch-stw8500/hardware.h b/include/asm-arm/arch-stw8500/hardware.h deleted file mode 100644 index df55a841d..000000000 --- a/include/asm-arm/arch-stw8500/hardware.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* Peripheral clusters */ - -#define U8500_PER3_BASE 0x80000000 -#define U8500_PER2_BASE 0x80110000 -#define U8500_PER1_BASE 0x80120000 -#define U8500_PER4_BASE 0x80150000 - -#define U8500_PER6_BASE 0xa03c0000 -#define U8500_PER7_BASE 0xa03d0000 -#define U8500_PER5_BASE 0xa03e0000 - -/* GPIO */ - -#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) -#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80) - -#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000) -#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80) -#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100) -#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180) - -#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000) -#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80) - -#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000) - -/* Per7 */ -#define U8500_MTU0_BASE_ED (U8500_PER7_BASE + 0xa000) -#define U8500_MTU1_BASE_ED (U8500_PER7_BASE + 0xb000) -#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) - -/* Per6 */ -#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000) -#define U8500_MTU1_BASE_v1 (U8500_PER6_BASE + 0x7000) -#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) - -/* Per5 */ -#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) - -/* Per4 */ -#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) - -/* Per3 */ -#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) -#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) - -/* Per2 */ -#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000) -#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000) -#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000) -#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) - -/* Per1 */ -#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) -#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) -#define U8500_SPI3_BASE (U8500_PER2_BASE + 0x9000) -#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) - -#define U8500_BOOTROM_BASE 0x90000000 -#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4) -#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-stw8500/mtu.h b/include/asm-arm/arch-stw8500/mtu.h deleted file mode 100755 index a87be9ef4..000000000 --- a/include/asm-arm/arch-stw8500/mtu.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2009 Alessandro Rubini - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MTU_H -#define __ASM_ARCH_MTU_H - -/* - * The MTU device hosts four different counters, with 4 set of - * registers. These are register names. - */ - -#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ -#define MTU_RIS 0x04 /* Raw interrupt status */ -#define MTU_MIS 0x08 /* Masked interrupt status */ -#define MTU_ICR 0x0C /* Interrupt clear register */ - -/* per-timer registers take 0..3 as argument */ -#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ -#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ -#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ -#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ - -/* bits for the control register */ -#define MTU_CRn_ENA 0x80 -#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CRn_PRESCALE_MASK 0x0c -#define MTU_CRn_PRESCALE_1 0x00 -#define MTU_CRn_PRESCALE_16 0x04 -#define MTU_CRn_PRESCALE_256 0x08 -#define MTU_CRn_32BITS 0x02 -#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ - -/* Other registers are usual amba/primecell registers, currently not used */ -#define MTU_ITCR 0xff0 -#define MTU_ITOP 0xff4 - -#define MTU_PERIPH_ID0 0xfe0 -#define MTU_PERIPH_ID1 0xfe4 -#define MTU_PERIPH_ID2 0xfe8 -#define MTU_PERIPH_ID3 0xfeC - -#define MTU_PCELL0 0xff0 -#define MTU_PCELL1 0xff4 -#define MTU_PCELL2 0xff8 -#define MTU_PCELL3 0xffC - -#endif /* __ASM_ARCH_MTU_H */ -- cgit v1.2.3