From 202d94875c98b7b573f136c4f353609758ed9733 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 15 Sep 2009 22:21:58 -0500 Subject: ppc/85xx: Fix LCRR_CLKDIV defines For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala Acked-by: Peter Tyser --- include/asm-ppc/fsl_lbc.h | 8 ++++++++ include/configs/XPEDITE5170.h | 2 +- include/configs/XPEDITE5200.h | 2 +- include/configs/XPEDITE5370.h | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index a28082e56..08d31e12e 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -311,9 +311,17 @@ */ #define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 +#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ + defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ + defined(CONFIG_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#else +#define LCRR_CLKDIV_4 0x00000002 +#define LCRR_CLKDIV_8 0x00000004 +#define LCRR_CLKDIV_16 0x00000008 +#endif /* LTEDR - Transfer Error Check Disable Register */ diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index 242466ae1..30642cdfe 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) /* * NAND flash configuration diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index deda20843..d79231b8b 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -103,7 +103,7 @@ * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) /* * NAND flash configuration diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 3c58ebe39..65e1afddc 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) /* * NAND flash configuration -- cgit v1.2.3 From 0e905ac28b1e039d74e63232293972bff6b5a0ce Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 18 Sep 2009 11:45:09 +0800 Subject: ppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- Makefile | 4 +--- include/configs/MPC8536DS.h | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 0b61d057f..99837a383 100644 --- a/Makefile +++ b/Makefile @@ -2448,9 +2448,7 @@ ATUM8548_config: unconfig MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale MPC8540ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 4746e2ead..faca8059a 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_MPC8536DS_36BIT +#ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT 1 #endif -- cgit v1.2.3 From f9edcc10e6cb497dd7dcbaf691cfd1859abae27a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:23:45 -0500 Subject: ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS Signed-off-by: Kumar Gala --- Makefile | 7 +------ include/configs/MPC8572DS.h | 4 ++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 99837a383..8672336f1 100644 --- a/Makefile +++ b/Makefile @@ -2514,12 +2514,7 @@ MPC8569MDS_config: unconfig MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _36BIT_,$@)" ] ; then \ - echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ - $(XECHO) "... enabling 36-bit physical addressing." ; \ - fi - @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8572DS ppc mpc85xx mpc8572ds freescale P2020DS_36BIT_config \ P2020DS_config: unconfig diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 55c1f29b1..000f8f62d 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- cgit v1.2.3 From a0f9e0e0f06033807de0ae017ad4d9cf5ddff84b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:26:37 -0500 Subject: ppc/85xx: Simplify the top makefile for 36-bit config for P2020DS Signed-off-by: Kumar Gala --- Makefile | 7 +------ include/configs/P2020DS.h | 4 ++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 8672336f1..1e256698f 100644 --- a/Makefile +++ b/Makefile @@ -2518,12 +2518,7 @@ MPC8572DS_config: unconfig P2020DS_36BIT_config \ P2020DS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _36BIT_,$@)" ] ; then \ - echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ - $(XECHO) "... enabling 36-bit physical addressing." ; \ - fi - @$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale + @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale P1011RDB_config: unconfig @mkdir -p $(obj)include diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 2a2b9acf5..b48c1999f 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- cgit v1.2.3 From 62ca21c442e18fec118ec83e183d64ea49966ce7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:31:53 -0500 Subject: ppc/85xx: Simplify the top makefile for P1_P2_RDB boards Signed-off-by: Kumar Gala --- Makefile | 22 ++++------------------ include/configs/P1_P2_RDB.h | 13 +++++++++++++ 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/Makefile b/Makefile index 1e256698f..d8daa8950 100644 --- a/Makefile +++ b/Makefile @@ -2520,25 +2520,11 @@ P2020DS_36BIT_config \ P2020DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale -P1011RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P1011" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - -P1020RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P1020" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - -P2010RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P2010" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - +P1011RDB_config \ +P1020RDB_config \ +P2010RDB_config \ P2020RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P2020" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale + @$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 6d44d6c8d..8e97ad068 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,19 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_P1011RDB +#define CONFIG_P1011 +#endif +#ifdef CONFIG_MK_P1020RDB +#define CONFIG_P1020 +#endif +#ifdef CONFIG_MK_P2010RDB +#define CONFIG_P2010 +#endif +#ifdef CONFIG_MK_P2020RDB +#define CONFIG_P2020 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- cgit v1.2.3 From 93a83872c707891bad22f7776d79a650c870601f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 10:09:04 -0500 Subject: ppc/85xx: Clean up p1_p2_rdb PCI setup General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/pci.c | 42 +++++++++++++++++++++-------------------- drivers/pci/fsl_pci_init.c | 2 +- 2 files changed, 23 insertions(+), 21 deletions(-) diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index a3617d570..4c08f9efa 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -41,60 +41,62 @@ static struct pci_controller pcie2_hose; void pci_init_board(void) { - struct fsl_pci_info pci_info[2]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = in_be32(&gur->devdisr); - uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; - int num = 0; + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, io_sel, host_agent; int first_free_busno = 0; + int num = 0; int pcie_ep, pcie_configured; + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; + debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); + puts("\n"); #ifdef CONFIG_PCIE2 - SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - puts ("\n PCIE2 connected to Slot 1 as "); - printf ("%s (base address %lx)", - pcie_ep ? "End Point": "Root Complex", pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num], + SET_STD_PCIE_INFO(pci_info[num], 2); + printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); - num++; } else { printf (" PCIE2: disabled\n"); } + puts("\n"); #else - set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE1 - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - puts ("\n PCIE1 connected to Slot 2 as "); - printf ("%s (base address %lx)", + SET_STD_PCIE_INFO(pci_info[num], 1); + printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num], + first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); - num++; } else { printf (" PCIE1: disabled\n"); } + puts("\n"); #else - set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 885542c1e..87944bfad 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -450,7 +450,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num, + printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num, hose->first_busno, hose->last_busno); return(hose->last_busno + 1); -- cgit v1.2.3 From 4958af8735207640181c4423e41b24ee7418361a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 09:42:01 -0500 Subject: ppc/85xx: Clean up p2020ds PCI setup code Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala --- board/freescale/p2020ds/p2020ds.c | 150 +++++++++----------------------------- 1 file changed, 33 insertions(+), 117 deletions(-) diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 7ad9be88c..e38c0145e 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -192,69 +192,42 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno = 0; - #ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel, host_agent; + int first_free_busno = 0; + int num = 0; - volatile ccsr_fsl_pci_t *pci; - struct pci_controller *hose; int pcie_ep, pcie_configured; - struct pci_region *r; -/* u32 temp32; */ + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf(" eTSEC2 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf(" eTSEC3 is in sgmii mode.\n"); + puts("\n"); #ifdef CONFIG_PCIE2 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - hose = &pcie2_hose; pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { - printf("\n PCIE2 connected to ULI as %s (base addr %x)", + SET_STD_PCIE_INFO(pci_info[num], 2); + printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno = hose->last_busno+1; - printf(" PCIE2 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); /* * The workaround doesn't work on p2020 because the location @@ -279,104 +252,47 @@ void pci_init_board(void) } else { printf(" PCIE2: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE3 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - hose = &pcie3_hose; pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { - printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)", + SET_STD_PCIE_INFO(pci_info[num], 3); + printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno+1; - printf(" PCIE3 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); } else { printf(" PCIE3: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 - pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - hose = &pcie1_hose; pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { - printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)", + SET_STD_PCIE_INFO(pci_info[num], 1); + printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - printf("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno = first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno = hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno, hose->last_busno); - + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf(" PCIE1: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif -- cgit v1.2.3 From f61dae7c9dc526410faec15ce352b11fc36a560b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 10:20:09 -0500 Subject: ppc/85xx: Clean up mpc8572DS PCI setup code Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala --- board/freescale/mpc8572ds/mpc8572ds.c | 230 +++++++++++----------------------- 1 file changed, 73 insertions(+), 157 deletions(-) diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index c69934ca6..933dd127e 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -160,189 +160,105 @@ static struct pci_controller pcie2_hose; static struct pci_controller pcie3_hose; #endif -int first_free_busno=0; #ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + struct fsl_pci_info pci_info[3]; + u32 devdisr, pordevsr, io_sel, host_agent, temp32; + int first_free_busno = 0; + int num = 0; + + int pcie_ep, pcie_configured; + + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16; debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) printf (" eTSEC1 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf (" eTSEC3 is in sgmii mode.\n"); - if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) + if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) printf (" eTSEC4 is in sgmii mode.\n"); - + puts("\n"); #ifdef CONFIG_PCIE3 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; - struct pci_controller *hose = &pcie3_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); - struct pci_region *r = hose->regions; - u32 temp32; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ - printf ("\n PCIE3 connected to ULI as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_MEM_BUS, - CONFIG_SYS_PCIE3_MEM_PHYS, - CONFIG_SYS_PCIE3_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE3_IO_BUS, - CONFIG_SYS_PCIE3_IO_PHYS, - CONFIG_SYS_PCIE3_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCIE3 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - /* - * Activate ULI1575 legacy chip by performing a fake - * memory access. Needed to make ULI RTC work. - * Device 1d has the first on-board memory BAR. - */ - - pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ), - PCI_BASE_ADDRESS_1, &temp32); - if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { - void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), - temp32, 4, 0); - debug(" uli1572 read to %p\n", p); - in_be32(p); - } - } else { - printf (" PCIE3: disabled\n"); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ + SET_STD_PCIE_INFO(pci_info[num], 3); + printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie3_hose, first_free_busno); + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + * Device 1d has the first on-board memory BAR. + */ + pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0), + PCI_BASE_ADDRESS_1, &temp32); + if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) { + void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0), + temp32, 4, 0); + debug(" uli1572 read to %p\n", p); + in_be32(p); } - + } else { + printf (" PCIE3: disabled\n"); } + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE2 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ - printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf (" PCIE2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - } else { - printf (" PCIE2: disabled\n"); - } - + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ + SET_STD_PCIE_INFO(pci_info[num], 2); + printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); + } else { + printf (" PCIE2: disabled\n"); } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif -#ifdef CONFIG_PCIE1 - { - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - struct pci_region *r = hose->regions; - - if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", - (uint)pci); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf(" PCIE1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); - - } else { - printf (" PCIE1: disabled\n"); - } +#ifdef CONFIG_PCIE1 + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "End Point" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); + } else { + printf (" PCIE1: disabled\n"); } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif } #endif -- cgit v1.2.3 From 002741ae862c1c7e3dad89d020e392e6add1c05d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 19 Sep 2009 11:20:54 -0500 Subject: ppc/85xx: Clean up use of LAWAR defines On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by: Kumar Gala --- board/atum8548/law.c | 2 +- board/freescale/mpc8536ds/law.c | 6 +++--- board/freescale/mpc8540ads/law.c | 2 +- board/freescale/mpc8544ds/law.c | 6 +++--- board/freescale/mpc8560ads/law.c | 2 +- board/freescale/mpc8572ds/law.c | 6 +++--- board/freescale/p1_p2_rdb/law.c | 4 ++-- board/freescale/p2020ds/law.c | 6 +++--- board/pm854/law.c | 2 +- board/pm856/law.c | 2 +- board/socrates/law.c | 4 ++-- board/stx/stxgp3/law.c | 2 +- board/stx/stxssa/law.c | 2 +- board/xes/xpedite5200/law.c | 2 +- include/asm-ppc/mmu.h | 9 ++------- 15 files changed, 26 insertions(+), 31 deletions(-) diff --git a/board/atum8548/law.c b/board/atum8548/law.c index b70b0910d..724b1bf0b 100644 --- a/board/atum8548/law.c +++ b/board/atum8548/law.c @@ -49,7 +49,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2), SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 31614d238..1f11563f5 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -31,11 +31,11 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index f5644e154..4640c1daf 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c index 317ba2696..3d308c8e5 100644 --- a/board/freescale/mpc8544ds/law.c +++ b/board/freescale/mpc8544ds/law.c @@ -30,10 +30,10 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), /* contains both PCIE3 MEM & IO space */ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3), diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c index f5644e154..4640c1daf 100644 --- a/board/freescale/mpc8560ads/law.c +++ b/board/freescale/mpc8560ads/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c index 02ea0ec59..e13bb5336 100644 --- a/board/freescale/mpc8572ds/law.c +++ b/board/freescale/mpc8572ds/law.c @@ -29,11 +29,11 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/p1_p2_rdb/law.c b/board/freescale/p1_p2_rdb/law.c index 12d2bf478..1320d5da0 100644 --- a/board/freescale/p1_p2_rdb/law.c +++ b/board/freescale/p1_p2_rdb/law.c @@ -26,9 +26,9 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c index da297c5ab..28ed2ed5e 100644 --- a/board/freescale/p2020ds/law.c +++ b/board/freescale/p2020ds/law.c @@ -29,11 +29,11 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), + SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), + SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), diff --git a/board/pm854/law.c b/board/pm854/law.c index 39e8dbbd5..ac21d7a27 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/pm856/law.c b/board/pm856/law.c index 39e8dbbd5..ac21d7a27 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/law.c b/board/socrates/law.c index 71cff8cf0..cb55fd43d 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -52,9 +52,9 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #if defined(CONFIG_SYS_FPGA_BASE) - SET_LAW(CONFIG_SYS_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif - SET_LAW(CONFIG_SYS_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxgp3/law.c b/board/stx/stxgp3/law.c index ba89f0edc..af0ac0998 100644 --- a/board/stx/stxgp3/law.c +++ b/board/stx/stxgp3/law.c @@ -52,7 +52,7 @@ struct law_entry law_table[] = { /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxssa/law.c b/board/stx/stxssa/law.c index 55dde6675..e3c34ed87 100644 --- a/board/stx/stxssa/law.c +++ b/board/stx/stxssa/law.c @@ -54,7 +54,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), /* Map the whole localbus, including flash and reset latch. */ - SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/xes/xpedite5200/law.c b/board/xes/xpedite5200/law.c index 386f9c587..bbfcb9da8 100644 --- a/board/xes/xpedite5200/law.c +++ b/board/xes/xpedite5200/law.c @@ -40,7 +40,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #if CONFIG_SYS_PCI1_MEM_PHYS SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_8M, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1), #endif #if CONFIG_SYS_PCI2_MEM_PHYS SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2), diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index a019d0b39..d516d9140 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -504,13 +504,7 @@ extern int num_tlb_entries; #endif #endif -#if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 -#else -#define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_TRGT_IF 0x00F00000 -#endif +#ifdef CONFIG_MPC83xx #define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F @@ -554,6 +548,7 @@ extern int num_tlb_entries; #define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) #define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) #define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) +#endif #ifdef CONFIG_440 /* General */ -- cgit v1.2.3 From bd42bbb858dde713f023fc2e4f512ec174a1a8d2 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:46 -0400 Subject: sbc8548: replace README with completely new document The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices. Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/Makefile | 4 +- board/sbc8548/sbc8548.c | 3 +- doc/README.sbc8548 | 189 +++++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 173 insertions(+), 23 deletions(-) diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index 9919a6efe..09e5c2e18 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -2,8 +2,8 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# (C) Copyright 2004 Wind River Systems Inc . -# Added support for Wind River SBC8560 board +# (C) Copyright 2007 Wind River Systems Inc . +# Added support for Wind River SBC8548 board # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index e5b21b555..4192eea8c 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -1,5 +1,6 @@ /* - * Copyright 2007 Wind River Systemes, Inc. + * Copyright 2007,2009 Wind River Systems, Inc. + * * Copyright 2007 Embedded Specialties, Inc. * * Copyright 2004, 2007 Freescale Semiconductor. diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index b34d0406c..d72d97d02 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -1,27 +1,176 @@ -Wind River SBC8548 reference board -=========================== +Intro: +====== -Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. ------------------------------ +The SBC8548 is a stand alone single board computer with a 1GHz +MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz +memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, +and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC +ethernet connections. -1. Building U-Boot ------------------- -The SBC8548 code is known to build using ELDK 4.1. +U-boot Configuration: +===================== - $ make sbc8548_config - Configuring for sbc8548 board... +The following possible u-boot configuration targets are available: - $ make + 1) sbc8548_config + 2) sbc8548_PCI_33_config + 3) sbc8548_PCI_66_config + 4) sbc8548_PCI_33_PCIE_config + 5) sbc8548_PCI_66_PCIE_config +Generally speaking, most people should choose to use #5. Details +of each choice are listed below. -2. Switch and Jumper Settings ------------------------------ -All Jumpers & Switches are in their default positions. Please refer to -the board documentation for details. Some settings control CPU voltages -and settings may change with board revisions. +Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. -3. Known limitations --------------------- -PCI: - The code to support PCI is currently disabled and has not been verified. +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with a _PCI_33_ config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. [The above discussion assumes that the SW2[1-4] has not been changed +to reflect a different CCB:SYSCLK ratio] + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. Options four and five are just repeats of option two +and three, but with PCI-e support enabled as well. + +PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx +is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with +a 33MHz PCI configuration is currently untested.) + + => pci 0 + Scanning PCI devices on bus 0 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 00.00.00 0x1057 0x0012 Processor 0x20 + 00.01.00 0x8086 0x1026 Network controller 0x00 + => pci 1 + Scanning PCI devices on bus 1 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 01.00.00 0x1957 0x0012 Processor 0x20 + => pci 2 + Scanning PCI devices on bus 2 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 02.00.00 0x1148 0x9e00 Network controller 0x00 + => + + +Hardware Reference: +=================== + +The following contains some summary information on hardware settings +that are relevant to u-boot, based on the board manual. For the +most up to date and complete details of the board, please request the +reference manual ERG-00327-001.pdf from www.windriver.com + +Boot flash: + intel V28F640Jx, 8192x8 (one device) at 0xff80_0000 + +Sodimm flash: + intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + + + Jumpers: + +Jumper Name ON OFF +---------------------------------------------------------------- +JP12 CS0/CS6 swap see note[*] see note[*] + +JP13 SODIMM flash write OK writes disabled + write prot. + +JP14 HRESET/TRST joined isolated + +JP15 PWR ON when AC pwr use S1 for on/off + +JP16 Demo LEDs lit not lit + +JP19 PCI mode PCI PCI-X + + +[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash +onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 +is jumpered parallel to the LBC-SDRAM, then /CS0 is for the +SODIMM flash and /CS6 is for the boot flash. Note that in this +alternate setting, you also need to switch SW2.8 to ON. Currently +u-boot doesn't support booting off the SODIMM in this alternate +setting without manually altering BR0/OR0 and BR6/OR6 in the +board config file appropriately. + + + Switches: + +The defaults are marked with a * + +Name Desc. ON OFF +------------------------------------------------------------------ +S1 Pwr toggle n/a n/a + +SW2.1 CFG_SYS_PLL0 1 0* +SW2.2 CFG_SYS_PLL1 1* 0 +SW2.3 CFG_SYS_PLL2 1* 0 +SW2.4 CFG_SYS_PLL3 1 0* +SW2.5 CFG_CORE_PLL0 1* 0 +SW2.6 CFG_CORE_PLL1 1 0* +SW2.7 CFG_CORE_PLL2 1* 0 +SW2.8 CFG_ROM_LOC1 1 0* + +SW3.1 CFG_HOST_AGT0 1* 0 +SW3.2 CFG_HOST_AGT1 1* 0 +SW3.3 CFG_HOST_AGT2 1* 0 +SW3.4 CFG_IO_PORTS0 1* 0 +SW3.5 CFG_IO_PORTS0 1 0* +SW3.6 CFG_IO_PORTS0 1 0* + +SerDes CLK(MHz) SW5.1 SW5.2 +---------------------------------------------- +25 0 0 +100* 1 0 +125 0 1 +200 1 1 + +SerDes CLK spread SW5.3 SW5.4 +---------------------------------------------- ++/- 0.25% 0 0 +-0.50% 1 0 +-0.75% 0 1 +No Spread* 1 1 + +SW4 settings are readable from the EPLD and are currently not used for +any hardware settings (i.e. user configuration switches). + + LEDs: + +Name Desc. ON OFF +------------------------------------------------------------------ +D13 PCI/PCI-X PCI-X PCI +D14 3.3V PWR 3.3V no power +D15 SYSCLK 66MHz 33MHz + + + Default Memory Map: + +start end CS width Desc. +---------------------------------------------------------------------- +0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) +f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) +f800_0000 f8b0_1fff CS5 - EPLD +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) +ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) + +The EPLD on CS5 demuxes the following devices at the following offsets: + +offset size width device +-------------------------------------------------------- +0 1fff 8 7 segment display LED +10_0000 1fff 4 user switches +30_0000 1fff 4 HW Rev. register +b0_0000 1fff 8 8kB EEPROM -- cgit v1.2.3 From 82b7725b6d46d9ad2b962b4cdfa896bd5ee32fb5 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Sat, 19 Sep 2009 17:50:17 +0530 Subject: ppc/85xx: 32bit DDR changes for P1020/P1011 The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/ddr.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index d1e659b46..37c4b0a3b 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -23,10 +23,13 @@ #include #include #include +#include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); @@ -203,24 +206,40 @@ phys_size_t fixed_sdram (void) { sys_info_t sysinfo; char buf[32]; + fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL; + size_t ddr_size; + struct cpu_type *cpu; get_sys_info(&sysinfo); printf("Configuring DDR for %s MT/s data rate\n", strmhz(buf, sysinfo.freqDDRBus)); if(sysinfo.freqDDRBus <= DATARATE_400MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_400, 0); + ddr_cfg_regs = &ddr_cfg_regs_400; else if(sysinfo.freqDDRBus <= DATARATE_533MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_533, 0); + ddr_cfg_regs = &ddr_cfg_regs_533; else if(sysinfo.freqDDRBus <= DATARATE_667MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_667, 0); + ddr_cfg_regs = &ddr_cfg_regs_667; else if(sysinfo.freqDDRBus <= DATARATE_800MHZ) - fsl_ddr_set_memctl_regs(&ddr_cfg_regs_800, 0); + ddr_cfg_regs = &ddr_cfg_regs_800; else panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, sysinfo.freqDDRBus)); - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + cpu = gd->cpu; + /* P1020 and it's derivatives support max 32bit DDR width */ + if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE; + ddr_cfg_regs->cs[0].bnds = 0x0000001F; + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); + } + else + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + + fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0); + + return ddr_size; } phys_size_t initdram(int board_type) -- cgit v1.2.3 From 94ca091456d5c3040ddd6351c80cf3e74393f9be Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:44 -0400 Subject: sbc8548: enable use of PCI network cards Create a board_eth_init to allow a place to hook in the PCI ethernet init after all the eTSEC are up and configured. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 4192eea8c..fc78a7c6a 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include #include @@ -491,6 +493,13 @@ pci_init_board(void) } +int board_eth_init(bd_t *bis) +{ + tsec_standard_init(bis); + pci_eth_init(bis); + return 0; /* otherwise cpu_eth_init gets run */ +} + int last_stage_init(void) { return 0; -- cgit v1.2.3 From 7b1f1399e876587e0a268a5a471dd444bfbc3114 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:39 -0400 Subject: sbc8548: delete unused MPC8548CDS info carried over from port There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 63 +++++------------------------------------------ include/configs/sbc8548.h | 9 ------- 2 files changed, 6 insertions(+), 66 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index fc78a7c6a..fff7dab98 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -314,35 +314,9 @@ long int fixed_sdram (void) } #endif -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it. - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_sbc8548_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - -static struct pci_controller pci1_hose = { - config_table: pci_sbc8548_config_table}; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif /* CONFIG_PCI1 */ #ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; @@ -359,24 +333,20 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - struct pci_config_table *table; struct pci_region *r = hose->regions; uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); - uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter" ); @@ -395,12 +365,6 @@ pci_init_board(void) PCI_REGION_IO); hose->region_count = r - hose->regions; - /* relocate config table pointers */ - hose->config_table = \ - (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); - for (table = hose->config_table; table && table->vendor; table++) - table->config_device += gd->reloc_off; - hose->first_busno=first_free_busno; fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); @@ -425,33 +389,18 @@ pci_init_board(void) gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif -#ifdef CONFIG_PCI2 -{ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } -} -#else - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ -#endif /* CONFIG_PCI2 */ + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */ #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", + printf ("\n PCIE at base address %x", (uint)pci); if (pci->pme_msg_det) { diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 838b4db9a..3d05afbba 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,6 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_PCI2 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -343,14 +342,6 @@ #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -- cgit v1.2.3 From 2c40acd3525b75db3fcd3f5a5bd40445679b5547 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:40 -0400 Subject: sbc8548: get_clock_freq is not valid for this board The get_clock_freq() comes from freescale/common/cadmus.c and is only valid for the CDS based 85xx reference platforms. It would be nice if we could read the 33 vs. 66MHz status somehow, but in the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other non-CDS boards do. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index fff7dab98..031658107 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -339,13 +339,13 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", + (pci_speed == 33000000) ? "33" : + (pci_speed == 66000000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_arb ? "arbiter" : "external-arbiter" ); -- cgit v1.2.3 From ded58f4153923dfff16d2f96495bd7acf1f7e10e Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Wed, 23 Sep 2009 17:30:57 -0400 Subject: sbc8548: cosmetic line re-wrap Fix the extra long lines to be consistent with u-boot coding style. No functional change here. Signed-off-by: Paul Gortmaker --- board/sbc8548/tlb.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 18d11f6dc..ddcb532ee 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -31,13 +31,16 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -62,7 +65,8 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 2: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), -- cgit v1.2.3 From 9b3ba24f18900633a394416cc056c44a1a6eb754 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:41 -0400 Subject: sbc8548: enable access to second bank of flash The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/tlb.c | 28 ++++++++++++++++++++++++---- include/configs/sbc8548.h | 8 +++++--- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index ddcb532ee..a0b4e36e7 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -45,13 +45,15 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 0), /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff800000 16M TLB for 8MB FLASH + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 56M 8MB -> 64MB of user flash + * 0xff800000 8M boot FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000, + CONFIG_SYS_ALT_FLASH + 0x800000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), + 0, 0, BOOKE_PAGESZ_64M, 1), /* * TLB 1: 256M Non-cacheable, guarded @@ -107,6 +109,24 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 7: 4M Non-cacheable, guarded + * 0xfb800000 4M 1st 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4M, 1), + + /* + * TLB 8: 4M Non-cacheable, guarded + * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, + CONFIG_SYS_ALT_FLASH + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4M, 1), + }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3d05afbba..5c1411f66 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -163,6 +163,7 @@ */ #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff800801 @@ -171,9 +172,10 @@ #define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_ALT_FLASH} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -- cgit v1.2.3 From fc38eb98ff226f2c53eecbee033a6ab7619473dc Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:02 -0400 Subject: sbc8548: remove eTSEC3/4 voltage hack With only eTSEC1 and 2 being brought out to RJ-45 connectors, we aren't interested in the eTSEC3/4 voltage hack on this board Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 031658107..96a5f421a 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -52,7 +52,6 @@ int board_early_init_f (void) int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; @@ -64,11 +63,6 @@ int checkboard (void) */ local_bus_init (); - /* - * Hack TSEC 3 and 4 IO voltages. - */ - gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ - ecm->eedr = 0xffffffff; /* clear ecm errors */ ecm->eeer = 0xffffffff; /* enable ecm errors */ return 0; -- cgit v1.2.3 From 0c7e4d45d9fb3c9e503ee93d50572d346dae150e Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:03 -0400 Subject: sbc8548: use I/O accessors Sweep throught the board specific file and replace the various register proddings with the equivalent I/O accessors. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 91 ++++++++++++++++++++++++------------------------- 1 file changed, 45 insertions(+), 46 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 96a5f421a..ce998e1c2 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -56,15 +56,15 @@ int checkboard (void) volatile u_char *rev= (void *)CONFIG_SYS_BD_REV; printf ("Board: Wind River SBC8548 Rev. 0x%01x\n", - (*rev) >> 4); + in_8(rev) >> 4); /* * Initialize local bus. */ local_bus_init (); - ecm->eedr = 0xffffffff; /* clear ecm errors */ - ecm->eeer = 0xffffffff; /* enable ecm errors */ + out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ + out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ return 0; } @@ -86,7 +86,7 @@ initdram(int board_type) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - gur->ddrdllcr = 0x81000000; + out_be32(&gur->ddrdllcr, 0x81000000); asm("sync;isync;msync"); udelay(200); } @@ -123,24 +123,24 @@ local_bus_init(void) sys_info_t sysinfo; get_sys_info(&sysinfo); - clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; + clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2; lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - gur->lbiuiplldcr1 = 0x00078080; + out_be32(&gur->lbiuiplldcr1, 0x00078080); if (clkdiv == 16) { - gur->lbiuiplldcr0 = 0x7c0f1bf0; + out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); } else if (clkdiv == 8) { - gur->lbiuiplldcr0 = 0x6c0f1bf0; + out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); } else if (clkdiv == 4) { - gur->lbiuiplldcr0 = 0x5c0f1bf0; + out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); } - lbc->lcrr |= 0x00030000; + setbits_be32(&lbc->lcrr, 0x00030000); asm("sync;isync;msync"); - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ + out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */ + out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */ } /* @@ -163,18 +163,18 @@ sdram_init(void) /* * Setup SDRAM Base and Option Registers */ - lbc->or3 = CONFIG_SYS_OR3_PRELIM; + out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM); asm("msync"); - lbc->br3 = CONFIG_SYS_BR3_PRELIM; + out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); asm("msync"); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT); + out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR); asm("msync"); /* @@ -186,7 +186,7 @@ sdram_init(void) /* * Issue PRECHARGE ALL command. */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_PCHALL); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -196,7 +196,7 @@ sdram_init(void) * Issue 8 AUTO REFRESH commands. */ for (idx = 0; idx < 8; idx++) { - lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_ARFRSH); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -206,7 +206,7 @@ sdram_init(void) /* * Issue 8 MODE-set command. */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_MRW); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -215,7 +215,7 @@ sdram_init(void) /* * Issue NORMAL OP command. */ - lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL; + out_be32(&lbc->lsdmr, lsdmr_common | LSDMR_OP_NORMAL); asm("sync;msync"); *sdram_addr = 0xff; ppcDcbf((unsigned long) sdram_addr); @@ -263,45 +263,44 @@ testdram(void) } #endif -#if !defined(CONFIG_SPD_EEPROM) +#if !defined(CONFIG_SPD_EEPROM) +#define CONFIG_SYS_DDR_CONTROL 0xc300c000 /************************************************************************* * fixed_sdram init -- doesn't use serial presence detect. * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. ************************************************************************/ long int fixed_sdram (void) { - #define CONFIG_SYS_DDR_CONTROL 0xc300c000 - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - ddr->cs0_bnds = 0x0000007f; - ddr->cs1_bnds = 0x008000ff; - ddr->cs2_bnds = 0x00000000; - ddr->cs3_bnds = 0x00000000; - ddr->cs0_config = 0x80010101; - ddr->cs1_config = 0x80010101; - ddr->cs2_config = 0x00000000; - ddr->cs3_config = 0x00000000; - ddr->timing_cfg_3 = 0x00000000; - ddr->timing_cfg_0 = 0x00220802; - ddr->timing_cfg_1 = 0x38377322; - ddr->timing_cfg_2 = 0x0fa044C7; - ddr->sdram_cfg = 0x4300C000; - ddr->sdram_cfg_2 = 0x24401000; - ddr->sdram_mode = 0x23C00542; - ddr->sdram_mode_2 = 0x00000000; - ddr->sdram_interval = 0x05080100; - ddr->sdram_md_cntl = 0x00000000; - ddr->sdram_data_init = 0x00000000; - ddr->sdram_clk_cntl = 0x03800000; + out_be32(&ddr->cs0_bnds, 0x0000007f); + out_be32(&ddr->cs1_bnds, 0x008000ff); + out_be32(&ddr->cs2_bnds, 0x00000000); + out_be32(&ddr->cs3_bnds, 0x00000000); + out_be32(&ddr->cs0_config, 0x80010101); + out_be32(&ddr->cs1_config, 0x80010101); + out_be32(&ddr->cs2_config, 0x00000000); + out_be32(&ddr->cs3_config, 0x00000000); + out_be32(&ddr->timing_cfg_3, 0x00000000); + out_be32(&ddr->timing_cfg_0, 0x00220802); + out_be32(&ddr->timing_cfg_1, 0x38377322); + out_be32(&ddr->timing_cfg_2, 0x0fa044C7); + out_be32(&ddr->sdram_cfg, 0x4300C000); + out_be32(&ddr->sdram_cfg_2, 0x24401000); + out_be32(&ddr->sdram_mode, 0x23C00542); + out_be32(&ddr->sdram_mode_2, 0x00000000); + out_be32(&ddr->sdram_interval, 0x05080100); + out_be32(&ddr->sdram_md_cntl, 0x00000000); + out_be32(&ddr->sdram_data_init, 0x00000000); + out_be32(&ddr->sdram_clk_cntl, 0x03800000); asm("sync;isync;msync"); udelay(500); #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; + out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); #endif return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; -- cgit v1.2.3 From 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:04 -0400 Subject: sbc8548: correct local bus SDRAM size from 64M to 128M The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/sbc8548.c | 8 +++++++- board/sbc8548/tlb.c | 23 ++++++++++++++++------- include/configs/sbc8548.h | 42 ++++++++++++++++++++++++++++++++++++++---- 3 files changed, 61 insertions(+), 12 deletions(-) diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index ce998e1c2..f4bfd925a 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -149,7 +149,7 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) +#if defined(CONFIG_SYS_LBC_SDRAM_SIZE) uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -169,6 +169,12 @@ sdram_init(void) out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM); asm("msync"); + out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM); + asm("msync"); + + out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM); + asm("msync"); + out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); asm("msync"); diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index a0b4e36e7..a1795fcfb 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -93,14 +93,23 @@ struct fsl_e_tlb_entry tlb_table[] = { /* * TLB 5: 64M Cacheable, non-guarded - * 0xf0000000 64M LBC SDRAM + * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_64M, 1), /* - * TLB 6: 16M Cacheable, non-guarded + * TLB 6: 64M Cacheable, non-guarded + * 0xf4000000 64M LBC SDRAM Second half + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -108,24 +117,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 7, BOOKE_PAGESZ_16M, 1), /* - * TLB 7: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1), /* - * TLB 8: 4M Non-cacheable, guarded + * TLB 9: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 9, BOOKE_PAGESZ_4M, 1), }; diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 5c1411f66..009931df5 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -197,13 +197,13 @@ #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 /* - * SDRAM on the Local Bus + * SDRAM on the Local Bus (CS3 and CS4) */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ /* - * Base Register 3 and Option Register 3 configure SDRAM. + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR3, need: @@ -221,7 +221,7 @@ #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR3, need: * 64MB mask for AM, OR3[0:7] = 1111 1100 @@ -236,6 +236,40 @@ #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 +/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -- cgit v1.2.3 From a8b3e90f798e0cca5f11c912f9d0823a1c5b6c24 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:01 -0400 Subject: fsl_pci: create a SET_STD_PCI_INFO() helper wrapper Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_pci.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index b9972dabe..2790da7ed 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -173,6 +173,18 @@ struct fsl_pci_info { int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); +#define SET_STD_PCI_INFO(x, num) \ +{ \ + x.regs = CONFIG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.pci_num = num; \ +} + #define SET_STD_PCIE_INFO(x, num) \ { \ x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ -- cgit v1.2.3 From fdc7eb90b504daa020f290604d50da8f7cb70d8a Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:05 -0400 Subject: sbc8548: update PCI/PCI-e support code The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- board/sbc8548/law.c | 12 ++++- board/sbc8548/sbc8548.c | 129 ++++++++++++++-------------------------------- board/sbc8548/tlb.c | 53 +++++++++---------- include/configs/sbc8548.h | 45 ++++++++-------- 4 files changed, 96 insertions(+), 143 deletions(-) diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index e8c7ae2a2..6d1efc0c6 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -32,8 +32,10 @@ * * 0x0000_0000 0x0fff_ffff DDR 256M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe200_0000 0xe27f_ffff PCI1 IO 8M + * 0xe280_0000 0xe2ff_ffff PCIe IO 8M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf8b0_0000 0xf80f_ffff EEPROM 1M * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M @@ -48,8 +50,14 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif +#ifdef CONFIG_SYS_PCI1_MEM_PHYS SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), +#endif +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index f4bfd925a..194f6ab96 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -321,125 +321,74 @@ static struct pci_controller pci1_hose; static struct pci_controller pcie1_hose; #endif /* CONFIG_PCIE1 */ -int first_free_busno=0; +#ifdef CONFIG_PCI void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct fsl_pci_info pci_info[2]; + u32 devdisr, pordevsr, porpllsr, io_sel; + int first_free_busno = 0; + int num = 0; -#ifdef CONFIG_PCI1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; - struct pci_controller *hose = &pci1_hose; - struct pci_region *r = hose->regions; +#ifdef CONFIG_PCIE1 + int pcie_configured; +#endif - uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ - uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ + devdisr = in_be32(&gur->devdisr); + pordevsr = in_be32(&gur->pordevsr); + porpllsr = in_be32(&gur->porpllsr); + io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ + debug(" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); + +#ifdef CONFIG_PCI1 + if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { + uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */ - if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33000000) ? "33" : (pci_speed == 66000000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", - pci_arb ? "arbiter" : "external-arbiter" - ); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, - CONFIG_SYS_PCI1_IO_SIZE, - PCI_REGION_IO); - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - first_free_busno=hose->last_busno+1; - printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); -#ifdef CONFIG_PCIX_CHECK - if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - printf("PCI-X will only work at 66 MHz\n"); - - reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); - } -#endif + pci_arb ? "arbiter" : "external-arbiter"); + + SET_STD_PCI_INFO(pci_info[num], 1); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pci1_hose, first_free_busno); } else { printf (" PCI: disabled\n"); } -} + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */ #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - struct pci_region *r = hose->regions; - - int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); - - if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE at base address %x", - (uint)pci); - - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); - } - printf ("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); - - first_free_busno=hose->last_busno+1; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ + SET_STD_PCIE_INFO(pci_info[num], 1); + printf (" PCIE at base address %lx\n", pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); } else { printf (" PCIE: disabled\n"); } - } + + puts("\n"); #else - gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif - } +#endif int board_eth_init(bd_t *bis) { diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index a1795fcfb..38bdeb37c 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -56,60 +56,53 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_64M, 1), /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), + 0, 1, BOOKE_PAGESZ_1G, 1), /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Cacheable, non-guarded + * TLB 2: 256M Cacheable, non-guarded * 0x0 256M DDR SDRAM */ - #if !defined(CONFIG_SPD_EEPROM) +#if !defined(CONFIG_SPD_EEPROM) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 3, BOOKE_PAGESZ_256M, 1), - #endif + 0, 2, BOOKE_PAGESZ_256M, 1), +#endif /* - * TLB 4: 64M Non-cacheable, guarded + * TLB 3: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO + * 0xe2000000 8M PCI1 IO + * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), + 0, 3, BOOKE_PAGESZ_64M, 1), /* - * TLB 5: 64M Cacheable, non-guarded + * TLB 4: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_64M, 1), /* - * TLB 6: 64M Cacheable, non-guarded + * TLB 5: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), + 0, 5, BOOKE_PAGESZ_64M, 1), /* - * TLB 7: 16M Cacheable, non-guarded + * TLB 6: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -117,24 +110,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16M, 1), + 0, 6, BOOKE_PAGESZ_16M, 1), /* - * TLB 8: 4M Non-cacheable, guarded + * TLB 7: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 7, BOOKE_PAGESZ_4M, 1), /* - * TLB 9: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1), }; diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 009931df5..1f340ed7f 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,14 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#ifdef CONFIG_PCI +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif +#ifdef CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -343,31 +350,27 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ -#endif +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ #endif #ifdef CONFIG_RIO @@ -386,7 +389,7 @@ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- cgit v1.2.3 From 2738bc8df65ec905094d83f62f87fed123a03b9c Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:06 -0400 Subject: sbc8548: allow enabling PCI via a make config option Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- MAKEALL | 4 ++++ Makefile | 8 ++++++-- include/configs/sbc8548.h | 43 +++++++++++++++++++++++++++++++++---------- 3 files changed, 43 insertions(+), 12 deletions(-) diff --git a/MAKEALL b/MAKEALL index 1d50c3430..b394adbef 100755 --- a/MAKEALL +++ b/MAKEALL @@ -399,6 +399,10 @@ LIST_85xx=" \ PM856 \ sbc8540 \ sbc8548 \ + sbc8548_PCI_33 \ + sbc8548_PCI_66 \ + sbc8548_PCI_33_PCIE \ + sbc8548_PCI_66_PCIE \ sbc8560 \ socrates \ stxgp3 \ diff --git a/Makefile b/Makefile index d8daa8950..55ee25d8a 100644 --- a/Makefile +++ b/Makefile @@ -2544,8 +2544,12 @@ sbc8540_66_config: unconfig fi @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 -sbc8548_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548 +sbc8548_config \ +sbc8548_PCI_33_config \ +sbc8548_PCI_66_config \ +sbc8548_PCI_33_PCIE_config \ +sbc8548_PCI_66_PCIE_config: unconfig + @$(MKCONFIG) -t $(@:_config=) sbc8548 ppc mpc85xx sbc8548 sbc8560_config \ sbc8560_33_config \ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 1f340ed7f..d10792a22 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Wind River Systems + * Copyright 2007,2009 Wind River Systems * Copyright 2007 Embedded Specialties, Inc. * Copyright 2004, 2007 Freescale Semiconductor. * @@ -24,23 +24,40 @@ /* * sbc8548 board configuration file - * - * Please refer to doc/README.sbc85xx for more info. - * + * Please refer to doc/README.sbc8548 for more info. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#define CONFIG_PCI1 +#endif + +#ifdef CONFIG_MK_66 +#define CONFIG_SYS_CLK_DIV 1 +#endif + +#ifdef CONFIG_MK_33 +#define CONFIG_SYS_CLK_DIV 2 +#endif + +#ifdef CONFIG_MK_PCIE +#define CONFIG_PCIE1 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ -#undef CONFIG_PCI /* enable any pci type devices */ -#undef CONFIG_PCI1 /* PCI controller 1 */ -#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO #ifdef CONFIG_PCI @@ -58,7 +75,13 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ +/* + * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] + */ +#ifndef CONFIG_SYS_CLK_DIV +#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ +#endif +#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) /* * These can be toggled for performance analysis, otherwise use default. @@ -316,7 +339,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */ +#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -- cgit v1.2.3 From 928435d11b898870415910efff87a4d6399cecb8 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Mon, 21 Sep 2009 17:19:17 -0400 Subject: sbc85x0: tidy up Makefile to use new configuration script. Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- Makefile | 18 ++---------------- include/configs/SBC8540.h | 19 +++++++++++-------- include/configs/sbc8560.h | 17 ++++++++++++----- 3 files changed, 25 insertions(+), 29 deletions(-) diff --git a/Makefile b/Makefile index 55ee25d8a..9c5b2a5c9 100644 --- a/Makefile +++ b/Makefile @@ -2535,14 +2535,7 @@ PM856_config: unconfig sbc8540_config \ sbc8540_33_config \ sbc8540_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - $(XECHO) "... 66 MHz PCI" ; \ - else \ - $(XECHO) "... 33 MHz PCI" ; \ - fi - @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560 + @$(MKCONFIG) -t $(@:_config=) SBC8540 ppc mpc85xx sbc8560 sbc8548_config \ sbc8548_PCI_33_config \ @@ -2554,14 +2547,7 @@ sbc8548_PCI_66_PCIE_config: unconfig sbc8560_config \ sbc8560_33_config \ sbc8560_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _66_,$@)" ] ; then \ - echo "#define CONFIG_PCI_66" >>$(obj)include/config.h ; \ - $(XECHO) "... 66 MHz PCI" ; \ - else \ - $(XECHO) "... 33 MHz PCI" ; \ - fi - @$(MKCONFIG) -a sbc8560 ppc mpc85xx sbc8560 + @$(MKCONFIG) -t $(@:_config=) sbc8560 ppc mpc85xx sbc8560 socrates_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 272b5dd56..7cde39bf2 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -24,22 +24,25 @@ * MA 02111-1307 USA */ -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8540 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 #endif + #define TSEC_DEBUG -/* High Level Configuration Options */ +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 46c94bf16..a6b15f74c 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -24,16 +24,23 @@ * MA 02111-1307 USA */ -/* sbc8560 board configuration file */ -/* please refer to doc/README.sbc8560 for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8560 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -- cgit v1.2.3 From 8439f05cfd8cbb38485376a34d9fe297ba262737 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 21 Sep 2009 23:09:28 -0500 Subject: mpc8610hpcd: Use common 86xx fdt fixup code Using the common 86xx fdt fixups removes some board-specific code and should make the mpc8610hpcd easier to maintain in the long run. Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 98111eb60..358148faf 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -387,19 +387,7 @@ void pci_init_board(void) void ft_board_setup(void *blob, bd_t *bd) { - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 4, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "bus-frequency", bd->bi_busfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "clock-frequency", bd->bi_intfreq, 1); - do_fixup_by_prop_u32(blob, "device_type", "soc", 4, - "bus-frequency", bd->bi_busfreq, 1); - - do_fixup_by_compat_u32(blob, "ns16550", - "clock-frequency", bd->bi_busfreq, 1); - - fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize); + ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI1 ft_fsl_pci_setup(blob, "pci0", &pci1_hose); -- cgit v1.2.3 From 098bcbae3172d73d24ca8ba196328d901eed4132 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:10 +0800 Subject: ppc/85xx: add ld script file for boot from NAND The first stage 4K image uses a seperate ld script file to generate 4K image. This patch moves it to the cpu/mpc85xx/* to make it avaliable for 85xx platform. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/u-boot-nand_spl.lds | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 cpu/mpc85xx/u-boot-nand_spl.lds diff --git a/cpu/mpc85xx/u-boot-nand_spl.lds b/cpu/mpc85xx/u-boot-nand_spl.lds new file mode 100644 index 000000000..fef3e42e0 --- /dev/null +++ b/cpu/mpc85xx/u-boot-nand_spl.lds @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + . = 0xfff00000; + .text : { + *(.text) + } + _etext = .; + + .reloc : { + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + . = ALIGN(8); + .data : { + *(.rodata*) + *(.data*) + *(.sdata*) + } + _edata = .; + + . = ALIGN(8); + __init_begin = .; + __init_end = .; + + .resetvec ADDR(.text) + 0xffc : { + *(.resetvec) + } = 0xffff + + __bss_start = .; + .bss : { + *(.sbss) + *(.bss) + } + _end = .; +} +ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big"); -- cgit v1.2.3 From 266139b88b43ae1d87abb5f5431e6f57b801795f Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:34 +0800 Subject: immap_85xx: add porpllsr's plat ratio definition Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index e7d412dba..39fdb8e94 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1542,6 +1542,8 @@ typedef struct ccsr_gur { #endif #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 +#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e +#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 #define MPC85xx_PORBMSR_HA_SHIFT 16 -- cgit v1.2.3 From 234a89d911ce28e46372f555d7c14e28424f2b0d Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:21 +0800 Subject: ppc/85xx: add cpu init config file for boot from NAND When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init_nand.c | 63 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 cpu/mpc85xx/cpu_init_nand.c diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c new file mode 100644 index 000000000..184cca4c5 --- /dev/null +++ b/cpu/mpc85xx/cpu_init_nand.c @@ -0,0 +1,63 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +void cpu_init_f(void) +{ + ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + + /* + * LCRR - Clock Ratio Register - set up local bus timing + * when needed + */ + out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8); + +#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM) + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM); + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM); +#else +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined +#endif + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + char *l2srbar; + int i; + + out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); + + /* set MBECCDIS=1, SBECCDIS=1 */ + out_be32(&l2cache->l2errdis, + (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); + + /* set L2E=1 & L2SRAM=001 */ + out_be32(&l2cache->l2ctl, + (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); + + /* Initialize L2 SRAM to zero */ + l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR; + for (i = 0; i < CONFIG_SYS_L2_SIZE; i++) + l2srbar[i] = 0; +#endif +} -- cgit v1.2.3 From cb0ff65c619efacdc0ba69aa8ee6ede7dd364a38 Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Tue, 22 Sep 2009 12:48:27 +0530 Subject: 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQ The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 723f473da..61e0fb063 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -27,6 +27,7 @@ #include #include #include +#include #ifdef CONFIG_FSL_ESDHC #include #endif @@ -148,8 +149,14 @@ static inline void ft_fixup_l2cache(void *blob) } if (cpu) { - len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller", - cpu->name); + if (isdigit(cpu->name[0])) + len = sprintf(compat_buf, + "fsl,mpc%s-l2-cache-controller", cpu->name); + else + len = sprintf(compat_buf, + "fsl,%c%s-l2-cache-controller", + tolower(cpu->name[0]), cpu->name + 1); + sprintf(&compat_buf[len + 1], "cache"); } fdt_setprop(blob, off, "cache-unified", NULL, 0); -- cgit v1.2.3 From 25bacf7a2b096496e2c58f2de4e5b2bce8fba038 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 22 Sep 2009 15:45:44 -0500 Subject: ppc/85xx: Fix enabling of L2 cache We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 4 ++-- cpu/mpc85xx/release.S | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a6d1e999b..a8d83b1c8 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -336,8 +336,8 @@ int cpu_init_r(void) u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ - mtspr(SPRN_L2CSR0, L2CSR0_L2FI); - while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) + mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); + while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; /* enable the cache */ diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 074b056b7..ecbd0d585 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -102,7 +102,8 @@ __secondary_start_page: #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync - lis r3,L2CSR0_L2FI@h + lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l mtspr SPRN_L2CSR0,r3 1: mfspr r3,SPRN_L2CSR0 -- cgit v1.2.3 From 01df521217957d77d53c2d570183eded7030938f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Sep 2009 09:43:12 -0500 Subject: ppc/p4080: Add p4080 platform immap definitions The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_lbc.h | 4 + include/asm-ppc/immap_85xx.h | 287 ++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 271 insertions(+), 20 deletions(-) diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index 08d31e12e..5723de643 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -317,6 +317,10 @@ #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#elif defined(CONFIG_FSL_CORENET) +#define LCRR_CLKDIV_8 0x00000002 +#define LCRR_CLKDIV_16 0x00000004 +#define LCRR_CLKDIV_32 0x00000008 #else #define LCRR_CLKDIV_4 0x00000002 #define LCRR_CLKDIV_8 0x00000004 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 39fdb8e94..100dfe106 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -16,6 +16,29 @@ #include #include +typedef struct ccsr_local { + u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */ + u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */ + u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */ +#define CCSRAR_C 0x80000000 /* Commit */ + u8 res1[4]; + u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */ + u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */ + u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */ + u8 res2[4]; + u32 bstrh; /* 0x20 - Boot space translation register high */ + u32 bstrl; /* 0x24 - Boot space translation register Low */ + u32 bstrar; /* 0x28 - Boot space translation attributes register */ + u8 res3[0xbd4]; + struct { + u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */ + u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */ + u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */ + u8 res4[4]; + } law[32]; + u8 res35[0x204]; +} ccsr_local_t; + /* * Local-Access Registers and ECM Registers(0x0000-0x2000) */ @@ -165,7 +188,21 @@ typedef struct ccsr_ddr { uint debug_2; uint debug_3; uint debug_4; - char res12[240]; + uint debug_5; + uint debug_6; + uint debug_7; + uint debug_8; + uint debug_9; + uint debug_10; + uint debug_11; + uint debug_12; + uint debug_13; /* +0xF30 */ + uint debug_14; + uint debug_15; + uint debug_16; + uint debug_17; + uint debug_18; /* +0xF44 */ + char res12[184]; } ccsr_ddr_t; /* @@ -1531,6 +1568,193 @@ typedef struct par_io { /* * Global Utilities Register Block(0xe_0000-0xf_ffff) */ +#ifdef CONFIG_FSL_CORENET +typedef struct ccsr_gur { + u32 porsr1; /* 0xe0000 - POR status register */ + u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */ + u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */ + u8 res2[12]; + u32 gpiocr; /* 0xe0030 - GPIO control register */ + u8 res3[12]; + u32 gpoutdr; /* 0xe0040 - General-purpose output data register */ + u8 res4[12]; + u32 gpindr; /* 0xe0050 - General-purpose input data register */ + u8 res5[12]; + u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + u8 res6[12]; + u32 devdisr; /* 0xe0070 - Device disable control */ +#define FSL_CORENET_DEVDISR_PCIE1 0x80000000 +#define FSL_CORENET_DEVDISR_PCIE2 0x40000000 +#define FSL_CORENET_DEVDISR_PCIE3 0x20000000 +#define FSL_CORENET_DEVDISR_RMU 0x08000000 +#define FSL_CORENET_DEVDISR_SRIO1 0x04000000 +#define FSL_CORENET_DEVDISR_SRIO2 0x02000000 +#define FSL_CORENET_DEVDISR_DMA1 0x00400000 +#define FSL_CORENET_DEVDISR_DMA2 0x00200000 +#define FSL_CORENET_DEVDISR_DDR1 0x00100000 +#define FSL_CORENET_DEVDISR_DDR2 0x00080000 +#define FSL_CORENET_DEVDISR_DBG 0x00010000 +#define FSL_CORENET_DEVDISR_NAL 0x00008000 +#define FSL_CORENET_DEVDISR_ELBC 0x00001000 +#define FSL_CORENET_DEVDISR_USB1 0x00000800 +#define FSL_CORENET_DEVDISR_USB2 0x00000400 +#define FSL_CORENET_DEVDISR_ESDHC 0x00000100 +#define FSL_CORENET_DEVDISR_GPIO 0x00000080 +#define FSL_CORENET_DEVDISR_ESPI 0x00000040 +#define FSL_CORENET_DEVDISR_I2C1 0x00000020 +#define FSL_CORENET_DEVDISR_I2C2 0x00000010 +#define FSL_CORENET_DEVDISR_DUART1 0x00000002 +#define FSL_CORENET_DEVDISR_DUART2 0x00000001 + u8 res7[12]; + u32 powmgtcsr; /* 0xe0080 - Power management status and control register */ + u8 res8[12]; + u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */ + u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */ + u8 res9[8]; + u32 pvr; /* 0xe00a0 - Processor version register */ + u32 svr; /* 0xe00a4 - System version register */ + u8 res10[8]; + u32 rstcr; /* 0xe00b0 - Reset control register */ + u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */ + u8 res11[8]; + u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */ + u8 res12[4]; /* Reserved: RSTRQMR2 */ + u32 rstrqsr1; /* 0xe00c8 - Reset request status register */ + u8 res13[4]; /* Reserved: RSTRQSR2 */ + u8 res14[4]; /* Reserved: RSTRQWDTMRU */ + u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */ + u8 res15[4]; /* Reserved: RSTRQWDTSRU */ + u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */ + u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */ + u32 brrl; /* 0xe00e4 Boot release register */ + u8 res17[24]; + u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */ +#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 +#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 +#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 +#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 + u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/ + u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */ + u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/ + u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */ + u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/ + u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */ + u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/ + u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/ + u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/ + u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/ + u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/ + u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/ + u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/ + u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/ + u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/ + u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/ + u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/ + u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/ + u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/ + u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/ + u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/ + u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/ + u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/ + u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/ + u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/ + u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/ + u8 res22[52]; /* Reserved: for future LIODN register expansion */ + u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/ + u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/ + u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/ + u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/ + u8 res23[48]; /* Reserved: for future LIODN register expansion */ + u8 res24[64]; /* Reserved */ + u32 pblsr; /* 0xe0600 Preboot loader status register*/ + u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/ + u32 dmacr1; /* 0xe0608 DMA control register*/ + u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/ + u32 gensr1; /* 0xe0610 General status register*/ + u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/ + u32 gencr1; /* 0xe0620 General control register*/ + u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/ + u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */ + u32 cgensrl; /* 0xe0634 Core general status register*/ + u8 res29[8]; /* Reserved */ + u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */ + u32 cgencrl; /* 0xe0634 Core general control register*/ + u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */ + u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/ + u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */ +} ccsr_gur_t; + +typedef struct ccsr_clk { + u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */ + u8 res1[0x1c]; + u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */ + u8 res2[0x1c]; + u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */ + u8 res3[0x1c]; + u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */ + u8 res4[0x1c]; + u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */ + u8 res5[0x1c]; + u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */ + u8 res6[0x1c]; + u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */ + u8 res7[0x1c]; + u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */ + u8 res8[0x71c]; + u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */ + u8 res10[0x1c]; + u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */ + u8 res11[0x1c]; + u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */ + u8 res12[0x1c]; + u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */ + u8 res13[0x39c]; + u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */ + u8 res14[0x1c]; + u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */ + u8 res15[0x3dc]; +} ccsr_clk_t; + +typedef struct ccsr_rcpm { + u8 res1[4]; /* 0xe2000 - Reserved */ + u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */ + u8 res2[4]; /* 0xe2008 - Reserved */ + u32 cdozcrl; /* 0xe200c - Core Doze Control Register */ + u8 res3[4]; /* 0xe2010 - Reserved */ + u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */ + u8 res4[4]; /* 0xe2018 - Reserved */ + u32 cnapcrl; /* 0xe201c - Core Nap Control Register */ + u8 res5[4]; /* 0xe2020 - Reserved */ + u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */ + u8 res6[4]; /* 0xe2028 - Reserved */ + u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */ + u8 res7[4]; /* 0xe2030 - Reserved */ + u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */ + u8 res8[8]; /* Reserved */ + u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */ + u8 res9[12]; /* Reserved */ + u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */ + u8 res10[12]; /* Reserved */ + u8 res11[4]; /* Reserved */ + u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */ + u8 res12[4]; /* Reserved */ + u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */ + u8 res13[4]; /* Reserved */ + u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */ + u8 res14[4]; /* Reserved */ + u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */ + u8 res15[4]; /* Reserved */ + u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */ + u8 res16[4]; /* Reserved */ + u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */ + u8 res17[4]; /* Reserved */ + u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */ + u8 res18[0xf68]; +} ccsr_rcpm_t; + +#else typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ #ifdef CONFIG_MPC8536 @@ -1647,42 +1871,65 @@ typedef struct ccsr_gur { uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; +#endif + +#ifdef CONFIG_FSL_CORENET +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 +#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 +#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000 +#else +#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 +#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 +#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 +#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 +#endif + +#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 -#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET) +#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) +#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) #define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) #define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) #define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) #define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) #define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) #define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) #define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_USB_ADDR \ -- cgit v1.2.3 From 418ec8584343f04048e2cc7ee96b6b29be54ad97 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:32:23 -0500 Subject: ppc/p4080: Add support for CoreNet style platform LAWs On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala --- drivers/misc/fsl_law.c | 126 ++++++++++++++++++++++++++++++++++++++++++---- include/asm-ppc/fsl_law.h | 31 ++++++++++++ 2 files changed, 146 insertions(+), 11 deletions(-) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index aa877c65f..7c59c887f 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -29,7 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define LAWAR_EN 0x80000000 /* number of LAWs in the hw implementation */ #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) @@ -46,6 +45,56 @@ DECLARE_GLOBAL_DATA_PTR; #error FSL_HW_NUM_LAWS not defined for this platform #endif +#ifdef CONFIG_FSL_CORENET +void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) +{ + volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + + gd->used_laws |= (1 << idx); + + out_be32(&ccm->law[idx].lawar, 0); + out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32)); + out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff); + out_be32(&ccm->law[idx].lawar, LAW_EN | ((u32)id << 20) | (u32)sz); + + /* Read back so that we sync the writes */ + in_be32(&ccm->law[idx].lawar); +} + +void disable_law(u8 idx) +{ + volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + + gd->used_laws &= ~(1 << idx); + + out_be32(&ccm->law[idx].lawar, 0); + out_be32(&ccm->law[idx].lawbarh, 0); + out_be32(&ccm->law[idx].lawbarl, 0); + + /* Read back so that we sync the writes */ + in_be32(&ccm->law[idx].lawar); + + return; +} + +static int get_law_entry(u8 i, struct law_entry *e) +{ + volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + u32 lawar; + + lawar = in_be32(&ccm->law[i].lawar); + + if (!(lawar & LAW_EN)) + return 0; + + e->addr = ((u64)in_be32(&ccm->law[i].lawbarh) << 32) | + in_be32(&ccm->law[i].lawbarl); + e->size = lawar & 0x3f; + e->trgt_id = (lawar >> 20) & 0xff; + + return 1; +} +#else void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); @@ -56,12 +105,49 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) out_be32(lawar, 0); out_be32(lawbar, addr >> 12); - out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); + out_be32(lawar, LAW_EN | ((u32)id << 20) | (u32)sz); /* Read back so that we sync the writes */ in_be32(lawar); } +void disable_law(u8 idx) +{ + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); + volatile u32 *lawbar = base + 8 * idx; + volatile u32 *lawar = base + 8 * idx + 2; + + gd->used_laws &= ~(1 << idx); + + out_be32(lawar, 0); + out_be32(lawbar, 0); + + /* Read back so that we sync the writes */ + in_be32(lawar); + + return; +} + +static int get_law_entry(u8 i, struct law_entry *e) +{ + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); + volatile u32 *lawbar = base + 8 * i; + volatile u32 *lawar = base + 8 * i + 2; + u32 temp; + + temp = in_be32(lawar); + + if (!(temp & LAW_EN)) + return 0; + + e->addr = (u64)in_be32(lawbar) << 12; + e->size = temp & 0x3f; + e->trgt_id = (temp >> 20) & 0xff; + + return 1; +} +#endif + int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx = ffz(gd->used_laws); @@ -94,18 +180,30 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) return idx; } -void disable_law(u8 idx) +struct law_entry find_law(phys_addr_t addr) { - volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); - volatile u32 *lawbar = base + 8 * idx; - volatile u32 *lawar = base + 8 * idx + 2; + struct law_entry entry; + int i; - gd->used_laws &= ~(1 << idx); + entry.index = -1; + entry.addr = 0; + entry.size = 0; + entry.trgt_id = 0; - out_be32(lawar, 0); - out_be32(lawbar, 0); + for (i = 0; i < FSL_HW_NUM_LAWS; i++) { + u64 upper; - return; + if (!get_law_entry(i, &entry)) + continue; + + upper = entry.addr + (2ull << entry.size); + if ((addr >= entry.addr) && (addr < upper)) { + entry.index = i; + break; + } + } + + return entry; } void print_laws(void) @@ -173,7 +271,13 @@ void init_laws(void) { int i; +#if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); +#elif FSL_HW_NUM_LAWS == 32 + gd->used_laws = 0; +#else +#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes +#endif for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index e06a1a6e0..31bb7545b 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -1,8 +1,18 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + #ifndef _FSL_LAW_H_ #define _FSL_LAW_H_ #include +#define LAW_EN 0x80000000 + #define SET_LAW_ENTRY(idx, a, sz, trgt) \ { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } @@ -36,6 +46,25 @@ enum law_size { LAW_SIZE_32G, }; +#ifdef CONFIG_FSL_CORENET +enum law_trgt_if { + LAW_TRGT_IF_PCIE_1 = 0x00, + LAW_TRGT_IF_PCIE_2 = 0x01, + LAW_TRGT_IF_PCIE_3 = 0x02, + LAW_TRGT_IF_RIO_1 = 0x08, + LAW_TRGT_IF_RIO_2 = 0x09, + + LAW_TRGT_IF_DDR_1 = 0x10, + LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ + LAW_TRGT_IF_DDR_INTRLV = 0x14, + + LAW_TRGT_IF_BMAN = 0x18, + LAW_TRGT_IF_DCSR = 0x1d, + LAW_TRGT_IF_LBC = 0x1f, + LAW_TRGT_IF_QMAN = 0x3c, +}; +#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 +#else enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, @@ -64,6 +93,7 @@ enum law_trgt_if { #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif +#endif /* CONFIG_FSL_CORENET */ struct law_entry { int index; @@ -76,6 +106,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); +extern struct law_entry find_law(phys_addr_t addr); extern void disable_law(u8 idx); extern void init_laws(void); extern void print_laws(void); -- cgit v1.2.3 From a880cf3e0e1c220d780eccd0b101170c4499485d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:44:00 -0500 Subject: ppc/p4080: CoreNet platfrom style CCSRBAR setting On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala Signed-off-by: Scott Wood --- cpu/mpc85xx/cpu_init_early.c | 72 +++++++++++++++++++++++++++++++++----------- 1 file changed, 54 insertions(+), 18 deletions(-) diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c index 7886f868f..32aa94b61 100644 --- a/cpu/mpc85xx/cpu_init_early.c +++ b/cpu/mpc85xx/cpu_init_early.c @@ -24,6 +24,51 @@ DECLARE_GLOBAL_DATA_PTR; +#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) +#ifdef CONFIG_FSL_CORENET +static void setup_ccsrbar(void) +{ + u32 temp; + volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + volatile ccsr_local_t *ccm; + + /* + * We can't call set_law() because we haven't moved + * CCSR yet. + */ + ccm = (void *)ccsr_virt; + + out_be32(&ccm->law[0].lawbarh, + (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->law[0].lawar, + LAW_EN | (0x1e << 20) | LAW_SIZE_4K); + + in_be32((u32 *)(ccsr_virt + 0)); + in_be32((u32 *)(ccsr_virt + 1)); + isync(); + + ccm = (void *)CONFIG_SYS_CCSRBAR; + /* Now use the temporary LAW to move CCSR */ + out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->ccsrar, CCSRAR_C); + temp = in_be32(&ccm->ccsrar); + disable_law(0); +} +#else +static void setup_ccsrbar(void) +{ + u32 temp; + volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); + + temp = in_be32(ccsr_virt); + out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); + temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); +} +#endif +#endif + /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { @@ -50,24 +95,15 @@ void cpu_init_early_f(void) /* set up CCSR if we want it moved */ #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) - { - u32 temp; - volatile u32 *ccsr_virt = - (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); - - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); - /* mas1 is the same as above */ - mas2 = FSL_BOOKE_MAS2((u32)ccsr_virt, MAS2_I|MAS2_G); - mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, - MAS3_SW|MAS3_SR); - mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); - - write_tlb(mas0, mas1, mas2, mas3, mas7); - - temp = in_be32(ccsr_virt); - out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); - temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); - } + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); + /* mas1 is the same as above */ + mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G); + mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR); + mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT); + + write_tlb(mas0, mas1, mas2, mas3, mas7); + + setup_ccsrbar(); #endif init_laws(); -- cgit v1.2.3 From 39a7e7fd538cdf49e7e8a2f0634ea5e15e12b4ec Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:44:39 -0500 Subject: ppc/p4080: CoreNet platfrom style secondary core release The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around. Signed-off-by: Kumar Gala --- cpu/mpc85xx/mp.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index fa65bed08..b5c6020c7 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -135,7 +136,67 @@ ulong get_spin_addr(void) return addr; } -static void pq3_mp_up(unsigned long bootpg) +#ifdef CONFIG_FSL_CORENET +static void plat_mp_up(unsigned long bootpg) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)get_spin_addr(); + volatile ccsr_gur_t *gur; + volatile ccsr_local_t *ccm; + volatile ccsr_rcpm_t *rcpm; + volatile ccsr_pic_t *pic; + int timeout = 10; + u32 nr_cpus; + struct law_entry e; + + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + + nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; + + whoami = in_be32(&pic->whoami); + cpu_up_mask = 1 << whoami; + out_be32(&ccm->bstrl, bootpg); + + e = find_law(bootpg); + out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); + + /* disable time base at the platform */ + out_be32(&rcpm->ctbenrl, cpu_up_mask); + + /* release the hounds */ + up = ((1 << nr_cpus) - 1); + out_be32(&gur->brrl, up); + + /* wait for everyone */ + while (timeout) { + int i; + for (i = 0; i < nr_cpus; i++) { + if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, up); + + /* enable time base at the platform */ + out_be32(&rcpm->ctbenrl, 0); + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); +} +#else +static void plat_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_addr(); @@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); } +#endif void cpu_mp_lmb_reserve(struct lmb *lmb) { @@ -217,7 +279,7 @@ void setup_mp(void) if (i != -1) { /* map reset page to bootpg so we can copy code there */ disable_tlb(i); - + set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ @@ -234,7 +296,7 @@ void setup_mp(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ - pq3_mp_up(bootpg); + plat_mp_up(bootpg); } else { puts("WARNING: No reset page TLB. " "Skipping secondary core setup\n"); -- cgit v1.2.3 From 7e4259bba4c56536760e42d32dacfb3233f216fd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:39:17 -0500 Subject: ppc/p4080: Add various p4080 related defines (and p4040) There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala --- cpu/mpc85xx/Makefile | 1 + cpu/mpc8xxx/cpu.c | 4 ++++ drivers/misc/fsl_law.c | 2 ++ include/asm-ppc/config.h | 6 ++++-- include/asm-ppc/processor.h | 4 ++++ 5 files changed, 15 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 3ef00e850..56de7eb38 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 00791e11b..d191263f5 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -72,6 +72,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P4040, P4040, 4), + CPU_TYPE_ENTRY(P4040, P4040_E, 4), + CPU_TYPE_ENTRY(P4080, P4080, 8), + CPU_TYPE_ENTRY(P4080, P4080_E, 8), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 7c59c887f..425eb181b 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -41,6 +41,8 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 +#elif defined(CONFIG_PPC_P4080) +#define FSL_HW_NUM_LAWS 32 #else #error FSL_HW_NUM_LAWS not defined for this platform #endif diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 5670d06a4..e35b0b77f 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -40,9 +40,11 @@ #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_P4080) +#define CONFIG_MAX_CPUS 8 #else -#define CONFIG_MAX_CPUS 1 +#define CONFIG_MAX_CPUS 1 #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 3764a5a51..d009957d8 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1031,6 +1031,10 @@ #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P4040 0x820100 +#define SVR_P4040_E 0x820900 +#define SVR_P4080 0x820000 +#define SVR_P4080_E 0x820800 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 -- cgit v1.2.3 From 3c2a67eec8a0facc865b400caca52e7f6b7adf01 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 01:52:37 -0500 Subject: ppc/p4080: Handle timebase enabling and frequency reporting On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ cpu/mpc85xx/fdt.c | 2 +- 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4c8..25c04169f 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else return (gd->bus_clk + 4UL)/8UL; +#endif } diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a8d83b1c8..53369349d 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) * initialize a bunch of registers */ +#ifdef CONFIG_FSL_CORENET +static void corenet_tb_init(void) +{ + volatile ccsr_rcpm_t *rcpm = + (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + volatile ccsr_pic_t *pic = + (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + u32 whoami = in_be32(&pic->whoami); + + /* Enable the timebase register for this core */ + out_be32(&rcpm->ctbenrl, (1 << whoami)); +} +#endif + void cpu_init_f (void) { volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -229,6 +243,9 @@ void cpu_init_f (void) #if defined(CONFIG_FSL_DMA) dma_init(); #endif +#ifdef CONFIG_FSL_CORENET + corenet_tb_init(); +#endif } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 61e0fb063..efb651882 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -294,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_add_enet_stashing(blob); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", bd->bi_busfreq / 8, 1); + "timebase-frequency", get_tbclk(), 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); get_sys_info(&sysinfo); -- cgit v1.2.3 From 39aaca1f66a0e5b1204b0789f6c0097938c00ad1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:46:19 -0500 Subject: ppc/p4080: Determine various chip frequencies on CoreNet platforms The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu.c | 45 +++++++++++++++++++++++++--- cpu/mpc85xx/speed.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/e500.h | 6 ++++ 3 files changed, 133 insertions(+), 4 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 25c04169f..0cc6e0323 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -46,11 +46,20 @@ int checkcpu (void) char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#else u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; +#endif +#else +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = 0; #else u32 ddr_ratio = 0; #endif +#endif /* CONFIG_DDR_CLK_FREQ */ int i; svr = get_svr(); @@ -111,6 +120,19 @@ int checkcpu (void) } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); +#ifdef CONFIG_FSL_CORENET + if (ddr_sync == 1) { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); + } else { + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); + } +#else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", @@ -118,22 +140,26 @@ int checkcpu (void) strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: - printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: - printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", + printf(" DDR:%-4s MHz (%s MT/s data rate) " + "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } +#endif - if (sysinfo.freqLocalBus > LCRR_CLKDIV) + if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); - else + } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); + } #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); @@ -143,6 +169,17 @@ int checkcpu (void) printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif +#ifdef CONFIG_SYS_DPAA_FMAN + for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { + printf(" FMAN%d: %s MHz\n", i, + strmhz(buf1, sysinfo.freqFMan[i])); + } +#endif + +#ifdef CONFIG_SYS_DPAA_PME + printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); +#endif + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2fdcefb21..0244b5c1b 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,6 @@ /* * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. + * * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -37,6 +38,90 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + + const u8 core_cplx_PLL[16] = { + [ 0] = 0, /* CC1 PPL / 1 */ + [ 1] = 0, /* CC1 PPL / 2 */ + [ 2] = 0, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 1, /* CC2 PPL / 2 */ + [ 6] = 1, /* CC2 PPL / 4 */ + [ 8] = 2, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_PLL_div[16] = { + [ 0] = 1, /* CC1 PPL / 1 */ + [ 1] = 2, /* CC1 PPL / 2 */ + [ 2] = 4, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 2, /* CC2 PPL / 2 */ + [ 6] = 4, /* CC2 PPL / 4 */ + [ 8] = 1, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sysInfo->freqSystemBus = sysclk; + sysInfo->freqDDRBus = sysclk; + freqCC_PLL[0] = sysclk; + freqCC_PLL[1] = sysclk; + freqCC_PLL[2] = sysclk; + freqCC_PLL[3] = sysclk; + + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; + freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; + freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; + freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; + + rcw_tmp = in_be32(&gur->rcwsr[3]); + for (i = 0; i < cpu_numcores(); i++) { + u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + + sysInfo->freqProcessor[i] = + freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; + } + +#define PME_CLK_SEL 0x80000000 +#define FM1_CLK_SEL 0x40000000 +#define FM2_CLK_SEL 0x20000000 + rcw_tmp = in_be32(&gur->rcwsr[7]); + +#ifdef CONFIG_SYS_DPAA_PME + if (rcw_tmp & PME_CLK_SEL) + sysInfo->freqPME = freqCC_PLL[2] / 2; + else + sysInfo->freqPME = sysInfo->freqSystemBus / 2; +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + if (rcw_tmp & FM1_CLK_SEL) + sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; +#if (CONFIG_SYS_NUM_FMAN) == 2 + if (rcw_tmp & FM2_CLK_SEL) + sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; +#endif +#endif + +#else uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; @@ -67,6 +152,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif +#endif #ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) diff --git a/include/e500.h b/include/e500.h index f8c82661a..e1708b9dc 100644 --- a/include/e500.h +++ b/include/e500.h @@ -15,6 +15,12 @@ typedef struct unsigned long freqDDRBus; unsigned long freqLocalBus; unsigned long freqQE; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freqFMan[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freqPME; +#endif } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ -- cgit v1.2.3