From e0198035a245378312f372573f67356521addebd Mon Sep 17 00:00:00 2001 From: Gregory Hermant Date: Thu, 10 Nov 2011 22:14:13 +0200 Subject: Increase FSMC data-phase timing for ethernet controller SRAM transfers The ethernet controller reportedly suffers data corruption of transfers from SRAM through the Flexible Smart Memory Controller on some PDK boards. Increasing the data-phase timing for the transfers fixes these problems. --- board/st/u8500/u8500.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c index cf6c73d58..70f5dc955 100644 --- a/board/st/u8500/u8500.c +++ b/board/st/u8500/u8500.c @@ -646,8 +646,11 @@ int board_late_init(void) /* setup FSMC for LAN controler */ writel(0x305b, 0x80000000); - /* the default is too slow */ - writel(0x01010110, 0x80000004); + /* + * the default is too slow + * NOTE: below this some boards corrupt data in SRAM transfers + */ + writel(0x01010210, 0x80000004); } /* enable 3V6 for GBF chip */ -- cgit v1.2.3