From bf9e3b38f77c2eac620263dd60437c6ec47a27bf Mon Sep 17 00:00:00 2001 From: wdenk Date: Thu, 12 Feb 2004 00:47:09 +0000 Subject: * Some code cleanup * Patch by Josef Baumgartner, 10 Feb 2004: Fixes for Coldfire port * Patch by Brad Kemp, 11 Feb 2004: Fix CFI flash driver problems --- board/gen860t/fpga.c | 229 ++++++++++++++++++++++-------------------------- board/gen860t/gen860t.c | 151 +++++++++++++++---------------- board/gen860t/ioport.c | 194 ++++++++++++++++++++++------------------ 3 files changed, 287 insertions(+), 287 deletions(-) (limited to 'board/gen860t') diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 2c4fbf14c..37788d539 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -72,30 +72,27 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { }; Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - { Xilinx_Virtex2, - slave_selectmap, - XILINX_XC2V3000_SIZE, - (void *)&fpga_fns, - 0 - } + {Xilinx_Virtex2, + slave_selectmap, + XILINX_XC2V3000_SIZE, + (void *) &fpga_fns, + 0} }; /* * Display FPGA revision information */ -void -print_fpga_revision(void) +void print_fpga_revision (void) { - vu_long *rev_p = (vu_long *)0x60000008; - - printf("FPGA Revision 0x%.8lx" - " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n", - *rev_p, - ((*rev_p >> 28) & 0xf), - ((*rev_p >> 20) & 0xff), - ((*rev_p >> 12) & 0xff), - ((*rev_p >> 8) & 0xf), - (*rev_p & 0xff)); + vu_long *rev_p = (vu_long *) 0x60000008; + + printf ("FPGA Revision 0x%.8lx" + " (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n", + *rev_p, + ((*rev_p >> 28) & 0xf), + ((*rev_p >> 20) & 0xff), + ((*rev_p >> 12) & 0xff), + ((*rev_p >> 8) & 0xf), (*rev_p & 0xff)); } @@ -106,10 +103,9 @@ print_fpga_revision(void) * problems with bus charging. * Return 0 on failure, 1 on success. */ -int -test_fpga_ibtr(void) +int test_fpga_ibtr (void) { - vu_long *ibtr_p = (vu_long *)0x60000010; + vu_long *ibtr_p = (vu_long *) 0x60000010; vu_long readback; vu_long compare; int i; @@ -118,40 +114,41 @@ test_fpga_ibtr(void) int pass = 1; static const ulong bitpattern[] = { - 0xdeadbeef, /* magic ID pattern for debug */ - 0x00000001, /* single bit */ - 0x00000003, /* two adjacent bits */ - 0x00000007, /* three adjacent bits */ - 0x0000000F, /* four adjacent bits */ - 0x00000005, /* two non-adjacent bits */ - 0x00000015, /* three non-adjacent bits */ - 0x00000055, /* four non-adjacent bits */ - 0xaaaaaaaa, /* alternating 1/0 */ + 0xdeadbeef, /* magic ID pattern for debug */ + 0x00000001, /* single bit */ + 0x00000003, /* two adjacent bits */ + 0x00000007, /* three adjacent bits */ + 0x0000000F, /* four adjacent bits */ + 0x00000005, /* two non-adjacent bits */ + 0x00000015, /* three non-adjacent bits */ + 0x00000055, /* four non-adjacent bits */ + 0xaaaaaaaa, /* alternating 1/0 */ }; for (i = 0; i < 1024; i++) { for (j = 0; j < 31; j++) { - for (k = 0; k < sizeof(bitpattern)/sizeof(bitpattern[0]); k++) { + for (k = 0; + k < sizeof (bitpattern) / sizeof (bitpattern[0]); + k++) { *ibtr_p = compare = (bitpattern[k] << j); readback = *ibtr_p; if (readback != ~compare) { - printf("%s:%d: FPGA test fail: expected 0x%.8lx" - " actual 0x%.8lx\n", - __FUNCTION__, __LINE__, ~compare, readback); + printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback); pass = 0; break; } } - if (!pass) break; + if (!pass) + break; } - if (!pass) break; + if (!pass) + break; } if (pass) { - printf("FPGA inverting bus test passed\n"); - print_fpga_revision(); - } - else { - printf("** FPGA inverting bus test failed\n"); + printf ("FPGA inverting bus test passed\n"); + print_fpga_revision (); + } else { + printf ("** FPGA inverting bus test failed\n"); } return pass; } @@ -160,19 +157,17 @@ test_fpga_ibtr(void) /* * Set the active-low FPGA reset signal. */ -void -fpga_reset(int assert) +void fpga_reset (int assert) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; - PRINTF("%s:%d: RESET ", __FUNCTION__, __LINE__); + PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__); if (assert) { immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF("asserted\n"); - } - else { + PRINTF ("asserted\n"); + } else { immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM); - PRINTF("deasserted\n"); + PRINTF ("deasserted\n"); } } @@ -181,54 +176,52 @@ fpga_reset(int assert) * Initialize the SelectMap interface. We assume that the mode and the * initial state of all of the port pins have already been set! */ -void -fpga_selectmap_init(void) +void fpga_selectmap_init (void) { - PRINTF("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__); - fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ + PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, + __LINE__); + fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */ } /* * Initialize the fpga. Return 1 on success, 0 on failure. */ -int -gen860t_init_fpga(void) +int gen860t_init_fpga (void) { DECLARE_GLOBAL_DATA_PTR; int i; - PRINTF("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", - __FUNCTION__, __LINE__, gd->reloc_off); - fpga_init(gd->reloc_off); - fpga_selectmap_init(); + PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); + fpga_init (gd->reloc_off); + fpga_selectmap_init (); - for(i=0; i < CONFIG_FPGA_COUNT; i++) { - PRINTF("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); - fpga_add(fpga_xilinx, &fpga[i]); + for (i = 0; i < CONFIG_FPGA_COUNT; i++) { + PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); + fpga_add (fpga_xilinx, &fpga[i]); } - return 1; + return 1; } /* * Set the FPGA's active-low SelectMap program line to the specified level */ -int -fpga_pgm_fn(int assert, int flush, int cookie) +int fpga_pgm_fn (int assert, int flush, int cookie) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; - PRINTF("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); + PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__); if (assert) { - immap->im_ioport.iop_padat &= ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF("asserted\n"); - } - else { - immap->im_ioport.iop_padat |= (0x8000 >> FPGA_PROGRAM_BIT_NUM); - PRINTF("deasserted\n"); + immap->im_ioport.iop_padat &= + ~(0x8000 >> FPGA_PROGRAM_BIT_NUM); + PRINTF ("asserted\n"); + } else { + immap->im_ioport.iop_padat |= + (0x8000 >> FPGA_PROGRAM_BIT_NUM); + PRINTF ("deasserted\n"); } return assert; } @@ -238,18 +231,16 @@ fpga_pgm_fn(int assert, int flush, int cookie) * Test the state of the active-low FPGA INIT line. Return 1 on INIT * asserted (low). */ -int -fpga_init_fn(int cookie) +int fpga_init_fn (int cookie) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; - PRINTF("%s:%d: INIT check... ", __FUNCTION__, __LINE__); - if(immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { - PRINTF("high\n"); + PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__); + if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) { + PRINTF ("high\n"); return 0; - } - else { - PRINTF("low\n"); + } else { + PRINTF ("low\n"); return 1; } } @@ -258,18 +249,16 @@ fpga_init_fn(int cookie) /* * Test the state of the active-high FPGA DONE pin */ -int -fpga_done_fn(int cookie) +int fpga_done_fn (int cookie) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *) CFG_IMMR; - PRINTF("%s:%d: DONE check... ", __FUNCTION__, __LINE__); + PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__); if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) { - PRINTF("high\n"); + PRINTF ("high\n"); return FPGA_SUCCESS; - } - else { - PRINTF("low\n"); + } else { + PRINTF ("low\n"); return FPGA_FAIL; } } @@ -278,43 +267,40 @@ fpga_done_fn(int cookie) /* * Read FPGA SelectMap data. */ -int -fpga_read_data_fn(unsigned char *data, int cookie) +int fpga_read_data_fn (unsigned char *data, int cookie) { - vu_char *p = (vu_char *)SELECTMAP_BASE; + vu_char *p = (vu_char *) SELECTMAP_BASE; *data = *p; #if 0 - PRINTF("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int)data, data); + PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data); #endif - return (int)data; + return (int) data; } /* * Write data to the FPGA SelectMap port */ -int -fpga_write_data_fn(unsigned char data, int flush, int cookie) +int fpga_write_data_fn (unsigned char data, int flush, int cookie) { - vu_char *p = (vu_char *)SELECTMAP_BASE; + vu_char *p = (vu_char *) SELECTMAP_BASE; #if 0 - PRINTF("%s: Write Data 0x%x\n", __FUNCTION__, (int)data); + PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data); #endif *p = data; - return (int)data; + return (int) data; } /* * Abort and FPGA operation */ -int -fpga_abort_fn(int cookie) +int fpga_abort_fn (int cookie) { - PRINTF("%s:%d: FPGA program sequence aborted\n", - __FUNCTION__, __LINE__); + PRINTF ("%s:%d: FPGA program sequence aborted\n", + __FUNCTION__, __LINE__); return FPGA_FAIL; } @@ -324,11 +310,10 @@ fpga_abort_fn(int cookie) * FPGA reset is asserted to keep the FPGA from starting up after * configuration. */ -int -fpga_pre_config_fn(int cookie) +int fpga_pre_config_fn (int cookie) { - PRINTF("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(TRUE); + PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); + fpga_reset (TRUE); return 0; } @@ -337,22 +322,21 @@ fpga_pre_config_fn(int cookie) * FPGA post configuration function. Blip the FPGA reset line and then see if * the FPGA appears to be running. */ -int -fpga_post_config_fn(int cookie) +int fpga_post_config_fn (int cookie) { int rc; - PRINTF("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - fpga_reset(TRUE); - udelay(1000); - fpga_reset(FALSE); + PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); + fpga_reset (TRUE); + udelay (1000); + fpga_reset (FALSE); udelay (1000); /* * Use the FPGA,s inverting bus test register to do a simple test of the * processor interface. */ - rc = test_fpga_ibtr(); + rc = test_fpga_ibtr (); return rc; } @@ -367,32 +351,27 @@ fpga_post_config_fn(int cookie) * going low during configuration, so there is no need for a separate error * function. */ -int -fpga_clk_fn(int assert_clk, int flush, int cookie) +int fpga_clk_fn (int assert_clk, int flush, int cookie) { return assert_clk; } -int -fpga_cs_fn(int assert_cs, int flush, int cookie) +int fpga_cs_fn (int assert_cs, int flush, int cookie) { return assert_cs; } -int -fpga_wr_fn(int assert_write, int flush, int cookie) +int fpga_wr_fn (int assert_write, int flush, int cookie) { return assert_write; } -int -fpga_err_fn(int cookie) +int fpga_err_fn (int cookie) { return 0; } -int -fpga_busy_fn(int cookie) +int fpga_busy_fn (int cookie) { return 0; } diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c index 434055ce6..f1d173ebc 100644 --- a/board/gen860t/gen860t.c +++ b/board/gen860t/gen860t.c @@ -94,7 +94,7 @@ const uint sdram_upm_table[] = { 0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, /* exception (offset 0x3C in upm ram) */ - }; +}; const uint selectmap_upm_table[] = { /* single read (offset 0x00 in upm ram) */ @@ -124,63 +124,61 @@ const uint selectmap_upm_table[] = { /* * Check board identity. Always successful (gives information only) */ -int -checkboard(void) +int checkboard (void) { DECLARE_GLOBAL_DATA_PTR; - unsigned char *s; - unsigned char buf[64]; - int i; + unsigned char *s; + unsigned char buf[64]; + int i; - i = getenv_r("board_id", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; + i = getenv_r ("board_id", buf, sizeof (buf)); + s = (i > 0) ? buf : NULL; if (s) { - printf("%s ", s); + printf ("%s ", s); } else { - printf(" "); + printf (" "); } - i = getenv_r("serial#", buf, sizeof(buf)); - s = (i>0) ? buf : NULL; + i = getenv_r ("serial#", buf, sizeof (buf)); + s = (i > 0) ? buf : NULL; if (s) { - printf("S/N %s\n", s); + printf ("S/N %s\n", s); } else { - printf("S/N \n"); + printf ("S/N \n"); } - printf("CPU at %s MHz, ",strmhz(buf, gd->cpu_clk)); - printf("local bus at %s MHz\n", strmhz(buf, gd->bus_clk)); - return (0); + printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk)); + printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk)); + return (0); } /* * Initialize SDRAM */ -long int -initdram(int board_type) +long int initdram (int board_type) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; - - upmconfig(UPMA, - (uint *)sdram_upm_table, - sizeof(sdram_upm_table) / sizeof(uint) - ); - - /* - * Setup MAMR register - */ - memctl->memc_mptpr = CFG_MPTPR_1BK_8K; - memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ - - /* - * Map CS1* to SDRAM bank - */ - memctl->memc_or1 = CFG_OR1; - memctl->memc_br1 = CFG_BR1; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; + + upmconfig (UPMA, + (uint *) sdram_upm_table, + sizeof (sdram_upm_table) / sizeof (uint) + ); + + /* + * Setup MAMR register + */ + memctl->memc_mptpr = CFG_MPTPR_1BK_8K; + memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ + + /* + * Map CS1* to SDRAM bank + */ + memctl->memc_or1 = CFG_OR1; + memctl->memc_br1 = CFG_BR1; /* * Perform SDRAM initialization sequence: @@ -193,31 +191,31 @@ initdram(int board_type) * Program SDRAM for standard operation, sequential burst, burst length * of 4, CAS latency of 2. */ - memctl->memc_mar = 0x00000000; + memctl->memc_mar = 0x00000000; memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF(0) | UPMA_NOP_ADDR; - udelay(200); - memctl->memc_mar = 0x00000000; + MCR_MLCF (0) | UPMA_NOP_ADDR; + udelay (200); + memctl->memc_mar = 0x00000000; memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF(4) | UPMA_PRECHARGE_ADDR; + MCR_MLCF (4) | UPMA_PRECHARGE_ADDR; - memctl->memc_mar = 0x00000000; + memctl->memc_mar = 0x00000000; memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF(2) | UPM_REFRESH_ADDR; + MCR_MLCF (2) | UPM_REFRESH_ADDR; - memctl->memc_mar = 0x00000088; + memctl->memc_mar = 0x00000088; memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF(1) | UPMA_MRS_ADDR; + MCR_MLCF (1) | UPMA_MRS_ADDR; - memctl->memc_mar = 0x00000000; + memctl->memc_mar = 0x00000000; memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 | - MCR_MLCF(0) | UPMA_NOP_ADDR; + MCR_MLCF (0) | UPMA_NOP_ADDR; /* * Enable refresh */ - memctl->memc_mamr |= MAMR_PTAE; + memctl->memc_mamr |= MAMR_PTAE; - return (SDRAM_SIZE); + return (SDRAM_SIZE); } /* @@ -225,42 +223,39 @@ initdram(int board_type) * The DOC lives in the CS2* space */ #if (CONFIG_COMMANDS & CFG_CMD_DOC) -extern void -doc_probe(ulong physadr); +extern void doc_probe (ulong physadr); -void -doc_init(void) +void doc_init (void) { - printf("Probing at 0x%.8x: ", DOC_BASE); - doc_probe(DOC_BASE); + printf ("Probing at 0x%.8x: ", DOC_BASE); + doc_probe (DOC_BASE); } #endif /* * Miscellaneous intialization */ -int -misc_init_r (void) +int misc_init_r (void) { - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile memctl8xx_t *memctl = &immr->im_memctl; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immr->im_memctl; /* * Set up UPMB to handle the Virtex FPGA SelectMap interface */ - upmconfig(UPMB, (uint *)selectmap_upm_table, - sizeof(selectmap_upm_table) / sizeof(uint)); + upmconfig (UPMB, (uint *) selectmap_upm_table, + sizeof (selectmap_upm_table) / sizeof (uint)); - memctl->memc_mbmr = 0x0; + memctl->memc_mbmr = 0x0; - config_mpc8xx_ioports(immr); + config_mpc8xx_ioports (immr); #if (CONFIG_COMMANDS & CFG_CMD_MII) - mii_init(); + mii_init (); #endif #if (CONFIG_FPGA) - gen860t_init_fpga(); + gen860t_init_fpga (); #endif return 0; } @@ -268,8 +263,7 @@ misc_init_r (void) /* * Final init hook before entering command loop. */ -int -last_stage_init(void) +int last_stage_init (void) { #if !defined(CONFIG_SC) unsigned char buf[256]; @@ -278,15 +272,15 @@ last_stage_init(void) /* * Turn the beeper volume all the way down in case this is a warm boot. */ - set_beeper_volume(-64); - init_beeper(); + set_beeper_volume (-64); + init_beeper (); /* * Read the environment to see what to do with the beeper */ - i = getenv_r("beeper", buf, sizeof(buf)); + i = getenv_r ("beeper", buf, sizeof (buf)); if (i > 0) { - do_beeper(buf); + do_beeper (buf); } #endif return 0; @@ -295,11 +289,10 @@ last_stage_init(void) /* * Stub to make POST code happy. Can't self-poweroff, so just hang. */ -void -board_poweroff(void) +void board_poweroff (void) { - puts("### Please power off the board ###\n"); - while (1); + puts ("### Please power off the board ###\n"); + while (1); } #ifdef CONFIG_POST @@ -307,9 +300,9 @@ board_poweroff(void) * Returns 1 if keys pressed to start the power-on long-running tests * Called from board_init_f(). */ -int post_hotkeys_pressed(void) +int post_hotkeys_pressed (void) { - return 0; /* No hotkeys supported */ + return 0; /* No hotkeys supported */ } #endif diff --git a/board/gen860t/ioport.c b/board/gen860t/ioport.c index 7b3ebd449..1fc95455a 100644 --- a/board/gen860t/ioport.c +++ b/board/gen860t/ioport.c @@ -199,16 +199,16 @@ const mpc8xx_iop_conf_t iop_conf_tab[NUM_PORTS][PORT_BITS] = { * Configure the MPC8XX I/O ports per the ioport configuration table * (taken from ./cpu/mpc8260/cpu_init.c) */ -void -config_mpc8xx_ioports(volatile immap_t *immr) +void config_mpc8xx_ioports (volatile immap_t * immr) { - int portnum; + int portnum; - for (portnum = 0; portnum < NUM_PORTS; portnum++) { + for (portnum = 0; portnum < NUM_PORTS; portnum++) { uint pmsk = 0, ppar = 0, psor = 0, pdir = 0; uint podr = 0, pdat = 0, pint = 0; uint msk = 1; - mpc8xx_iop_conf_t *iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][0]; + mpc8xx_iop_conf_t *iopc = + (mpc8xx_iop_conf_t *) & iop_conf_tab[portnum][0]; mpc8xx_iop_conf_t *eiopc = iopc + PORT_BITS; /* @@ -216,104 +216,132 @@ config_mpc8xx_ioports(volatile immap_t *immr) * in the configuration tables. */ if (portnum != 1) { - iopc = (mpc8xx_iop_conf_t *)&iop_conf_tab[portnum][2]; + iopc = (mpc8xx_iop_conf_t *) & + iop_conf_tab[portnum][2]; } /* * NOTE: index 0 refers to pin 17, index 17 refers to pin 0 */ while (iopc < eiopc) { - if (iopc->conf) { + if (iopc->conf) { pmsk |= msk; - if (iopc->ppar) ppar |= msk; - if (iopc->psor) psor |= msk; - if (iopc->pdir) pdir |= msk; - if (iopc->podr) podr |= msk; - if (iopc->pdat) pdat |= msk; - if (iopc->pint) pint |= msk; - } - msk <<= 1; - iopc++; + if (iopc->ppar) + ppar |= msk; + if (iopc->psor) + psor |= msk; + if (iopc->pdir) + pdir |= msk; + if (iopc->podr) + podr |= msk; + if (iopc->pdat) + pdat |= msk; + if (iopc->pint) + pint |= msk; + } + msk <<= 1; + iopc++; } - PRINTF("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, portnum); + PRINTF ("%s:%d:\n portnum=%d ", __FUNCTION__, __LINE__, + portnum); #ifdef IOPORT_DEBUG - switch(portnum) { - case 0: printf("(A)\n"); break; - case 1: printf("(B)\n"); break; - case 2: printf("(C)\n"); break; - case 3: printf("(D)\n"); break; - default: printf("(?)\n"); break; + switch (portnum) { + case 0: + printf ("(A)\n"); + break; + case 1: + printf ("(B)\n"); + break; + case 2: + printf ("(C)\n"); + break; + case 3: + printf ("(D)\n"); + break; + default: + printf ("(?)\n"); + break; } #endif - PRINTF(" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n" - " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n", - ppar, pdir, podr, pdat, psor, pint, pmsk); + PRINTF (" ppar=0x%.8x pdir=0x%.8x podr=0x%.8x\n" + " pdat=0x%.8x psor=0x%.8x pint=0x%.8x pmsk=0x%.8x\n", + ppar, pdir, podr, pdat, psor, pint, pmsk); /* * Have to handle the ioports on a port-by-port basis since there * are three different flavors. */ if (pmsk != 0) { - uint tpmsk = ~pmsk; + uint tpmsk = ~pmsk; - if (0 == portnum) { /* port A */ - immr->im_ioport.iop_papar &= tpmsk; - immr->im_ioport.iop_padat = - (immr->im_ioport.iop_padat & tpmsk) | pdat; - immr->im_ioport.iop_padir = - (immr->im_ioport.iop_padir & tpmsk) | pdir; - immr->im_ioport.iop_paodr = - (immr->im_ioport.iop_paodr & tpmsk) | podr; - immr->im_ioport.iop_papar |= ppar; - } - else if (1 == portnum) { /* port B */ - immr->im_cpm.cp_pbpar &= tpmsk; - immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & tpmsk) | pdat; - immr->im_cpm.cp_pbdir = (immr->im_cpm.cp_pbdir & tpmsk) | pdir; - immr->im_cpm.cp_pbodr = (immr->im_cpm.cp_pbodr & tpmsk) | podr; - immr->im_cpm.cp_pbpar |= ppar; - } - else if (2 == portnum) { /* port C */ - immr->im_ioport.iop_pcpar &= tpmsk; - immr->im_ioport.iop_pcdat = - (immr->im_ioport.iop_pcdat & tpmsk) | pdat; - immr->im_ioport.iop_pcdir = - (immr->im_ioport.iop_pcdir & tpmsk) | pdir; - immr->im_ioport.iop_pcint = - (immr->im_ioport.iop_pcint & tpmsk) | pint; - immr->im_ioport.iop_pcso = - (immr->im_ioport.iop_pcso & tpmsk) | psor; - immr->im_ioport.iop_pcpar |= ppar; - } - else if (3 == portnum) { /* port D */ - immr->im_ioport.iop_pdpar &= tpmsk; - immr->im_ioport.iop_pddat = - (immr->im_ioport.iop_pddat & tpmsk) | pdat; - immr->im_ioport.iop_pddir = - (immr->im_ioport.iop_pddir & tpmsk) | pdir; - immr->im_ioport.iop_pdpar |= ppar; + if (0 == portnum) { /* port A */ + immr->im_ioport.iop_papar &= tpmsk; + immr->im_ioport.iop_padat = + (immr->im_ioport. + iop_padat & tpmsk) | pdat; + immr->im_ioport.iop_padir = + (immr->im_ioport. + iop_padir & tpmsk) | pdir; + immr->im_ioport.iop_paodr = + (immr->im_ioport. + iop_paodr & tpmsk) | podr; + immr->im_ioport.iop_papar |= ppar; + } else if (1 == portnum) { /* port B */ + immr->im_cpm.cp_pbpar &= tpmsk; + immr->im_cpm.cp_pbdat = + (immr->im_cpm. + cp_pbdat & tpmsk) | pdat; + immr->im_cpm.cp_pbdir = + (immr->im_cpm. + cp_pbdir & tpmsk) | pdir; + immr->im_cpm.cp_pbodr = + (immr->im_cpm. + cp_pbodr & tpmsk) | podr; + immr->im_cpm.cp_pbpar |= ppar; + } else if (2 == portnum) { /* port C */ + immr->im_ioport.iop_pcpar &= tpmsk; + immr->im_ioport.iop_pcdat = + (immr->im_ioport. + iop_pcdat & tpmsk) | pdat; + immr->im_ioport.iop_pcdir = + (immr->im_ioport. + iop_pcdir & tpmsk) | pdir; + immr->im_ioport.iop_pcint = + (immr->im_ioport. + iop_pcint & tpmsk) | pint; + immr->im_ioport.iop_pcso = + (immr->im_ioport. + iop_pcso & tpmsk) | psor; + immr->im_ioport.iop_pcpar |= ppar; + } else if (3 == portnum) { /* port D */ + immr->im_ioport.iop_pdpar &= tpmsk; + immr->im_ioport.iop_pddat = + (immr->im_ioport. + iop_pddat & tpmsk) | pdat; + immr->im_ioport.iop_pddir = + (immr->im_ioport. + iop_pddir & tpmsk) | pdir; + immr->im_ioport.iop_pdpar |= ppar; } } - } + } - PRINTF("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x" - " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_papar, immr->im_ioport.iop_padir, - immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat); - PRINTF("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x" - " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__, - immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir, - immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat); - PRINTF("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x" - " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ", - __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar, - immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat, - immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint); - PRINTF("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x" - " pddat=0x%.4x\n", __FUNCTION__, __LINE__, - immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir, - immr->im_ioport.iop_pddat); + PRINTF ("%s:%d: Port A:\n papar=0x%.4x padir=0x%.4x" + " paodr=0x%.4x\n padat=0x%.4x\n", __FUNCTION__, __LINE__, + immr->im_ioport.iop_papar, immr->im_ioport.iop_padir, + immr->im_ioport.iop_paodr, immr->im_ioport.iop_padat); + PRINTF ("%s:%d: Port B:\n pbpar=0x%.8x pbdir=0x%.8x" + " pbodr=0x%.8x\n pbdat=0x%.8x\n", __FUNCTION__, __LINE__, + immr->im_cpm.cp_pbpar, immr->im_cpm.cp_pbdir, + immr->im_cpm.cp_pbodr, immr->im_cpm.cp_pbdat); + PRINTF ("%s:%d: Port C:\n pcpar=0x%.4x pcdir=0x%.4x" + " pcdat=0x%.4x\n pcso=0x%.4x pcint=0x%.4x\n ", + __FUNCTION__, __LINE__, immr->im_ioport.iop_pcpar, + immr->im_ioport.iop_pcdir, immr->im_ioport.iop_pcdat, + immr->im_ioport.iop_pcso, immr->im_ioport.iop_pcint); + PRINTF ("%s:%d: Port D:\n pdpar=0x%.4x pddir=0x%.4x" + " pddat=0x%.4x\n", __FUNCTION__, __LINE__, + immr->im_ioport.iop_pdpar, immr->im_ioport.iop_pddir, + immr->im_ioport.iop_pddat); } - -/* vim: set ts=4 sw=4 tw=78: */ -- cgit v1.2.3