From 511e4f9e7f7b6719e4d91d7f0fc89412b13b5150 Mon Sep 17 00:00:00 2001 From: Pieter Voorthuijsen Date: Mon, 17 Mar 2008 09:27:56 +0100 Subject: ppc4xx: Enable cache support on the ALPR board Signed-off-by: Pieter Voorthuijsen --- board/prodrive/alpr/init.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'board/prodrive') diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 135674c26..76164ce1d 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -90,7 +90,16 @@ tlbtab: tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I ) tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X ) tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X ) +#ifdef CONFIG_4xx_DCACHE + tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G) +#else tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) +#endif tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I ) /* PCI */ -- cgit v1.2.3