From 5b0055547f0246908b79cc300170d87380b69e18 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 25 Feb 2009 12:31:32 +0800 Subject: 83xx: Fix some bugs in spd sdram code 1. RD_TO_PRE missed to add the AL, and need min 2 clocks for tRTP according to DDR2 JEDEC spec. 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. 3. add the support of DDR2-533,667,800 DIMMs 4. cpo 5. make the AL to min to gain better performance. The Micron MT9HTF6472CHY-667D1 DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. items 1, 2 and 5: Acked-by: Joakim Tjernlund Reported-by: Joakim Tjernlund Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'cpu/mpc83xx') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 42a4e675d..ff15cda7a 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -319,7 +319,20 @@ long int spd_sdram() ddrc_clk = gd->mem_clk / 1000000; effective_data_rate = 0; - if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ + if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */ + if (spd.cas_lat & 0x08) + caslat = 3; + else + caslat = 4; + if (ddrc_clk <= 460 && ddrc_clk > 350) + effective_data_rate = 400; + else if (ddrc_clk <=350 && ddrc_clk > 280) + effective_data_rate = 333; + else if (ddrc_clk <= 280 && ddrc_clk > 230) + effective_data_rate = 266; + else + effective_data_rate = 200; + } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ if (ddrc_clk <= 460 && ddrc_clk > 350) { /* DDR controller clk at 350~460 */ effective_data_rate = 400; /* 5ns */ @@ -466,6 +479,8 @@ long int spd_sdram() } else { twr_clk = picos_to_clk(spd.twr * 250); twtr_clk = picos_to_clk(spd.twtr * 250); + if (twtr_clk < 2) + twtr_clk = 2; } /* @@ -529,7 +544,7 @@ long int spd_sdram() if (spd.mem_type == SPD_MEMTYPE_DDR2 && (odt_wr_cfg || odt_rd_cfg) && (caslat < 4)) { - add_lat = trcd_clk - 1; + add_lat = 4 - caslat; if ((add_lat + caslat) < 4) { add_lat = 0; } @@ -566,6 +581,9 @@ long int spd_sdram() /* Convert SPD value from quarter nanos to picos. */ trtp_clk = picos_to_clk(spd.trtp * 250); + if (trtp_clk < 2) + trtp_clk = 2; + trtp_clk += add_lat; cke_min_clk = 3; /* By the book. */ four_act = picos_to_clk(37500); /* By the book. 1k pages? */ @@ -579,7 +597,9 @@ long int spd_sdram() if (spd.mem_type == SPD_MEMTYPE_DDR2) { if (effective_data_rate == 266) { cpo = 0x4; /* READ_LAT + 1/2 */ - } else if (effective_data_rate == 333 || effective_data_rate == 400) { + } else if (effective_data_rate == 333) { + cpo = 0x6; /* READ_LAT + 1 */ + } else if (effective_data_rate == 400) { cpo = 0x7; /* READ_LAT + 5/4 */ } else { /* Automatic calibration */ -- cgit v1.2.3