From ad006f9896b3cc1d8d2b855f27bbd1ad4482abe1 Mon Sep 17 00:00:00 2001 From: Joakim Axelsson Date: Mon, 25 Oct 2010 15:45:31 +0200 Subject: db8500: Split arch_cpu code from board First patch to split cpu_arch SoC-code away from board code. Added usage of arch_cpu_init() which is the corresponding to board_init(). Moved db8500 code from board/st/u8500/u8500.c to cpu/arm_cortexa9/db8500/cpu.c. Also created include/asm/arch-db8500/cpu.h and include/asm/arch-db8500/prcmu.h. ST-Ericsson ID: None Signed-off-by: Joakim Axelsson Change-Id: I403d7d4f6c655c0d383afb3cb3be7e7df96683a3 Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/7150 Reviewed-by: Joakim AXELSSON Tested-by: Joakim AXELSSON Reviewed-by: QATOOLS Reviewed-by: Michael BRANDT Tested-by: Michael BRANDT --- cpu/arm_cortexa9/db8500/Makefile | 1 + cpu/arm_cortexa9/db8500/cpu.c | 137 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 138 insertions(+) create mode 100644 cpu/arm_cortexa9/db8500/cpu.c (limited to 'cpu') diff --git a/cpu/arm_cortexa9/db8500/Makefile b/cpu/arm_cortexa9/db8500/Makefile index 39034bb18..32be6e4fb 100644 --- a/cpu/arm_cortexa9/db8500/Makefile +++ b/cpu/arm_cortexa9/db8500/Makefile @@ -31,6 +31,7 @@ CFLAGS += -Wall -Wextra -Werror -Wno-unused-parameter # Please keep one file per line and in alphabetical order COBJS += clock.o +COBJS += cpu.o COBJS += interrupts.o COBJS += prcmu.o COBJS += timer.o diff --git a/cpu/arm_cortexa9/db8500/cpu.c b/cpu/arm_cortexa9/db8500/cpu.c new file mode 100644 index 000000000..25b4a0462 --- /dev/null +++ b/cpu/arm_cortexa9/db8500/cpu.c @@ -0,0 +1,137 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Joakim Axelsson + * for ST-Ericsson. + * + * Origin: Most part are moved here from old board code for u8500. + * + * License terms: GNU General Public License (GPL), version 2. + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_ARCH_CPU_INIT + +/* Old table to init ED version of db8500. Should be removed */ +unsigned int addr_vall_arr[] = { +0x8011F000, 0x0000FFFF, /* Clocks for HSI TODO Enable reqd only */ +0x8011F008, 0x00001CFF, /* Clocks for HSI TODO Enable reqd only */ +0x8000F000, 0x00007FFF, /* Clocks for I2C TODO Enable reqd only */ +0x8000F008, 0x00007FFF, /* Clocks for I2C TODO Enable reqd only */ +0x80157020, 0x00000150, /* I2C 48MHz clock */ +0x8012F000, 0x00007FFF, /* Clocks for SD TODO Enable reqd only */ +0x8012F008, 0x00007FFF, /* Clocks for SD TODO Enable reqd only */ +0xA03DF000, 0x0000000D, /* Clock for MTU Timers */ +0x8011E00C, 0x00000000, /* GPIO ALT FUNC for EMMC */ +0x8011E004, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ +0x8011E020, 0x0000FFE0, /* GPIO ALT FUNC for EMMC */ +0x8011E024, 0x00000000, /* GPIO ALT FUNC for EMMC */ +0x8012E000, 0x20000000, /* GPIO ALT FUNC for UART */ +0x8012E00C, 0x00000000, /* GPIO ALT FUNC for SD */ +0x8012E004, 0x0FFC0000, /* GPIO ALT FUNC for SD */ +0x8012E020, 0x60000000, /* GPIO ALT FUNC for SD */ +0x8012E024, 0x60000000, /* GPIO ALT FUNC for SD */ +0x801571E4, 0x0000000C, /* PRCMU settings for B2R2, PRCM_APE_RESETN_SET_REG */ +0x80157024, 0x00000130, /* PRCMU settings for EMMC/SD */ +0xA03FF000, 0x00000003, /* USB */ +0xA03FF008, 0x00000001, /* USB */ +0xA03FE00C, 0x00000000, /* USB */ +0xA03FE020, 0x00000FFF, /* USB */ +0xA03FE024, 0x00000000 /* USB */ +}; + +static void init_regs(void) +{ + /* FIXME Remove magic register array settings for ED also */ + if (u8500_is_earlydrop()) { + unsigned i; + + for (i = 0; i < ARRAY_SIZE(addr_vall_arr)/2; i++) + *((volatile unsigned int *)(addr_vall_arr[2 * i])) + = addr_vall_arr[(2 * i) + 1]; + } else { + struct prcmu *prcmu = (struct prcmu *) U8500_PRCMU_BASE; + + /* Enable timers */ + writel(1 << 17, &prcmu->tcr); + + u8500_prcmu_enable(&prcmu->per1clk_mgt); + u8500_prcmu_enable(&prcmu->per2clk_mgt); + u8500_prcmu_enable(&prcmu->per3clk_mgt); + u8500_prcmu_enable(&prcmu->per5clk_mgt); + u8500_prcmu_enable(&prcmu->per6clk_mgt); + u8500_prcmu_enable(&prcmu->per7clk_mgt); + + u8500_prcmu_enable(&prcmu->uartclk_mgt); + u8500_prcmu_enable(&prcmu->i2cclk_mgt); + + u8500_prcmu_enable(&prcmu->sdmmcclk_mgt); + + u8500_clock_enable(1, 9, -1); /* GPIO0 */ + + if (u8500_is_earlydrop()) + u8500_clock_enable(2, 12, -1); /* GPIO1 */ + else + u8500_clock_enable(2, 11, -1); /* GPIO1 */ + + u8500_clock_enable(3, 8, -1); /* GPIO2 */ + u8500_clock_enable(5, 1, -1); /* GPIO3 */ + + u8500_clock_enable(3, 6, 6); /* UART2 */ + + u8500_clock_enable(3, 3, 3); /* I2C0 */ + + u8500_clock_enable(1, 5, 5); /* SDI0 */ + u8500_clock_enable(2, 4, 2); /* SDI4 */ + + if (u8500_is_earlydrop()) + u8500_clock_enable(7, 2, -1); /* MTU0 */ + else if (cpu_is_u8500v1()) + u8500_clock_enable(6, 7, -1); /* MTU0 */ + else if (cpu_is_u8500v2()) + u8500_clock_enable(6, 6, -1); /* MTU0 */ + + if (!u8500_is_earlydrop()) + u8500_clock_enable(3, 4, 4); /* SDI2 */ + + /* + * Enabling clocks for all devices which are AMBA devices in the + * kernel. Otherwise they will not get probe()'d because the + * peripheral ID register will not be powered. + */ + + /* XXX: some of these differ between ED/V1 */ + + u8500_clock_enable(1, 1, 1); /* UART1 */ + u8500_clock_enable(1, 0, 0); /* UART0 */ + + u8500_clock_enable(3, 2, 2); /* SSP1 */ + u8500_clock_enable(3, 1, 1); /* SSP0 */ + + u8500_clock_enable(2, 8, -1); /* SPI0 */ + u8500_clock_enable(2, 5, 3); /* MSP2 */ + } +} + +/* + * SOC specific cpu init + */ +int arch_cpu_init(void) +{ + if (u8500_is_earlydrop()) + /* MTU timer clock always enabled (not clocked) */ + writel(0x20000, PRCM_TCR); + + icache_enable(); + init_regs(); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + -- cgit v1.2.3