From 82fd1f8da9add2d74532cf78d224485f0042d00d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:53:01 -0500 Subject: 85xx: Add support for e500mc cache stashing The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 5 +++++ cpu/mpc85xx/fdt.c | 18 ++++++++++++++++++ cpu/mpc85xx/release.S | 13 +++++++++++++ cpu/mpc85xx/start.S | 8 +++++++- 4 files changed, 43 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0041a60df..16ce82c99 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -357,6 +357,11 @@ int cpu_init_r(void) while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + mtspr(SPRN_L2CSR1, (32 + 1)); +#endif + /* enable the cache */ mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index de2dcac81..5f9aeb10b 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -197,6 +197,15 @@ static inline void ft_fixup_l2cache(void *blob) goto next; } +#ifdef CONFIG_SYS_CACHE_STASHING + { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + if (reg) + fdt_setprop_cell(blob, l2_off, "cache-stash-id", + (*reg * 2) + 32 + 1); + } +#endif + fdt_setprop(blob, l2_off, "cache-unified", NULL, 0); fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size); fdt_setprop_cell(blob, l2_off, "cache-size", size); @@ -252,6 +261,15 @@ static inline void ft_fixup_cache(void *blob) fdt_setprop_cell(blob, off, "d-cache-size", dsize); fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); +#ifdef CONFIG_SYS_CACHE_STASHING + { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + if (reg) + fdt_setprop_cell(blob, off, "cache-stash-id", + (*reg * 2) + 32 + 0); + } +#endif + /* i-side config */ isize = (l1cfg1 & 0x7ff) * 1024; inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 433ff0254..55eca7286 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -99,6 +99,13 @@ __secondary_start_page: slwi r8,r4,5 add r10,r3,r8 +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + slwi r8,r4,1 + addi r8,r8,32 + mtspr L1CSR2,r8 +#endif + #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync @@ -110,6 +117,12 @@ __secondary_start_page: and. r1,r3,r2 bne 1b +#ifdef CONFIG_SYS_CACHE_STASHING + /* set stash id to (coreID) * 2 + 32 + L2 (1) */ + addi r3,r8,1 + mtspr SPRN_L2CSR1,r3 +#endif + lis r3,CONFIG_SYS_INIT_L2CSR0@h ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l mtspr SPRN_L2CSR0,r3 diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 6a865283d..7e60e67c3 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -102,6 +102,12 @@ _start_e500: * */ +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + li r2,(32 + 0) + mtspr L1CSR2,r2 +#endif + lis r2,L1CSR0_CPE@H /* enable parity */ ori r2,r2,L1CSR0_DCE mtspr L1CSR0,r2 /* enable L1 Dcache */ -- cgit v1.2.3 From 178e39e199e9c985e5e5e968d60d7243fceb5616 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 17 Sep 2009 00:01:14 -0500 Subject: ppc/8xxx: Don't use pci_cfg on FSL_CORENET platforms The FSL_CORENET platforms use a completely different means to determine which PCIe port is enabled as well as if its a host or agent/end-point. Signed-off-by: Kumar Gala --- cpu/mpc8xxx/pci_cfg.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c index 9c7d92c4d..ea129c52a 100644 --- a/cpu/mpc8xxx/pci_cfg.c +++ b/cpu/mpc8xxx/pci_cfg.c @@ -210,10 +210,12 @@ static struct pci_info pci_config_info[] = .cfg = (1 << 2) | (1 << 4), }, }; +#elif defined(CONFIG_FSL_CORENET) #else #error Need to define pci_config_info for processor #endif +#ifndef CONFIG_FSL_CORENET int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent) { return ((1 << host_agent) & pci_config_info[trgt].agent); @@ -223,3 +225,4 @@ int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) { return ((1 << io_sel) & pci_config_info[trgt].cfg); } +#endif -- cgit v1.2.3 From bcad21fda187f7d8d5d2c026c395cca35a9c700e Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:46:28 -0500 Subject: 85xx: Add support to set DPAA (data path) devices clock frequencies Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080. Signed-off-by: Kumar Gala --- cpu/mpc85xx/fdt.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 5f9aeb10b..af0e78e07 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -297,6 +297,40 @@ void fdt_add_enet_stashing(void *fdt) do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); } +#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) +static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq) +{ + const char *path = fdt_get_alias(blob, alias); + + int off = fdt_path_offset(blob, path); + + if (off >= 0) { + off = fdt_setprop_cell(blob, off, "clock-frequency", freq); + if (off > 0) + printf("WARNING enable to set clock-frequency " + "for %s: %s\n", alias, fdt_strerror(off)); + } +} + +static void ft_fixup_dpaa_clks(void *blob) +{ + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]); + +#if (CONFIG_SYS_NUM_FMAN == 2) + ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]); +#endif + +#ifdef CONFIG_SYS_DPAA_PME + ft_fixup_clks(blob, "pme", sysinfo.freqPME); +#endif +} +#else +#define ft_fixup_dpaa_clks(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -360,4 +394,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif + + ft_fixup_dpaa_clks(blob); } -- cgit v1.2.3 From ee53650dad2fede057e93fdf6f8cd72b29ef7cd0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 4 Nov 2009 13:00:55 -0600 Subject: ppc/8xxx: Remove is_fsl_pci_agent All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala --- cpu/mpc8xxx/pci_cfg.c | 44 +++----------------------------------------- drivers/pci/fsl_pci_init.c | 9 +++++++++ include/asm-ppc/fsl_pci.h | 5 +++-- 3 files changed, 15 insertions(+), 43 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c index ea129c52a..d53781b62 100644 --- a/cpu/mpc8xxx/pci_cfg.c +++ b/cpu/mpc8xxx/pci_cfg.c @@ -25,19 +25,14 @@ #include struct pci_info { - u16 agent; u16 cfg; }; -/* The agent field is a bit mask in which each bit represents the value of - * cfg_host_agt[] signal and the bit is set of the given interface would be - * in agent/end-point mode for the given interface. - * - * The same idea is true of the cfg field. The bit will be set if the - * interface would be enabled based on the value of cfg_IO_ports[] signal +/* The cfg field is a bit mask in which each bit represents the value of + * cfg_IO_ports[] signal and the bit is set if the interface would be + * enabled based on the value of cfg_IO_ports[] signal * * On MPC86xx/PQ3 based systems: - * we extract cfg_host_agt from GUTS register PORBMSR * we extract cfg_IO_ports from GUTS register PORDEVSR * * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems @@ -48,7 +43,6 @@ struct pci_info { static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 0) | (1 << 2), .cfg = 0, }, }; @@ -56,7 +50,6 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 0), .cfg = 0, }, }; @@ -64,19 +57,15 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 5), .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 3), .cfg = (1 << 5) | (1 << 7), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 1), .cfg = (1 << 7), }, }; @@ -84,20 +73,16 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 5), .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 3), .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 1), .cfg = (1 << 6) | (1 << 7), }, }; @@ -105,16 +90,13 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI_1] = { - .agent = (1 << 4) | (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCI_2] = { - .agent = (1 << 4) | (1 << 6), .cfg = 0, }, /* PCI_2 is always host and we dont use iosel to determine enable/disable */ [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 2), .cfg = (1 << 3) | (1 << 4) | (1 << 7), }, }; @@ -122,11 +104,9 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI] = { - .agent = (1 << 0) | (1 << 4) | (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 2) | (1 << 4), .cfg = (1 << 3) | (1 << 4) | (1 << 7), }, }; @@ -134,7 +114,6 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 6), .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 0xc) | (1 << 0xf), }, @@ -143,16 +122,13 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), .cfg = (1 << 2) | (1 << 3) | (1 << 7) | (1 << 0xb) | (1 << 0xc) | (1 << 0xf), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), .cfg = (1 << 3) | (1 << 7), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), .cfg = (1 << 7), }, }; @@ -160,15 +136,12 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCI_1] = { - .agent = (1 << 4) | (1 << 5) | (1 << 6), .cfg = 0, }, [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 2) | (1 << 5), .cfg = (1 << 1) | (1 << 4), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 1) | (1 << 4), .cfg = (1 << 0) | (1 << 4), }, }; @@ -176,7 +149,6 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = 0, /* we dont use agent on 8641 */ .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 0xe) | (1 << 0xf), }, @@ -185,11 +157,9 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 1), .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 2), .cfg = (1 << 0xe), }, }; @@ -197,16 +167,13 @@ static struct pci_info pci_config_info[] = static struct pci_info pci_config_info[] = { [LAW_TRGT_IF_PCIE_1] = { - .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | (1 << 0xd) | (1 << 0xe) | (1 << 0xf), }, [LAW_TRGT_IF_PCIE_2] = { - .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), .cfg = (1 << 2) | (1 << 0xe), }, [LAW_TRGT_IF_PCIE_3] = { - .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), .cfg = (1 << 2) | (1 << 4), }, }; @@ -216,11 +183,6 @@ static struct pci_info pci_config_info[] = #endif #ifndef CONFIG_FSL_CORENET -int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent) -{ - return ((1 << host_agent) & pci_config_info[trgt].agent); -} - int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) { return ((1 << io_sel) & pci_config_info[trgt].cfg); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 170cc257c..fe57926d7 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -86,6 +86,15 @@ static void set_inbound_window(volatile pit_t *pi, out_be32(&pi->piwar, flag | sz); } +int fsl_setup_hose(struct pci_controller *hose, unsigned long addr) +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr; + + pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + + return fsl_is_pci_agent(hose); +} + static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, u64 out_lo, u8 pcie_cap, volatile pit_t *pi) diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index a5f72f5cd..db61e7e9c 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -1,4 +1,5 @@ -/* (C) Copyright 2007 Freescale Semiconductor, Inc. +/* + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,9 +23,9 @@ #include -int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent); int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); +int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); -- cgit v1.2.3 From 94e9411b9dda182dd63d53ba6ea640c98b35db5f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 12 Nov 2009 10:26:16 -0600 Subject: ppc/85xx: Add tracking of TLB CAM usage We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala --- cpu/mpc85xx/cpu_init.c | 1 + cpu/mpc85xx/tlb.c | 64 +++++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/config.h | 7 +++++ include/asm-ppc/global_data.h | 3 ++ include/asm-ppc/mmu.h | 2 ++ 5 files changed, 77 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 16ce82c99..e0126d331 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -246,6 +246,7 @@ void cpu_init_f (void) #ifdef CONFIG_FSL_CORENET corenet_tb_init(); #endif + init_used_tlb_cams(); } diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index ea5deb297..234fdaa60 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -56,12 +56,74 @@ void init_tlbs(void) } #ifndef CONFIG_NAND_SPL +static inline void use_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->used_tlb_cams[i] |= (1 << bit); +} + +static inline void free_tlb_cam(u8 idx) +{ + int i = idx / 32; + int bit = idx % 32; + + gd->used_tlb_cams[i] &= ~(1 << bit); +} + +void init_used_tlb_cams(void) +{ + int i; + unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) + gd->used_tlb_cams[i] = 0; + + /* walk all the entries */ + for (i = 0; i < num_cam; i++) { + u32 _mas1; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); + + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + /* if the entry isn't valid skip it */ + if ((_mas1 & MAS1_VALID)) + use_tlb_cam(i); + } +} + +int find_free_tlbcam(void) +{ + int i; + u32 idx; + + for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) { + idx = ffz(gd->used_tlb_cams[i]); + + if (idx != 32) + break; + } + + idx += i * 32; + + if (idx >= CONFIG_SYS_NUM_TLBCAMS) + return -1; + + return idx; +} + void set_tlb(u8 tlb, u32 epn, u64 rpn, u8 perms, u8 wimge, u8 ts, u8 esel, u8 tsize, u8 iprot) { u32 _mas0, _mas1, _mas2, _mas3, _mas7; + if (tlb == 1) + use_tlb_cam(esel); + _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0); _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize); _mas2 = FSL_BOOKE_MAS2(epn, wimge); @@ -80,6 +142,8 @@ void disable_tlb(u8 esel) { u32 _mas0, _mas1, _mas2, _mas3, _mas7; + free_tlb_cam(esel); + _mas0 = FSL_BOOKE_MAS0(1, esel, 0); _mas1 = 0; _mas2 = 0; diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index d5f82b44f..796707eaf 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -63,6 +63,13 @@ #define CONFIG_TSECV2 #endif +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500MC) +#define CONFIG_SYS_NUM_TLBCAMS 64 +#elif defined(CONFIG_E500) +#define CONFIG_SYS_NUM_TLBCAMS 16 +#endif + /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 55e7e2066..3f1191874 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { #if defined(CONFIG_FSL_LAW) u32 used_laws; #endif +#if defined(CONFIG_E500) + u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; +#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index ec22a5058..fd1024947 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -479,6 +479,8 @@ extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); extern int find_tlb_idx(void *addr, u8 tlbsel); +extern void init_used_tlb_cams(void); +extern int find_free_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); -- cgit v1.2.3 From 355f4f85e90ce2e6d91883012c2993be7970c8b1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 13 Nov 2009 09:04:19 -0600 Subject: ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala --- cpu/mpc85xx/tlb.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 234fdaa60..b3037acea 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -227,14 +227,10 @@ void init_addr_map(void) } #endif -#ifndef CONFIG_SYS_DDR_TLB_START -#define CONFIG_SYS_DDR_TLB_START 8 -#endif - unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) { + int i; unsigned int tlb_size; - unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20; @@ -244,10 +240,14 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg) /* Convert (4^max) kB to (2^max) bytes */ max_cam = max_cam * 2 + 10; - for (; size && ram_tlb_index < 16; ram_tlb_index++) { + for (i = 0; size && i < 8; i++) { + int ram_tlb_index = find_free_tlbcam(); u32 camsize = __ilog2_u64(size) & ~1U; u32 align = __ilog2(ram_tlb_address) & ~1U; + if (ram_tlb_index == -1) + break; + if (align == -2) align = max_cam; if (camsize > align) camsize = align; -- cgit v1.2.3 From f5ecc6e027150289c2a46db7cec197b2b6da893c Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 17 Nov 2009 20:01:24 -0600 Subject: p4080: add readback to bootpage translation window We need to add the readback to bootpage translation LAW to make it effect. Signed-off-by: Dave Liu Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala --- cpu/mpc85xx/mp.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 7626eb8e7..8568f5dba 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -165,6 +165,9 @@ static void plat_mp_up(unsigned long bootpg) e = find_law(bootpg); out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); + /* readback to sync write */ + in_be32(&ccm->bstrar); + /* disable time base at the platform */ out_be32(&rcpm->ctbenrl, cpu_up_mask); -- cgit v1.2.3 From abc76eb6a6936a99811eda256222b3927427f8e2 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 17 Nov 2009 20:21:20 -0600 Subject: ppc/85xx: Map boot page guarded for MP boot We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala --- board/freescale/mpc8572ds/tlb.c | 2 +- board/freescale/p1_p2_rdb/tlb.c | 2 +- board/freescale/p2020ds/tlb.c | 2 +- cpu/mpc85xx/mp.c | 2 +- cpu/mpc85xx/release.S | 4 ++-- 5 files changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c index d832f8974..6a2a0b57f 100644 --- a/board/freescale/mpc8572ds/tlb.c +++ b/board/freescale/mpc8572ds/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 0009913ea..93d0bf7bc 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -44,7 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c index b2e562aeb..36ad086d0 100644 --- a/board/freescale/p2020ds/tlb.c +++ b/board/freescale/p2020ds/tlb.c @@ -47,7 +47,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 1), /* *I*G* - CCSRBAR */ diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 8568f5dba..6530cb176 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -312,7 +312,7 @@ void setup_mp(void) disable_tlb(i); set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 55eca7286..00c4c547f 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -166,8 +166,8 @@ __secondary_start_page: lis r11,(MAS1_VALID|MAS1_IPROT)@h ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr SPRN_MAS1,r11 - oris r11,r13,(MAS2_I)@h - ori r11,r13,(MAS2_I)@l + oris r11,r13,(MAS2_I|MAS2_G)@h + ori r11,r13,(MAS2_I|MAS2_G)@l mtspr SPRN_MAS2,r11 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l -- cgit v1.2.3 From bc20f9a9527afe8ae406a74f74765d4323f04922 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 9 Dec 2009 17:28:17 -0600 Subject: ppc/p4080: Fix reporting of PME & FM clock frequencies We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL backwards so we report the wrong frequency. Signed-off-by: Kumar Gala --- cpu/mpc85xx/speed.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 795908240..2103e2edf 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo) #ifdef CONFIG_SYS_DPAA_PME if (rcw_tmp & PME_CLK_SEL) - sysInfo->freqPME = freqCC_PLL[2] / 2; - else sysInfo->freqPME = sysInfo->freqSystemBus / 2; + else + sysInfo->freqPME = freqCC_PLL[2] / 2; #endif #ifdef CONFIG_SYS_DPAA_FMAN if (rcw_tmp & FM1_CLK_SEL) - sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; - else sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; + else + sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; #if (CONFIG_SYS_NUM_FMAN) == 2 if (rcw_tmp & FM2_CLK_SEL) - sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; - else sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; + else + sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; #endif #endif -- cgit v1.2.3 From 0a71c92c7e1e565111cb34cd389a21ec500ca5c1 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 16 Dec 2009 10:24:36 -0600 Subject: fsl-ddr: Fix power-down timing settings 1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc8xxx/ddr/ctrl_regs.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 250504145..a92f1a330 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -188,12 +188,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr) * The DDR3 spec has not tXARD, * we use the tXP instead of it. * tXP=max(3nCK, 7.5ns) for DDR3. - * we use the tXP=6 * spec has not the tAXPD, we use * tAXPD=8, need design to confirm. */ - act_pd_exit_mclk = 6; - pre_pd_exit_mclk = 6; + int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + act_pd_exit_mclk = picos_to_mclk(tXP); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 8; tmrd_mclk = 4; #else /* CONFIG_FSL_DDR2 */ -- cgit v1.2.3 From bdc9f7b5eab8d5edd8a8cc5d80ef080836b00e85 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 16 Dec 2009 10:24:37 -0600 Subject: fsl-ddr: add the override for write leveling add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++++++++++++++------ cpu/mpc8xxx/ddr/options.c | 1 + include/asm-ppc/fsl_ddr_sdram.h | 7 ++++++- 3 files changed, 21 insertions(+), 7 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index a92f1a330..5e37ca6b8 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1002,8 +1002,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) } /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, - unsigned int wrlvl_en) +static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, + const memctl_options_t *popts) { /* * First DQS pulse rising edge after margining mode @@ -1030,8 +1030,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, /* tWL_DQSEN min = 25 nCK, we set it 32 */ wrlvl_dqsen = 0x5; /* - * Write leveling sample time at least need 14 clocks - * due to tWLO = 9, we set it 15 clocks + * Write leveling sample time at least need 6 clocks + * higher than tWLO to allow enough time for progagation + * delay and sampling the prime data bits. */ wrlvl_smpl = 0xf; /* @@ -1044,9 +1045,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, * Write leveling start time * The value use for the DQS_ADJUST for the first sample * when write leveling is enabled. - * we set it 1 clock delay */ wrlvl_start = 0x8; + /* + * Override the write leveling sample and start time + * according to specific board + */ + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; + } } ddr->ddr_wrlvl_cntl = (0 @@ -1332,7 +1340,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_5(ddr); set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en); + set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); set_ddr_sr_cntr(ddr, sr_it); diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 2e030c11a..3dcd33ddf 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; + popts->wrlvl_override = 0; #endif /* diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 69b857b41..15ab675dc 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -177,6 +177,11 @@ typedef struct memctl_options_s { unsigned int clk_adjust; /* */ unsigned int cpo_override; unsigned int write_data_delay; /* DQS adjust */ + + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int half_strength_driver_enable; unsigned int twoT_en; unsigned int threeT_en; -- cgit v1.2.3 From 1aa3d08a0244506b94031522e54fe06ee7a5ae0e Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 16 Dec 2009 10:24:38 -0600 Subject: fsl-ddr: add override for the Rtt_Wr Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc8xxx/ddr/ctrl_regs.c | 10 +++++++--- include/asm-ppc/fsl_ddr_sdram.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 5e37ca6b8..3be7e2271 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -576,18 +576,22 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr) +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ #if defined(CONFIG_FSL_DDR3) - unsigned int rtt_wr = 2; /* 120 ohm Rtt_WR */ + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ unsigned int cwl = compute_cas_write_latency() - 5; unsigned int pasr = 0; /* partial array self refresh disable */ + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + esdmode2 = (0 | ((rtt_wr & 0x3) << 9) | ((srt & 0x1) << 7) @@ -1330,7 +1334,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_cfg_2(ddr, popts); set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency); - set_ddr_sdram_mode_2(ddr); + set_ddr_sdram_mode_2(ddr, popts); set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 15ab675dc..3216a5063 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -192,6 +192,7 @@ typedef struct memctl_options_s { /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ /* Automatic self refresh */ unsigned int auto_self_refresh_en; -- cgit v1.2.3 From 3e731aaba30c7011edf6391072eee845ed1b816f Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 16 Dec 2009 10:24:39 -0600 Subject: fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave In chip-select interleaving case, we also need set the ODT_RD_CFG and ODT_WR_CFG in cs1_config register. Signed-off-by: Dave Liu Signed-off-by: Kumar Gala --- cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 3be7e2271..adc4f6ee3 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1197,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, /* Don't set up boundaries for other CS * other than CS0, if bank interleaving * is enabled and not CS2+CS3 interleaved. + * But we need to set the ODT_RD_CFG and + * ODT_WR_CFG for CS1_CONFIG here. */ + set_csn_config(i, ddr, popts, dimm_params); break; } -- cgit v1.2.3 From 7693640acd5222f5a64e59ccf5e3bc511e8054b9 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 8 Dec 2009 09:10:04 +0100 Subject: mpc83xx: spd_sdram.c: Disable memory controller before initializing The memory controller could already be enabled, when spd_sdram() is called. This could be the case for example, when the SDRAM is initialized by the JTAG debugger. The "sync" after the register access via the accessor function is still needed, because the macro uses the sync before the real write is done. So until not all accesses are converted to using accessor functions, this sync still needs to be made "manually" here. Signed-off-by: Stefan Roese Cc: Reinhard Arlt Acked-by: Dave Liu Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 0f611804a..44aaa9abc 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -150,6 +151,14 @@ long int spd_sdram() unsigned int ddrc_ecc_enable; unsigned int pvr = get_pvr(); + /* + * First disable the memory controller (could be enabled + * by the debugger) + */ + clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0); + sync(); + isync(); + /* Read SPD parameters with I2C */ CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); #ifdef SPD_DEBUG -- cgit v1.2.3 From a3f5da1bee9a8c343a411080d7d468bdc78794a4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 7 Jan 2010 08:56:00 +0100 Subject: mpc83xx: add support configure bus parking Add support to configure bus parking mode and master in bus arbitration configuration (ACR). Add this for the kmeter1 port: Configure bus arbiter with recommended values from Freescale to improve bus latency/throughput for application with intensive QuiccEngine activity. Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu_init.c | 12 ++++++++++++ include/configs/kmeter1.h | 8 ++++++++ 2 files changed, 20 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 0d6a5fec9..75b45222b 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -69,6 +69,12 @@ void cpu_init_f (volatile immap_t * im) #endif #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ (ACR_RPTCNT << ACR_RPTCNT_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ + (ACR_APARK << ACR_APARK_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ + (ACR_PARKM << ACR_PARKM_SHIFT) | #endif 0; __be32 acr_val = @@ -77,6 +83,12 @@ void cpu_init_f (volatile immap_t * im) #endif #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ + (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) | +#endif +#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ + (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) | #endif 0; __be32 spcr_mask = diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index bec08dab1..b02332650 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -71,6 +71,14 @@ */ #define CONFIG_SYS_IMMR 0xE0000000 +/* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + /* * DDR Setup */ -- cgit v1.2.3