From d414aae552bc229dafcad92028effb4a8306c7a5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 9 Nov 2009 09:29:34 -0500 Subject: OMAP3: Fix SDRC init Defaults are for Infineon DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits Signed-off-by: Nishanth Menon --- cpu/arm_cortexa8/omap3/mem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'cpu') diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 2c2d4f7b4..dfb7e4c2a 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early) writel(SDRC_SHARING, &sdrc_base->sharing); /* Disable Power Down of CKE cuz of 1 CKE on combo part */ - writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power); + writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH, + &sdrc_base->power); writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); -- cgit v1.2.3