From f4f7f7d70bc982d6689f09bf97e62caec223629f Mon Sep 17 00:00:00 2001 From: Michael Brandt Date: Fri, 19 Feb 2010 10:15:10 +0100 Subject: HREF V1 updates This patch is part of WP254081 which depends on WP252006. * Fixed I2C, use real timeouts instead of counter * Undefined CONFIG_BOOTTIME, since it as to be changed to new timer.c * Merged V1 patches from Bangalore The patches were merged manually, because of the differences of the U-Boot baseline (Bangalore U-Boot 1.3.1, Lund 2009.11). The original patches were created by Rabin Vincent . and were applied originally to Branches: blr_lsp, remotes/origin/blr_lsp Follows: qpppaaa_20100210_094651 0001-u8500-gpio-add-I2C0-altfun.patch 0002-u8500-use-correct-v1-macros.patch 0003-emmc-clean-up-paritioning.patch 0004-u8500-remove-incorrect-ram-settings.patch 0005-u8500-gpio-remove-unnecessary-ifdefs.patch 0006-u8500-add-ED-v1-detection-and-handle-eMMC-diff.patch 0008-u8500-mmc-don-t-disable-altfuns.patch 0009-u8500-gpio-remove-unused-defined.patch 0010-u8500-mmc-add-barrier-for-while-loop.patch 0011-u8500-mmc-handle-non-block-addressed-cards.patch 0012-u8500-mmc-remove-unused-gpio-settings-on-v1.patch 0013-u8500-emmc-build-fix.patch 0014-u8500-handle-v1-gpios-and-clocks.patch 0015-mmc-build-fix-for-block-addressing.patch 0016-u8500-add-clocks-and-hardware-files.patch 0017-u8500-enable-PRCUM-timers-reg-for-ED.patch 0018-u8500-handle-MTU-for-v1-ED.patch 0019-u8500-emmc-remove-unnecessary-GPIO-settings.patch 0020-u8500-remove-dead-code.patch 0021-u8500-add-working-MTU-timer.patch 0022-pl011-empty-rx-fifo-if-necessary.patch 0023-u8500-gpio-fix-cont-handling-in-altfunc.patch 0024-u8500-reduce-bootdelay-to-1-and-enable-zero-check.patch 0025-u8500-disable-forcing-of-verify-but-set-n-by-default.patch 0029-u8500-fix-some-gpio-settings.patch 0030-emmc-make-v1-paritioning-differences-explicit.patch Signed-off-by: Michael Brandt Change-Id: I1106702e393c34f630e71f071e06c3952b0d3a1a Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/182 Reviewed-by: Michael BRANDT Tested-by: Jonas ABERG Reviewed-by: Jonas ABERG --- cpu/arm_cortexa9/stw8500/timer.c | 92 ++++++++++++++++++++++------------------ 1 file changed, 50 insertions(+), 42 deletions(-) mode change 100755 => 100644 cpu/arm_cortexa9/stw8500/timer.c (limited to 'cpu') diff --git a/cpu/arm_cortexa9/stw8500/timer.c b/cpu/arm_cortexa9/stw8500/timer.c old mode 100755 new mode 100644 index f0d015c04..1760a6472 --- a/cpu/arm_cortexa9/stw8500/timer.c +++ b/cpu/arm_cortexa9/stw8500/timer.c @@ -22,58 +22,75 @@ #include #include -#include -#include +#include /* - * The timer is a decrementer, we'll left it free running at 2.4MHz. - * We have 2.4 ticks per microsecond and an overflow in almost 30min - * - * EABEJON: On HREF (atleast) there is no way the timer runs at 2.4MHz - * It is more likely that it around ~100 MHz with 1 as perscaler. - * Changing the perscaler setting to 16 gives a timer decrease rate of - * ~6.25MHz. - * - * Use the 3rd counter on MTU0 and let it run free since we're interested - * in how long time it takes to boot uboot+linux. Linux ux500 uses MTU0, - * timer0 and MTU1, timer0. - * + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. */ -#if 0 -#define TIMER_CLOCK (24 * 100 * 1000) -#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */ -#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */ -#endif - -#define TIMER_CLOCK (625 * 10 * 1000) -#define COUNT_TO_USEC(x) ((x) * 4 / 25) -#define USEC_TO_COUNT(x) ((x) * 25 / 4) - +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +#define TIMER_CLOCK (110 * 1000 * 1000) +#define COUNT_TO_USEC(x) ((x) / 110) +#define USEC_TO_COUNT(x) ((x) * 110) #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -/* Timer on MTU0 (from 0 to 3) */ -#define MTU_TIMER 2 - +static unsigned int timerbase; /* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(MTU_TIMER))) +#define READ_TIMER() (~readl(timerbase + MTU_VAL(0))) -/* Configure a free-running, auto-wrap counter with division by 16 as prescaler */ +/* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) { - writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_16 | MTU_CRn_32BITS, - CONFIG_SYS_TIMERBASE + MTU_CR(MTU_TIMER)); + timerbase = u8500_is_earlydrop() ? U8500_MTU0_BASE_ED + : U8500_MTU0_BASE_V1; + + writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, + timerbase + MTU_CR(0)); reset_timer(); - boottime_tag("uboot_init"); return 0; } /* Restart counting from 0 */ void reset_timer(void) { - writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(MTU_TIMER)); /* Immediate effect */ + writel(0, timerbase + MTU_LR(0)); /* Immediate effect */ } /* Return how many HZ passed since "base" */ @@ -82,14 +99,6 @@ ulong get_timer(ulong base) return TICKS_TO_HZ(READ_TIMER()) - base; } - -/* Return how many HZ passed since "base" */ -ulong get_raw_timer(void) -{ - return READ_TIMER(); -} - - /* Delay x useconds */ void udelay(unsigned long usec) { @@ -99,5 +108,4 @@ void udelay(unsigned long usec) end = ini + USEC_TO_COUNT(usec); while ((signed)(end - READ_TIMER()) > 0) ; - boottime_idle_add(USEC_TO_COUNT(usec)); } -- cgit v1.2.3