From 492fb1fdbcdd5e21be0b6742c15f76c648f0653b Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Tue, 3 Nov 2009 18:08:41 +0900 Subject: Move s3c24x0 header files to asm-arm/arch-s3c24x0/ This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- drivers/serial/serial_s3c24x0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/serial') diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index c2c72e456..914d07cda 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -20,9 +20,9 @@ #include #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif DECLARE_GLOBAL_DATA_PTR; -- cgit v1.2.3 From 47e801bec360e69e4b087a141d015b318e1b0212 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Wed, 4 Nov 2009 16:07:59 +0900 Subject: s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xx This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang --- board/samsung/smdk6400/lowlevel_init.S | 2 +- board/samsung/smdk6400/smdk6400.c | 2 +- cpu/arm1176/cpu.c | 2 +- cpu/arm1176/s3c64xx/cpu_init.S | 2 +- cpu/arm1176/s3c64xx/reset.S | 2 +- cpu/arm1176/s3c64xx/speed.c | 2 +- cpu/arm1176/s3c64xx/timer.c | 2 +- cpu/arm1176/start.S | 2 +- drivers/mtd/nand/s3c64xx.c | 2 +- drivers/serial/s3c64xx.c | 2 +- drivers/usb/host/s3c64xx-hcd.c | 2 +- include/asm-arm/arch-s3c64xx/s3c6400.h | 895 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-s3c64xx/s3c64x0.h | 90 ++++ include/s3c6400.h | 895 --------------------------------- include/s3c64x0.h | 90 ---- 15 files changed, 996 insertions(+), 996 deletions(-) create mode 100644 include/asm-arm/arch-s3c64xx/s3c6400.h create mode 100644 include/asm-arm/arch-s3c64xx/s3c64x0.h delete mode 100644 include/s3c6400.h delete mode 100644 include/s3c64x0.h (limited to 'drivers/serial') diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 47f72f613..30d88780d 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -34,7 +34,7 @@ #include #include -#include +#include #ifdef CONFIG_SERIAL1 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index 561c0c831..78aaa9e13 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -30,7 +30,7 @@ #include #include -#include +#include /* ------------------------------------------------------------------------- */ #define CS8900_Tacs 0x0 /* 0clk address set-up */ diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index d1a332748..2c0014f2b 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include static void cache_flush (void); diff --git a/cpu/arm1176/s3c64xx/cpu_init.S b/cpu/arm1176/s3c64xx/cpu_init.S index 32bb467f2..df88cba34 100644 --- a/cpu/arm1176/s3c64xx/cpu_init.S +++ b/cpu/arm1176/s3c64xx/cpu_init.S @@ -24,7 +24,7 @@ */ #include -#include +#include .globl mem_ctrl_asm_init mem_ctrl_asm_init: diff --git a/cpu/arm1176/s3c64xx/reset.S b/cpu/arm1176/s3c64xx/reset.S index 315b13f8d..eae572e4f 100644 --- a/cpu/arm1176/s3c64xx/reset.S +++ b/cpu/arm1176/s3c64xx/reset.S @@ -21,7 +21,7 @@ * MA 02111-1307 USA */ -#include +#include .globl reset_cpu reset_cpu: diff --git a/cpu/arm1176/s3c64xx/speed.c b/cpu/arm1176/s3c64xx/speed.c index 5c335a55a..11962acad 100644 --- a/cpu/arm1176/s3c64xx/speed.c +++ b/cpu/arm1176/s3c64xx/speed.c @@ -31,7 +31,7 @@ */ #include -#include +#include #define APLL 0 #define MPLL 1 diff --git a/cpu/arm1176/s3c64xx/timer.c b/cpu/arm1176/s3c64xx/timer.c index 22a5b7770..85ce9cd99 100644 --- a/cpu/arm1176/s3c64xx/timer.c +++ b/cpu/arm1176/s3c64xx/timer.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include static ulong timer_load_val; diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index cb891df17..2bb9bf208 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -35,7 +35,7 @@ #ifdef CONFIG_ENABLE_MMU #include #endif -#include +#include #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index edaf55a14..084e47564 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/serial/s3c64xx.c b/drivers/serial/s3c64xx.c index 1b974e04f..6d22df7cf 100644 --- a/drivers/serial/s3c64xx.c +++ b/drivers/serial/s3c64xx.c @@ -23,7 +23,7 @@ #include -#include +#include #ifdef CONFIG_SERIAL1 #define UART_NR S3C64XX_UART0 diff --git a/drivers/usb/host/s3c64xx-hcd.c b/drivers/usb/host/s3c64xx-hcd.c index 274a4ed30..cd295dabb 100644 --- a/drivers/usb/host/s3c64xx-hcd.c +++ b/drivers/usb/host/s3c64xx-hcd.c @@ -25,7 +25,7 @@ */ #include -#include +#include int usb_cpu_init(void) { diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h new file mode 100644 index 000000000..e527c08b1 --- /dev/null +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h @@ -0,0 +1,895 @@ +/* + * (C) Copyright 2007 + * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. + * - only support for S3C6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c6400.h + * + * Based on S3C6400 User's manual Rev 0.0 + ************************************************/ + +#ifndef __S3C6400_H__ +#define __S3C6400_H__ + +#define S3C64XX_UART_CHANNELS 3 +#define S3C64XX_SPI_CHANNELS 2 + +#include + +#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 + +/* Clock & Power Controller for mDirac3*/ +#define APLL_LOCK_OFFSET 0x00 +#define MPLL_LOCK_OFFSET 0x04 +#define EPLL_LOCK_OFFSET 0x08 +#define APLL_CON_OFFSET 0x0C +#define MPLL_CON_OFFSET 0x10 +#define EPLL_CON0_OFFSET 0x14 +#define EPLL_CON1_OFFSET 0x18 +#define CLK_SRC_OFFSET 0x1C +#define CLK_DIV0_OFFSET 0x20 +#define CLK_DIV1_OFFSET 0x24 +#define CLK_DIV2_OFFSET 0x28 +#define CLK_OUT_OFFSET 0x2C +#define HCLK_GATE_OFFSET 0x30 +#define PCLK_GATE_OFFSET 0x34 +#define SCLK_GATE_OFFSET 0x38 +#define AHB_CON0_OFFSET 0x100 +#define AHB_CON1_OFFSET 0x104 +#define AHB_CON2_OFFSET 0x108 +#define SELECT_DMA_OFFSET 0x110 +#define SW_RST_OFFSET 0x114 +#define SYS_ID_OFFSET 0x118 +#define MEM_SYS_CFG_OFFSET 0x120 +#define QOS_OVERRIDE0_OFFSET 0x124 +#define QOS_OVERRIDE1_OFFSET 0x128 +#define MEM_CFG_STAT_OFFSET 0x12C +#define PWR_CFG_OFFSET 0x804 +#define EINT_MASK_OFFSET 0x808 +#define NOR_CFG_OFFSET 0x810 +#define STOP_CFG_OFFSET 0x814 +#define SLEEP_CFG_OFFSET 0x818 +#define OSC_FREQ_OFFSET 0x820 +#define OSC_STABLE_OFFSET 0x824 +#define PWR_STABLE_OFFSET 0x828 +#define FPC_STABLE_OFFSET 0x82C +#define MTC_STABLE_OFFSET 0x830 +#define OTHERS_OFFSET 0x900 +#define RST_STAT_OFFSET 0x904 +#define WAKEUP_STAT_OFFSET 0x908 +#define BLK_PWR_STAT_OFFSET 0x90C +#define INF_REG0_OFFSET 0xA00 +#define INF_REG1_OFFSET 0xA04 +#define INF_REG2_OFFSET 0xA08 +#define INF_REG3_OFFSET 0xA0C +#define INF_REG4_OFFSET 0xA10 +#define INF_REG5_OFFSET 0xA14 +#define INF_REG6_OFFSET 0xA18 +#define INF_REG7_OFFSET 0xA1C + +#define OSC_CNT_VAL_OFFSET 0x824 +#define PWR_CNT_VAL_OFFSET 0x828 +#define FPC_CNT_VAL_OFFSET 0x82C +#define MTC_CNT_VAL_OFFSET 0x830 + +#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) +#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) +#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) +#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) +#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) +#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) +#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) +#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) +#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) +#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) +#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) +#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) +#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) +#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) +#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) +#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) +#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) +#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) +#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + SELECT_DMA_OFFSET) +#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) +#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) +#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MEM_SYS_CFG_OFFSET) +#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + QOS_OVERRIDE0_OFFSET) +#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + QOS_OVERRIDE1_OFFSET) +#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MEM_CFG_STAT_OFFSET) +#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) +#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) +#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) +#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) +#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) +#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) +#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + OSC_CNT_VAL_OFFSET) +#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + PWR_CNT_VAL_OFFSET) +#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + FPC_CNT_VAL_OFFSET) +#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MTC_CNT_VAL_OFFSET) +#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) +#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) +#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + WAKEUP_STAT_OFFSET) +#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + BLK_PWR_STAT_OFFSET) +#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) +#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) +#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) +#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) +#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) +#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) +#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) +#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) + +#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) +#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) +#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) +#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) +#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) +#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) +#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) +#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) +#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) +#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) +#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) +#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) +#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) +#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) +#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) +#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) +#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) +#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) +#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) +#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) +#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) +#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) +#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) +#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) +#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) +#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) +#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) +#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) +#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) +#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) +#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) +#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) +#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) +#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) +#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) +#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) +#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) +#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) +#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) +#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) +#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) +#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) +#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) +#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) +#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) +#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) +#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) + + +/* + * GPIO + */ +#define ELFIN_GPIO_BASE 0x7f008000 + +#define GPACON_OFFSET 0x00 +#define GPADAT_OFFSET 0x04 +#define GPAPUD_OFFSET 0x08 +#define GPACONSLP_OFFSET 0x0C +#define GPAPUDSLP_OFFSET 0x10 +#define GPBCON_OFFSET 0x20 +#define GPBDAT_OFFSET 0x24 +#define GPBPUD_OFFSET 0x28 +#define GPBCONSLP_OFFSET 0x2C +#define GPBPUDSLP_OFFSET 0x30 +#define GPCCON_OFFSET 0x40 +#define GPCDAT_OFFSET 0x44 +#define GPCPUD_OFFSET 0x48 +#define GPCCONSLP_OFFSET 0x4C +#define GPCPUDSLP_OFFSET 0x50 +#define GPDCON_OFFSET 0x60 +#define GPDDAT_OFFSET 0x64 +#define GPDPUD_OFFSET 0x68 +#define GPDCONSLP_OFFSET 0x6C +#define GPDPUDSLP_OFFSET 0x70 +#define GPECON_OFFSET 0x80 +#define GPEDAT_OFFSET 0x84 +#define GPEPUD_OFFSET 0x88 +#define GPECONSLP_OFFSET 0x8C +#define GPEPUDSLP_OFFSET 0x90 +#define GPFCON_OFFSET 0xA0 +#define GPFDAT_OFFSET 0xA4 +#define GPFPUD_OFFSET 0xA8 +#define GPFCONSLP_OFFSET 0xAC +#define GPFPUDSLP_OFFSET 0xB0 +#define GPGCON_OFFSET 0xC0 +#define GPGDAT_OFFSET 0xC4 +#define GPGPUD_OFFSET 0xC8 +#define GPGCONSLP_OFFSET 0xCC +#define GPGPUDSLP_OFFSET 0xD0 +#define GPHCON0_OFFSET 0xE0 +#define GPHCON1_OFFSET 0xE4 +#define GPHDAT_OFFSET 0xE8 +#define GPHPUD_OFFSET 0xEC +#define GPHCONSLP_OFFSET 0xF0 +#define GPHPUDSLP_OFFSET 0xF4 +#define GPICON_OFFSET 0x100 +#define GPIDAT_OFFSET 0x104 +#define GPIPUD_OFFSET 0x108 +#define GPICONSLP_OFFSET 0x10C +#define GPIPUDSLP_OFFSET 0x110 +#define GPJCON_OFFSET 0x120 +#define GPJDAT_OFFSET 0x124 +#define GPJPUD_OFFSET 0x128 +#define GPJCONSLP_OFFSET 0x12C +#define GPJPUDSLP_OFFSET 0x130 +#define MEM0DRVCON_OFFSET 0x1D0 +#define MEM1DRVCON_OFFSET 0x1D4 +#define GPKCON0_OFFSET 0x800 +#define GPKCON1_OFFSET 0x804 +#define GPKDAT_OFFSET 0x808 +#define GPKPUD_OFFSET 0x80C +#define GPLCON0_OFFSET 0x810 +#define GPLCON1_OFFSET 0x814 +#define GPLDAT_OFFSET 0x818 +#define GPLPUD_OFFSET 0x81C +#define GPMCON_OFFSET 0x820 +#define GPMDAT_OFFSET 0x824 +#define GPMPUD_OFFSET 0x828 +#define GPNCON_OFFSET 0x830 +#define GPNDAT_OFFSET 0x834 +#define GPNPUD_OFFSET 0x838 +#define GPOCON_OFFSET 0x140 +#define GPODAT_OFFSET 0x144 +#define GPOPUD_OFFSET 0x148 +#define GPOCONSLP_OFFSET 0x14C +#define GPOPUDSLP_OFFSET 0x150 +#define GPPCON_OFFSET 0x160 +#define GPPDAT_OFFSET 0x164 +#define GPPPUD_OFFSET 0x168 +#define GPPCONSLP_OFFSET 0x16C +#define GPPPUDSLP_OFFSET 0x170 +#define GPQCON_OFFSET 0x180 +#define GPQDAT_OFFSET 0x184 +#define GPQPUD_OFFSET 0x188 +#define GPQCONSLP_OFFSET 0x18C +#define GPQPUDSLP_OFFSET 0x190 + +#define EINTPEND_OFFSET 0x924 + +#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) +#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) +#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) +#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) +#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) +#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) +#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) +#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) +#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) +#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) +#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) +#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) +#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) +#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) +#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) +#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) +#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) +#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) +#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) +#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) +#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) +#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) +#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) +#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) +#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) +#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) +#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) +#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) +#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) +#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) +#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) +#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) +#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) +#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) +#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) +#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) +#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) +#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) +#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) +#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) +#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) +#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) +#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) +#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) +#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) +#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) +#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) +#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) +#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) +#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) +#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) +#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) +#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) +#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) +#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) +#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) +#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) +#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) +#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) +#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) +#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) +#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) +#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) +#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) +#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) +#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) +#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) +#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) +#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) +#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) +#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) +#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) +#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) +#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) +#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) +#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) +#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) +#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) +#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) +#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) + +/* + * Bus Matrix + */ +#define ELFIN_MEM_SYS_CFG 0x7e00f120 + +#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) + +#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 +#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT + +#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) +#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) +#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) +#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) +#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) +#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) +#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) +#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) +#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) +#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) +#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) +#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) +#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) +#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) +#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) +#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) +#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) +#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) +#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) +#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) +#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) +#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) +#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) +#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) +#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) +#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) +#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) +#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) +#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) +#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) +#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) +#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) +#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) +#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) +#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) +#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) +#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) +#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) +#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) +#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) +#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) +#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) +#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) +#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) +#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) +#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) +#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) +#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) +#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) +#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) +#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) +#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) +#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) +#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) +#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) +#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) +#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) +#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) +#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) +#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) +#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) +#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) +#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) +#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) +#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) +#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) +#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) +#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) +#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) +#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) +#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) +#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) +#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) +#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) +#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) +#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) +#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) +#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) +#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) +#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) + +/* + * Memory controller + */ +#define ELFIN_SROM_BASE 0x70000000 + +#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) +#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) +#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) +#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) +#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) +#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) +#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) + +/* + * SDRAM Controller + */ +#define ELFIN_DMC0_BASE 0x7e000000 +#define ELFIN_DMC1_BASE 0x7e001000 + +#define INDEX_DMC_MEMC_STATUS 0x00 +#define INDEX_DMC_MEMC_CMD 0x04 +#define INDEX_DMC_DIRECT_CMD 0x08 +#define INDEX_DMC_MEMORY_CFG 0x0C +#define INDEX_DMC_REFRESH_PRD 0x10 +#define INDEX_DMC_CAS_LATENCY 0x14 +#define INDEX_DMC_T_DQSS 0x18 +#define INDEX_DMC_T_MRD 0x1C +#define INDEX_DMC_T_RAS 0x20 +#define INDEX_DMC_T_RC 0x24 +#define INDEX_DMC_T_RCD 0x28 +#define INDEX_DMC_T_RFC 0x2C +#define INDEX_DMC_T_RP 0x30 +#define INDEX_DMC_T_RRD 0x34 +#define INDEX_DMC_T_WR 0x38 +#define INDEX_DMC_T_WTR 0x3C +#define INDEX_DMC_T_XP 0x40 +#define INDEX_DMC_T_XSR 0x44 +#define INDEX_DMC_T_ESR 0x48 +#define INDEX_DMC_MEMORY_CFG2 0x4C +#define INDEX_DMC_CHIP_0_CFG 0x200 +#define INDEX_DMC_CHIP_1_CFG 0x204 +#define INDEX_DMC_CHIP_2_CFG 0x208 +#define INDEX_DMC_CHIP_3_CFG 0x20C +#define INDEX_DMC_USER_STATUS 0x300 +#define INDEX_DMC_USER_CONFIG 0x304 + +/* + * Memory Chip direct command + */ +#define DMC_NOP0 0x0c0000 +#define DMC_NOP1 0x1c0000 +#define DMC_PA0 0x000000 /* Precharge all */ +#define DMC_PA1 0x100000 +#define DMC_AR0 0x040000 /* Autorefresh */ +#define DMC_AR1 0x140000 +#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ +#define DMC_SDR_MR1 0x180032 +#define DMC_DDR_MR0 0x080162 +#define DMC_DDR_MR1 0x180162 +#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ +#define DMC_mDDR_MR1 0x180032 +#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ +#define DMC_mSDR_EMR1 0x1a0000 +#define DMC_DDR_EMR0 0x090000 +#define DMC_DDR_EMR1 0x190000 +#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ +#define DMC_mDDR_EMR1 0x1a0000 + +/* + * Definitions for memory configuration + * Set memory configuration + * active_chips = 1'b0 (1 chip) + * qos_master_chip = 3'b000(ARID[3:0]) + * memory burst = 3'b010(burst 4) + * stop_mem_clock = 1'b0(disable dynamical stop) + * auto_power_down = 1'b0(disable auto power-down mode) + * power_down_prd = 6'b00_0000(0 cycle for auto power-down) + * ap_bit = 1'b0 (bit position of auto-precharge is 10) + * row_bits = 3'b010(# row address 13) + * column_bits = 3'b010(# column address 10 ) + * + * Set user configuration + * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR + * + * Set chip select for chip [n] + * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff + * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] + */ + +/* + * Nand flash controller + */ +#define ELFIN_NAND_BASE 0x70200000 + +#define NFCONF_OFFSET 0x00 +#define NFCONT_OFFSET 0x04 +#define NFCMMD_OFFSET 0x08 +#define NFADDR_OFFSET 0x0c +#define NFDATA_OFFSET 0x10 +#define NFMECCDATA0_OFFSET 0x14 +#define NFMECCDATA1_OFFSET 0x18 +#define NFSECCDATA0_OFFSET 0x1c +#define NFSBLK_OFFSET 0x20 +#define NFEBLK_OFFSET 0x24 +#define NFSTAT_OFFSET 0x28 +#define NFESTAT0_OFFSET 0x2c +#define NFESTAT1_OFFSET 0x30 +#define NFMECC0_OFFSET 0x34 +#define NFMECC1_OFFSET 0x38 +#define NFSECC_OFFSET 0x3c +#define NFMLCBITPT_OFFSET 0x40 + +#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) +#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) +#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) +#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) +#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) +#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) +#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) +#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) +#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) +#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) +#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) +#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) +#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) +#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) +#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) +#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) + +#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) +#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) +#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) +#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) +#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) +#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) +#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) +#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) +#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) +#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) +#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) +#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) +#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) +#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) +#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) +#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) + +#define NFCONF_ECC_4BIT (1<<24) + +#define NFCONT_ECC_ENC (1<<18) +#define NFCONT_WP (1<<16) +#define NFCONT_MECCLOCK (1<<7) +#define NFCONT_SECCLOCK (1<<6) +#define NFCONT_INITMECC (1<<5) +#define NFCONT_INITSECC (1<<4) +#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) +#define NFCONT_CS_ALT (1<<2) +#define NFCONT_CS (1<<1) +#define NFCONT_ENABLE (1<<0) + +#define NFSTAT_ECCENCDONE (1<<7) +#define NFSTAT_ECCDECDONE (1<<6) +#define NFSTAT_RnB (1<<0) + +#define NFESTAT0_ECCBUSY (1<<31) + +/* + * Interrupt + */ +#define ELFIN_VIC0_BASE_ADDR 0x71200000 +#define ELFIN_VIC1_BASE_ADDR 0x71300000 +#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ +#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ +#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ +#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ +#define oVECTADDR 0xF00 /* VIC ADDRESS */ + +/* + * Watchdog timer + */ +#define ELFIN_WATCHDOG_BASE 0x7E004000 + +#define WTCON_REG __REG(0x7E004004) +#define WTDAT_REG __REG(0x7E004008) +#define WTCNT_REG __REG(0x7E00400C) + + +/* + * UART + */ +#define ELFIN_UART_BASE 0x7F005000 + +#define ELFIN_UART0_OFFSET 0x0000 +#define ELFIN_UART1_OFFSET 0x0400 +#define ELFIN_UART2_OFFSET 0x0800 + +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 + +#define ULCON0_REG __REG(0x7F005000) +#define UCON0_REG __REG(0x7F005004) +#define UFCON0_REG __REG(0x7F005008) +#define UMCON0_REG __REG(0x7F00500C) +#define UTRSTAT0_REG __REG(0x7F005010) +#define UERSTAT0_REG __REG(0x7F005014) +#define UFSTAT0_REG __REG(0x7F005018) +#define UMSTAT0_REG __REG(0x7F00501c) +#define UTXH0_REG __REG(0x7F005020) +#define URXH0_REG __REG(0x7F005024) +#define UBRDIV0_REG __REG(0x7F005028) +#define UDIVSLOT0_REG __REG(0x7F00502c) +#define UINTP0_REG __REG(0x7F005030) +#define UINTSP0_REG __REG(0x7F005034) +#define UINTM0_REG __REG(0x7F005038) + +#define ULCON1_REG __REG(0x7F005400) +#define UCON1_REG __REG(0x7F005404) +#define UFCON1_REG __REG(0x7F005408) +#define UMCON1_REG __REG(0x7F00540C) +#define UTRSTAT1_REG __REG(0x7F005410) +#define UERSTAT1_REG __REG(0x7F005414) +#define UFSTAT1_REG __REG(0x7F005418) +#define UMSTAT1_REG __REG(0x7F00541c) +#define UTXH1_REG __REG(0x7F005420) +#define URXH1_REG __REG(0x7F005424) +#define UBRDIV1_REG __REG(0x7F005428) +#define UDIVSLOT1_REG __REG(0x7F00542c) +#define UINTP1_REG __REG(0x7F005430) +#define UINTSP1_REG __REG(0x7F005434) +#define UINTM1_REG __REG(0x7F005438) + +#define UTRSTAT_TX_EMPTY (1 << 2) +#define UTRSTAT_RX_READY (1 << 0) +#define UART_ERR_MASK 0xF + +/* + * PWM timer + */ +#define ELFIN_TIMER_BASE 0x7F006000 + +#define TCFG0_REG __REG(0x7F006000) +#define TCFG1_REG __REG(0x7F006004) +#define TCON_REG __REG(0x7F006008) +#define TCNTB0_REG __REG(0x7F00600c) +#define TCMPB0_REG __REG(0x7F006010) +#define TCNTO0_REG __REG(0x7F006014) +#define TCNTB1_REG __REG(0x7F006018) +#define TCMPB1_REG __REG(0x7F00601c) +#define TCNTO1_REG __REG(0x7F006020) +#define TCNTB2_REG __REG(0x7F006024) +#define TCMPB2_REG __REG(0x7F006028) +#define TCNTO2_REG __REG(0x7F00602c) +#define TCNTB3_REG __REG(0x7F006030) +#define TCMPB3_REG __REG(0x7F006034) +#define TCNTO3_REG __REG(0x7F006038) +#define TCNTB4_REG __REG(0x7F00603c) +#define TCNTO4_REG __REG(0x7F006040) + +/* Fields */ +#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ +#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ +#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ +#define fTCFG1_MUX4 Fld(4, 16) +/* bits */ +#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) +#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) +#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) +#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ +#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ +#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ +#define COUNT_4_ON (TCON_4_ONOFF * 1) +#define COUNT_4_OFF (TCON_4_ONOFF * 0) +#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ +#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) +#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) +#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ +#define TIMER3_IVT_ON (TCON_3_INVERT * 1) +#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) +#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ +#define TIMER3_MANUP (TCON_3_MAN*1) +#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) +#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ +#define TIMER3_ON (TCON_3_ONOFF * 1) +#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) + +#if defined(CONFIG_CLK_400_100_50) +#define STARTUP_AMDIV 400 +#define STARTUP_MDIV 400 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_400_133_66) +#define STARTUP_AMDIV 400 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_533_133_66) +#define STARTUP_AMDIV 533 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_667_133_66) +#define STARTUP_AMDIV 667 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#endif + +#define STARTUP_PCLKDIV 3 +#define STARTUP_HCLKX2DIV 1 +#define STARTUP_HCLKDIV 1 +#define STARTUP_MPLLDIV 1 +#define STARTUP_APLLDIV 0 + +#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ + (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) +#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_MDIV) + +#if defined(CONFIG_SYNC_MODE) +#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_MDIV) +#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ + (STARTUP_HCLKDIV + 1)) +#else +#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_AMDIV) +#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ + (STARTUP_HCLKDIV + 1)) +#endif + + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG2 0xB45 +#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ +#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ + +/* Memory Parameters */ +/* DDR Parameters */ +#define DDR_tREFRESH 7800 /* ns */ +#define DDR_tRAS 45 /* ns (min: 45ns)*/ +#define DDR_tRC 68 /* ns (min: 67.5ns)*/ +#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ +#define DDR_tRFC 80 /* ns (min: 80ns)*/ +#define DDR_tRP 23 /* ns (min: 22.5ns)*/ +#define DDR_tRRD 15 /* ns (min: 15ns)*/ +#define DDR_tWR 15 /* ns (min: 15ns)*/ +#define DDR_tXSR 120 /* ns (min: 120ns)*/ +#define DDR_CASL 3 /* CAS Latency 3 */ + +/* + * mDDR memory configuration + */ + +#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) + +#define DMC_DDR_BA_EMRS 2 +#define DMC_DDR_MEM_CASLAT 3 +/* 6 Set Cas Latency to 3 */ +#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) +/* Min 0.75 ~ 1.25 */ +#define DMC_DDR_t_DQSS 1 +/* Min 2 tck */ +#define DMC_DDR_t_MRD 2 +/* 7, Min 45ns */ +#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) +/* 10, Min 67.5ns */ +#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) +/* 4,5(TRM), Min 22.5ns */ +#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) +#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) +/* 11,18(TRM) Min 80ns */ +#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) +#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) +/* 4, 5(TRM) Min 22.5ns */ +#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) +#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) +/* 3, Min 15ns */ +#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) +/* Min 15ns */ +#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) +#define DMC_DDR_t_WTR 2 +/* 1tck + tIS(1.5ns) */ +#define DMC_DDR_t_XP 2 +/* 17, Min 120ns */ +#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) +#define DMC_DDR_t_ESR DMC_DDR_t_XSR +/* TRM 2656 */ +#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) +/* 2b01 : mDDR */ +#define DMC_DDR_USER_CONFIG 1 + +#ifndef __ASSEMBLY__ +enum s3c64xx_uarts_nr { + S3C64XX_UART0, + S3C64XX_UART1, + S3C64XX_UART2, +}; + +#include "s3c64x0.h" + +static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) +{ + return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); +} +#endif + +#endif /*__S3C6400_H__*/ diff --git a/include/asm-arm/arch-s3c64xx/s3c64x0.h b/include/asm-arm/arch-s3c64xx/s3c64x0.h new file mode 100644 index 000000000..0bbf1d0c4 --- /dev/null +++ b/include/asm-arm/arch-s3c64xx/s3c64x0.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2003 + * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : S3C64XX.h + * Version : 31.3.2003 + * + * common stuff for SAMSUNG S3C64XX SoC + ************************************************/ + +#ifndef __S3C64XX_H__ +#define __S3C64XX_H__ + +#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) +#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! +#endif + +#include + +/* UART (see manual chapter 11) */ +typedef struct { + volatile u32 ULCON; + volatile u32 UCON; + volatile u32 UFCON; + volatile u32 UMCON; + volatile u32 UTRSTAT; + volatile u32 UERSTAT; + volatile u32 UFSTAT; + volatile u32 UMSTAT; +#ifdef __BIG_ENDIAN + volatile u8 res1[3]; + volatile u8 UTXH; + volatile u8 res2[3]; + volatile u8 URXH; +#else /* Little Endian */ + volatile u8 UTXH; + volatile u8 res1[3]; + volatile u8 URXH; + volatile u8 res2[3]; +#endif + volatile u32 UBRDIV; +#ifdef __BIG_ENDIAN + volatile u8 res3[2]; + volatile u16 UDIVSLOT; +#else + volatile u16 UDIVSLOT; + volatile u8 res3[2]; +#endif +} s3c64xx_uart; + +/* PWM TIMER (see manual chapter 10) */ +typedef struct { + volatile u32 TCNTB; + volatile u32 TCMPB; + volatile u32 TCNTO; +} s3c64xx_timer; + +typedef struct { + volatile u32 TCFG0; + volatile u32 TCFG1; + volatile u32 TCON; + s3c64xx_timer ch[4]; + volatile u32 TCNTB4; + volatile u32 TCNTO4; +} s3c64xx_timers; + +#endif /*__S3C64XX_H__*/ diff --git a/include/s3c6400.h b/include/s3c6400.h deleted file mode 100644 index e527c08b1..000000000 --- a/include/s3c6400.h +++ /dev/null @@ -1,895 +0,0 @@ -/* - * (C) Copyright 2007 - * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. - * - only support for S3C6400 - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c6400.h - * - * Based on S3C6400 User's manual Rev 0.0 - ************************************************/ - -#ifndef __S3C6400_H__ -#define __S3C6400_H__ - -#define S3C64XX_UART_CHANNELS 3 -#define S3C64XX_SPI_CHANNELS 2 - -#include - -#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* Clock & Power Controller for mDirac3*/ -#define APLL_LOCK_OFFSET 0x00 -#define MPLL_LOCK_OFFSET 0x04 -#define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 -#define EPLL_CON1_OFFSET 0x18 -#define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 -#define CLK_DIV2_OFFSET 0x28 -#define CLK_OUT_OFFSET 0x2C -#define HCLK_GATE_OFFSET 0x30 -#define PCLK_GATE_OFFSET 0x34 -#define SCLK_GATE_OFFSET 0x38 -#define AHB_CON0_OFFSET 0x100 -#define AHB_CON1_OFFSET 0x104 -#define AHB_CON2_OFFSET 0x108 -#define SELECT_DMA_OFFSET 0x110 -#define SW_RST_OFFSET 0x114 -#define SYS_ID_OFFSET 0x118 -#define MEM_SYS_CFG_OFFSET 0x120 -#define QOS_OVERRIDE0_OFFSET 0x124 -#define QOS_OVERRIDE1_OFFSET 0x128 -#define MEM_CFG_STAT_OFFSET 0x12C -#define PWR_CFG_OFFSET 0x804 -#define EINT_MASK_OFFSET 0x808 -#define NOR_CFG_OFFSET 0x810 -#define STOP_CFG_OFFSET 0x814 -#define SLEEP_CFG_OFFSET 0x818 -#define OSC_FREQ_OFFSET 0x820 -#define OSC_STABLE_OFFSET 0x824 -#define PWR_STABLE_OFFSET 0x828 -#define FPC_STABLE_OFFSET 0x82C -#define MTC_STABLE_OFFSET 0x830 -#define OTHERS_OFFSET 0x900 -#define RST_STAT_OFFSET 0x904 -#define WAKEUP_STAT_OFFSET 0x908 -#define BLK_PWR_STAT_OFFSET 0x90C -#define INF_REG0_OFFSET 0xA00 -#define INF_REG1_OFFSET 0xA04 -#define INF_REG2_OFFSET 0xA08 -#define INF_REG3_OFFSET 0xA0C -#define INF_REG4_OFFSET 0xA10 -#define INF_REG5_OFFSET 0xA14 -#define INF_REG6_OFFSET 0xA18 -#define INF_REG7_OFFSET 0xA1C - -#define OSC_CNT_VAL_OFFSET 0x824 -#define PWR_CNT_VAL_OFFSET 0x828 -#define FPC_CNT_VAL_OFFSET 0x82C -#define MTC_CNT_VAL_OFFSET 0x830 - -#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - SELECT_DMA_OFFSET) -#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_CFG_STAT_OFFSET) -#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MTC_CNT_VAL_OFFSET) -#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - BLK_PWR_STAT_OFFSET) -#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - -#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) -#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) -#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) -#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) -#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - - -/* - * GPIO - */ -#define ELFIN_GPIO_BASE 0x7f008000 - -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4 -#define GPFPUD_OFFSET 0xA8 -#define GPFCONSLP_OFFSET 0xAC -#define GPFPUDSLP_OFFSET 0xB0 -#define GPGCON_OFFSET 0xC0 -#define GPGDAT_OFFSET 0xC4 -#define GPGPUD_OFFSET 0xC8 -#define GPGCONSLP_OFFSET 0xCC -#define GPGPUDSLP_OFFSET 0xD0 -#define GPHCON0_OFFSET 0xE0 -#define GPHCON1_OFFSET 0xE4 -#define GPHDAT_OFFSET 0xE8 -#define GPHPUD_OFFSET 0xEC -#define GPHCONSLP_OFFSET 0xF0 -#define GPHPUDSLP_OFFSET 0xF4 -#define GPICON_OFFSET 0x100 -#define GPIDAT_OFFSET 0x104 -#define GPIPUD_OFFSET 0x108 -#define GPICONSLP_OFFSET 0x10C -#define GPIPUDSLP_OFFSET 0x110 -#define GPJCON_OFFSET 0x120 -#define GPJDAT_OFFSET 0x124 -#define GPJPUD_OFFSET 0x128 -#define GPJCONSLP_OFFSET 0x12C -#define GPJPUDSLP_OFFSET 0x130 -#define MEM0DRVCON_OFFSET 0x1D0 -#define MEM1DRVCON_OFFSET 0x1D4 -#define GPKCON0_OFFSET 0x800 -#define GPKCON1_OFFSET 0x804 -#define GPKDAT_OFFSET 0x808 -#define GPKPUD_OFFSET 0x80C -#define GPLCON0_OFFSET 0x810 -#define GPLCON1_OFFSET 0x814 -#define GPLDAT_OFFSET 0x818 -#define GPLPUD_OFFSET 0x81C -#define GPMCON_OFFSET 0x820 -#define GPMDAT_OFFSET 0x824 -#define GPMPUD_OFFSET 0x828 -#define GPNCON_OFFSET 0x830 -#define GPNDAT_OFFSET 0x834 -#define GPNPUD_OFFSET 0x838 -#define GPOCON_OFFSET 0x140 -#define GPODAT_OFFSET 0x144 -#define GPOPUD_OFFSET 0x148 -#define GPOCONSLP_OFFSET 0x14C -#define GPOPUDSLP_OFFSET 0x150 -#define GPPCON_OFFSET 0x160 -#define GPPDAT_OFFSET 0x164 -#define GPPPUD_OFFSET 0x168 -#define GPPCONSLP_OFFSET 0x16C -#define GPPPUDSLP_OFFSET 0x170 -#define GPQCON_OFFSET 0x180 -#define GPQDAT_OFFSET 0x184 -#define GPQPUD_OFFSET 0x188 -#define GPQCONSLP_OFFSET 0x18C -#define GPQPUDSLP_OFFSET 0x190 - -#define EINTPEND_OFFSET 0x924 - -#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Bus Matrix - */ -#define ELFIN_MEM_SYS_CFG 0x7e00f120 - -#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) - -#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 -#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT - -#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Memory controller - */ -#define ELFIN_SROM_BASE 0x70000000 - -#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) -#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) -#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) -#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) -#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) -#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) -#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) - -/* - * SDRAM Controller - */ -#define ELFIN_DMC0_BASE 0x7e000000 -#define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS 0x00 -#define INDEX_DMC_MEMC_CMD 0x04 -#define INDEX_DMC_DIRECT_CMD 0x08 -#define INDEX_DMC_MEMORY_CFG 0x0C -#define INDEX_DMC_REFRESH_PRD 0x10 -#define INDEX_DMC_CAS_LATENCY 0x14 -#define INDEX_DMC_T_DQSS 0x18 -#define INDEX_DMC_T_MRD 0x1C -#define INDEX_DMC_T_RAS 0x20 -#define INDEX_DMC_T_RC 0x24 -#define INDEX_DMC_T_RCD 0x28 -#define INDEX_DMC_T_RFC 0x2C -#define INDEX_DMC_T_RP 0x30 -#define INDEX_DMC_T_RRD 0x34 -#define INDEX_DMC_T_WR 0x38 -#define INDEX_DMC_T_WTR 0x3C -#define INDEX_DMC_T_XP 0x40 -#define INDEX_DMC_T_XSR 0x44 -#define INDEX_DMC_T_ESR 0x48 -#define INDEX_DMC_MEMORY_CFG2 0x4C -#define INDEX_DMC_CHIP_0_CFG 0x200 -#define INDEX_DMC_CHIP_1_CFG 0x204 -#define INDEX_DMC_CHIP_2_CFG 0x208 -#define INDEX_DMC_CHIP_3_CFG 0x20C -#define INDEX_DMC_USER_STATUS 0x300 -#define INDEX_DMC_USER_CONFIG 0x304 - -/* - * Memory Chip direct command - */ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 /* Precharge all */ -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 /* Autorefresh */ -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ -#define DMC_mDDR_EMR1 0x1a0000 - -/* - * Definitions for memory configuration - * Set memory configuration - * active_chips = 1'b0 (1 chip) - * qos_master_chip = 3'b000(ARID[3:0]) - * memory burst = 3'b010(burst 4) - * stop_mem_clock = 1'b0(disable dynamical stop) - * auto_power_down = 1'b0(disable auto power-down mode) - * power_down_prd = 6'b00_0000(0 cycle for auto power-down) - * ap_bit = 1'b0 (bit position of auto-precharge is 10) - * row_bits = 3'b010(# row address 13) - * column_bits = 3'b010(# column address 10 ) - * - * Set user configuration - * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - * - * Set chip select for chip [n] - * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] - */ - -/* - * Nand flash controller - */ -#define ELFIN_NAND_BASE 0x70200000 - -#define NFCONF_OFFSET 0x00 -#define NFCONT_OFFSET 0x04 -#define NFCMMD_OFFSET 0x08 -#define NFADDR_OFFSET 0x0c -#define NFDATA_OFFSET 0x10 -#define NFMECCDATA0_OFFSET 0x14 -#define NFMECCDATA1_OFFSET 0x18 -#define NFSECCDATA0_OFFSET 0x1c -#define NFSBLK_OFFSET 0x20 -#define NFEBLK_OFFSET 0x24 -#define NFSTAT_OFFSET 0x28 -#define NFESTAT0_OFFSET 0x2c -#define NFESTAT1_OFFSET 0x30 -#define NFMECC0_OFFSET 0x34 -#define NFMECC1_OFFSET 0x38 -#define NFSECC_OFFSET 0x3c -#define NFMLCBITPT_OFFSET 0x40 - -#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_ECC_4BIT (1<<24) - -#define NFCONT_ECC_ENC (1<<18) -#define NFCONT_WP (1<<16) -#define NFCONT_MECCLOCK (1<<7) -#define NFCONT_SECCLOCK (1<<6) -#define NFCONT_INITMECC (1<<5) -#define NFCONT_INITSECC (1<<4) -#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) -#define NFCONT_CS_ALT (1<<2) -#define NFCONT_CS (1<<1) -#define NFCONT_ENABLE (1<<0) - -#define NFSTAT_ECCENCDONE (1<<7) -#define NFSTAT_ECCDECDONE (1<<6) -#define NFSTAT_RnB (1<<0) - -#define NFESTAT0_ECCBUSY (1<<31) - -/* - * Interrupt - */ -#define ELFIN_VIC0_BASE_ADDR 0x71200000 -#define ELFIN_VIC1_BASE_ADDR 0x71300000 -#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ -#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ -#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ -#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ -#define oVECTADDR 0xF00 /* VIC ADDRESS */ - -/* - * Watchdog timer - */ -#define ELFIN_WATCHDOG_BASE 0x7E004000 - -#define WTCON_REG __REG(0x7E004004) -#define WTDAT_REG __REG(0x7E004008) -#define WTCNT_REG __REG(0x7E00400C) - - -/* - * UART - */ -#define ELFIN_UART_BASE 0x7F005000 - -#define ELFIN_UART0_OFFSET 0x0000 -#define ELFIN_UART1_OFFSET 0x0400 -#define ELFIN_UART2_OFFSET 0x0800 - -#define ULCON_OFFSET 0x00 -#define UCON_OFFSET 0x04 -#define UFCON_OFFSET 0x08 -#define UMCON_OFFSET 0x0C -#define UTRSTAT_OFFSET 0x10 -#define UERSTAT_OFFSET 0x14 -#define UFSTAT_OFFSET 0x18 -#define UMSTAT_OFFSET 0x1C -#define UTXH_OFFSET 0x20 -#define URXH_OFFSET 0x24 -#define UBRDIV_OFFSET 0x28 -#define UDIVSLOT_OFFSET 0x2C -#define UINTP_OFFSET 0x30 -#define UINTSP_OFFSET 0x34 -#define UINTM_OFFSET 0x38 - -#define ULCON0_REG __REG(0x7F005000) -#define UCON0_REG __REG(0x7F005004) -#define UFCON0_REG __REG(0x7F005008) -#define UMCON0_REG __REG(0x7F00500C) -#define UTRSTAT0_REG __REG(0x7F005010) -#define UERSTAT0_REG __REG(0x7F005014) -#define UFSTAT0_REG __REG(0x7F005018) -#define UMSTAT0_REG __REG(0x7F00501c) -#define UTXH0_REG __REG(0x7F005020) -#define URXH0_REG __REG(0x7F005024) -#define UBRDIV0_REG __REG(0x7F005028) -#define UDIVSLOT0_REG __REG(0x7F00502c) -#define UINTP0_REG __REG(0x7F005030) -#define UINTSP0_REG __REG(0x7F005034) -#define UINTM0_REG __REG(0x7F005038) - -#define ULCON1_REG __REG(0x7F005400) -#define UCON1_REG __REG(0x7F005404) -#define UFCON1_REG __REG(0x7F005408) -#define UMCON1_REG __REG(0x7F00540C) -#define UTRSTAT1_REG __REG(0x7F005410) -#define UERSTAT1_REG __REG(0x7F005414) -#define UFSTAT1_REG __REG(0x7F005418) -#define UMSTAT1_REG __REG(0x7F00541c) -#define UTXH1_REG __REG(0x7F005420) -#define URXH1_REG __REG(0x7F005424) -#define UBRDIV1_REG __REG(0x7F005428) -#define UDIVSLOT1_REG __REG(0x7F00542c) -#define UINTP1_REG __REG(0x7F005430) -#define UINTSP1_REG __REG(0x7F005434) -#define UINTM1_REG __REG(0x7F005438) - -#define UTRSTAT_TX_EMPTY (1 << 2) -#define UTRSTAT_RX_READY (1 << 0) -#define UART_ERR_MASK 0xF - -/* - * PWM timer - */ -#define ELFIN_TIMER_BASE 0x7F006000 - -#define TCFG0_REG __REG(0x7F006000) -#define TCFG1_REG __REG(0x7F006004) -#define TCON_REG __REG(0x7F006008) -#define TCNTB0_REG __REG(0x7F00600c) -#define TCMPB0_REG __REG(0x7F006010) -#define TCNTO0_REG __REG(0x7F006014) -#define TCNTB1_REG __REG(0x7F006018) -#define TCMPB1_REG __REG(0x7F00601c) -#define TCNTO1_REG __REG(0x7F006020) -#define TCNTB2_REG __REG(0x7F006024) -#define TCMPB2_REG __REG(0x7F006028) -#define TCNTO2_REG __REG(0x7F00602c) -#define TCNTB3_REG __REG(0x7F006030) -#define TCMPB3_REG __REG(0x7F006034) -#define TCNTO3_REG __REG(0x7F006038) -#define TCNTB4_REG __REG(0x7F00603c) -#define TCNTO4_REG __REG(0x7F006040) - -/* Fields */ -#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ -#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ -#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ -#define fTCFG1_MUX4 Fld(4, 16) -/* bits */ -#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) -#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) -#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) -#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ -#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ -#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ -#define COUNT_4_ON (TCON_4_ONOFF * 1) -#define COUNT_4_OFF (TCON_4_ONOFF * 0) -#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ -#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) -#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) -#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ -#define TIMER3_IVT_ON (TCON_3_INVERT * 1) -#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) -#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ -#define TIMER3_MANUP (TCON_3_MAN*1) -#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) -#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ -#define TIMER3_ON (TCON_3_ONOFF * 1) -#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) - -#if defined(CONFIG_CLK_400_100_50) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 400 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_400_133_66) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_533_133_66) -#define STARTUP_AMDIV 533 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_667_133_66) -#define STARTUP_AMDIV 667 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#endif - -#define STARTUP_PCLKDIV 3 -#define STARTUP_HCLKX2DIV 1 -#define STARTUP_HCLKDIV 1 -#define STARTUP_MPLLDIV 1 -#define STARTUP_APLLDIV 0 - -#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ - (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) -#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) - -#if defined(CONFIG_SYNC_MODE) -#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#else -#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_AMDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#endif - - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ -#define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ - -/* Memory Parameters */ -/* DDR Parameters */ -#define DDR_tREFRESH 7800 /* ns */ -#define DDR_tRAS 45 /* ns (min: 45ns)*/ -#define DDR_tRC 68 /* ns (min: 67.5ns)*/ -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ -#define DDR_tRFC 80 /* ns (min: 80ns)*/ -#define DDR_tRP 23 /* ns (min: 22.5ns)*/ -#define DDR_tRRD 15 /* ns (min: 15ns)*/ -#define DDR_tWR 15 /* ns (min: 15ns)*/ -#define DDR_tXSR 120 /* ns (min: 120ns)*/ -#define DDR_CASL 3 /* CAS Latency 3 */ - -/* - * mDDR memory configuration - */ - -#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) - -#define DMC_DDR_BA_EMRS 2 -#define DMC_DDR_MEM_CASLAT 3 -/* 6 Set Cas Latency to 3 */ -#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) -/* Min 0.75 ~ 1.25 */ -#define DMC_DDR_t_DQSS 1 -/* Min 2 tck */ -#define DMC_DDR_t_MRD 2 -/* 7, Min 45ns */ -#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) -/* 10, Min 67.5ns */ -#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) -/* 4,5(TRM), Min 22.5ns */ -#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) -#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) -/* 11,18(TRM) Min 80ns */ -#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) -#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) -/* 4, 5(TRM) Min 22.5ns */ -#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) -#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) -/* 3, Min 15ns */ -#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) -/* Min 15ns */ -#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) -#define DMC_DDR_t_WTR 2 -/* 1tck + tIS(1.5ns) */ -#define DMC_DDR_t_XP 2 -/* 17, Min 120ns */ -#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) -#define DMC_DDR_t_ESR DMC_DDR_t_XSR -/* TRM 2656 */ -#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) -/* 2b01 : mDDR */ -#define DMC_DDR_USER_CONFIG 1 - -#ifndef __ASSEMBLY__ -enum s3c64xx_uarts_nr { - S3C64XX_UART0, - S3C64XX_UART1, - S3C64XX_UART2, -}; - -#include "s3c64x0.h" - -static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) -{ - return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); -} -#endif - -#endif /*__S3C6400_H__*/ diff --git a/include/s3c64x0.h b/include/s3c64x0.h deleted file mode 100644 index 0bbf1d0c4..000000000 --- a/include/s3c64x0.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2003 - * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : S3C64XX.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C64XX SoC - ************************************************/ - -#ifndef __S3C64XX_H__ -#define __S3C64XX_H__ - -#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) -#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! -#endif - -#include - -/* UART (see manual chapter 11) */ -typedef struct { - volatile u32 ULCON; - volatile u32 UCON; - volatile u32 UFCON; - volatile u32 UMCON; - volatile u32 UTRSTAT; - volatile u32 UERSTAT; - volatile u32 UFSTAT; - volatile u32 UMSTAT; -#ifdef __BIG_ENDIAN - volatile u8 res1[3]; - volatile u8 UTXH; - volatile u8 res2[3]; - volatile u8 URXH; -#else /* Little Endian */ - volatile u8 UTXH; - volatile u8 res1[3]; - volatile u8 URXH; - volatile u8 res2[3]; -#endif - volatile u32 UBRDIV; -#ifdef __BIG_ENDIAN - volatile u8 res3[2]; - volatile u16 UDIVSLOT; -#else - volatile u16 UDIVSLOT; - volatile u8 res3[2]; -#endif -} s3c64xx_uart; - -/* PWM TIMER (see manual chapter 10) */ -typedef struct { - volatile u32 TCNTB; - volatile u32 TCMPB; - volatile u32 TCNTO; -} s3c64xx_timer; - -typedef struct { - volatile u32 TCFG0; - volatile u32 TCFG1; - volatile u32 TCON; - s3c64xx_timer ch[4]; - volatile u32 TCNTB4; - volatile u32 TCNTO4; -} s3c64xx_timers; - -#endif /*__S3C64XX_H__*/ -- cgit v1.2.3 From 940032260914076b1594906334b2e3f7af6fb7cf Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Tue, 10 Nov 2009 20:23:50 +0900 Subject: s5pc1xx: serial: fix the error check logic Because of Frame error, Parity error and Overrun error are occured only receive operation, need to masking when error checking. Signed-off-by: Minkyu Kang --- drivers/serial/serial_s5pc1xx.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) (limited to 'drivers/serial') diff --git a/drivers/serial/serial_s5pc1xx.c b/drivers/serial/serial_s5pc1xx.c index 68c06a919..73669a9f1 100644 --- a/drivers/serial/serial_s5pc1xx.c +++ b/drivers/serial/serial_s5pc1xx.c @@ -98,14 +98,24 @@ int serial_init_dev(const int dev_index) return 0; } -static int serial_err_check(const int dev_index) +static int serial_err_check(const int dev_index, int op) { struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + unsigned int mask; + + /* + * UERSTAT + * Break Detect [3] + * Frame Err [2] : receive operation + * Parity Err [1] : receive operation + * Overrun Err [0] : receive operation + */ + if (op) + mask = 0x8; + else + mask = 0xf; - if (readl(&uart->uerstat) & 0xf) - return 1; - - return 0; + return readl(&uart->uerstat) & mask; } /* @@ -119,7 +129,7 @@ int serial_getc_dev(const int dev_index) /* wait for character to arrive */ while (!(readl(&uart->utrstat) & 0x1)) { - if (serial_err_check(dev_index)) + if (serial_err_check(dev_index, 0)) return 0; } @@ -135,7 +145,7 @@ void serial_putc_dev(const char c, const int dev_index) /* wait for room in the tx FIFO */ while (!(readl(&uart->utrstat) & 0x2)) { - if (serial_err_check(dev_index)) + if (serial_err_check(dev_index, 1)) return; } -- cgit v1.2.3 From ac67804fbb2d82a19170066c02af7053d474ce8d Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Tue, 17 Nov 2009 18:30:34 +0900 Subject: Add a unified s3c24x0 header file This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- board/mpl/vcma9/vcma9.c | 2 +- board/mpl/vcma9/vcma9.h | 2 +- board/samsung/smdk2400/smdk2400.c | 2 +- board/samsung/smdk2410/smdk2410.c | 2 +- board/sbc2410x/sbc2410x.c | 2 +- board/trab/cmd_trab.c | 2 +- board/trab/rs485.c | 2 +- board/trab/rs485.h | 2 +- board/trab/trab.c | 2 +- board/trab/trab_fkt.c | 2 +- board/trab/tsc2000.c | 2 +- board/trab/vfd.c | 2 +- cpu/arm920t/s3c24x0/interrupts.c | 6 +----- cpu/arm920t/s3c24x0/speed.c | 13 +++---------- cpu/arm920t/s3c24x0/timer.c | 15 +++------------ cpu/arm920t/s3c24x0/usb.c | 17 +++++++---------- cpu/arm920t/s3c24x0/usb_ohci.c | 11 +++-------- cpu/arm920t/start.S | 4 ++-- drivers/i2c/s3c24x0_i2c.c | 6 +----- drivers/mtd/nand/s3c2410_nand.c | 2 +- drivers/rtc/s3c24x0_rtc.c | 6 +----- drivers/serial/serial_s3c24x0.c | 6 +----- drivers/usb/host/ohci-hcd.c | 3 +-- include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h | 27 +++++++++++++++++++++++++++ include/common.h | 5 +++-- include/configs/VCMA9.h | 7 ++++--- include/configs/sbc2410x.h | 7 ++++--- include/configs/smdk2400.h | 7 ++++--- include/configs/smdk2410.h | 7 ++++--- include/configs/trab.h | 9 +++++---- 30 files changed, 87 insertions(+), 95 deletions(-) create mode 100644 include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h (limited to 'drivers/serial') diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index f3bd28845..1835677a8 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 2c4305c6a..94fd2faf3 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -25,7 +25,7 @@ * Global routines used for VCMA9 *****************************************************************************/ -#include +#include extern int mem_test(unsigned long start, unsigned long ramsize,int mode); diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index be0c70ad0..1294d3f1b 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -27,7 +27,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index a8cf2874a..5d1a8bb0c 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -27,7 +27,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 6768c028c..3a936778e 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -30,7 +30,7 @@ #include #include -#include +#include #if defined(CONFIG_CMD_NAND) #include diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index a01ffcc02..472d7d81e 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include /* diff --git a/board/trab/rs485.c b/board/trab/rs485.c index f402c5990..ad0c13665 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -22,7 +22,7 @@ */ #include -#include +#include #include "rs485.h" static void rs485_setbrg (void); diff --git a/board/trab/rs485.h b/board/trab/rs485.h index 4a2d83f0b..16d69bbd5 100644 --- a/board/trab/rs485.h +++ b/board/trab/rs485.h @@ -24,7 +24,7 @@ #ifndef _RS485_H_ #define _RS485_H_ -#include +#include int rs485_init (void); int rs485_getc (void); diff --git a/board/trab/trab.c b/board/trab/trab.c index f8836ff37..71fd22c15 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index 940e12f25..2df9a0440 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include "tsc2000.h" #include "rs485.h" diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index f757202de..5890624f0 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -26,7 +26,7 @@ */ #include -#include +#include #include #include #include "tsc2000.h" diff --git a/board/trab/vfd.c b/board/trab/vfd.c index 8d9a05716..b7eb8cce0 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 3e8422e14..879fda66a 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -31,11 +31,7 @@ #include -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #include void do_irq (struct pt_regs *pt_regs) diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c index 85c73a3ee..b13283a79 100644 --- a/cpu/arm920t/s3c24x0/speed.c +++ b/cpu/arm920t/s3c24x0/speed.c @@ -30,15 +30,10 @@ */ #include -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) +#ifdef CONFIG_S3C24X0 #include - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #define MPLL 0 #define UPLL 1 @@ -100,6 +95,4 @@ ulong get_UCLK(void) return get_PLLCLK(UPLL); } -#endif /* defined(CONFIG_S3C2400) || - defined (CONFIG_S3C2410) || - defined (CONFIG_TRAB) */ +#endif /* CONFIG_S3C24X0 */ diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 2667da6e8..cd06f6b58 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -30,17 +30,10 @@ */ #include -#if defined(CONFIG_S3C2400) || \ - defined(CONFIG_S3C2410) || \ - defined(CONFIG_TRAB) +#ifdef CONFIG_S3C24X0 #include - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include int timer_load_val = 0; static ulong timer_clk; @@ -225,6 +218,4 @@ void reset_cpu(ulong ignored) /*NOTREACHED*/ } -#endif /* defined(CONFIG_S3C2400) || - defined (CONFIG_S3C2410) || - defined (CONFIG_TRAB) */ +#endif /* CONFIG_S3C24X0 */ diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index 5e19cda8f..e468ed08f 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -23,15 +23,11 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) - -#if defined(CONFIG_S3C2400) -# include -#elif defined(CONFIG_S3C2410) -# include -#endif +#if defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) +#include #include int usb_cpu_init(void) @@ -70,5 +66,6 @@ int usb_cpu_init_fail(void) return 0; } -# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ -#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) */ diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 41119922e..5aa8d64a5 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -36,14 +36,9 @@ #include /* #include no PCI on the S3C24X0 */ -#ifdef CONFIG_USB_OHCI - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) +#include #include #include #include @@ -1757,4 +1752,4 @@ int usb_lowlevel_stop(void) return 0; } -#endif /* CONFIG_USB_OHCI */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */ diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 114427a16..779f192e5 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -131,7 +131,7 @@ copyex: bne copyex #endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) +#ifdef CONFIG_S3C24X0 /* turn off the watchdog */ # if defined(CONFIG_S3C2400) @@ -166,7 +166,7 @@ copyex: ldr r0, =CLKDIVN mov r1, #3 str r1, [r0] -#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ +#endif /* CONFIG_S3C24X0 */ /* * we do sys-critical inits only at reboot, diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 8fecc6e3f..c8371cf73 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -27,11 +27,7 @@ */ #include -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #include #include diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index 2f89b8c96..a27d47e5f 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #define S3C2410_NFCONF_EN (1<<15) diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 2d78f93ae..04de5ca54 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -30,11 +30,7 @@ #if (defined(CONFIG_CMD_DATE)) -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #include #include diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 914d07cda..5dd4dd816 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -19,11 +19,7 @@ */ #include -#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 67d478f87..b03a60044 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -65,8 +65,7 @@ #endif #if defined(CONFIG_ARM920T) || \ - defined(CONFIG_S3C2400) || \ - defined(CONFIG_S3C2410) || \ + defined(CONFIG_S3C24X0) || \ defined(CONFIG_S3C6400) || \ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h new file mode 100644 index 000000000..c37d4a108 --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef CONFIG_S3C2400 + #include +#elif defined CONFIG_S3C2410 + #include +#else + #error Please define the s3c24x0 cpu type +#endif diff --git a/include/common.h b/include/common.h index f7c93bf5a..8ee80c139 100644 --- a/include/common.h +++ b/include/common.h @@ -495,8 +495,9 @@ int prt_mpc8220_clks (void); ulong get_OPB_freq (void); ulong get_PCI_freq (void); #endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ - defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400) +#if defined(CONFIG_S3C24X0) || \ + defined(CONFIG_LH7A40X) || \ + defined(CONFIG_S3C6400) ulong get_FCLK (void); ulong get_HCLK (void); ulong get_PCLK (void); diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 618b7f0a7..ebc81c400 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,9 +33,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index e6886cf7f..025ad0953 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -43,9 +43,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */ diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index a1beb65d0..fd51219af 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -34,9 +34,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ +#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index c57751bf9..f9d1e5518 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -33,9 +33,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ diff --git a/include/configs/trab.h b/include/configs/trab.h index 97f30cea7..9827195e8 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -40,10 +40,11 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_TRAB 1 /* on a TRAB Board */ -#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ +#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ +#define CONFIG_TRAB 1 /* on a TRAB Board */ +#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ /* automatic software updates (see board/trab/auto_update.c) */ #define CONFIG_AUTO_UPDATE 1 -- cgit v1.2.3 From f298e4b6dd56df3e35a13a6ddd572ca3baf06ad2 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sat, 31 Oct 2009 12:37:41 -0500 Subject: OMAP3 Add usb device support This change adds the usb device support for musb. Omap3 platform support added at the same level as davinci. The interface for usbtty to use the musb device support was added. Verified on omap3 beagle, zoom1 and zoom2. Signed-off-by: Tom Rix --- drivers/serial/usbtty.h | 2 + drivers/usb/musb/Makefile | 2 + drivers/usb/musb/musb_core.c | 8 +- drivers/usb/musb/musb_core.h | 40 ++ drivers/usb/musb/musb_debug.h | 205 +++++++++ drivers/usb/musb/musb_udc.c | 963 ++++++++++++++++++++++++++++++++++++++++++ drivers/usb/musb/omap3.c | 129 ++++++ drivers/usb/musb/omap3.h | 48 +++ include/usb.h | 3 +- include/usb/musb_udc.h | 54 +++ 10 files changed, 1451 insertions(+), 3 deletions(-) create mode 100644 drivers/usb/musb/musb_debug.h create mode 100644 drivers/usb/musb/musb_udc.c create mode 100644 drivers/usb/musb/omap3.c create mode 100644 drivers/usb/musb/omap3.h create mode 100644 include/usb/musb_udc.h (limited to 'drivers/serial') diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index f746d6317..6b6c4a162 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -29,6 +29,8 @@ #include #elif defined(CONFIG_OMAP1510) #include +#elif defined(CONFIG_MUSB_UDC) +#include #elif defined(CONFIG_PXA27X) #include #endif diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile index 09e0a5f32..f2ccd9fe0 100644 --- a/drivers/usb/musb/Makefile +++ b/drivers/usb/musb/Makefile @@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_musb.a COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o +COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o COBJS-$(CONFIG_USB_DAVINCI) += davinci.o +COBJS-$(CONFIG_USB_OMAP3) += omap3.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index ec57fc811..22f3dba0c 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -32,7 +32,9 @@ struct musb_regs *musbr; */ void musb_start(void) { +#if defined(CONFIG_MUSB_HCD) u8 devctl; +#endif /* disable all interrupts */ writew(0, &musbr->intrtxe); @@ -74,9 +76,10 @@ void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) /* Configure fifo size and fifo base address */ writeb(idx, &musbr->txfifosz); writew(fifoaddr >> 3, &musbr->txfifoadd); + + csr = readw(&musbr->txcsr); #if defined(CONFIG_MUSB_HCD) /* clear the data toggle bit */ - csr = readw(&musbr->txcsr); writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); #endif /* Flush fifo if required */ @@ -87,9 +90,10 @@ void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) /* Configure fifo size and fifo base address */ writeb(idx, &musbr->rxfifosz); writew(fifoaddr >> 3, &musbr->rxfifoadd); + + csr = readw(&musbr->rxcsr); #if defined(CONFIG_MUSB_HCD) /* clear the data toggle bit */ - csr = readw(&musbr->rxcsr); writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); #endif /* Flush fifo if required */ diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index f9da3f0b2..15c7f49a3 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -40,6 +40,36 @@ #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ +/* EP0 */ +struct musb_ep0_regs { + u16 reserved4; + u16 csr0; + u16 reserved5; + u16 reserved6; + u16 count0; + u8 host_type0; + u8 host_naklimit0; + u8 reserved7; + u8 reserved8; + u8 reserved9; + u8 configdata; +}; + +/* EP 1-15 */ +struct musb_epN_regs { + u16 txmaxp; + u16 txcsr; + u16 rxmaxp; + u16 rxcsr; + u16 rxcount; + u8 txtype; + u8 txinterval; + u8 rxtype; + u8 rxinterval; + u8 reserved0; + u8 fifosize; +}; + /* Mentor USB core register overlay structure */ struct musb_regs { /* common registers */ @@ -97,6 +127,16 @@ struct musb_regs { u8 rxhubaddr; u8 rxhubport; } tar[16]; + /* + * end point registers + * ep0 elements are valid when array index is 0 + * otherwise epN is valid + */ + union musb_ep_regs { + struct musb_ep0_regs ep0; + struct musb_epN_regs epN; + } ep[16]; + } __attribute__((aligned(32))); /* diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h new file mode 100644 index 000000000..62380ffc6 --- /dev/null +++ b/drivers/usb/musb/musb_debug.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Define MUSB_DEBUG before including this file to get debug macros */ +#ifdef MUSB_DEBUG + +#define MUSB_FLAGS_PRINT(v, x, y) \ + if (((v) & MUSB_##x##_##y)) \ + serial_printf("\t\t"#y"\n") + +static inline void musb_print_pwr(u8 b) +{ + serial_printf("\tpower 0x%2.2x\n", b); + MUSB_FLAGS_PRINT(b, POWER, ISOUPDATE); + MUSB_FLAGS_PRINT(b, POWER, SOFTCONN); + MUSB_FLAGS_PRINT(b, POWER, HSENAB); + MUSB_FLAGS_PRINT(b, POWER, HSMODE); + MUSB_FLAGS_PRINT(b, POWER, RESET); + MUSB_FLAGS_PRINT(b, POWER, RESUME); + MUSB_FLAGS_PRINT(b, POWER, SUSPENDM); + MUSB_FLAGS_PRINT(b, POWER, ENSUSPEND); +} + +static inline void musb_print_csr0(u16 w) +{ + serial_printf("\tcsr0 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, CSR0, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, CSR0_P, SVDSETUPEND); + MUSB_FLAGS_PRINT(w, CSR0_P, SVDRXPKTRDY); + MUSB_FLAGS_PRINT(w, CSR0_P, SENDSTALL); + MUSB_FLAGS_PRINT(w, CSR0_P, SETUPEND); + MUSB_FLAGS_PRINT(w, CSR0_P, DATAEND); + MUSB_FLAGS_PRINT(w, CSR0_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, CSR0, TXPKTRDY); + MUSB_FLAGS_PRINT(w, CSR0, RXPKTRDY); +} + +static inline void musb_print_intrusb(u8 b) +{ + serial_printf("\tintrusb 0x%2.2x\n", b); + MUSB_FLAGS_PRINT(b, INTR, VBUSERROR); + MUSB_FLAGS_PRINT(b, INTR, SESSREQ); + MUSB_FLAGS_PRINT(b, INTR, DISCONNECT); + MUSB_FLAGS_PRINT(b, INTR, CONNECT); + MUSB_FLAGS_PRINT(b, INTR, SOF); + MUSB_FLAGS_PRINT(b, INTR, RESUME); + MUSB_FLAGS_PRINT(b, INTR, SUSPEND); + + if (b & MUSB_INTR_BABBLE) + serial_printf("\t\tMUSB_INTR_RESET or MUSB_INTR_BABBLE\n"); + +} + +static inline void musb_print_intrtx(u16 w) +{ + serial_printf("\tintrtx 0x%4.4x\n", w); +} + +static inline void musb_print_intrrx(u16 w) +{ + serial_printf("\tintrx 0x%4.4x\n", w); +} + +static inline void musb_print_devctl(u8 b) +{ + serial_printf("\tdevctl 0x%2.2x\n", b); + if (b & MUSB_DEVCTL_BDEVICE) + serial_printf("\t\tB device\n"); + else + serial_printf("\t\tA device\n"); + if (b & MUSB_DEVCTL_FSDEV) + serial_printf("\t\tFast Device -(host mode)\n"); + if (b & MUSB_DEVCTL_LSDEV) + serial_printf("\t\tSlow Device -(host mode)\n"); + if (b & MUSB_DEVCTL_HM) + serial_printf("\t\tHost mode\n"); + else + serial_printf("\t\tPeripherial mode\n"); + if (b & MUSB_DEVCTL_HR) + serial_printf("\t\tHost request started(B device)\n"); + else + serial_printf("\t\tHost request finished(B device)\n"); + if (b & MUSB_DEVCTL_BDEVICE) { + if (b & MUSB_DEVCTL_SESSION) + serial_printf("\t\tStart of session(B device)\n"); + else + serial_printf("\t\tEnd of session(B device)\n"); + } else { + if (b & MUSB_DEVCTL_SESSION) + serial_printf("\t\tStart of session(A device)\n"); + else + serial_printf("\t\tEnd of session(A device)\n"); + } +} + +static inline void musb_print_config(u8 b) +{ + serial_printf("\tconfig 0x%2.2x\n", b); + if (b & MUSB_CONFIGDATA_MPRXE) + serial_printf("\t\tAuto combine rx bulk packets\n"); + if (b & MUSB_CONFIGDATA_MPTXE) + serial_printf("\t\tAuto split tx bulk packets\n"); + if (b & MUSB_CONFIGDATA_BIGENDIAN) + serial_printf("\t\tBig Endian ordering\n"); + else + serial_printf("\t\tLittle Endian ordering\n"); + if (b & MUSB_CONFIGDATA_HBRXE) + serial_printf("\t\tHigh speed rx iso endpoint\n"); + if (b & MUSB_CONFIGDATA_HBTXE) + serial_printf("\t\tHigh speed tx iso endpoint\n"); + if (b & MUSB_CONFIGDATA_DYNFIFO) + serial_printf("\t\tDynamic fifo sizing\n"); + if (b & MUSB_CONFIGDATA_SOFTCONE) + serial_printf("\t\tSoft Connect\n"); + if (b & MUSB_CONFIGDATA_UTMIDW) + serial_printf("\t\t16 bit data width\n"); + else + serial_printf("\t\t8 bit data width\n"); +} + +static inline void musb_print_rxmaxp(u16 w) +{ + serial_printf("\trxmaxp 0x%4.4x\n", w); +} + +static inline void musb_print_rxcsr(u16 w) +{ + serial_printf("\trxcsr 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, RXCSR, AUTOCLEAR); + MUSB_FLAGS_PRINT(w, RXCSR, DMAENAB); + MUSB_FLAGS_PRINT(w, RXCSR, DISNYET); + MUSB_FLAGS_PRINT(w, RXCSR, PID_ERR); + MUSB_FLAGS_PRINT(w, RXCSR, DMAMODE); + MUSB_FLAGS_PRINT(w, RXCSR, CLRDATATOG); + MUSB_FLAGS_PRINT(w, RXCSR, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, RXCSR, DATAERROR); + MUSB_FLAGS_PRINT(w, RXCSR, FIFOFULL); + MUSB_FLAGS_PRINT(w, RXCSR, RXPKTRDY); + MUSB_FLAGS_PRINT(w, RXCSR_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, RXCSR_P, SENDSTALL); + MUSB_FLAGS_PRINT(w, RXCSR_P, OVERRUN); + + if (w & MUSB_RXCSR_P_ISO) + serial_printf("\t\tiso mode\n"); + else + serial_printf("\t\tbulk mode\n"); + +} + +static inline void musb_print_txmaxp(u16 w) +{ + serial_printf("\ttxmaxp 0x%4.4x\n", w); +} + +static inline void musb_print_txcsr(u16 w) +{ + serial_printf("\ttxcsr 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, TXCSR, TXPKTRDY); + MUSB_FLAGS_PRINT(w, TXCSR, FIFONOTEMPTY); + MUSB_FLAGS_PRINT(w, TXCSR, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, TXCSR, CLRDATATOG); + MUSB_FLAGS_PRINT(w, TXCSR_P, UNDERRUN); + MUSB_FLAGS_PRINT(w, TXCSR_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, TXCSR_P, SENDSTALL); + + if (w & MUSB_TXCSR_MODE) + serial_printf("\t\tTX mode\n"); + else + serial_printf("\t\tRX mode\n"); +} + +#else + +/* stubs */ + +#define musb_print_pwr(b) +#define musb_print_csr0(w) +#define musb_print_intrusb(b) +#define musb_print_intrtx(w) +#define musb_print_intrrx(w) +#define musb_print_devctl(b) +#define musb_print_config(b) +#define musb_print_rxmaxp(w) +#define musb_print_rxcsr(w) +#define musb_print_txmaxp(w) +#define musb_print_txcsr(w) + +#endif /* MUSB_DEBUG */ diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c new file mode 100644 index 000000000..fc43cf4f0 --- /dev/null +++ b/drivers/usb/musb/musb_udc.c @@ -0,0 +1,963 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This file is a rewrite of the usb device part of + * repository git.omapzoom.org/repo/u-boot.git, branch master, + * file cpu/omap3/fastboot.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------- + * + * (C) Copyright 2008 - 2009 + * Windriver, + * Tom Rix + * + * ------------------------------------------------------------------------- + * + * The details of connecting the device to the uboot usb device subsystem + * came from the old omap3 repository www.sakoman.net/u-boot-omap3.git, + * branch omap3-dev-usb, file drivers/usb/usbdcore_musb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------- + * + * (C) Copyright 2008 Texas Instruments Incorporated. + * + * Based on + * u-boot OMAP1510 USB drivers (drivers/usbdcore_omap1510.c) + * twl4030 init based on linux (drivers/i2c/chips/twl4030_usb.c) + * + * Author: Diego Dompe (diego.dompe@ridgerun.com) + * Atin Malaviya (atin.malaviya@gmail.com) + * + * ------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "../gadget/ep0.h" +#include "musb_core.h" +#if defined(CONFIG_USB_OMAP3) +#include "omap3.h" +#elif defined(CONFIG_USB_DAVINCI) +#include "davinci.h" +#endif + +/* Define MUSB_DEBUG for debugging */ +/* #define MUSB_DEBUG */ +#include "musb_debug.h" + +#define MAX_ENDPOINT 15 + +#define GET_ENDPOINT(dev,ep) \ +(((struct usb_device_instance *)(dev))->bus->endpoint_array + ep) + +#define SET_EP0_STATE(s) \ +do { \ + if ((0 <= (s)) && (SET_ADDRESS >= (s))) { \ + if ((s) != ep0_state) { \ + if ((debug_setup) && (debug_level > 1)) \ + serial_printf("INFO : Changing state " \ + "from %s to %s in %s at " \ + "line %d\n", \ + ep0_state_strings[ep0_state],\ + ep0_state_strings[s], \ + __PRETTY_FUNCTION__, \ + __LINE__); \ + ep0_state = s; \ + } \ + } else { \ + if (debug_level > 0) \ + serial_printf("Error at %s %d with setting " \ + "state %d is invalid\n", \ + __PRETTY_FUNCTION__, __LINE__, s); \ + } \ +} while (0) + +/* static implies these initialized to 0 or NULL */ +static int debug_setup; +static int debug_level; +static struct musb_epinfo epinfo[MAX_ENDPOINT * 2]; +static enum ep0_state_enum { + IDLE = 0, + TX, + RX, + SET_ADDRESS +} ep0_state = IDLE; +static char *ep0_state_strings[4] = { + "IDLE", + "TX", + "RX", + "SET_ADDRESS", +}; + +static struct urb *ep0_urb; +struct usb_endpoint_instance *ep0_endpoint; +static struct usb_device_instance *udc_device; +static int enabled; + +#ifdef MUSB_DEBUG +static void musb_db_regs(void) +{ + u8 b; + u16 w; + + b = readb(&musbr->faddr); + serial_printf("\tfaddr 0x%2.2x\n", b); + + b = readb(&musbr->power); + musb_print_pwr(b); + + w = readw(&musbr->ep[0].ep0.csr0); + musb_print_csr0(w); + + b = readb(&musbr->devctl); + musb_print_devctl(b); + + b = readb(&musbr->ep[0].ep0.configdata); + musb_print_config(b); + + w = readw(&musbr->frame); + serial_printf("\tframe 0x%4.4x\n", w); + + b = readb(&musbr->index); + serial_printf("\tindex 0x%2.2x\n", b); + + w = readw(&musbr->ep[1].epN.rxmaxp); + musb_print_rxmaxp(w); + + w = readw(&musbr->ep[1].epN.rxcsr); + musb_print_rxcsr(w); + + w = readw(&musbr->ep[1].epN.txmaxp); + musb_print_txmaxp(w); + + w = readw(&musbr->ep[1].epN.txcsr); + musb_print_txcsr(w); +} +#else +#define musb_db_regs() +#endif /* DEBUG_MUSB */ + +static void musb_peri_softconnect(void) +{ + u8 power, devctl; + u8 intrusb; + u16 intrrx, intrtx; + + /* Power off MUSB */ + power = readb(&musbr->power); + power &= ~MUSB_POWER_SOFTCONN; + writeb(power, &musbr->power); + + /* Read intr to clear */ + intrusb = readb(&musbr->intrusb); + intrrx = readw(&musbr->intrrx); + intrtx = readw(&musbr->intrtx); + + udelay(1000 * 1000); /* 1 sec */ + + /* Power on MUSB */ + power = readb(&musbr->power); + power |= MUSB_POWER_SOFTCONN; + /* + * The usb device interface is usb 1.1 + * Disable 2.0 high speed by clearring the hsenable bit. + */ + power &= ~MUSB_POWER_HSENAB; + writeb(power, &musbr->power); + + /* Check if device is in b-peripheral mode */ + devctl = readb(&musbr->devctl); + if (!(devctl & MUSB_DEVCTL_BDEVICE) || + (devctl & MUSB_DEVCTL_HM)) { + serial_printf("ERROR : Unsupport USB mode\n"); + serial_printf("Check that mini-B USB cable is attached " + "to the device\n"); + } + + if (debug_setup && (debug_level > 1)) + musb_db_regs(); +} + +static void musb_peri_reset(void) +{ + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s reset\n", __PRETTY_FUNCTION__); + + if (ep0_endpoint) + ep0_endpoint->endpoint_address = 0xff; + + /* Sync sw and hw addresses */ + writeb(udc_device->address, &musbr->faddr); + + SET_EP0_STATE(IDLE); +} + +static void musb_peri_resume(void) +{ + /* noop */ +} + +static void musb_peri_ep0_stall(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_SENDSTALL; + writew(csr0, &musbr->ep[0].ep0.csr0); + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s stall\n", __PRETTY_FUNCTION__); +} + +static void musb_peri_ep0_ack_req(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_SVDRXPKTRDY; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_ep0_tx_ready(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_TXPKTRDY; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_ep0_tx_ready_and_last(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND); + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_peri_ep0_last(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_DATAEND; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_peri_ep0_set_address(void) +{ + u8 faddr; + writeb(udc_device->address, &musbr->faddr); + + /* Verify */ + faddr = readb(&musbr->faddr); + if (udc_device->address == faddr) { + SET_EP0_STATE(IDLE); + usbd_device_event_irq(udc_device, DEVICE_ADDRESS_ASSIGNED, 0); + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s Address set to %d\n", + __PRETTY_FUNCTION__, udc_device->address); + } else { + if (debug_level > 0) + serial_printf("ERROR : %s Address missmatch " + "sw %d vs hw %d\n", + __PRETTY_FUNCTION__, + udc_device->address, faddr); + } +} + +static void musb_peri_rx_ack(unsigned int ep) +{ + u16 peri_rxcsr; + + peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr); + peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY; + writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr); +} + +static void musb_peri_tx_ready(unsigned int ep) +{ + u16 peri_txcsr; + + peri_txcsr = readw(&musbr->ep[ep].epN.txcsr); + peri_txcsr |= MUSB_TXCSR_TXPKTRDY; + writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); +} + +static void musb_peri_ep0_zero_data_request(int err) +{ + musb_peri_ep0_ack_req(); + + if (err) { + musb_peri_ep0_stall(); + SET_EP0_STATE(IDLE); + } else { + + musb_peri_ep0_last(); + + /* USBD state */ + switch (ep0_urb->device_request.bRequest) { + case USB_REQ_SET_ADDRESS: + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s received set " + "address\n", __PRETTY_FUNCTION__); + break; + + case USB_REQ_SET_CONFIGURATION: + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s Configured\n", + __PRETTY_FUNCTION__); + usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); + break; + } + + /* EP0 state */ + if (USB_REQ_SET_ADDRESS == ep0_urb->device_request.bRequest) { + SET_EP0_STATE(SET_ADDRESS); + } else { + SET_EP0_STATE(IDLE); + } + } +} + +static void musb_peri_ep0_rx_data_request(void) +{ + /* + * This is the completion of the data OUT / RX + * + * Host is sending data to ep0 that is not + * part of setup. This comes from the cdc_recv_setup + * op that is device specific. + * + */ + musb_peri_ep0_ack_req(); + + ep0_endpoint->rcv_urb = ep0_urb; + ep0_urb->actual_length = 0; + SET_EP0_STATE(RX); +} + +static void musb_peri_ep0_tx_data_request(int err) +{ + if (err) { + musb_peri_ep0_stall(); + SET_EP0_STATE(IDLE); + } else { + musb_peri_ep0_ack_req(); + + ep0_endpoint->tx_urb = ep0_urb; + ep0_endpoint->sent = 0; + SET_EP0_STATE(TX); + } +} + +static void musb_peri_ep0_idle(void) +{ + u16 count0; + int err; + u16 csr0; + + /* + * Verify addresses + * A lot of confusion can be caused if the address + * in software, udc layer, does not agree with the + * hardware. Since the setting of the hardware address + * must be set after the set address request, the + * usb state machine is out of sync for a few frame. + * It is a good idea to run this check when changes + * are made to the state machine. + */ + if ((debug_level > 0) && + (ep0_state != SET_ADDRESS)) { + u8 faddr; + + faddr = readb(&musbr->faddr); + if (udc_device->address != faddr) { + serial_printf("ERROR : %s addresses do not" + "match sw %d vs hw %d\n", + __PRETTY_FUNCTION__, + udc_device->address, faddr); + udelay(1000 * 1000); + hang(); + } + } + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + if (!(MUSB_CSR0_RXPKTRDY & csr0)) + goto end; + + count0 = readw(&musbr->ep[0].ep0.count0); + if (count0 == 0) + goto end; + + if (count0 != 8) { + if ((debug_setup) && (debug_level > 1)) + serial_printf("WARN : %s SETUP incorrect size %d\n", + __PRETTY_FUNCTION__, count0); + musb_peri_ep0_stall(); + goto end; + } + + read_fifo(0, count0, &ep0_urb->device_request); + + if (debug_level > 2) + print_usb_device_request(&ep0_urb->device_request); + + if (ep0_urb->device_request.wLength == 0) { + err = ep0_recv_setup(ep0_urb); + + /* Zero data request */ + musb_peri_ep0_zero_data_request(err); + } else { + /* Is data coming or going ? */ + u8 reqType = ep0_urb->device_request.bmRequestType; + + if (USB_REQ_DEVICE2HOST == (reqType & USB_REQ_DIRECTION_MASK)) { + err = ep0_recv_setup(ep0_urb); + /* Device to host */ + musb_peri_ep0_tx_data_request(err); + } else { + /* + * Host to device + * + * The RX routine will call ep0_recv_setup + * when the data packet has arrived. + */ + musb_peri_ep0_rx_data_request(); + } + } + +end: + return; +} + +static void musb_peri_ep0_rx(void) +{ + /* + * This is the completion of the data OUT / RX + * + * Host is sending data to ep0 that is not + * part of setup. This comes from the cdc_recv_setup + * op that is device specific. + * + * Pass the data back to driver ep0_recv_setup which + * should give the cdc_recv_setup the chance to handle + * the rx + */ + u16 csr0; + u16 count0; + + if (debug_level > 3) { + if (0 != ep0_urb->actual_length) { + serial_printf("%s finished ? %d of %d\n", + __PRETTY_FUNCTION__, + ep0_urb->actual_length, + ep0_urb->device_request.wLength); + } + } + + if (ep0_urb->device_request.wLength == ep0_urb->actual_length) { + musb_peri_ep0_last(); + SET_EP0_STATE(IDLE); + ep0_recv_setup(ep0_urb); + return; + } + + csr0 = readw(&musbr->ep[0].ep0.csr0); + if (!(MUSB_CSR0_RXPKTRDY & csr0)) + return; + + count0 = readw(&musbr->ep[0].ep0.count0); + + if (count0) { + struct usb_endpoint_instance *endpoint; + u32 length; + u8 *data; + + endpoint = ep0_endpoint; + if (endpoint && endpoint->rcv_urb) { + struct urb *urb = endpoint->rcv_urb; + unsigned int remaining_space = urb->buffer_length - + urb->actual_length; + + if (remaining_space) { + int urb_bad = 0; /* urb is good */ + + if (count0 > remaining_space) + length = remaining_space; + else + length = count0; + + data = (u8 *) urb->buffer_data; + data += urb->actual_length; + + /* The common musb fifo reader */ + read_fifo(0, length, data); + + musb_peri_ep0_ack_req(); + + /* + * urb's actual_length is updated in + * usbd_rcv_complete + */ + usbd_rcv_complete(endpoint, length, urb_bad); + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s no space in " + "rcv buffer\n", + __PRETTY_FUNCTION__); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s problem with " + "endpoint\n", + __PRETTY_FUNCTION__); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s with nothing to do\n", + __PRETTY_FUNCTION__); + } +} + +static void musb_peri_ep0_tx(void) +{ + u16 csr0; + int transfer_size = 0; + unsigned int p, pm; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + /* Check for pending tx */ + if (csr0 & MUSB_CSR0_TXPKTRDY) + goto end; + + /* Check if this is the last packet sent */ + if (ep0_endpoint->sent >= ep0_urb->actual_length) { + SET_EP0_STATE(IDLE); + goto end; + } + + transfer_size = ep0_urb->actual_length - ep0_endpoint->sent; + /* Is the transfer size negative ? */ + if (transfer_size <= 0) { + if (debug_level > 0) + serial_printf("ERROR : %s problem with the" + " transfer size %d\n", + __PRETTY_FUNCTION__, + transfer_size); + SET_EP0_STATE(IDLE); + goto end; + } + + /* Truncate large transfers to the fifo size */ + if (transfer_size > ep0_endpoint->tx_packetSize) + transfer_size = ep0_endpoint->tx_packetSize; + + write_fifo(0, transfer_size, &ep0_urb->buffer[ep0_endpoint->sent]); + ep0_endpoint->sent += transfer_size; + + /* Done or more to send ? */ + if (ep0_endpoint->sent >= ep0_urb->actual_length) + musb_ep0_tx_ready_and_last(); + else + musb_ep0_tx_ready(); + + /* Wait a bit */ + pm = 10; + for (p = 0; p < pm; p++) { + csr0 = readw(&musbr->ep[0].ep0.csr0); + if (!(csr0 & MUSB_CSR0_TXPKTRDY)) + break; + + /* Double the delay. */ + udelay(1 << pm); + } + + if ((ep0_endpoint->sent >= ep0_urb->actual_length) && (p < pm)) + SET_EP0_STATE(IDLE); + +end: + return; +} + +static void musb_peri_ep0(void) +{ + u16 csr0; + + if (SET_ADDRESS == ep0_state) + return; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + /* Error conditions */ + if (MUSB_CSR0_P_SENTSTALL & csr0) { + csr0 &= ~MUSB_CSR0_P_SENTSTALL; + writew(csr0, &musbr->ep[0].ep0.csr0); + SET_EP0_STATE(IDLE); + } + if (MUSB_CSR0_P_SETUPEND & csr0) { + csr0 |= MUSB_CSR0_P_SVDSETUPEND; + writew(csr0, &musbr->ep[0].ep0.csr0); + SET_EP0_STATE(IDLE); + if ((debug_setup) && (debug_level > 1)) + serial_printf("WARN: %s SETUPEND\n", + __PRETTY_FUNCTION__); + } + + /* Normal states */ + if (IDLE == ep0_state) + musb_peri_ep0_idle(); + + if (TX == ep0_state) + musb_peri_ep0_tx(); + + if (RX == ep0_state) + musb_peri_ep0_rx(); +} + +static void musb_peri_rx_ep(unsigned int ep) +{ + u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount); + + if (peri_rxcount) { + struct usb_endpoint_instance *endpoint; + u32 length; + u8 *data; + + endpoint = GET_ENDPOINT(udc_device, ep); + if (endpoint && endpoint->rcv_urb) { + struct urb *urb = endpoint->rcv_urb; + unsigned int remaining_space = urb->buffer_length - + urb->actual_length; + + if (remaining_space) { + int urb_bad = 0; /* urb is good */ + + if (peri_rxcount > remaining_space) + length = remaining_space; + else + length = peri_rxcount; + + data = (u8 *) urb->buffer_data; + data += urb->actual_length; + + /* The common musb fifo reader */ + read_fifo(ep, length, data); + + musb_peri_rx_ack(ep); + + /* + * urb's actual_length is updated in + * usbd_rcv_complete + */ + usbd_rcv_complete(endpoint, length, urb_bad); + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d no space " + "in rcv buffer\n", + __PRETTY_FUNCTION__, ep); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d problem with " + "endpoint\n", + __PRETTY_FUNCTION__, ep); + } + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d with nothing to do\n", + __PRETTY_FUNCTION__, ep); + } +} + +static void musb_peri_rx(u16 intr) +{ + unsigned int ep; + + /* Check for EP0 */ + if (0x01 & intr) + musb_peri_ep0(); + + for (ep = 1; ep < 16; ep++) { + if ((1 << ep) & intr) + musb_peri_rx_ep(ep); + } +} + +static void musb_peri_tx(u16 intr) +{ + /* Check for EP0 */ + if (0x01 & intr) + musb_peri_ep0_tx(); + + /* + * Use this in the future when handling epN tx + * + * u8 ep; + * + * for (ep = 1; ep < 16; ep++) { + * if ((1 << ep) & intr) { + * / * handle tx for this endpoint * / + * } + * } + */ +} + +void udc_irq(void) +{ + /* This is a high freq called function */ + if (enabled) { + u8 intrusb; + + intrusb = readb(&musbr->intrusb); + + /* + * See drivers/usb/gadget/mpc8xx_udc.c for + * state diagram going from detached through + * configuration. + */ + if (MUSB_INTR_RESUME & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_ACTIVITY, 0); + musb_peri_resume(); + } + + musb_peri_ep0(); + + if (MUSB_INTR_RESET & intrusb) { + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + musb_peri_reset(); + } + + if (MUSB_INTR_DISCONNECT & intrusb) { + /* cable unplugged from hub/host */ + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + musb_peri_reset(); + usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); + } + + if (MUSB_INTR_SOF & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_ACTIVITY, 0); + musb_peri_resume(); + } + + if (MUSB_INTR_SUSPEND & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_INACTIVE, 0); + } + + if (ep0_state != SET_ADDRESS) { + u16 intrrx, intrtx; + + intrrx = readw(&musbr->intrrx); + intrtx = readw(&musbr->intrtx); + + if (intrrx) + musb_peri_rx(intrrx); + + if (intrtx) + musb_peri_tx(intrtx); + } else { + if (MUSB_INTR_SOF & intrusb) { + u8 faddr; + faddr = readb(&musbr->faddr); + /* + * Setting of the address can fail. + * Normally it succeeds the second time. + */ + if (udc_device->address != faddr) + musb_peri_ep0_set_address(); + } + } + } +} + +void udc_set_nak(int ep_num) +{ + /* noop */ +} + +void udc_unset_nak(int ep_num) +{ + /* noop */ +} + +int udc_endpoint_write(struct usb_endpoint_instance *endpoint) +{ + int ret = 0; + + /* Transmit only if the hardware is available */ + if (endpoint->tx_urb && endpoint->state == 0) { + unsigned int ep = endpoint->endpoint_address & + USB_ENDPOINT_NUMBER_MASK; + + u16 peri_txcsr = readw(&musbr->ep[ep].epN.txcsr); + + /* Error conditions */ + if (peri_txcsr & MUSB_TXCSR_P_UNDERRUN) { + peri_txcsr &= ~MUSB_TXCSR_P_UNDERRUN; + writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); + } + + if (debug_level > 1) + musb_print_txcsr(peri_txcsr); + + /* Check if a packet is waiting to be sent */ + if (!(peri_txcsr & MUSB_TXCSR_TXPKTRDY)) { + u32 length; + u8 *data; + struct urb *urb = endpoint->tx_urb; + unsigned int remaining_packet = urb->actual_length - + endpoint->sent; + + if (endpoint->tx_packetSize < remaining_packet) + length = endpoint->tx_packetSize; + else + length = remaining_packet; + + data = (u8 *) urb->buffer; + data += endpoint->sent; + + /* common musb fifo function */ + write_fifo(ep, length, data); + + musb_peri_tx_ready(ep); + + endpoint->last = length; + /* usbd_tx_complete will take care of updating 'sent' */ + usbd_tx_complete(endpoint); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s Problem with urb %p " + "or ep state %d\n", + __PRETTY_FUNCTION__, + endpoint->tx_urb, endpoint->state); + } + + return ret; +} + +void udc_setup_ep(struct usb_device_instance *device, unsigned int id, + struct usb_endpoint_instance *endpoint) +{ + if (0 == id) { + /* EP0 */ + ep0_endpoint = endpoint; + ep0_endpoint->endpoint_address = 0xff; + ep0_urb = usbd_alloc_urb(device, endpoint); + } else if (MAX_ENDPOINT >= id) { + int ep_addr; + + /* Check the direction */ + ep_addr = endpoint->endpoint_address; + if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) { + /* IN */ + epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize; + } else { + /* OUT */ + epinfo[id * 2].epsize = endpoint->rcv_packetSize; + } + + musb_configure_ep(&epinfo[0], + sizeof(epinfo) / sizeof(struct musb_epinfo)); + } else { + if (debug_level > 0) + serial_printf("ERROR : %s endpoint request %d " + "exceeds maximum %d\n", + __PRETTY_FUNCTION__, id, MAX_ENDPOINT); + } +} + +void udc_connect(void) +{ + /* noop */ +} + +void udc_disconnect(void) +{ + /* noop */ +} + +void udc_enable(struct usb_device_instance *device) +{ + /* Save the device structure pointer */ + udc_device = device; + + enabled = 1; +} + +void udc_disable(void) +{ + enabled = 0; +} + +void udc_startup_events(struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq(device, DEVICE_INIT, 0); + + /* + * The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq(device, DEVICE_CREATE, 0); + + /* Resets the address to 0 */ + usbd_device_event_irq(device, DEVICE_RESET, 0); + + udc_enable(device); +} + +int udc_init(void) +{ + int ret; + int ep_loop; + + ret = musb_platform_init(); + if (ret < 0) + goto end; + + /* Configure all the endpoint FIFO's and start usb controller */ + musbr = musb_cfg.regs; + + /* Initialize the endpoints */ + for (ep_loop = 0; ep_loop < MAX_ENDPOINT * 2; ep_loop++) { + epinfo[ep_loop].epnum = (ep_loop / 2) + 1; + epinfo[ep_loop].epdir = ep_loop % 2; /* OUT, IN */ + epinfo[ep_loop].epsize = 0; + } + + musb_peri_softconnect(); + + ret = 0; +end: + + return ret; +} diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c new file mode 100644 index 000000000..3e502e7d8 --- /dev/null +++ b/drivers/usb/musb/omap3.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This is file is based on + * repository git.gitorious.org/u-boot-omap3/mainline.git, + * branch omap3-dev-usb, file drivers/usb/host/omap3530_usb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------ + * + * Copyright (c) 2009 Texas Instruments + * + * ------------------------------------------------------------------------ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "omap3.h" + +static int platform_needs_initialization = 1; + +struct musb_config musb_cfg = { + (struct musb_regs *)MENTOR_USB0_BASE, + OMAP3_USB_TIMEOUT, + 0 +}; + +/* + * OMAP3 USB OTG registers. + */ +struct omap3_otg_regs { + u32 revision; + u32 sysconfig; + u32 sysstatus; + u32 interfsel; + u32 simenable; + u32 forcestdby; +}; + +static struct omap3_otg_regs *otg; + +#define OMAP3_OTG_SYSCONFIG_SMART_STANDBY_MODE 0x2000 +#define OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE 0x1000 +#define OMAP3_OTG_SYSCONFIG_SMART_IDLE_MODE 0x0010 +#define OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE 0x0008 +#define OMAP3_OTG_SYSCONFIG_ENABLEWAKEUP 0x0004 +#define OMAP3_OTG_SYSCONFIG_SOFTRESET 0x0002 +#define OMAP3_OTG_SYSCONFIG_AUTOIDLE 0x0001 + +#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001 + +#define OMAP3_OTG_INTERFSEL_OMAP 0x0001 + +#define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001 + + +#ifdef DEBUG_MUSB_OMAP3 +static void musb_db_otg_regs(void) +{ + u32 l; + l = readl(&otg->revision); + serial_printf("OTG_REVISION 0x%x\n", l); + l = readl(&otg->sysconfig); + serial_printf("OTG_SYSCONFIG 0x%x\n", l); + l = readl(&otg->sysstatus); + serial_printf("OTG_SYSSTATUS 0x%x\n", l); + l = readl(&otg->interfsel); + serial_printf("OTG_INTERFSEL 0x%x\n", l); + l = readl(&otg->forcestdby); + serial_printf("OTG_FORCESTDBY 0x%x\n", l); +} +#endif + +int musb_platform_init(void) +{ + int ret = -1; + + if (platform_needs_initialization) { + u32 stdby; + + if (twl4030_usb_ulpi_init()) { + serial_printf("ERROR: %s Could not initialize PHY\n", + __PRETTY_FUNCTION__); + goto end; + } + + otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE; + + /* Set OTG to always be on */ + writel(OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE | + OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE, &otg->sysconfig); + + /* Set the interface */ + writel(OMAP3_OTG_INTERFSEL_OMAP, &otg->interfsel); + + /* Clear force standby */ + stdby = readl(&otg->forcestdby); + stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY; + writel(stdby, &otg->forcestdby); + + platform_needs_initialization = 0; + } + + ret = platform_needs_initialization; +end: + return ret; + +} + +void musb_platform_deinit(void) +{ + /* noop */ +} diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h new file mode 100644 index 000000000..20fc9d294 --- /dev/null +++ b/drivers/usb/musb/omap3.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This file is based on the file drivers/usb/musb/davinci.h + * + * This is the unique part of its copyright: + * + * -------------------------------------------------------------------- + * + * Copyright (c) 2008 Texas Instruments + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + * + * -------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUSB_OMAP3_H_ +#define _MUSB_OMAP3_H_ + +#include "musb_core.h" + +/* Base address of MUSB registers */ +#define MENTOR_USB0_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) + +/* Base address of OTG registers */ +#define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400) + +/* Timeout for USB module */ +#define OMAP3_USB_TIMEOUT 0x3FFFFFF + +int musb_platform_init(void); + +#endif /* _MUSB_OMAP3_H */ + diff --git a/include/usb.h b/include/usb.h index 4148d67e1..1cc3e4229 100644 --- a/include/usb.h +++ b/include/usb.h @@ -131,7 +131,8 @@ struct usb_device { #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ - defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) + defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \ + defined(CONFIG_USB_OMAP3) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); diff --git a/include/usb/musb_udc.h b/include/usb/musb_udc.h new file mode 100644 index 000000000..ef37dbbcc --- /dev/null +++ b/include/usb/musb_udc.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MUSB_UDC_H__ +#define __MUSB_UDC_H__ + +#include + +/* UDC level routines */ +void udc_irq(void); +void udc_set_nak(int ep_num); +void udc_unset_nak(int ep_num); +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); +void udc_setup_ep(struct usb_device_instance *device, unsigned int id, + struct usb_endpoint_instance *endpoint); +void udc_connect(void); +void udc_disconnect(void); +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); +void udc_startup_events(struct usb_device_instance *device); +int udc_init(void); + +/* usbtty */ +#ifdef CONFIG_USB_TTY + +#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */ +#define UDC_INT_ENDPOINT 1 +#define UDC_INT_PACKET_SIZE 64 +#define UDC_OUT_ENDPOINT 2 +#define UDC_OUT_PACKET_SIZE 64 +#define UDC_IN_ENDPOINT 3 +#define UDC_IN_PACKET_SIZE 64 +#define UDC_BULK_PACKET_SIZE 64 + +#endif /* CONFIG_USB_TTY */ + +#endif /* __MUSB_UDC_H__ */ + -- cgit v1.2.3