From 3814ea4f0002536ac592480b2cdafa319a16e329 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 14 Oct 2009 19:27:26 -0400 Subject: Blackfin: TWI/I2C: add timeout to transfer The current transfer code relies on ctrlc() to abort transfers, but this requires user interactivity. Naturalize the process with a timeout. Signed-off-by: Mike Frysinger --- drivers/i2c/bfin-twi_i2c.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index e79063407..5ef30beca 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -60,6 +60,9 @@ struct i2c_msg { u8 *abuf; /* addr buffer */ }; +/* Allow msec timeout per ~byte transfer */ +#define I2C_TIMEOUT 10 + /** * wait_for_completion - manage the actual i2c transfer * @msg: the i2c msg @@ -67,8 +70,9 @@ struct i2c_msg { static int wait_for_completion(struct i2c_msg *msg) { uint16_t int_stat; + ulong timebase = get_timer(0); - while (!ctrlc()) { + do { int_stat = bfin_read_TWI_INT_STAT(); if (int_stat & XMTSERV) { @@ -103,7 +107,7 @@ static int wait_for_completion(struct i2c_msg *msg) debugi("processing MERR"); bfin_write_TWI_INT_STAT(MERR); SSYNC(); - break; + return msg->len; } if (int_stat & MCOMP) { debugi("processing MCOMP"); @@ -116,7 +120,12 @@ static int wait_for_completion(struct i2c_msg *msg) } else break; } - } + + /* If we were able to do something, reset timeout */ + if (int_stat) + timebase = get_timer(0); + + } while (get_timer(timebase) < I2C_TIMEOUT); return msg->len; } -- cgit v1.2.3 From 08a1c6258c2a04cead33eac50d96ea89979dcb94 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 14 Oct 2009 19:27:27 -0400 Subject: Blackfin: TWI/I2C: implement bus speed get/set functions While we're here, improve the speed calculation a bit to match the HRM. Signed-off-by: Mike Frysinger --- drivers/i2c/bfin-twi_i2c.c | 59 +++++++++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index 5ef30beca..73a78d223 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -26,6 +26,7 @@ #ifdef TWI0_CLKDIV #define bfin_write_TWI_CLKDIV(val) bfin_write_TWI0_CLKDIV(val) +#define bfin_read_TWI_CLKDIV(val) bfin_read_TWI0_CLKDIV(val) #define bfin_write_TWI_CONTROL(val) bfin_write_TWI0_CONTROL(val) #define bfin_read_TWI_CONTROL(val) bfin_read_TWI0_CONTROL(val) #define bfin_write_TWI_MASTER_ADDR(val) bfin_write_TWI0_MASTER_ADDR(val) @@ -44,8 +45,21 @@ #ifdef CONFIG_TWICLK_KHZ # error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED #endif -#if CONFIG_SYS_I2C_SPEED > 400000 -# error The Blackfin I2C hardware can only operate at 400KHz max + +/* + * The way speed is changed into duty often results in integer truncation + * with 50% duty, so we'll force rounding up to the next duty by adding 1 + * to the max. In practice this will get us a speed of something like + * 385 KHz. The other limit is easy to handle as it is only 8 bits. + */ +#define I2C_SPEED_MAX 400000 +#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) +#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) +#define I2C_DUTY_MIN 0xff /* 8 bit limited */ +#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) +/* Note: duty is inverse of speed, so the comparisons below are correct */ +#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN +# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" #endif /* All transfers are described by this data structure */ @@ -213,7 +227,36 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, return ret; } -/* +/** + * i2c_set_bus_speed - set i2c bus speed + * @speed: bus speed (in HZ) + */ +int i2c_set_bus_speed(unsigned int speed) +{ + u16 clkdiv = I2C_SPEED_TO_DUTY(speed); + + /* Set TWI interface clock */ + if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) + return -1; + bfin_write_TWI_CLKDIV((clkdiv << 8) | (clkdiv & 0xff)); + + /* Don't turn it on */ + bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + + return 0; +} + +/** + * i2c_get_bus_speed - get i2c bus speed + * @speed: bus speed (in HZ) + */ +unsigned int i2c_get_bus_speed(void) +{ + /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ + return 5000000 / (bfin_read_TWI_CLKDIV() & 0xff); +} + +/** * i2c_init - initialize the i2c bus * @speed: bus speed (in HZ) * @slaveaddr: address of device in slave mode (0 - not slave) @@ -229,15 +272,9 @@ void i2c_init(int speed, int slaveaddr) bfin_write_TWI_CONTROL(prescale); /* Set TWI interface clock as specified */ - bfin_write_TWI_CLKDIV( - ((5 * 1024 / (speed / 1000)) << 8) | - ((5 * 1024 / (speed / 1000)) & 0xFF) - ); - - /* Don't turn it on */ - bfin_write_TWI_MASTER_CTL(speed > 100000 ? FAST : 0); + i2c_set_bus_speed(speed); - /* But enable it */ + /* Enable it */ bfin_write_TWI_CONTROL(TWI_ENA | prescale); SSYNC(); -- cgit v1.2.3 From 08ea550eef310e9d59d83f3cfd57a902373bf17f Mon Sep 17 00:00:00 2001 From: Valentin Yakovenkov Date: Mon, 26 Oct 2009 18:49:06 -0400 Subject: new PCA9564 i2c bridge driver Signed-off-by: Valentin Yakovenkov Signed-off-by: Mike Frysinger --- drivers/i2c/Makefile | 1 + drivers/i2c/pca9564_i2c.c | 189 ++++++++++++++++++++++++++++++++++++++++++++++ include/pca9564.h | 50 ++++++++++++ 3 files changed, 240 insertions(+) create mode 100644 drivers/i2c/pca9564_i2c.c create mode 100644 include/pca9564.h (limited to 'drivers') diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 4a12976e3..b860e89f8 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -33,6 +33,7 @@ COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o +COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o diff --git a/drivers/i2c/pca9564_i2c.c b/drivers/i2c/pca9564_i2c.c new file mode 100644 index 000000000..199a9ee39 --- /dev/null +++ b/drivers/i2c/pca9564_i2c.c @@ -0,0 +1,189 @@ +/* + * File: drivers/i2c/pca9564.c + * Based on: drivers/i2c/s3c44b0_i2c.c + * Author: + * + * Created: 2009-06-23 + * Description: PCA9564 i2c bridge driver + * + * Modified: + * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ + * + * Bugs: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include + +#define PCA_STA (CONFIG_PCA9564_BASE + 0) +#define PCA_TO (CONFIG_PCA9564_BASE + 0) +#define PCA_DAT (CONFIG_PCA9564_BASE + (1 << 2)) +#define PCA_ADR (CONFIG_PCA9564_BASE + (2 << 2)) +#define PCA_CON (CONFIG_PCA9564_BASE + (3 << 2)) + +static unsigned char pca_read_reg(unsigned int reg) +{ + return readb((void *)reg); +} + +static void pca_write_reg(unsigned int reg, unsigned char value) +{ + writeb(value, (void *)reg); +} + +static int pca_wait_busy(void) +{ + unsigned int timeout = 10000; + + while (!(pca_read_reg(PCA_CON) & PCA_CON_SI) && --timeout) + udelay(1); + + if (timeout == 0) + debug("I2C timeout!\n"); + + debug("CON = 0x%02x, STA = 0x%02x\n", pca_read_reg(PCA_CON), + pca_read_reg(PCA_STA)); + + return timeout ? 0 : 1; +} + +/*=====================================================================*/ +/* Public Functions */ +/*=====================================================================*/ + +/*----------------------------------------------------------------------- + * Initialization + */ +void i2c_init(int speed, int slaveaddr) +{ + pca_write_reg(PCA_CON, PCA_CON_ENSIO | speed); +} + +/* + * Probe the given I2C chip address. Returns 0 if a chip responded, + * not 0 on failure. + */ + +int i2c_probe(uchar chip) +{ + unsigned char res; + + pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO); + pca_wait_busy(); + + pca_write_reg(PCA_CON, PCA_CON_STA | PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1) | 1); + res = pca_wait_busy(); + + if ((res == 0) && (pca_read_reg(PCA_STA) == 0x48)) + res = 1; + + pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO); + + return res; +} + +/* + * Read/Write interface: + * chip: I2C chip address, range 0..127 + * addr: Memory (register) address within the chip + * alen: Number of bytes to use for addr (typically 1, 2 for larger + * memories, 0 for register type devices with only one + * register) + * buffer: Where to read/write the data + * len: How many bytes to read/write + * + * Returns: 0 on success, not 0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1)); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + if (alen > 0) { + pca_write_reg(PCA_DAT, addr); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO); + + udelay(500); + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, (chip << 1) | 1); + pca_wait_busy(); + + for (i = 0; i < len; ++i) { + if (i == len - 1) + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + else + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_AA); + + pca_wait_busy(); + buffer[i] = pca_read_reg(PCA_DAT); + + } + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STO); + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int i; + + pca_write_reg(PCA_CON, PCA_CON_ENSIO | PCA_CON_STA); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + pca_write_reg(PCA_DAT, chip << 1); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + + if (alen > 0) { + pca_write_reg(PCA_DAT, addr); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + for (i = 0; i < len; ++i) { + pca_write_reg(PCA_DAT, buffer[i]); + pca_wait_busy(); + pca_write_reg(PCA_CON, PCA_CON_ENSIO); + } + + pca_write_reg(PCA_CON, PCA_CON_STO | PCA_CON_ENSIO); + + return 0; +} diff --git a/include/pca9564.h b/include/pca9564.h new file mode 100644 index 000000000..3e75259e0 --- /dev/null +++ b/include/pca9564.h @@ -0,0 +1,50 @@ +/* + * File: include/pca9564.h + * Author: + * + * Created: 2009-06-23 + * Description: PCA9564 i2c bridge driver + * + * Modified: + * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ + * + * Bugs: + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PCA9564_H +#define _PCA9564_H + +/* Clock speeds for the bus */ +#define PCA_CON_330kHz 0x00 +#define PCA_CON_288kHz 0x01 +#define PCA_CON_217kHz 0x02 +#define PCA_CON_146kHz 0x03 +#define PCA_CON_88kHz 0x04 +#define PCA_CON_59kHz 0x05 +#define PCA_CON_44kHz 0x06 +#define PCA_CON_36kHz 0x07 + +#define PCA_CON_AA 0x80 /* Assert Acknowledge */ +#define PCA_CON_ENSIO 0x40 /* Enable */ +#define PCA_CON_STA 0x20 /* Start */ +#define PCA_CON_STO 0x10 /* Stop */ +#define PCA_CON_SI 0x08 /* Serial Interrupt */ +#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */ + +#endif + -- cgit v1.2.3 From c28d3bbe963f4c57937d6fdc1dd63cd3562c147c Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 23 Oct 2009 12:03:13 +0200 Subject: video: mb862xx: improve board-specific Lime configuration To avoid board-specific code accessing the mb862xx registers directly, the public function mb862xx_probe() has been introduced. Furthermore, the "Change of Clock Frequency" and "Set Memory I/F Mode" registers are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR, respectively. The BSPs for the socrates and lwmon5 boards have been adapted accordingly. Signed-off-by: Wolfgang Grandegger --- board/lwmon5/lwmon5.c | 7 ------- board/socrates/socrates.c | 46 +++++++--------------------------------------- drivers/video/mb862xx.c | 34 +++++++++++++++++++++++++++++++++- include/configs/lwmon5.h | 10 ++++------ include/configs/socrates.h | 5 +++++ include/mb862xx.h | 5 +++++ 6 files changed, 54 insertions(+), 53 deletions(-) (limited to 'drivers') diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index ef7f2e8dc..d36ea04e8 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -532,13 +532,6 @@ unsigned int board_video_init (void) udelay(500); gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1); - /* Lime memory clock adjusted to 100MHz */ - out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ); - /* Wait untill time expired. Because of requirements in lime manual */ - udelay(300); - /* Write lime controller memory parameters */ - out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); - mb862xx.winSizeX = 640; mb862xx.winSizeY = 480; mb862xx.gdfBytesPP = 2; diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 51d66d517..9183c15f2 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -268,17 +268,6 @@ ft_board_setup(void *blob, bd_t *bd) } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -#define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C) -#define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038) -#define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC) -/* Lime clock frequency */ -#define CONFIG_SYS_LIME_CLK_100MHZ 0x00000 -#define CONFIG_SYS_LIME_CLK_133MHZ 0x10000 -/* SDRAM parameter */ -#define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63 - -#define DISPLAY_WIDTH 800 -#define DISPLAY_HEIGHT 480 #define DEFAULT_BRIGHTNESS 25 #define BACKLIGHT_ENABLE (1 << 31) @@ -308,14 +297,12 @@ const gdc_regs *board_get_regs (void) return init_regs; } -#define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0) -#define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084) int lime_probe(void) { volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); uint cfg_br2; uint cfg_or2; - uint reg; + int type; cfg_br2 = memctl->br2; cfg_or2 = memctl->or2; @@ -325,21 +312,15 @@ int lime_probe(void) memctl->or2 = 0xfc000410; memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901; - /* Try to access GDC ID/Revision registers */ - reg = in_be32((void *)CONFIG_SYS_LIME_CID); - reg = in_be32((void *)CONFIG_SYS_LIME_CID); - if (reg == 0x303) { - reg = in_be32((void *)CONFIG_SYS_LIME_REV); - reg = in_be32((void *)CONFIG_SYS_LIME_REV); - reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0; - } else - reg = 0; + /* Get controller type */ + type = mb862xx_probe(CONFIG_SYS_LIME_BASE); /* Restore previous CS2 configuration */ memctl->br2 = 0; memctl->or2 = cfg_or2; memctl->br2 = cfg_br2; - return reg; + + return (type == MB862XX_TYPE_LIME) ? 1 : 0; } /* Returns Lime base address */ @@ -348,21 +329,8 @@ unsigned int board_video_init (void) if (!lime_probe()) return 0; - /* - * Reset Lime controller - */ - out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1); - udelay(200); - - /* Set Lime clock to 133MHz */ - out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ); - /* Delay required */ - udelay(300); - /* Set memory parameters */ - out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE); - - mb862xx.winSizeX = DISPLAY_WIDTH; - mb862xx.winSizeY = DISPLAY_HEIGHT; + mb862xx.winSizeX = 800; + mb862xx.winSizeY = 480; mb862xx.gdfIndex = GDF_15BIT_555RGB; mb862xx.gdfBytesPP = 2; diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index a8676cc64..bb212a852 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -340,6 +340,30 @@ unsigned int card_init (void) } #endif + +#if !defined(CONFIG_VIDEO_CORALP) +int mb862xx_probe(unsigned int addr) +{ + GraphicDevice *dev = &mb862xx; + unsigned int reg; + + dev->frameAdrs = addr; + dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; + + /* Try to access GDC ID/Revision registers */ + reg = HOST_RD_REG (GC_CID); + reg = HOST_RD_REG (GC_CID); + if (reg == 0x303) { + reg = DE_RD_REG(GC_REV); + reg = DE_RD_REG(GC_REV); + if ((reg & ~0xff) == 0x20050100) + return MB862XX_TYPE_LIME; + } + + return 0; +} +#endif + void *video_hw_init (void) { GraphicDevice *dev = &mb862xx; @@ -359,8 +383,16 @@ void *video_hw_init (void) if ((dev->frameAdrs = board_video_init ()) == 0) { puts ("Controller not found!\n"); return NULL; - } else + } else { puts ("Lime\n"); + + /* Set Change of Clock Frequency Register */ + HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF); + /* Delay required */ + udelay(300); + /* Set Memory I/F Mode Register) */ + HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR); + } #endif de_init (); diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 777a4d6cf..67434f55c 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -495,8 +495,6 @@ /*----------------------------------------------------------------------- * Graphics (Fujitsu Lime) *----------------------------------------------------------------------*/ -/* SDRAM Clock frequency adjustment register */ -#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038 /* Lime Clock frequency is to set 100MHz */ #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000 #if 0 @@ -504,15 +502,15 @@ #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000 #endif -/* SDRAM Parameter register */ -#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars and pixel flare on display when 133MHz was configured. According to SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */ #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ #else -#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2 +#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2 +#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ #endif /*----------------------------------------------------------------------- diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 35feed0fe..3321aa24e 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -210,6 +210,11 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ +/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ +#define CONFIG_SYS_MB862xx_CCF 0x10000 +/* SDRAM parameter */ +#define CONFIG_SYS_MB862xx_MMR 0x4157BA63 + /* Serial Port */ #define CONFIG_CONS_INDEX 1 diff --git a/include/mb862xx.h b/include/mb862xx.h index 43f01e7d9..009da03f7 100644 --- a/include/mb862xx.h +++ b/include/mb862xx.h @@ -32,6 +32,8 @@ #define PCI_DEVICE_ID_CORAL_P 0x2019 #define PCI_DEVICE_ID_CORAL_PA 0x201E +#define MB862XX_TYPE_LIME 0x1 + #define GC_HOST_BASE 0x01fc0000 #define GC_DISP_BASE 0x01fd0000 #define GC_DRAW_BASE 0x01ff0000 @@ -39,6 +41,7 @@ /* Host interface registers */ #define GC_SRST 0x0000002c #define GC_CCF 0x00000038 +#define GC_CID 0x000000f0 #define GC_MMR 0x0000fffc /* @@ -99,6 +102,7 @@ #define GC_FC 0x00000480 #define GC_BC 0x00000484 #define GC_FIFO 0x000004a0 +#define GC_REV 0x00008084 #define GC_GEO_FIFO 0x00008400 typedef struct { @@ -106,6 +110,7 @@ typedef struct { unsigned int value; } gdc_regs; +int mb862xx_probe(unsigned int addr); const gdc_regs *board_get_regs (void); unsigned int board_video_init (void); void board_backlight_switch(int); -- cgit v1.2.3 From 5d16ca87100ea58c93c46b9f0264981eaed49568 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Fri, 23 Oct 2009 12:03:14 +0200 Subject: video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp mode The new IPEK01 board can use the 32 bpp mode for the Lime graphics controller. For this mode, video accelaration does not work. This patch makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL, which is enabled for the lwmon5 and the socrates board for backward compatibility. Signed-off-by: Anatolij Gustschin Signed-off-by: Wolfgang Grandegger --- drivers/video/cfb_console.c | 2 ++ drivers/video/mb862xx.c | 16 +++++++++++++++- include/configs/lwmon5.h | 1 + include/configs/socrates.h | 1 + 4 files changed, 19 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index fbc4df9f6..0df321cd4 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -146,9 +146,11 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the #ifdef CONFIG_VIDEO_CORALP #define VIDEO_FB_LITTLE_ENDIAN #endif +#ifdef CONFIG_VIDEO_MB862xx_ACCEL #define VIDEO_HW_RECTFILL #define VIDEO_HW_BITBLT #endif +#endif /*****************************************************************************/ /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */ diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index bb212a852..edf34aa06 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -89,6 +89,7 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 }; (GC_DISP_BASE | GC_L0PAL0) + \ ((idx) << 2)), (val)) +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) static void gdc_sw_reset (void) { GraphicDevice *dev = &mb862xx; @@ -129,6 +130,7 @@ static void de_wait_slots (int slots) break; } } +#endif #if !defined(CONFIG_VIDEO_CORALP) static void board_disp_init (void) @@ -144,11 +146,13 @@ static void board_disp_init (void) #endif /* - * Init drawing engine + * Init drawing engine if accel enabled. + * Also clears visible framebuffer. */ static void de_init (void) { GraphicDevice *dev = &mb862xx; +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000; dev->dprBase = dev->frameAdrs + GC_DRAW_BASE; @@ -174,6 +178,14 @@ static void de_init (void) DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX); /* sync with SW access to framebuffer */ de_wait (); +#else + unsigned int i, *p; + + i = dev->winSizeX * dev->winSizeY; + p = (unsigned int *)dev->frameAdrs; + while (i--) + *p++ = 0; +#endif } #if defined(CONFIG_VIDEO_CORALP) @@ -421,6 +433,7 @@ void video_set_lut (unsigned int index, unsigned char r, L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b)); } +#if defined(CONFIG_VIDEO_MB862xx_ACCEL) /* * Drawing engine Fill and BitBlt screen region */ @@ -462,3 +475,4 @@ void video_hw_bitblt (unsigned int bpp, unsigned int src_x, DE_WR_FIFO ((height << 16) | width); de_wait (); /* sync */ } +#endif diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 67434f55c..927b80f9e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -344,6 +344,7 @@ /* Video console */ #define CONFIG_VIDEO #define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_CONSOLE_EXTRA_INFO diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3321aa24e..59a4b2837 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -198,6 +198,7 @@ #define CONFIG_VIDEO #define CONFIG_VIDEO_MB862xx +#define CONFIG_VIDEO_MB862xx_ACCEL #define CONFIG_CFB_CONSOLE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -- cgit v1.2.3 From 229b6dce675c729ee0ea2d7b61fbcda89b23b6b8 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Fri, 23 Oct 2009 12:03:15 +0200 Subject: video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01 In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words for D32 accesses due to the diffferent connecting to the GDC bus. This patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP, which should be set for all board using the mb862xx in 16 bpp mode. For the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set. Signed-off-by: Wolfgang Grandegger --- drivers/video/cfb_console.c | 2 +- include/configs/lwmon5.h | 1 + include/configs/socrates.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 0df321cd4..16d6689f2 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -321,7 +321,7 @@ void console_cursor (int state); #else #define SWAP16(x) (x) #define SWAP32(x) (x) -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) +#if defined(VIDEO_FB_16BPP_WORD_SWAP) #define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) #else #define SHORTSWAP32(x) (x) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 927b80f9e..011dd5c81 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -349,6 +349,7 @@ #define CONFIG_VIDEO_LOGO #define CONFIG_CONSOLE_EXTRA_INFO #define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_SW_CURSOR diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 59a4b2837..3632b847f 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -204,6 +204,7 @@ #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_CONSOLE_EXTRA_INFO #define VIDEO_FB_16BPP_PIXEL_SWAP +#define VIDEO_FB_16BPP_WORD_SWAP #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_VIDEO_SW_CURSOR -- cgit v1.2.3 From aaa8eec532876c47acfd31bf9b573a00eaad92ae Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Fri, 30 Oct 2009 13:51:23 -0400 Subject: NAND: Update to support 64 bit device size This patch adds support for NANDs greater than 2 GB. Patch is based on the MTD NAND driver in the kernel. Signed-off-by: Sandeep Paulraj Signed-off-by: Scott Wood --- drivers/mtd/nand/nand_base.c | 26 ++++++++++++++++---------- drivers/mtd/nand/nand_bbt.c | 41 +++++++++++++++++++++++------------------ include/linux/mtd/nand.h | 2 +- include/linux/mtd/partitions.h | 4 ++-- 4 files changed, 42 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 426bb95e9..30a3e9e74 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2211,13 +2211,15 @@ static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt) { - int page, len, status, pages_per_block, ret, chipnr; + int page, status, pages_per_block, ret, chipnr; struct nand_chip *chip = mtd->priv; - int rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS]={0}; + loff_t rewrite_bbt[CONFIG_SYS_NAND_MAX_CHIPS] = {0}; unsigned int bbt_masked_page = 0xffffffff; + loff_t len; - MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n", - (unsigned int) instr->addr, (unsigned int) instr->len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%012llx, " + "len = %llu\n", (unsigned long long) instr->addr, + (unsigned long long) instr->len); /* Start address must align on block boundary */ if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) { @@ -2313,7 +2315,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page); instr->state = MTD_ERASE_FAILED; - instr->fail_addr = (page << chip->page_shift); + instr->fail_addr = ((loff_t)page << chip->page_shift); goto erase_exit; } @@ -2323,7 +2325,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, */ if (bbt_masked_page != 0xffffffff && (page & BBT_PAGE_MASK) == bbt_masked_page) - rewrite_bbt[chipnr] = (page << chip->page_shift); + rewrite_bbt[chipnr] = + ((loff_t)page << chip->page_shift); /* Increment page address and decrement length */ len -= (1 << chip->phys_erase_shift); @@ -2370,8 +2373,8 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, continue; /* update the BBT for chip */ MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt " - "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr], - chip->bbt_td->pages[chipnr]); + "(%d:0x%0llx 0x%0x)\n", chipnr, rewrite_bbt[chipnr], + chip->bbt_td->pages[chipnr]); nand_update_bbt(mtd, rewrite_bbt[chipnr]); } @@ -2566,7 +2569,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, if (!mtd->name) mtd->name = type->name; - chip->chipsize = type->chipsize << 20; + chip->chipsize = (uint64_t)type->chipsize << 20; /* Newer devices have all the information in additional id bytes */ if (!type->pagesize) { @@ -2624,7 +2627,10 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1; - chip->chip_shift = ffs(chip->chipsize) - 1; + if (chip->chipsize & 0xffffffff) + chip->chip_shift = ffs(chip->chipsize) - 1; + else + chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31; /* Set the bad block position */ chip->badblockpos = mtd->writesize > 512 ? diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index d68a315f1..2fe68abe1 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -182,16 +182,19 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, if (tmp == msk) continue; if (reserved_block_code && (tmp == reserved_block_code)) { - printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%08x\n", - ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + printk(KERN_DEBUG "nand_read_bbt: Reserved block at 0x%012llx\n", + (loff_t)((offs << 2) + + (act >> 1)) << + this->bbt_erase_shift); this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06); mtd->ecc_stats.bbtblocks++; continue; } /* Leave it for now, if its matured we can move this * message to MTD_DEBUG_LEVEL0 */ - printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%08x\n", - ((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n", + (loff_t)((offs << 2) + (act >> 1)) << + this->bbt_erase_shift); /* Factory marked bad or worn out ? */ if (tmp == 0) this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); @@ -295,8 +298,8 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the primary version, if available */ if (td->options & NAND_BBT_VERSION) { - scan_read_raw(mtd, buf, td->pages[0] << this->page_shift, - mtd->writesize); + scan_read_raw(mtd, buf, (loff_t)td->pages[0] << + this->page_shift, mtd->writesize); td->version[0] = buf[mtd->writesize + td->veroffs]; printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", td->pages[0], td->version[0]); @@ -304,8 +307,8 @@ static int read_abs_bbts(struct mtd_info *mtd, uint8_t *buf, /* Read the mirror version, if available */ if (md && (md->options & NAND_BBT_VERSION)) { - scan_read_raw(mtd, buf, md->pages[0] << this->page_shift, - mtd->writesize); + scan_read_raw(mtd, buf, (loff_t)md->pages[0] << + this->page_shift, mtd->writesize); md->version[0] = buf[mtd->writesize + md->veroffs]; printk(KERN_DEBUG "Bad block table at page %d, version 0x%02X\n", md->pages[0], md->version[0]); @@ -422,7 +425,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, numblocks = this->chipsize >> (this->bbt_erase_shift - 1); startblock = chip * numblocks; numblocks += startblock; - from = startblock << (this->bbt_erase_shift - 1); + from = (loff_t)startblock << (this->bbt_erase_shift - 1); } for (i = startblock; i < numblocks;) { @@ -440,8 +443,8 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf, if (ret) { this->bbt[i >> 3] |= 0x03 << (i & 0x6); MTDDEBUG (MTD_DEBUG_LEVEL0, - "Bad eraseblock %d at 0x%08x\n", - i >> 1, (unsigned int)from); + "Bad eraseblock %d at 0x%012llx\n", + i >> 1, (unsigned long long)from); mtd->ecc_stats.badblocks++; } @@ -507,7 +510,7 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr for (block = 0; block < td->maxblocks; block++) { int actblock = startblock + dir * block; - loff_t offs = actblock << this->bbt_erase_shift; + loff_t offs = (loff_t)actblock << this->bbt_erase_shift; /* Read first page */ scan_read_raw(mtd, buf, offs, mtd->writesize); @@ -731,7 +734,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, memset(&einfo, 0, sizeof(einfo)); einfo.mtd = mtd; - einfo.addr = (unsigned long)to; + einfo.addr = to; einfo.len = 1 << this->bbt_erase_shift; res = nand_erase_nand(mtd, &einfo, 1); if (res < 0) @@ -741,8 +744,9 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf, if (res < 0) goto outerr; - printk(KERN_DEBUG "Bad block table written to 0x%08x, version " - "0x%02X\n", (unsigned int)to, td->version[chip]); + printk(KERN_DEBUG "Bad block table written to 0x%012llx, " + "version 0x%02X\n", (unsigned long long)to, + td->version[chip]); /* Mark it as used */ td->pages[chip] = page; @@ -922,7 +926,8 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) newval = oldval | (0x2 << (block & 0x06)); this->bbt[(block >> 3)] = newval; if ((oldval != newval) && td->reserved_block_code) - nand_update_bbt(mtd, block << (this->bbt_erase_shift - 1)); + nand_update_bbt(mtd, (loff_t)block << + (this->bbt_erase_shift - 1)); continue; } update = 0; @@ -943,7 +948,8 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td) new ones have been marked, then we need to update the stored bbts. This should only happen once. */ if (update && td->reserved_block_code) - nand_update_bbt(mtd, (block - 2) << (this->bbt_erase_shift - 1)); + nand_update_bbt(mtd, (loff_t)(block - 2) << + (this->bbt_erase_shift - 1)); } } @@ -1039,7 +1045,6 @@ int nand_update_bbt(struct mtd_info *mtd, loff_t offs) if (!this->bbt || !td) return -EINVAL; - len = mtd->size >> (this->bbt_erase_shift + 2); /* Allocate a temporary buffer for one eraseblock incl. oob */ len = (1 << this->bbt_erase_shift); len += (len >> this->page_shift) * mtd->oobsize; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index cb7c19a43..94ad0c0e3 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -397,7 +397,7 @@ struct nand_chip { int bbt_erase_shift; int chip_shift; int numchips; - unsigned long chipsize; + uint64_t chipsize; int pagemask; int pagebuf; int subpagesize; diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index 10166757b..d1d9a96d5 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -38,8 +38,8 @@ struct mtd_partition { char *name; /* identifier string */ - u_int32_t size; /* partition size */ - u_int32_t offset; /* offset within the master MTD space */ + uint64_t size; /* partition size */ + uint64_t offset; /* offset within the master MTD space */ u_int32_t mask_flags; /* master MTD flags to mask out for this partition */ struct nand_ecclayout *ecclayout; /* out of band layout for this partition (NAND only)*/ struct mtd_info **mtdp; /* pointer to store the MTD object */ -- cgit v1.2.3 From 4f41e7ea1a17ba7207ca41379bf344b317e72c12 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 7 Nov 2009 14:24:06 -0500 Subject: NAND: Correct the "chip_shift" calculation This patch updates the "chip_shift" calculation in the NAND driver. This is being done to sync up the NAND driver with the kernel NAND driver. Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/nand_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 30a3e9e74..d5c53fed1 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2628,7 +2628,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1; if (chip->chipsize & 0xffffffff) - chip->chip_shift = ffs(chip->chipsize) - 1; + chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; else chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 31; -- cgit v1.2.3 From 36e0b98ec832bb5ec42d6e249058d5b84f75dff8 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 7 Nov 2009 14:24:20 -0500 Subject: NAND: Remove commented out code Patch removes already commented out dead code Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/nand_base.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index d5c53fed1..744663442 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2767,7 +2767,6 @@ int nand_scan_tail(struct mtd_info *mtd) default: printk(KERN_WARNING "No oob scheme defined for " "oobsize %d\n", mtd->oobsize); -/* BUG(); */ } } -- cgit v1.2.3 From aad4a28b2518e1d24ee606d9ea31f9b4dd029777 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 7 Nov 2009 14:24:34 -0500 Subject: NAND: Subpage shift for ecc_steps equal to 16 This was originally part of Thomas Gleixner's patch for adding support for 4KiB pages. This is not part of the U-Boot NAND driver so updating the driver with this to sync up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/nand_base.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 744663442..b3b2be211 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2895,6 +2895,7 @@ int nand_scan_tail(struct mtd_info *mtd) break; case 4: case 8: + case 16: mtd->subpage_sft = 2; break; } -- cgit v1.2.3 From e25ee0396226fb56679702d0361cf2645504e7f6 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 7 Nov 2009 14:24:50 -0500 Subject: NAND: Updating comments/explanations in the NAND driver Patch updates the comments and explanations for the arguments to various functions. Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/nand_base.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index b3b2be211..cfd582af9 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -893,6 +893,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read */ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page) @@ -907,6 +908,7 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read */ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page) @@ -946,9 +948,9 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function * @mtd: mtd info structure * @chip: nand chip info structure - * @dataofs offset of requested data within the page - * @readlen data length - * @buf: buffer to store read data + * @data_offs: offset of requested data within the page + * @readlen: data length + * @bufpoi: buffer to store read data */ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi) { @@ -1028,6 +1030,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3 * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read * * Not for syndrome calculating ecc controllers which need a special oob layout */ @@ -1072,6 +1075,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read * * Hardware ECC for large page chips, require OOB to be read first. * For this ECC mode, the write_page method is re-used from ECC_HW. @@ -1120,6 +1124,7 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, * @mtd: mtd info structure * @chip: nand chip info structure * @buf: buffer to store read data + * @page: page number to read * * The hw generator calculates the error syndrome automatically. Therefor * we need a special oob layout and handling. @@ -2728,7 +2733,6 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips) /** * nand_scan_tail - [NAND Interface] Scan for the NAND device * @mtd: MTD device structure - * @maxchips: Number of chips to scan for * * This is the second phase of the normal nand_scan() function. It * fills out all the uninitialized function pointers with the defaults -- cgit v1.2.3 From 18b5a4b43af3c8359cb568f4fa32d6b9dcebbf26 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 7 Nov 2009 14:25:03 -0500 Subject: NAND: Update check condition for nand_read_page_hwecc API The patch updates the check condition for determining whether the ECC corrections has failed. This makes it similar to what is in the kernel NAND driver. Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/nand_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index cfd582af9..52b0c1a76 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1062,7 +1062,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, int stat; stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); - if (stat == -1) + if (stat < 0) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; -- cgit v1.2.3 From 5df3c2b62cebaa0ddb2817364f93726e5dbe3525 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Sat, 7 Nov 2009 14:25:18 -0500 Subject: NAND: Don't walk past end of oobfree[] When computing oobavail from the list of free areas in the OOB, don't assume there will always be an unused slot at the end. This syncs up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/nand_base.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 52b0c1a76..cf032a622 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2871,7 +2871,8 @@ int nand_scan_tail(struct mtd_info *mtd) * the out of band area */ chip->ecc.layout->oobavail = 0; - for (i = 0; chip->ecc.layout->oobfree[i].length; i++) + for (i = 0; chip->ecc.layout->oobfree[i].length + && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++) chip->ecc.layout->oobavail += chip->ecc.layout->oobfree[i].length; mtd->oobavail = chip->ecc.layout->oobavail; -- cgit v1.2.3 From 7e86661cd777eec1e81c5e57c468e81138fda983 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Sat, 7 Nov 2009 16:27:01 -0500 Subject: NAND: fix "raw" reads with ECC syndrome layouts The syndrome based page read/write routines store ECC, and possibly other "OOB" data, right after each chunk of ECC'd data. With ECC chunk size of 512 bytes and a large page (2KiB) NAND, the layout is: data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines use a traditional layout -- data OOB, disregarding the prepad and postpad values -- so when they're used with that type of ECC hardware, those calls mix up the data and OOB. Which means, in particular, that bad block tables won't be found on startup, with data corruption and related chaos ensuing. The current syndrome-based drivers in mainline all seem to use one chunk per page; presumably they haven't noticed such bugs. Fix this, by adding read/write page_raw_syndrome() routines as siblings of the existing non-raw routines; "raw" just means to bypass the ECC computations, not change data and OOB layout. Signed-off-by: David Brownell Signed-off-by: Andrew Morton Signed-off-by: David Woodhouse --- drivers/mtd/nand/nand_base.c | 100 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 96 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index cf032a622..6da261c04 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -894,6 +894,8 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this) * @chip: nand chip info structure * @buf: buffer to store read data * @page: page number to read + * + * Not for syndrome calculating ecc controllers, which use a special oob layout */ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, uint8_t *buf, int page) @@ -903,6 +905,48 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, return 0; } +/** + * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + * + * We need a special oob layout and handling even when OOB isn't used. + */ +static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + uint8_t *oob = chip->oob_poi; + int steps, size; + + for (steps = chip->ecc.steps; steps > 0; steps--) { + chip->read_buf(mtd, buf, eccsize); + buf += eccsize; + + if (chip->ecc.prepad) { + chip->read_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->read_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->read_buf(mtd, oob, size); + + return 0; +} + /** * nand_read_page_swecc - [REPLACABLE] software ecc based page read function * @mtd: mtd info structure @@ -1682,6 +1726,8 @@ static int nand_read_oob(struct mtd_info *mtd, loff_t from, * @mtd: mtd info structure * @chip: nand chip info structure * @buf: data buffer + * + * Not for syndrome calculating ecc controllers, which use a special oob layout */ static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t *buf) @@ -1690,6 +1736,44 @@ static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); } +/** + * nand_write_page_raw_syndrome - [Intern] raw page write function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: data buffer + * + * We need a special oob layout and handling even when ECC isn't checked. + */ +static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf) +{ + int eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + uint8_t *oob = chip->oob_poi; + int steps, size; + + for (steps = chip->ecc.steps; steps > 0; steps--) { + chip->write_buf(mtd, buf, eccsize); + buf += eccsize; + + if (chip->ecc.prepad) { + chip->write_buf(mtd, oob, chip->ecc.prepad); + oob += chip->ecc.prepad; + } + + chip->read_buf(mtd, oob, eccbytes); + oob += eccbytes; + + if (chip->ecc.postpad) { + chip->write_buf(mtd, oob, chip->ecc.postpad); + oob += chip->ecc.postpad; + } + } + + size = mtd->oobsize - (oob - chip->oob_poi); + if (size) + chip->write_buf(mtd, oob, size); +} /** * nand_write_page_swecc - [REPLACABLE] software ecc based page write function * @mtd: mtd info structure @@ -2781,10 +2865,6 @@ int nand_scan_tail(struct mtd_info *mtd) * check ECC mode, default to software if 3byte/512byte hardware ECC is * selected and we have 256 byte pagesize fallback to software ECC */ - if (!chip->ecc.read_page_raw) - chip->ecc.read_page_raw = nand_read_page_raw; - if (!chip->ecc.write_page_raw) - chip->ecc.write_page_raw = nand_write_page_raw; switch (chip->ecc.mode) { case NAND_ECC_HW_OOB_FIRST: @@ -2804,6 +2884,10 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_hwecc; if (!chip->ecc.write_page) chip->ecc.write_page = nand_write_page_hwecc; + if (!chip->ecc.read_page_raw) + chip->ecc.read_page_raw = nand_read_page_raw; + if (!chip->ecc.write_page_raw) + chip->ecc.write_page_raw = nand_write_page_raw; if (!chip->ecc.read_oob) chip->ecc.read_oob = nand_read_oob_std; if (!chip->ecc.write_oob) @@ -2825,6 +2909,10 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_syndrome; if (!chip->ecc.write_page) chip->ecc.write_page = nand_write_page_syndrome; + if (!chip->ecc.read_page_raw) + chip->ecc.read_page_raw = nand_read_page_raw_syndrome; + if (!chip->ecc.write_page_raw) + chip->ecc.write_page_raw = nand_write_page_raw_syndrome; if (!chip->ecc.read_oob) chip->ecc.read_oob = nand_read_oob_syndrome; if (!chip->ecc.write_oob) @@ -2843,6 +2931,8 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_swecc; chip->ecc.read_subpage = nand_read_subpage; chip->ecc.write_page = nand_write_page_swecc; + chip->ecc.read_page_raw = nand_read_page_raw; + chip->ecc.write_page_raw = nand_write_page_raw; chip->ecc.read_oob = nand_read_oob_std; chip->ecc.write_oob = nand_write_oob_std; chip->ecc.size = 256; @@ -2855,6 +2945,8 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.read_page = nand_read_page_raw; chip->ecc.write_page = nand_write_page_raw; chip->ecc.read_oob = nand_read_oob_std; + chip->ecc.read_page_raw = nand_read_page_raw; + chip->ecc.write_page_raw = nand_write_page_raw; chip->ecc.write_oob = nand_write_oob_std; chip->ecc.size = mtd->writesize; chip->ecc.bytes = 0; -- cgit v1.2.3 From 35209cbceebe212a8c5ec17d552960f8bd4725f3 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 20 Oct 2009 16:58:17 +0800 Subject: fsl_elbc_nand: remove the bbt descriptors relocation fixup The commit 66372fe2 manually relocated the bbt pattern pointer, which can be removed by using full relocation. Signed-off-by: Mingkai Hu --- drivers/mtd/nand/fsl_elbc_nand.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index 50cb4aa9d..146e9bf3c 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -766,9 +766,6 @@ int board_nand_init(struct nand_chip *nand) nand->waitfunc = fsl_elbc_wait; /* set up nand options */ - /* redirect the pointer of bbt pattern to RAM */ - bbt_main_descr.pattern = bbt_pattern; - bbt_mirror_descr.pattern = mirror_pattern; nand->bbt_td = &bbt_main_descr; nand->bbt_md = &bbt_mirror_descr; @@ -815,7 +812,6 @@ int board_nand_init(struct nand_chip *nand) /* Large-page-specific setup */ if (or & OR_FCM_PGS) { priv->page_size = 1; - largepage_memorybased.pattern = scan_ff_pattern; nand->badblock_pattern = &largepage_memorybased; /* adjust ecc setup if needed */ -- cgit v1.2.3 From cacbe919584193f64e74088e03f068e52775bb86 Mon Sep 17 00:00:00 2001 From: Amul Kumar Saha Date: Fri, 6 Nov 2009 17:15:31 +0530 Subject: Flex-OneNAND driver support This patch adds support for Flex-OneNAND devices. Signed-off-by: Rohit Hagargundgi Signed-off-by: Amul Kumar Saha --- drivers/mtd/onenand/onenand_base.c | 742 +++++++++++++++++++++++++++++++----- drivers/mtd/onenand/onenand_bbt.c | 14 +- drivers/mtd/onenand/onenand_uboot.c | 4 +- include/linux/mtd/onenand.h | 16 +- include/linux/mtd/onenand_regs.h | 18 +- include/onenand_uboot.h | 10 + 6 files changed, 703 insertions(+), 101 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 368fa6ef6..f9273ab97 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -9,6 +9,11 @@ * auto-placement support, read-while load support, various fixes * Copyright (C) Nokia Corporation, 2007 * + * Rohit Hagargundgi , + * Amul Kumar Saha : + * Flex-OneNAND support + * Copyright (C) Samsung Electronics, 2009 + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -24,7 +29,7 @@ #include /* It should access 16-bit instead of 8-bit */ -static inline void *memcpy_16(void *dst, const void *src, unsigned int len) +static void *memcpy_16(void *dst, const void *src, unsigned int len) { void *ret = dst; short *d = dst; @@ -36,6 +41,27 @@ static inline void *memcpy_16(void *dst, const void *src, unsigned int len) return ret; } +/** + * onenand_oob_128 - oob info for Flex-Onenand with 4KB page + * For now, we expose only 64 out of 80 ecc bytes + */ +static struct nand_ecclayout onenand_oob_128 = { + .eccbytes = 64, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, + 102, 103, 104, 105 + }, + .oobfree = { + {2, 4}, {18, 4}, {34, 4}, {50, 4}, + {66, 4}, {82, 4}, {98, 4}, {114, 4} + } +}; + /** * onenand_oob_64 - oob info for large (2KB) page */ @@ -74,6 +100,14 @@ static const unsigned char ffchars[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 80 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 96 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 112 */ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 128 */ }; /** @@ -179,6 +213,85 @@ static int onenand_buffer_address(int dataram1, int sectors, int count) return ((bsa << ONENAND_BSA_SHIFT) | bsc); } +/** + * flexonenand_block - Return block number for flash address + * @param this - OneNAND device structure + * @param addr - Address for which block number is needed + */ +static unsigned int flexonenand_block(struct onenand_chip *this, loff_t addr) +{ + unsigned int boundary, blk, die = 0; + + if (ONENAND_IS_DDP(this) && addr >= this->diesize[0]) { + die = 1; + addr -= this->diesize[0]; + } + + boundary = this->boundary[die]; + + blk = addr >> (this->erase_shift - 1); + if (blk > boundary) + blk = (blk + boundary + 1) >> 1; + + blk += die ? this->density_mask : 0; + return blk; +} + +unsigned int onenand_block(struct onenand_chip *this, loff_t addr) +{ + if (!FLEXONENAND(this)) + return addr >> this->erase_shift; + return flexonenand_block(this, addr); +} + +/** + * flexonenand_addr - Return address of the block + * @this: OneNAND device structure + * @block: Block number on Flex-OneNAND + * + * Return address of the block + */ +static loff_t flexonenand_addr(struct onenand_chip *this, int block) +{ + loff_t ofs = 0; + int die = 0, boundary; + + if (ONENAND_IS_DDP(this) && block >= this->density_mask) { + block -= this->density_mask; + die = 1; + ofs = this->diesize[0]; + } + + boundary = this->boundary[die]; + ofs += (loff_t) block << (this->erase_shift - 1); + if (block > (boundary + 1)) + ofs += (loff_t) (block - boundary - 1) + << (this->erase_shift - 1); + return ofs; +} + +loff_t onenand_addr(struct onenand_chip *this, int block) +{ + if (!FLEXONENAND(this)) + return (loff_t) block << this->erase_shift; + return flexonenand_addr(this, block); +} + +/** + * flexonenand_region - [Flex-OneNAND] Return erase region of addr + * @param mtd MTD device structure + * @param addr address whose erase region needs to be identified + */ +int flexonenand_region(struct mtd_info *mtd, loff_t addr) +{ + int i; + + for (i = 0; i < mtd->numeraseregions; i++) + if (addr < mtd->eraseregions[i].offset) + break; + return i - 1; +} + /** * onenand_get_density - [DEFAULT] Get OneNAND density * @param dev_id OneNAND device ID @@ -205,10 +318,11 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) { struct onenand_chip *this = mtd->priv; - int value, readcmd = 0; + int value; int block, page; + /* Now we use page size operation */ - int sectors = 4, count = 4; + int sectors = 0, count = 0; /* Address translation */ switch (cmd) { @@ -220,15 +334,28 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, page = -1; break; + case FLEXONENAND_CMD_PI_ACCESS: + /* addr contains die index */ + block = addr * this->density_mask; + page = -1; + break; + case ONENAND_CMD_ERASE: case ONENAND_CMD_BUFFERRAM: - block = (int)(addr >> this->erase_shift); + block = onenand_block(this, addr); page = -1; break; + case FLEXONENAND_CMD_READ_PI: + cmd = ONENAND_CMD_READ; + block = addr * this->density_mask; + page = 0; + break; + default: - block = (int)(addr >> this->erase_shift); - page = (int)(addr >> this->page_shift); + block = onenand_block(this, addr); + page = (int) (addr + - onenand_addr(this, block)) >> this->page_shift; page &= this->page_mask; break; } @@ -240,8 +367,11 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); - /* Switch to the next data buffer */ - ONENAND_SET_NEXT_BUFFERRAM(this); + if (ONENAND_IS_MLC(this)) + ONENAND_SET_BUFFERRAM0(this); + else + /* Switch to the next data buffer */ + ONENAND_SET_NEXT_BUFFERRAM(this); return 0; } @@ -252,7 +382,7 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); - /* Write 'DFS, FBA' of Flash */ + /* Select DataRAM for DDP */ value = onenand_bufferram_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); @@ -262,10 +392,14 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, int dataram; switch (cmd) { + case FLEXONENAND_CMD_RECOVER_LSB: case ONENAND_CMD_READ: case ONENAND_CMD_READOOB: - dataram = ONENAND_SET_NEXT_BUFFERRAM(this); - readcmd = 1; + if (ONENAND_IS_MLC(this)) + dataram = ONENAND_SET_BUFFERRAM0(this); + else + dataram = ONENAND_SET_NEXT_BUFFERRAM(this); + break; default: @@ -291,6 +425,29 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, return 0; } +/** + * onenand_read_ecc - return ecc status + * @param this onenand chip structure + */ +static int onenand_read_ecc(struct onenand_chip *this) +{ + int ecc, i; + + if (!FLEXONENAND(this)) + return this->read_word(this->base + ONENAND_REG_ECC_STATUS); + + for (i = 0; i < 4; i++) { + ecc = this->read_word(this->base + + ((ONENAND_REG_ECC_STATUS + i) << 1)); + if (likely(!ecc)) + continue; + if (ecc & FLEXONENAND_UNCORRECTABLE_ERROR) + return ONENAND_ECC_2BIT_ALL; + } + + return 0; +} + /** * onenand_wait - [DEFAULT] wait until the command is done * @param mtd MTD device structure @@ -305,7 +462,7 @@ static int onenand_wait(struct mtd_info *mtd, int state) struct onenand_chip *this = mtd->priv; unsigned int flags = ONENAND_INT_MASTER; unsigned int interrupt = 0; - unsigned int ctrl, ecc; + unsigned int ctrl; while (1) { interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); @@ -315,6 +472,14 @@ static int onenand_wait(struct mtd_info *mtd, int state) ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); + if (interrupt & ONENAND_INT_READ) { + int ecc = onenand_read_ecc(this); + if (ecc & ONENAND_ECC_2BIT_ALL) { + printk("onenand_wait: ECC error = 0x%04x\n", ecc); + return -EBADMSG; + } + } + if (ctrl & ONENAND_CTRL_ERROR) { printk("onenand_wait: controller error = 0x%04x\n", ctrl); if (ctrl & ONENAND_CTRL_LOCK) @@ -324,14 +489,6 @@ static int onenand_wait(struct mtd_info *mtd, int state) return -EIO; } - if (interrupt & ONENAND_INT_READ) { - ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); - if (ecc & ONENAND_ECC_2BIT_ALL) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_wait: ECC error = 0x%04x\n", ecc); - return -EBADMSG; - } - } return 0; } @@ -499,7 +656,7 @@ static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) if (found && ONENAND_IS_DDP(this)) { /* Select DataRAM for DDP */ - int block = (int) (addr >> this->erase_shift); + int block = onenand_block(this, addr); int value = onenand_bufferram_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); } @@ -631,6 +788,45 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, return 0; } +/** + * onenand_recover_lsb - [Flex-OneNAND] Recover LSB page data + * @param mtd MTD device structure + * @param addr address to recover + * @param status return value from onenand_wait + * + * MLC NAND Flash cell has paired pages - LSB page and MSB page. LSB page has + * lower page address and MSB page has higher page address in paired pages. + * If power off occurs during MSB page program, the paired LSB page data can + * become corrupt. LSB page recovery read is a way to read LSB page though page + * data are corrupted. When uncorrectable error occurs as a result of LSB page + * read after power up, issue LSB page recovery read. + */ +static int onenand_recover_lsb(struct mtd_info *mtd, loff_t addr, int status) +{ + struct onenand_chip *this = mtd->priv; + int i; + + /* Recovery is only for Flex-OneNAND */ + if (!FLEXONENAND(this)) + return status; + + /* check if we failed due to uncorrectable error */ + if (status != -EBADMSG && status != ONENAND_BBT_READ_ECC_ERROR) + return status; + + /* check if address lies in MLC region */ + i = flexonenand_region(mtd, addr); + if (mtd->eraseregions[i].erasesize < (1 << this->erase_shift)) + return status; + + printk("onenand_recover_lsb:" + "Attempting to recover from uncorrectable read\n"); + + /* Issue the LSB page recovery command */ + this->command(mtd, FLEXONENAND_CMD_RECOVER_LSB, addr, this->writesize); + return this->wait(mtd, FL_READING); +} + /** * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band * @param mtd MTD device structure @@ -673,6 +869,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, stats = mtd->ecc_stats; /* Read-while-load method */ + /* Note: We can't use this feature in MLC */ /* Do first load to bufferRAM */ if (read < len) { @@ -680,6 +877,8 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, this->main_buf = buf; this->command(mtd, ONENAND_CMD_READ, from, writesize); ret = this->wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); onenand_update_bufferram(mtd, from, !ret); if (ret == -EBADMSG) ret = 0; @@ -694,7 +893,7 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, while (!ret) { /* If there is more to load then start next load */ from += thislen; - if (read + thislen < len) { + if (!ONENAND_IS_MLC(this) && read + thislen < len) { this->main_buf = buf + thislen; this->command(mtd, ONENAND_CMD_READ, from, writesize); /* @@ -728,6 +927,16 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, oobcolumn = 0; } + if (ONENAND_IS_MLC(this) && (read + thislen < len)) { + this->command(mtd, ONENAND_CMD_READ, from, writesize); + ret = this->wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); + onenand_update_bufferram(mtd, from, !ret); + if (ret == -EBADMSG) + ret = 0; + } + /* See if we are done */ read += thislen; if (read == len) @@ -735,16 +944,19 @@ static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, /* Set up for next read from bufferRAM */ if (unlikely(boundary)) this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); - ONENAND_SET_NEXT_BUFFERRAM(this); + if (!ONENAND_IS_MLC(this)) + ONENAND_SET_NEXT_BUFFERRAM(this); buf += thislen; thislen = min_t(int, writesize, len - read); column = 0; - /* Now wait for load */ - ret = this->wait(mtd, FL_READING); - onenand_update_bufferram(mtd, from, !ret); - if (ret == -EBADMSG) - ret = 0; + if (!ONENAND_IS_MLC(this)) { + /* Now wait for load */ + ret = this->wait(mtd, FL_READING); + onenand_update_bufferram(mtd, from, !ret); + if (ret == -EBADMSG) + ret = 0; + } } /* @@ -781,7 +993,7 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, size_t len = ops->ooblen; mtd_oob_mode_t mode = ops->mode; u_char *buf = ops->oobbuf; - int ret = 0; + int ret = 0, readcmd; from += ops->ooboffs; @@ -812,16 +1024,21 @@ static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, stats = mtd->ecc_stats; + readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB; + while (read < len) { thislen = oobsize - column; thislen = min_t(int, thislen, len); this->spare_buf = buf; - this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); + this->command(mtd, readcmd, from, mtd->oobsize); onenand_update_bufferram(mtd, from, 0); ret = this->wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); + if (ret && ret != -EBADMSG) { printk(KERN_ERR "onenand_read_oob_nolock: read failed = 0x%x\n", ret); break; @@ -945,9 +1162,12 @@ static int onenand_bbt_wait(struct mtd_info *mtd, int state) ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); if (interrupt & ONENAND_INT_READ) { - int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); - if (ecc & ONENAND_ECC_2BIT_ALL) + int ecc = onenand_read_ecc(this); + if (ecc & ONENAND_ECC_2BIT_ALL) { + printk(KERN_INFO "onenand_bbt_wait: ecc error = 0x%04x" + ", controller = 0x%04x\n", ecc, ctrl); return ONENAND_BBT_READ_ERROR; + } } else { printk(KERN_ERR "onenand_bbt_wait: read timeout!" "ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); @@ -976,12 +1196,14 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, { struct onenand_chip *this = mtd->priv; int read = 0, thislen, column; - int ret = 0; + int ret = 0, readcmd; size_t len = ops->ooblen; u_char *buf = ops->oobbuf; MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); + readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB; + /* Initialize return value */ ops->oobretlen = 0; @@ -1002,11 +1224,14 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, thislen = min_t(int, thislen, len); this->spare_buf = buf; - this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); + this->command(mtd, readcmd, from, mtd->oobsize); onenand_update_bufferram(mtd, from, 0); ret = this->bbt_wait(mtd, FL_READING); + if (unlikely(ret)) + ret = onenand_recover_lsb(mtd, from, ret); + if (ret) break; @@ -1044,9 +1269,11 @@ static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to { struct onenand_chip *this = mtd->priv; u_char *oob_buf = this->oob_buf; - int status, i; + int status, i, readcmd; - this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); + readcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_READ : ONENAND_CMD_READOOB; + + this->command(mtd, readcmd, to, mtd->oobsize); onenand_update_bufferram(mtd, to, 0); status = this->wait(mtd, FL_READING); if (status) @@ -1291,7 +1518,7 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, { struct onenand_chip *this = mtd->priv; int column, ret = 0, oobsize; - int written = 0; + int written = 0, oobcmd; u_char *oobbuf; size_t len = ops->ooblen; const u_char *buf = ops->oobbuf; @@ -1333,6 +1560,8 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, oobbuf = this->oob_buf; + oobcmd = ONENAND_IS_MLC(this) ? ONENAND_CMD_PROG : ONENAND_CMD_PROGOOB; + /* Loop until all data write */ while (written < len) { int thislen = min_t(int, oobsize, len - written); @@ -1348,7 +1577,14 @@ static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, memcpy(oobbuf + column, buf, thislen); this->write_bufferram(mtd, 0, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); - this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); + if (ONENAND_IS_MLC(this)) { + /* Set main area of DataRAM to 0xff*/ + memset(this->page_buf, 0xff, mtd->writesize); + this->write_bufferram(mtd, 0, ONENAND_DATARAM, + this->page_buf, 0, mtd->writesize); + } + + this->command(mtd, oobcmd, to, mtd->oobsize); onenand_update_bufferram(mtd, to, 0); if (ONENAND_IS_2PLANE(this)) { @@ -1475,34 +1711,54 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) { struct onenand_chip *this = mtd->priv; unsigned int block_size; - loff_t addr; - int len; - int ret = 0; - - MTDDEBUG (MTD_DEBUG_LEVEL3, - "onenand_erase: start = 0x%08x, len = %i\n", - (unsigned int)instr->addr, (unsigned int)instr->len); + loff_t addr = instr->addr; + unsigned int len = instr->len; + int ret = 0, i; + struct mtd_erase_region_info *region = NULL; + unsigned int region_end = 0; - block_size = (1 << this->erase_shift); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", + (unsigned int) addr, len); - /* Start address must align on block boundary */ - if (unlikely(instr->addr & (block_size - 1))) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_erase: Unaligned address\n"); + /* Do not allow erase past end of device */ + if (unlikely((len + addr) > mtd->size)) { + MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" + "Erase past end of device\n"); return -EINVAL; } - /* Length must align on block boundary */ - if (unlikely(instr->len & (block_size - 1))) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_erase: Length not block aligned\n"); - return -EINVAL; + if (FLEXONENAND(this)) { + /* Find the eraseregion of this address */ + i = flexonenand_region(mtd, addr); + region = &mtd->eraseregions[i]; + + block_size = region->erasesize; + region_end = region->offset + + region->erasesize * region->numblocks; + + /* Start address within region must align on block boundary. + * Erase region's start offset is always block start address. + */ + if (unlikely((addr - region->offset) & (block_size - 1))) { + MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" + " Unaligned address\n"); + return -EINVAL; + } + } else { + block_size = 1 << this->erase_shift; + + /* Start address must align on block boundary */ + if (unlikely(addr & (block_size - 1))) { + MTDDEBUG(MTD_DEBUG_LEVEL0, "onenand_erase:" + "Unaligned address\n"); + return -EINVAL; + } } - /* Do not allow erase past end of device */ - if (unlikely((instr->len + instr->addr) > mtd->size)) { + /* Length must align on block boundary */ + if (unlikely(len & (block_size - 1))) { MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_erase: Erase past end of device\n"); + "onenand_erase: Length not block aligned\n"); return -EINVAL; } @@ -1512,9 +1768,6 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) onenand_get_device(mtd, FL_ERASING); /* Loop throught the pages */ - len = instr->len; - addr = instr->addr; - instr->state = MTD_ERASING; while (len) { @@ -1541,14 +1794,7 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) else MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_erase: " "Failed erase, block %d\n", - (unsigned)(addr >> this->erase_shift)); - if (ret == -EPERM) - printk("onenand_erase: " - "Device is write protected!!!\n"); - else - printk("onenand_erase: " - "Failed erase, block %d\n", - (unsigned)(addr >> this->erase_shift)); + onenand_block(this, addr)); instr->state = MTD_ERASE_FAILED; instr->fail_addr = addr; @@ -1557,6 +1803,23 @@ int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) len -= block_size; addr += block_size; + + if (addr == region_end) { + if (!len) + break; + region++; + + block_size = region->erasesize; + region_end = region->offset + + region->erasesize * region->numblocks; + + if (len & (block_size - 1)) { + /* This has been checked at MTD + * partitioning level. */ + printk("onenand_erase: Unaligned address\n"); + goto erase_exit; + } + } } instr->state = MTD_ERASE_DONE; @@ -1634,7 +1897,7 @@ static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) int block; /* Get block number */ - block = ((int) ofs) >> bbm->bbt_erase_shift; + block = onenand_block(this, ofs); if (bbm->bbt) bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); @@ -1682,8 +1945,8 @@ static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int int start, end, block, value, status; int wp_status_mask; - start = ofs >> this->erase_shift; - end = len >> this->erase_shift; + start = onenand_block(this, ofs); + end = onenand_block(this, ofs + len); if (cmd == ONENAND_CMD_LOCK) wp_status_mask = ONENAND_WP_LS; @@ -1718,7 +1981,7 @@ static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int } /* Block lock scheme */ - for (block = start; block < start + end; block++) { + for (block = start; block < end; block++) { /* Set block address */ value = onenand_block_address(this, block); this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); @@ -1831,7 +2094,7 @@ static void onenand_unlock_all(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; loff_t ofs = 0; - size_t len = this->chipsize; + size_t len = mtd->size; if (this->options & ONENAND_HAS_UNLOCK_ALL) { /* Set start block address */ @@ -1847,14 +2110,12 @@ static void onenand_unlock_all(struct mtd_info *mtd) & ONENAND_CTRL_ONGO) continue; - return; - /* Check lock status */ if (onenand_check_lock_status(this)) return; /* Workaround for all block unlock in DDP */ - if (ONENAND_IS_DDP(this)) { + if (ONENAND_IS_DDP(this) && !FLEXONENAND(this)) { /* All blocks on another chip */ ofs = this->chipsize >> 1; len = this->chipsize >> 1; @@ -1906,6 +2167,14 @@ static void onenand_check_features(struct mtd_info *mtd) break; } + if (ONENAND_IS_MLC(this)) + this->options &= ~ONENAND_HAS_2PLANE; + + if (FLEXONENAND(this)) { + this->options &= ~ONENAND_HAS_CONT_LOCK; + this->options |= ONENAND_HAS_UNLOCK_ALL; + } + if (this->options & ONENAND_HAS_CONT_LOCK) printk(KERN_DEBUG "Lock scheme is Continuous Lock\n"); if (this->options & ONENAND_HAS_UNLOCK_ALL) @@ -1922,16 +2191,18 @@ static void onenand_check_features(struct mtd_info *mtd) */ char *onenand_print_device_info(int device, int version) { - int vcc, demuxed, ddp, density; + int vcc, demuxed, ddp, density, flexonenand; char *dev_info = malloc(80); char *p = dev_info; vcc = device & ONENAND_DEVICE_VCC_MASK; demuxed = device & ONENAND_DEVICE_IS_DEMUX; ddp = device & ONENAND_DEVICE_IS_DDP; - density = device >> ONENAND_DEVICE_DENSITY_SHIFT; - p += sprintf(dev_info, "%sOneNAND%s %dMB %sV 16-bit (0x%02x)", + density = onenand_get_density(device); + flexonenand = device & DEVICE_IS_FLEXONENAND; + p += sprintf(dev_info, "%s%sOneNAND%s %dMB %sV 16-bit (0x%02x)", demuxed ? "" : "Muxed ", + flexonenand ? "Flex-" : "", ddp ? "(DDP)" : "", (16 << density), vcc ? "2.65/3.3" : "1.8", device); @@ -1957,7 +2228,7 @@ static int onenand_check_maf(int manuf) char *name; int i; - for (i = 0; size; i++) + for (i = 0; i < size; i++) if (manuf == onenand_manuf_ids[i].id) break; @@ -1973,6 +2244,265 @@ static int onenand_check_maf(int manuf) return i == size; } +/** +* flexonenand_get_boundary - Reads the SLC boundary +* @param onenand_info - onenand info structure +* +* Fill up boundary[] field in onenand_chip +**/ +static int flexonenand_get_boundary(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + unsigned int die, bdry; + int ret, syscfg, locked; + + /* Disable ECC */ + syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); + this->write_word((syscfg | 0x0100), this->base + ONENAND_REG_SYS_CFG1); + + for (die = 0; die < this->dies; die++) { + this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0); + this->wait(mtd, FL_SYNCING); + + this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0); + ret = this->wait(mtd, FL_READING); + + bdry = this->read_word(this->base + ONENAND_DATARAM); + if ((bdry >> FLEXONENAND_PI_UNLOCK_SHIFT) == 3) + locked = 0; + else + locked = 1; + this->boundary[die] = bdry & FLEXONENAND_PI_MASK; + + this->command(mtd, ONENAND_CMD_RESET, 0, 0); + ret = this->wait(mtd, FL_RESETING); + + printk(KERN_INFO "Die %d boundary: %d%s\n", die, + this->boundary[die], locked ? "(Locked)" : "(Unlocked)"); + } + + /* Enable ECC */ + this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); + return 0; +} + +/** + * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info + * boundary[], diesize[], mtd->size, mtd->erasesize, + * mtd->eraseregions + * @param mtd - MTD device structure + */ +static void flexonenand_get_size(struct mtd_info *mtd) +{ + struct onenand_chip *this = mtd->priv; + int die, i, eraseshift, density; + int blksperdie, maxbdry; + loff_t ofs; + + density = onenand_get_density(this->device_id); + blksperdie = ((loff_t)(16 << density) << 20) >> (this->erase_shift); + blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0; + maxbdry = blksperdie - 1; + eraseshift = this->erase_shift - 1; + + mtd->numeraseregions = this->dies << 1; + + /* This fills up the device boundary */ + flexonenand_get_boundary(mtd); + die = 0; + ofs = 0; + i = -1; + for (; die < this->dies; die++) { + if (!die || this->boundary[die-1] != maxbdry) { + i++; + mtd->eraseregions[i].offset = ofs; + mtd->eraseregions[i].erasesize = 1 << eraseshift; + mtd->eraseregions[i].numblocks = + this->boundary[die] + 1; + ofs += mtd->eraseregions[i].numblocks << eraseshift; + eraseshift++; + } else { + mtd->numeraseregions -= 1; + mtd->eraseregions[i].numblocks += + this->boundary[die] + 1; + ofs += (this->boundary[die] + 1) << (eraseshift - 1); + } + if (this->boundary[die] != maxbdry) { + i++; + mtd->eraseregions[i].offset = ofs; + mtd->eraseregions[i].erasesize = 1 << eraseshift; + mtd->eraseregions[i].numblocks = maxbdry ^ + this->boundary[die]; + ofs += mtd->eraseregions[i].numblocks << eraseshift; + eraseshift--; + } else + mtd->numeraseregions -= 1; + } + + /* Expose MLC erase size except when all blocks are SLC */ + mtd->erasesize = 1 << this->erase_shift; + if (mtd->numeraseregions == 1) + mtd->erasesize >>= 1; + + printk(KERN_INFO "Device has %d eraseregions\n", mtd->numeraseregions); + for (i = 0; i < mtd->numeraseregions; i++) + printk(KERN_INFO "[offset: 0x%08llx, erasesize: 0x%05x," + " numblocks: %04u]\n", mtd->eraseregions[i].offset, + mtd->eraseregions[i].erasesize, + mtd->eraseregions[i].numblocks); + + for (die = 0, mtd->size = 0; die < this->dies; die++) { + this->diesize[die] = (loff_t) (blksperdie << this->erase_shift); + this->diesize[die] -= (loff_t) (this->boundary[die] + 1) + << (this->erase_shift - 1); + mtd->size += this->diesize[die]; + } +} + +/** + * flexonenand_check_blocks_erased - Check if blocks are erased + * @param mtd_info - mtd info structure + * @param start - first erase block to check + * @param end - last erase block to check + * + * Converting an unerased block from MLC to SLC + * causes byte values to change. Since both data and its ECC + * have changed, reads on the block give uncorrectable error. + * This might lead to the block being detected as bad. + * + * Avoid this by ensuring that the block to be converted is + * erased. + */ +static int flexonenand_check_blocks_erased(struct mtd_info *mtd, + int start, int end) +{ + struct onenand_chip *this = mtd->priv; + int i, ret; + int block; + struct mtd_oob_ops ops = { + .mode = MTD_OOB_PLACE, + .ooboffs = 0, + .ooblen = mtd->oobsize, + .datbuf = NULL, + .oobbuf = this->oob_buf, + }; + loff_t addr; + + printk(KERN_DEBUG "Check blocks from %d to %d\n", start, end); + + for (block = start; block <= end; block++) { + addr = flexonenand_addr(this, block); + if (onenand_block_isbad_nolock(mtd, addr, 0)) + continue; + + /* + * Since main area write results in ECC write to spare, + * it is sufficient to check only ECC bytes for change. + */ + ret = onenand_read_oob_nolock(mtd, addr, &ops); + if (ret) + return ret; + + for (i = 0; i < mtd->oobsize; i++) + if (this->oob_buf[i] != 0xff) + break; + + if (i != mtd->oobsize) { + printk(KERN_WARNING "Block %d not erased.\n", block); + return 1; + } + } + + return 0; +} + +/** + * flexonenand_set_boundary - Writes the SLC boundary + * @param mtd - mtd info structure + */ +int flexonenand_set_boundary(struct mtd_info *mtd, int die, + int boundary, int lock) +{ + struct onenand_chip *this = mtd->priv; + int ret, density, blksperdie, old, new, thisboundary; + loff_t addr; + + if (die >= this->dies) + return -EINVAL; + + if (boundary == this->boundary[die]) + return 0; + + density = onenand_get_density(this->device_id); + blksperdie = ((16 << density) << 20) >> this->erase_shift; + blksperdie >>= ONENAND_IS_DDP(this) ? 1 : 0; + + if (boundary >= blksperdie) { + printk("flexonenand_set_boundary:" + "Invalid boundary value. " + "Boundary not changed.\n"); + return -EINVAL; + } + + /* Check if converting blocks are erased */ + old = this->boundary[die] + (die * this->density_mask); + new = boundary + (die * this->density_mask); + ret = flexonenand_check_blocks_erased(mtd, min(old, new) + + 1, max(old, new)); + if (ret) { + printk(KERN_ERR "flexonenand_set_boundary: Please erase blocks before boundary change\n"); + return ret; + } + + this->command(mtd, FLEXONENAND_CMD_PI_ACCESS, die, 0); + this->wait(mtd, FL_SYNCING); + + /* Check is boundary is locked */ + this->command(mtd, FLEXONENAND_CMD_READ_PI, die, 0); + ret = this->wait(mtd, FL_READING); + + thisboundary = this->read_word(this->base + ONENAND_DATARAM); + if ((thisboundary >> FLEXONENAND_PI_UNLOCK_SHIFT) != 3) { + printk(KERN_ERR "flexonenand_set_boundary: boundary locked\n"); + goto out; + } + + printk(KERN_INFO "flexonenand_set_boundary: Changing die %d boundary: %d%s\n", + die, boundary, lock ? "(Locked)" : "(Unlocked)"); + + boundary &= FLEXONENAND_PI_MASK; + boundary |= lock ? 0 : (3 << FLEXONENAND_PI_UNLOCK_SHIFT); + + addr = die ? this->diesize[0] : 0; + this->command(mtd, ONENAND_CMD_ERASE, addr, 0); + ret = this->wait(mtd, FL_ERASING); + if (ret) { + printk("flexonenand_set_boundary:" + "Failed PI erase for Die %d\n", die); + goto out; + } + + this->write_word(boundary, this->base + ONENAND_DATARAM); + this->command(mtd, ONENAND_CMD_PROG, addr, 0); + ret = this->wait(mtd, FL_WRITING); + if (ret) { + printk("flexonenand_set_boundary:" + "Failed PI write for Die %d\n", die); + goto out; + } + + this->command(mtd, FLEXONENAND_CMD_PI_UPDATE, die, 0); + ret = this->wait(mtd, FL_WRITING); +out: + this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_REG_COMMAND); + this->wait(mtd, FL_RESETING); + if (!ret) + /* Recalculate device size on boundary change*/ + flexonenand_get_size(mtd); + + return ret; +} + /** * onenand_probe - [OneNAND Interface] Probe the OneNAND device * @param mtd MTD device structure @@ -2016,48 +2546,69 @@ static int onenand_probe(struct mtd_info *mtd) maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); + this->technology = this->read_word(this->base + ONENAND_REG_TECHNOLOGY); /* Check OneNAND device */ if (maf_id != bram_maf_id || dev_id != bram_dev_id) return -ENXIO; - /* FIXME : Current OneNAND MTD doesn't support Flex-OneNAND */ - if (dev_id & (1 << 9)) { - printk("Not yet support Flex-OneNAND\n"); - return -ENXIO; - } - /* Flash device information */ mtd->name = onenand_print_device_info(dev_id, ver_id); this->device_id = dev_id; this->version_id = ver_id; density = onenand_get_density(dev_id); + if (FLEXONENAND(this)) { + this->dies = ONENAND_IS_DDP(this) ? 2 : 1; + /* Maximum possible erase regions */ + mtd->numeraseregions = this->dies << 1; + mtd->eraseregions = malloc(sizeof(struct mtd_erase_region_info) + * (this->dies << 1)); + if (!mtd->eraseregions) + return -ENOMEM; + } + + /* + * For Flex-OneNAND, chipsize represents maximum possible device size. + * mtd->size represents the actual device size. + */ this->chipsize = (16 << density) << 20; - /* Set density mask. it is used for DDP */ - if (ONENAND_IS_DDP(this)) - this->density_mask = (1 << (density + 6)); - else - this->density_mask = 0; /* OneNAND page size & block size */ /* The data buffer size is equal to page size */ mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); + /* We use the full BufferRAM */ + if (ONENAND_IS_MLC(this)) + mtd->writesize <<= 1; + mtd->oobsize = mtd->writesize >> 5; /* Pagers per block is always 64 in OneNAND */ mtd->erasesize = mtd->writesize << 6; + /* + * Flex-OneNAND SLC area has 64 pages per block. + * Flex-OneNAND MLC area has 128 pages per block. + * Expose MLC erase size to find erase_shift and page_mask. + */ + if (FLEXONENAND(this)) + mtd->erasesize <<= 1; this->erase_shift = ffs(mtd->erasesize) - 1; this->page_shift = ffs(mtd->writesize) - 1; this->ppb_shift = (this->erase_shift - this->page_shift); this->page_mask = (mtd->erasesize / mtd->writesize) - 1; + /* Set density mask. it is used for DDP */ + if (ONENAND_IS_DDP(this)) + this->density_mask = this->chipsize >> (this->erase_shift + 1); /* It's real page size */ this->writesize = mtd->writesize; /* REVIST: Multichip handling */ - mtd->size = this->chipsize; + if (FLEXONENAND(this)) + flexonenand_get_size(mtd); + else + mtd->size = this->chipsize; /* Check OneNAND features */ onenand_check_features(mtd); @@ -2149,6 +2700,11 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) * Allow subpage writes up to oobsize. */ switch (mtd->oobsize) { + case 128: + this->ecclayout = &onenand_oob_128; + mtd->subpage_sft = 0; + break; + case 64: this->ecclayout = &onenand_oob_64; mtd->subpage_sft = 2; diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index d538f9582..135487772 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -69,6 +69,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, loff_t from; size_t readlen, ooblen; struct mtd_oob_ops ops; + int rgn; printk(KERN_INFO "Scanning device for bad blocks\n"); @@ -82,7 +83,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, /* Note that numblocks is 2 * (real numblocks) here; * see i += 2 below as it makses shifting and masking less painful */ - numblocks = mtd->size >> (bbm->bbt_erase_shift - 1); + numblocks = this->chipsize >> (bbm->bbt_erase_shift - 1); startblock = 0; from = 0; @@ -115,7 +116,12 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, } } i += 2; - from += (1 << bbm->bbt_erase_shift); + + if (FLEXONENAND(this)) { + rgn = flexonenand_region(mtd, from); + from += mtd->eraseregions[rgn].erasesize; + } else + from += (1 << bbm->bbt_erase_shift); } return 0; @@ -152,7 +158,7 @@ static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt) uint8_t res; /* Get block number * 2 */ - block = (int)(offs >> (bbm->bbt_erase_shift - 1)); + block = (int) (onenand_block(this, offs) << 1); res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03; MTDDEBUG (MTD_DEBUG_LEVEL2, @@ -191,7 +197,7 @@ int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd) struct bbm_info *bbm = this->bbm; int len, ret = 0; - len = mtd->size >> (this->erase_shift + 2); + len = this->chipsize >> (this->erase_shift + 2); /* Allocate memory (2bit per block) */ bbm->bbt = malloc(len); if (!bbm->bbt) { diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 9823b5b47..c642016c2 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -40,8 +40,10 @@ void onenand_init(void) onenand_scan(&onenand_mtd, 1); + if (onenand_chip.device_id & DEVICE_IS_FLEXONENAND) + puts("Flex-"); puts("OneNAND: "); - print_size(onenand_mtd.size, "\n"); + print_size(onenand_chip.chipsize, "\n"); #ifdef CONFIG_MTD_DEVICE /* diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 9a6f31752..68e174e31 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -20,8 +20,9 @@ #include #include +#define MAX_DIES 2 #define MAX_BUFFERRAM 2 -#define MAX_ONENAND_PAGESIZE (2048 + 64) +#define MAX_ONENAND_PAGESIZE (4096 + 128) /* Scan and identify a OneNAND device */ extern int onenand_scan (struct mtd_info *mtd, int max_chips); @@ -39,9 +40,14 @@ struct onenand_bufferram { /** * struct onenand_chip - OneNAND Private Flash Chip Data * @param base [BOARDSPECIFIC] address to access OneNAND + * @dies: [INTERN][FLEXONENAND] number of dies on chip + * @boundary: [INTERN][FLEXONENAND] Boundary of the dies + * @diesize: [INTERN][FLEXONENAND] Size of the dies * @param chipsize [INTERN] the size of one chip for multichip arrays * @param device_id [INTERN] device ID * @param verstion_id [INTERN] version ID + * @technology [INTERN] describes the internal NAND array technology such as SLC or MLC. + * @density_mask: [INTERN] chip density, used for DDP devices * @param options [BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about * @param erase_shift [INTERN] number of address bits in a block * @param page_shift [INTERN] number of address bits in a page @@ -64,9 +70,13 @@ struct onenand_bufferram { */ struct onenand_chip { void __iomem *base; + unsigned int dies; + unsigned int boundary[MAX_DIES]; + unsigned int diesize[MAX_DIES]; unsigned int chipsize; unsigned int device_id; unsigned int version_id; + unsigned int technology; unsigned int density_mask; unsigned int options; @@ -124,6 +134,8 @@ struct onenand_chip { #define ONENAND_SET_BUFFERRAM0(this) (this->bufferram_index = 0) #define ONENAND_SET_BUFFERRAM1(this) (this->bufferram_index = 1) +#define FLEXONENAND(this) (this->device_id & DEVICE_IS_FLEXONENAND) +#define ONENAND_IS_MLC(this) (this->technology & ONENAND_TECHNOLOGY_IS_MLC) #define ONENAND_IS_DDP(this) \ (this->device_id & ONENAND_DEVICE_IS_DDP) @@ -157,4 +169,6 @@ struct onenand_manufacturers { int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); +unsigned int onenand_block(struct onenand_chip *this, loff_t addr); +int flexonenand_region(struct mtd_info *mtd, loff_t addr); #endif /* __LINUX_MTD_ONENAND_H */ diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index 07fed1c60..8449a3cdc 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -67,6 +67,9 @@ /* * Device ID Register F001h (R) */ +#define DEVICE_IS_FLEXONENAND (1 << 9) +#define FLEXONENAND_PI_MASK (0x3ff) +#define FLEXONENAND_PI_UNLOCK_SHIFT (14) #define ONENAND_DEVICE_DENSITY_MASK (0xf) #define ONENAND_DEVICE_DENSITY_SHIFT (4) #define ONENAND_DEVICE_IS_DDP (1 << 3) @@ -83,6 +86,11 @@ */ #define ONENAND_VERSION_PROCESS_SHIFT (8) +/* + * Technology Register F006h (R) + */ +#define ONENAND_TECHNOLOGY_IS_MLC (1 << 0) + /* * Start Address 1 F100h (R/W) */ @@ -93,7 +101,7 @@ /* * Start Address 8 F107h (R/W) */ -#define ONENAND_FPA_MASK (0x3f) +#define ONENAND_FPA_MASK (0x7f) #define ONENAND_FPA_SHIFT (2) #define ONENAND_FSA_MASK (0x03) @@ -105,7 +113,7 @@ #define ONENAND_BSA_BOOTRAM (0 << 2) #define ONENAND_BSA_DATARAM0 (2 << 2) #define ONENAND_BSA_DATARAM1 (3 << 2) -#define ONENAND_BSC_MASK (0x03) +#define ONENAND_BSC_MASK (0x07) /* * Command Register F220h (R/W) @@ -125,9 +133,14 @@ #define ONENAND_CMD_ERASE_VERIFY (0x71) #define ONENAND_CMD_RESET (0xF0) #define ONENAND_CMD_READID (0x90) +#define FLEXONENAND_CMD_RESET (0xF3) +#define FLEXONENAND_CMD_PI_UPDATE (0x05) +#define FLEXONENAND_CMD_PI_ACCESS (0x66) +#define FLEXONENAND_CMD_RECOVER_LSB (0x05) /* NOTE: Those are not *REAL* commands */ #define ONENAND_CMD_BUFFERRAM (0x1978) +#define FLEXONENAND_CMD_READ_PI (0x1985) /* * System Configuration 1 Register F221h (R, R/W) @@ -190,5 +203,6 @@ #define ONENAND_ECC_2BIT (1 << 1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) #define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010) +#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010) #endif /* __ONENAND_REG_H */ diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index 49da9d08b..92279d56e 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -23,6 +23,7 @@ struct erase_info; struct onenand_chip; extern struct mtd_info onenand_mtd; +extern struct onenand_chip onenand_chip; /* board */ extern void onenand_board_init(struct mtd_info *); @@ -38,6 +39,15 @@ extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr); extern char *onenand_print_device_info(int device, int version); +extern unsigned onenand_block(struct onenand_chip *this, loff_t addr); + +extern loff_t onenand_addr(struct onenand_chip *this, int block); + +extern int flexonenand_region(struct mtd_info *mtd, loff_t addr); + +extern int flexonenand_set_boundary(struct mtd_info *mtd, int die, + int boundary, int lock); + /* S3C64xx */ extern void s3c64xx_onenand_init(struct mtd_info *); extern void s3c64xx_set_width_regs(struct onenand_chip *); -- cgit v1.2.3 From 1d2e96de56cc57e25a19bc40d297f36c4c4443a2 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Mon, 2 Nov 2009 20:36:26 +0100 Subject: OMAP2/3: I2C: Add support for second and third bus Add support to use second and third I2C bus, too. Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch back afterwards, then. Signed-off-by: Dirk Behme --- drivers/i2c/omap24xx_i2c.c | 166 +++++++++++++++++++++--------------- include/asm-arm/arch-omap24xx/i2c.h | 53 ++++++++---- include/asm-arm/arch-omap3/i2c.h | 49 +++++++---- 3 files changed, 170 insertions(+), 98 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 1a4c8c9ad..ff18991f0 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -29,6 +29,11 @@ static void wait_for_bb (void); static u16 wait_for_pin (void); static void flush_fifo(void); +static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE; + +static unsigned int bus_initialized[I2C_BUS_MAX]; +static unsigned int current_bus; + void i2c_init (int speed, int slaveadd) { int psc, fsscll, fssclh; @@ -95,30 +100,32 @@ void i2c_init (int speed, int slaveadd) sclh = (unsigned int)fssclh; } - writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ udelay(1000); - writew(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, &i2c_base->sysc); /* will probably self clear but */ - if (readw (I2C_CON) & I2C_CON_EN) { - writew (0, I2C_CON); + if (readw (&i2c_base->con) & I2C_CON_EN) { + writew (0, &i2c_base->con); udelay (50000); } - writew(psc, I2C_PSC); - writew(scll, I2C_SCLL); - writew(sclh, I2C_SCLH); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); /* own address */ - writew (slaveadd, I2C_OA); - writew (I2C_CON_EN, I2C_CON); + writew (slaveadd, &i2c_base->oa); + writew (I2C_CON_EN, &i2c_base->con); /* have to enable intrrupts or OMAP i2c module doesn't work */ writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); udelay (1000); flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); + + bus_initialized[current_bus] = 1; } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -130,19 +137,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) wait_for_bb (); /* one byte only */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* no stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - writeb (regoffset, I2C_DATA); + writeb (regoffset, &i2c_base->data); udelay (20000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c_base->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -151,28 +158,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - writew (0, I2C_CON); - while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (0, &i2c_base->con); + while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); } wait_for_bb (); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* read one byte from slave */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* need stop bit here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + &i2c_base->con); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = readb (I2C_DATA); + *value = readb (&i2c_base->data); #else - *value = readw (I2C_DATA); + *value = readw (&i2c_base->data); #endif udelay (20000); } else { @@ -180,17 +187,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) } if (!i2c_error) { - writew (I2C_CON_EN, I2C_CON); - while (readw (I2C_STAT) - || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c_base->con); + while (readw (&i2c_base->stat) + || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (10000); - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); } } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); return i2c_error; } @@ -203,12 +210,12 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) wait_for_bb (); /* two bytes */ - writew (2, I2C_CNT); + writew (2, &i2c_base->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c_base->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + I2C_CON_STP, &i2c_base->con); /* wait until state change */ status = wait_for_pin (); @@ -216,24 +223,24 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* send out 1 byte */ - writeb (regoffset, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (regoffset, &i2c_base->data); + writew (I2C_STAT_XRDY, &i2c_base->stat); status = wait_for_pin (); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ - writeb (value, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (value, &i2c_base->data); + writew (I2C_STAT_XRDY, &i2c_base->stat); } else { i2c_error = 1; } #else /* send out two bytes */ - writew ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, &i2c_base->data); #endif /* must have enough delay to allow BB bit to go low */ udelay (50000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c_base->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -243,18 +250,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (!i2c_error) { int eout = 200; - writew (I2C_CON_EN, I2C_CON); - while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c_base->con); + while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c_base->stat); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c_base->stat); + writew (0, &i2c_base->cnt); return i2c_error; } @@ -265,14 +272,14 @@ static void flush_fifo(void) * you get a bus error */ while(1){ - stat = readw(I2C_STAT); + stat = readw(&i2c_base->stat); if(stat == I2C_STAT_RRDY){ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - readb(I2C_DATA); + readb(&i2c_base->data); #else - readw(I2C_DATA); + readw(&i2c_base->data); #endif - writew(I2C_STAT_RRDY,I2C_STAT); + writew(I2C_STAT_RRDY,&i2c_base->stat); udelay(1000); }else break; @@ -283,7 +290,7 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == readw (I2C_OA)) { + if (chip == readw (&i2c_base->oa)) { return res; } @@ -291,27 +298,27 @@ int i2c_probe (uchar chip) wait_for_bb (); /* try to read one byte */ - writew (1, I2C_CNT); + writew (1, &i2c_base->cnt); /* set slave address */ - writew (chip, I2C_SA); + writew (chip, &i2c_base->sa); /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); /* enough delay for the NACK bit set */ udelay (50000); - if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); - writew(0xFFFF, I2C_STAT); + writew(0xFFFF, &i2c_base->stat); } else { - writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ - writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/ + writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - writew(0xFFFF, I2C_STAT); + writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, &i2c_base->stat); return res; } @@ -370,17 +377,17 @@ static void wait_for_bb (void) int timeout = 10; u16 stat; - writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - writew (stat, I2C_STAT); + writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/ + while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) { + writew (stat, &i2c_base->stat); udelay (50000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - readw (I2C_STAT)); + readw (&i2c_base->stat)); } - writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ } static u16 wait_for_pin (void) @@ -390,7 +397,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = readw (I2C_STAT); + status = readw (&i2c_base->stat); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -398,8 +405,33 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - readw (I2C_STAT)); - writew(0xFFFF, I2C_STAT); + readw (&i2c_base->stat)); + writew(0xFFFF, &i2c_base->stat); } return status; } + +int i2c_set_bus_num(unsigned int bus) +{ + if ((bus < 0) || (bus >= I2C_BUS_MAX)) { + printf("Bad bus: %d\n", bus); + return -1; + } + +#if I2C_BUS_MAX==3 + if (bus == 2) + i2c_base = (struct i2c *)I2C_BASE3; + else +#endif + if (bus == 1) + i2c_base = (struct i2c *)I2C_BASE2; + else + i2c_base = (struct i2c *)I2C_BASE1; + + current_bus = bus; + + if(!bus_initialized[current_bus]) + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + return 0; +} diff --git a/include/asm-arm/arch-omap24xx/i2c.h b/include/asm-arm/arch-omap24xx/i2c.h index 44db7a2d4..19046aaab 100644 --- a/include/asm-arm/arch-omap24xx/i2c.h +++ b/include/asm-arm/arch-omap24xx/i2c.h @@ -23,24 +23,45 @@ #ifndef _OMAP24XX_I2C_H_ #define _OMAP24XX_I2C_H_ -#define I2C_BASE 0x48070000 +#define I2C_BASE1 0x48070000 #define I2C_BASE2 0x48072000 /* nothing hooked up on h4 */ -#define I2C_REV (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_IV (I2C_BASE + 0x0c) -#define I2C_BUF (I2C_BASE + 0x14) -#define I2C_CNT (I2C_BASE + 0x18) -#define I2C_DATA (I2C_BASE + 0x1c) -#define I2C_SYSC (I2C_BASE + 0x20) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_OA (I2C_BASE + 0x28) -#define I2C_SA (I2C_BASE + 0x2c) -#define I2C_PSC (I2C_BASE + 0x30) -#define I2C_SCLL (I2C_BASE + 0x34) -#define I2C_SCLH (I2C_BASE + 0x38) -#define I2C_SYSTEST (I2C_BASE + 0x3c) +#define I2C_DEFAULT_BASE I2C_BASE1 + +struct i2c { + unsigned short rev; /* 0x00 */ + unsigned short res1; + unsigned short ie; /* 0x04 */ + unsigned short res2; + unsigned short stat; /* 0x08 */ + unsigned short res3; + unsigned short iv; /* 0x0C */ + unsigned short res4[3]; + unsigned short buf; /* 0x14 */ + unsigned short res5; + unsigned short cnt; /* 0x18 */ + unsigned short res6; + unsigned short data; /* 0x1C */ + unsigned short res7; + unsigned short sysc; /* 0x20 */ + unsigned short res8; + unsigned short con; /* 0x24 */ + unsigned short res9; + unsigned short oa; /* 0x28 */ + unsigned short res10; + unsigned short sa; /* 0x2C */ + unsigned short res11; + unsigned short psc; /* 0x30 */ + unsigned short res12; + unsigned short scll; /* 0x34 */ + unsigned short res13; + unsigned short sclh; /* 0x38 */ + unsigned short res14; + unsigned short systest; /* 0x3c */ + unsigned short res15; +}; + +#define I2C_BUS_MAX 2 /* I2C masks */ diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h index 8b339cce9..490e03bb6 100644 --- a/include/asm-arm/arch-omap3/i2c.h +++ b/include/asm-arm/arch-omap3/i2c.h @@ -25,21 +25,40 @@ #define I2C_DEFAULT_BASE I2C_BASE1 -#define I2C_REV (I2C_DEFAULT_BASE + 0x00) -#define I2C_IE (I2C_DEFAULT_BASE + 0x04) -#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) -#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) -#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) -#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) -#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) -#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) -#define I2C_CON (I2C_DEFAULT_BASE + 0x24) -#define I2C_OA (I2C_DEFAULT_BASE + 0x28) -#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) -#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) -#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) -#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) -#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) +struct i2c { + unsigned short rev; /* 0x00 */ + unsigned short res1; + unsigned short ie; /* 0x04 */ + unsigned short res2; + unsigned short stat; /* 0x08 */ + unsigned short res3; + unsigned short iv; /* 0x0C */ + unsigned short res4[3]; + unsigned short buf; /* 0x14 */ + unsigned short res5; + unsigned short cnt; /* 0x18 */ + unsigned short res6; + unsigned short data; /* 0x1C */ + unsigned short res7; + unsigned short sysc; /* 0x20 */ + unsigned short res8; + unsigned short con; /* 0x24 */ + unsigned short res9; + unsigned short oa; /* 0x28 */ + unsigned short res10; + unsigned short sa; /* 0x2C */ + unsigned short res11; + unsigned short psc; /* 0x30 */ + unsigned short res12; + unsigned short scll; /* 0x34 */ + unsigned short res13; + unsigned short sclh; /* 0x38 */ + unsigned short res14; + unsigned short systest; /* 0x3c */ + unsigned short res15; +}; + +#define I2C_BUS_MAX 3 /* I2C masks */ -- cgit v1.2.3 From 6cd752f927e515e63a038fa363edceec5a59c028 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Mon, 16 Nov 2009 13:32:01 -0500 Subject: NAND: Update read_read_subpage API check This patch updates a check condition in the NAND driver. The check condition is similat to what is in linux/next. Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/nand_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6da261c04..7171bdd51 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -1061,7 +1061,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3 int stat; stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); - if (stat < 0) + if (stat == -1) mtd->ecc_stats.failed++; else mtd->ecc_stats.corrected += stat; -- cgit v1.2.3 From 5e1ded558b7cc28a62c14598f6437023b6262444 Mon Sep 17 00:00:00 2001 From: "Hui.Tang" Date: Wed, 18 Nov 2009 16:24:04 +0800 Subject: S3C2410 NAND Flash Add Missing Function This patch add nand_read_buf() for S3C2410 NAND SPL. In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip, so nand->select_chip should also be initialized. Signed-off-by: Hui.Tang --- drivers/mtd/nand/s3c2410_nand.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index f2f3e722e..815c78eb6 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -36,6 +36,21 @@ #define S3C2410_ADDR_NALE 4 #define S3C2410_ADDR_NCLE 8 +#ifdef CONFIG_NAND_SPL + +/* in the early stage of NAND flash booting, printf() is not available */ +#define printf(fmt, args...) + +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = readb(this->IO_ADDR_R); +} +#endif + static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; @@ -83,9 +98,10 @@ void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code) { - ecc_code[0] = NFECC0; - ecc_code[1] = NFECC1; - ecc_code[2] = NFECC2; + struct s3c2410_nand *nand = s3c2410_get_base_nand(); + ecc_code[0] = readb(&nand->NFECC); + ecc_code[1] = readb(&nand->NFECC + 1); + ecc_code[2] = readb(&nand->NFECC + 2); debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", mtd , ecc_code[0], ecc_code[1], ecc_code[2]); @@ -130,8 +146,13 @@ int board_nand_init(struct nand_chip *nand) /* initialize nand_chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA; + nand->select_chip = NULL; + /* read_buf and write_buf are default */ /* read_byte and write_byte are default */ +#ifdef CONFIG_NAND_SPL + nand->read_buf = nand_read_buf; +#endif /* hwcontrol always must be implemented */ nand->cmd_ctrl = s3c2410_hwcontrol; @@ -142,7 +163,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.hwctl = s3c2410_nand_enable_hwecc; nand->ecc.calculate = s3c2410_nand_calculate_ecc; nand->ecc.correct = s3c2410_nand_correct_data; - nand->ecc.mode = NAND_ECC_HW3_512; + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; + nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; #else nand->ecc.mode = NAND_ECC_SOFT; #endif -- cgit v1.2.3 From 10a5a7991258019af155bc19b3b246aaa708b0e2 Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Thu, 19 Nov 2009 23:04:42 -0500 Subject: NAND: Add Support for 4K page size in DaVinci NAND driver This patch adds support for NAND devices with a page size of 4K in the DaVinci NAND driver. The layout matches the layout that TI uses for 4K page size NAND devices in the kernel NAND driver. Signed-off-by: Sandeep Paulraj --- drivers/mtd/nand/davinci_nand.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index eabaf3e77..41a95685f 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -182,13 +182,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char * #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { -/* - * TI uses a different layout for 4K page deviecs. Since the - * eccpos filed can hold only a limited number of entries, adding - * support for 4K page will result in compilation warnings - * 4K Support will be added later - */ -#ifdef CONFIG_SYS_NAND_PAGE_2K +#if defined(CONFIG_SYS_NAND_PAGE_2K) .eccbytes = 40, .eccpos = { 24, 25, 26, 27, 28, @@ -200,6 +194,21 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { .oobfree = { {.offset = 2, .length = 22, }, }, +#elif defined(CONFIG_SYS_NAND_PAGE_4K) + .eccbytes = 80, + .eccpos = { + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, + 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, + 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, + 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, + 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, + }, + .oobfree = { + {.offset = 2, .length = 46, }, + }, #endif }; -- cgit v1.2.3 From 4e574c4e2d3776d9db62dca4ca3c73be1574af43 Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Mon, 18 May 2009 13:20:54 +0200 Subject: at91: Extended soft_i2c driver for AT91SAM9263 SoC While hard_i2c support is not available (see http://lists.denx.de/pipermail/u-boot/2009-March/049751.html), this patch enables soft_i2c on AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski --- drivers/i2c/soft_i2c.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 59883a58f..9a4878391 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -34,6 +34,11 @@ #include #include #endif +#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ +#include +#include +#include +#endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include #endif -- cgit v1.2.3 From 9829cabbaa0474e94075bf7d62c99bdba996518b Mon Sep 17 00:00:00 2001 From: Sandeep Paulraj Date: Wed, 28 Oct 2009 19:16:43 -0400 Subject: Fix for Void function returning value in sbc35-a9g20 Void function was returning 0 in the m41t94 rtc driver. This makes it similar to m41t62 rtc driver. Signed-off-by: Sandeep Paulraj --- drivers/rtc/m41t94.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/rtc/m41t94.c b/drivers/rtc/m41t94.c index 02b41d91b..5b665bb01 100644 --- a/drivers/rtc/m41t94.c +++ b/drivers/rtc/m41t94.c @@ -120,5 +120,4 @@ void rtc_reset(void) * Could not be tested as the reset pin is not wired on * the sbc35-ag20 board */ - return 0; } -- cgit v1.2.3 From 492fb1fdbcdd5e21be0b6742c15f76c648f0653b Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Tue, 3 Nov 2009 18:08:41 +0900 Subject: Move s3c24x0 header files to asm-arm/arch-s3c24x0/ This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- board/mpl/vcma9/vcma9.c | 2 +- board/mpl/vcma9/vcma9.h | 2 +- board/samsung/smdk2400/smdk2400.c | 2 +- board/samsung/smdk2410/smdk2410.c | 2 +- board/sbc2410x/sbc2410x.c | 2 +- board/trab/cmd_trab.c | 2 +- board/trab/rs485.c | 2 +- board/trab/rs485.h | 2 +- board/trab/trab.c | 2 +- board/trab/trab_fkt.c | 2 +- board/trab/tsc2000.c | 2 +- board/trab/vfd.c | 2 +- cpu/arm920t/s3c24x0/interrupts.c | 4 +- cpu/arm920t/s3c24x0/speed.c | 4 +- cpu/arm920t/s3c24x0/timer.c | 4 +- cpu/arm920t/s3c24x0/usb.c | 4 +- cpu/arm920t/s3c24x0/usb_ohci.c | 4 +- drivers/i2c/s3c24x0_i2c.c | 4 +- drivers/mtd/nand/s3c2410_nand.c | 2 +- drivers/rtc/s3c24x0_rtc.c | 4 +- drivers/serial/serial_s3c24x0.c | 4 +- include/asm-arm/arch-s3c24x0/s3c2400.h | 136 +++++++ include/asm-arm/arch-s3c24x0/s3c2410.h | 146 ++++++++ include/asm-arm/arch-s3c24x0/s3c24x0.h | 656 +++++++++++++++++++++++++++++++++ include/s3c2400.h | 136 ------- include/s3c2410.h | 146 -------- include/s3c24x0.h | 656 --------------------------------- 27 files changed, 967 insertions(+), 967 deletions(-) create mode 100644 include/asm-arm/arch-s3c24x0/s3c2400.h create mode 100644 include/asm-arm/arch-s3c24x0/s3c2410.h create mode 100644 include/asm-arm/arch-s3c24x0/s3c24x0.h delete mode 100644 include/s3c2400.h delete mode 100644 include/s3c2410.h delete mode 100644 include/s3c24x0.h (limited to 'drivers') diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 4d8b579ca..f3bd28845 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index f46e0e4c5..9f32808c6 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -25,7 +25,7 @@ * Global routines used for VCMA9 *****************************************************************************/ -#include +#include extern int mem_test(unsigned long start, unsigned long ramsize,int mode); diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index 42bf00868..be0c70ad0 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -27,7 +27,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index fde773093..a8cf2874a 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -27,7 +27,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 7452c1f94..6768c028c 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -30,7 +30,7 @@ #include #include -#include +#include #if defined(CONFIG_CMD_NAND) #include diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index 04a36075b..a01ffcc02 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include /* diff --git a/board/trab/rs485.c b/board/trab/rs485.c index 7d5c0a2c9..f402c5990 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -22,7 +22,7 @@ */ #include -#include +#include #include "rs485.h" static void rs485_setbrg (void); diff --git a/board/trab/rs485.h b/board/trab/rs485.h index 9f0a5b9b4..4a2d83f0b 100644 --- a/board/trab/rs485.h +++ b/board/trab/rs485.h @@ -24,7 +24,7 @@ #ifndef _RS485_H_ #define _RS485_H_ -#include +#include int rs485_init (void); int rs485_getc (void); diff --git a/board/trab/trab.c b/board/trab/trab.c index ea782a913..f8836ff37 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index dc2a8d775..940e12f25 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include "tsc2000.h" #include "rs485.h" diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index fc501a8a4..f757202de 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -26,7 +26,7 @@ */ #include -#include +#include #include #include #include "tsc2000.h" diff --git a/board/trab/vfd.c b/board/trab/vfd.c index d5ad5bbdf..8d9a05716 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 914894613..3e8422e14 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -32,9 +32,9 @@ #include #if defined(CONFIG_S3C2400) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif #include diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c index 136c7794a..85c73a3ee 100644 --- a/cpu/arm920t/s3c24x0/speed.c +++ b/cpu/arm920t/s3c24x0/speed.c @@ -35,9 +35,9 @@ #include #if defined(CONFIG_S3C2400) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif #define MPLL 0 diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 20cedd463..2667da6e8 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -37,9 +37,9 @@ #include #if defined(CONFIG_S3C2400) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif int timer_load_val = 0; diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index b5ba8c4f3..5e19cda8f 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -27,9 +27,9 @@ # if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) #if defined(CONFIG_S3C2400) -# include +# include #elif defined(CONFIG_S3C2410) -# include +# include #endif #include diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 7672e4ce1..41119922e 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -39,9 +39,9 @@ #ifdef CONFIG_USB_OHCI #if defined(CONFIG_S3C2400) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif #include diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 55c6a12aa..8fecc6e3f 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -28,9 +28,9 @@ #include #if defined(CONFIG_S3C2400) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif #include diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index 815c78eb6..2f89b8c96 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #define S3C2410_NFCONF_EN (1<<15) diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 1ce34e38d..2d78f93ae 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -31,9 +31,9 @@ #if (defined(CONFIG_CMD_DATE)) #if defined(CONFIG_S3C2400) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif #include diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index c2c72e456..914d07cda 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -20,9 +20,9 @@ #include #if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) -#include +#include #elif defined(CONFIG_S3C2410) -#include +#include #endif DECLARE_GLOBAL_DATA_PTR; diff --git a/include/asm-arm/arch-s3c24x0/s3c2400.h b/include/asm-arm/arch-s3c24x0/s3c2400.h new file mode 100644 index 000000000..26bd4e49a --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c2400.h @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2400.h + * Version : 31.3.2003 + * + * Based on S3C2400X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2400_H__ +#define __S3C2400_H__ + +#define S3C24X0_UART_CHANNELS 2 +#define S3C24X0_SPI_CHANNELS 1 +#define PALETTE (0x14A00400) /* SJS */ + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, +}; + +/*S3C2400 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x14000000 +#define S3C24X0_USB_HOST_BASE 0x14200000 +#define S3C24X0_INTERRUPT_BASE 0x14400000 +#define S3C24X0_DMA_BASE 0x14600000 +#define S3C24X0_CLOCK_POWER_BASE 0x14800000 +#define S3C24X0_LCD_BASE 0x14A00000 +#define S3C24X0_UART_BASE 0x15000000 +#define S3C24X0_TIMER_BASE 0x15100000 +#define S3C24X0_USB_DEVICE_BASE 0x15200140 +#define S3C24X0_WATCHDOG_BASE 0x15300000 +#define S3C24X0_I2C_BASE 0x15400000 +#define S3C24X0_I2S_BASE 0x15508000 +#define S3C24X0_GPIO_BASE 0x15600000 +#define S3C24X0_RTC_BASE 0x15700000 +#define S3C24X0_ADC_BASE 0x15800000 +#define S3C24X0_SPI_BASE 0x15900000 +#define S3C2400_MMC_BASE 0x15A00000 + +/* include common stuff */ +#include + + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} +static inline struct s3c2400_adc *s3c2400_get_base_adc(void) +{ + return (struct s3c2400_adc *)S3C24X0_ADC_BASE; +} +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} +static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) +{ + return (struct s3c2400_mmc *)S3C2400_MMC_BASE; +} + +#endif /*__S3C2400_H__*/ diff --git a/include/asm-arm/arch-s3c24x0/s3c2410.h b/include/asm-arm/arch-s3c24x0/s3c2410.h new file mode 100644 index 000000000..be2e76e5f --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c2410.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2410.h + * Version : 31.3.2003 + * + * Based on S3C2410X User's manual Rev 1.1 + ************************************************/ + +#ifndef __S3C2410_H__ +#define __S3C2410_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2410 only supports 512 Byte HW ECC */ +#define S3C2410_ECCSIZE 512 +#define S3C2410_ECCBYTES 3 + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +}; + +/* S3C2410 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2410_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2410_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2410_SDI_BASE 0x5A000000 + + +/* include common stuff */ +#include + + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} +static inline struct s3c2410_nand *s3c2410_get_base_nand(void) +{ + return (struct s3c2410_nand *)S3C2410_NAND_BASE; +} +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} +static inline struct s3c2410_adc *s3c2410_get_base_adc(void) +{ + return (struct s3c2410_adc *)S3C2410_ADC_BASE; +} +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} +static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) +{ + return (struct s3c2410_sdi *)S3C2410_SDI_BASE; +} + +#endif /*__S3C2410_H__*/ diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0.h b/include/asm-arm/arch-s3c24x0/s3c24x0.h new file mode 100644 index 000000000..56a551aeb --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c24x0.h @@ -0,0 +1,656 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c24x0.h + * Version : 31.3.2003 + * + * common stuff for SAMSUNG S3C24X0 SoC + ************************************************/ + +#ifndef __S3C24X0_H__ +#define __S3C24X0_H__ + +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; + +/* Memory controller (see manual chapter 5) */ +struct s3c24x0_memctl { + S3C24X0_REG32 BWSCON; + S3C24X0_REG32 BANKCON[8]; + S3C24X0_REG32 REFRESH; + S3C24X0_REG32 BANKSIZE; + S3C24X0_REG32 MRSRB6; + S3C24X0_REG32 MRSRB7; +}; + + +/* USB HOST (see manual chapter 12) */ +struct s3c24x0_usb_host { + S3C24X0_REG32 HcRevision; + S3C24X0_REG32 HcControl; + S3C24X0_REG32 HcCommonStatus; + S3C24X0_REG32 HcInterruptStatus; + S3C24X0_REG32 HcInterruptEnable; + S3C24X0_REG32 HcInterruptDisable; + S3C24X0_REG32 HcHCCA; + S3C24X0_REG32 HcPeriodCuttendED; + S3C24X0_REG32 HcControlHeadED; + S3C24X0_REG32 HcControlCurrentED; + S3C24X0_REG32 HcBulkHeadED; + S3C24X0_REG32 HcBuldCurrentED; + S3C24X0_REG32 HcDoneHead; + S3C24X0_REG32 HcRmInterval; + S3C24X0_REG32 HcFmRemaining; + S3C24X0_REG32 HcFmNumber; + S3C24X0_REG32 HcPeriodicStart; + S3C24X0_REG32 HcLSThreshold; + S3C24X0_REG32 HcRhDescriptorA; + S3C24X0_REG32 HcRhDescriptorB; + S3C24X0_REG32 HcRhStatus; + S3C24X0_REG32 HcRhPortStatus1; + S3C24X0_REG32 HcRhPortStatus2; +}; + + +/* INTERRUPT (see manual chapter 14) */ +struct s3c24x0_interrupt { + S3C24X0_REG32 SRCPND; + S3C24X0_REG32 INTMOD; + S3C24X0_REG32 INTMSK; + S3C24X0_REG32 PRIORITY; + S3C24X0_REG32 INTPND; + S3C24X0_REG32 INTOFFSET; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 SUBSRCPND; + S3C24X0_REG32 INTSUBMSK; +#endif +}; + + +/* DMAS (see manual chapter 8) */ +struct s3c24x0_dma { + S3C24X0_REG32 DISRC; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 DISRCC; +#endif + S3C24X0_REG32 DIDST; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 DIDSTC; +#endif + S3C24X0_REG32 DCON; + S3C24X0_REG32 DSTAT; + S3C24X0_REG32 DCSRC; + S3C24X0_REG32 DCDST; + S3C24X0_REG32 DMASKTRIG; +#ifdef CONFIG_S3C2400 + S3C24X0_REG32 res[1]; +#endif +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 res[7]; +#endif +}; + +struct s3c24x0_dmas { + struct s3c24x0_dma dma[4]; +}; + + +/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ +/* (see S3C2410 manual chapter 7) */ +struct s3c24x0_clock_power { + S3C24X0_REG32 LOCKTIME; + S3C24X0_REG32 MPLLCON; + S3C24X0_REG32 UPLLCON; + S3C24X0_REG32 CLKCON; + S3C24X0_REG32 CLKSLOW; + S3C24X0_REG32 CLKDIVN; +}; + + +/* LCD CONTROLLER (see manual chapter 15) */ +struct s3c24x0_lcd { + S3C24X0_REG32 LCDCON1; + S3C24X0_REG32 LCDCON2; + S3C24X0_REG32 LCDCON3; + S3C24X0_REG32 LCDCON4; + S3C24X0_REG32 LCDCON5; + S3C24X0_REG32 LCDSADDR1; + S3C24X0_REG32 LCDSADDR2; + S3C24X0_REG32 LCDSADDR3; + S3C24X0_REG32 REDLUT; + S3C24X0_REG32 GREENLUT; + S3C24X0_REG32 BLUELUT; + S3C24X0_REG32 res[8]; + S3C24X0_REG32 DITHMODE; + S3C24X0_REG32 TPAL; +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 LCDINTPND; + S3C24X0_REG32 LCDSRCPND; + S3C24X0_REG32 LCDINTMSK; + S3C24X0_REG32 LPCSEL; +#endif +}; + + +/* NAND FLASH (see S3C2410 manual chapter 6) */ +struct s3c2410_nand { + S3C24X0_REG32 NFCONF; + S3C24X0_REG32 NFCMD; + S3C24X0_REG32 NFADDR; + S3C24X0_REG32 NFDATA; + S3C24X0_REG32 NFSTAT; + S3C24X0_REG32 NFECC; +}; + + +/* UART (see manual chapter 11) */ +struct s3c24x0_uart { + S3C24X0_REG32 ULCON; + S3C24X0_REG32 UCON; + S3C24X0_REG32 UFCON; + S3C24X0_REG32 UMCON; + S3C24X0_REG32 UTRSTAT; + S3C24X0_REG32 UERSTAT; + S3C24X0_REG32 UFSTAT; + S3C24X0_REG32 UMSTAT; +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 UTXH; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 URXH; +#else /* Little Endian */ + S3C24X0_REG8 UTXH; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 URXH; + S3C24X0_REG8 res2[3]; +#endif + S3C24X0_REG32 UBRDIV; +}; + + +/* PWM TIMER (see manual chapter 10) */ +struct s3c24x0_timer { + S3C24X0_REG32 TCNTB; + S3C24X0_REG32 TCMPB; + S3C24X0_REG32 TCNTO; +}; + +struct s3c24x0_timers { + S3C24X0_REG32 TCFG0; + S3C24X0_REG32 TCFG1; + S3C24X0_REG32 TCON; + struct s3c24x0_timer ch[4]; + S3C24X0_REG32 TCNTB4; + S3C24X0_REG32 TCNTO4; +}; + + +/* USB DEVICE (see manual chapter 13) */ +struct s3c24x0_usb_dev_fifos { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res[3]; + S3C24X0_REG8 EP_FIFO_REG; +#else /* little endian */ + S3C24X0_REG8 EP_FIFO_REG; + S3C24X0_REG8 res[3]; +#endif +}; + +struct s3c24x0_usb_dev_dmas { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 EP_DMA_CON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_DMA_UNIT; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_DMA_FIFO; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_DMA_TTC_L; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_DMA_TTC_M; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 EP_DMA_TTC_H; +#else /* little endian */ + S3C24X0_REG8 EP_DMA_CON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 EP_DMA_UNIT; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_DMA_FIFO; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_DMA_TTC_L; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_DMA_TTC_M; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_DMA_TTC_H; + S3C24X0_REG8 res6[3]; +#endif +}; + +struct s3c24x0_usb_device { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 FUNC_ADDR_REG; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 PWR_REG; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 EP_INT_REG; + S3C24X0_REG8 res4[15]; + S3C24X0_REG8 USB_INT_REG; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 EP_INT_EN_REG; + S3C24X0_REG8 res6[15]; + S3C24X0_REG8 USB_INT_EN_REG; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 FRAME_NUM1_REG; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 FRAME_NUM2_REG; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 INDEX_REG; + S3C24X0_REG8 res10[7]; + S3C24X0_REG8 MAXP_REG; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 IN_CSR2_REG; + S3C24X0_REG8 res13[7]; + S3C24X0_REG8 OUT_CSR1_REG; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 OUT_CSR2_REG; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 OUT_FIFO_CNT1_REG; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 OUT_FIFO_CNT2_REG; +#else /* little endian */ + S3C24X0_REG8 FUNC_ADDR_REG; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 PWR_REG; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 EP_INT_REG; + S3C24X0_REG8 res3[15]; + S3C24X0_REG8 USB_INT_REG; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 EP_INT_EN_REG; + S3C24X0_REG8 res5[15]; + S3C24X0_REG8 USB_INT_EN_REG; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 FRAME_NUM1_REG; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 FRAME_NUM2_REG; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 INDEX_REG; + S3C24X0_REG8 res9[7]; + S3C24X0_REG8 MAXP_REG; + S3C24X0_REG8 res10[7]; + S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 IN_CSR2_REG; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 OUT_CSR1_REG; + S3C24X0_REG8 res13[7]; + S3C24X0_REG8 OUT_CSR2_REG; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 OUT_FIFO_CNT1_REG; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 OUT_FIFO_CNT2_REG; + S3C24X0_REG8 res16[3]; +#endif /* __BIG_ENDIAN */ + struct s3c24x0_usb_dev_fifos fifo[5]; + struct s3c24x0_usb_dev_dmas dma[5]; +}; + + +/* WATCH DOG TIMER (see manual chapter 18) */ +struct s3c24x0_watchdog { + S3C24X0_REG32 WTCON; + S3C24X0_REG32 WTDAT; + S3C24X0_REG32 WTCNT; +}; + + +/* IIC (see manual chapter 20) */ +struct s3c24x0_i2c { + S3C24X0_REG32 IICCON; + S3C24X0_REG32 IICSTAT; + S3C24X0_REG32 IICADD; + S3C24X0_REG32 IICDS; +}; + + +/* IIS (see manual chapter 21) */ +struct s3c24x0_i2s { +#ifdef __BIG_ENDIAN + S3C24X0_REG16 res1; + S3C24X0_REG16 IISCON; + S3C24X0_REG16 res2; + S3C24X0_REG16 IISMOD; + S3C24X0_REG16 res3; + S3C24X0_REG16 IISPSR; + S3C24X0_REG16 res4; + S3C24X0_REG16 IISFCON; + S3C24X0_REG16 res5; + S3C24X0_REG16 IISFIFO; +#else /* little endian */ + S3C24X0_REG16 IISCON; + S3C24X0_REG16 res1; + S3C24X0_REG16 IISMOD; + S3C24X0_REG16 res2; + S3C24X0_REG16 IISPSR; + S3C24X0_REG16 res3; + S3C24X0_REG16 IISFCON; + S3C24X0_REG16 res4; + S3C24X0_REG16 IISFIFO; + S3C24X0_REG16 res5; +#endif +}; + + +/* I/O PORT (see manual chapter 9) */ +struct s3c24x0_gpio { +#ifdef CONFIG_S3C2400 + S3C24X0_REG32 PACON; + S3C24X0_REG32 PADAT; + + S3C24X0_REG32 PBCON; + S3C24X0_REG32 PBDAT; + S3C24X0_REG32 PBUP; + + S3C24X0_REG32 PCCON; + S3C24X0_REG32 PCDAT; + S3C24X0_REG32 PCUP; + + S3C24X0_REG32 PDCON; + S3C24X0_REG32 PDDAT; + S3C24X0_REG32 PDUP; + + S3C24X0_REG32 PECON; + S3C24X0_REG32 PEDAT; + S3C24X0_REG32 PEUP; + + S3C24X0_REG32 PFCON; + S3C24X0_REG32 PFDAT; + S3C24X0_REG32 PFUP; + + S3C24X0_REG32 PGCON; + S3C24X0_REG32 PGDAT; + S3C24X0_REG32 PGUP; + + S3C24X0_REG32 OPENCR; + + S3C24X0_REG32 MISCCR; + S3C24X0_REG32 EXTINT; +#endif +#ifdef CONFIG_S3C2410 + S3C24X0_REG32 GPACON; + S3C24X0_REG32 GPADAT; + S3C24X0_REG32 res1[2]; + S3C24X0_REG32 GPBCON; + S3C24X0_REG32 GPBDAT; + S3C24X0_REG32 GPBUP; + S3C24X0_REG32 res2; + S3C24X0_REG32 GPCCON; + S3C24X0_REG32 GPCDAT; + S3C24X0_REG32 GPCUP; + S3C24X0_REG32 res3; + S3C24X0_REG32 GPDCON; + S3C24X0_REG32 GPDDAT; + S3C24X0_REG32 GPDUP; + S3C24X0_REG32 res4; + S3C24X0_REG32 GPECON; + S3C24X0_REG32 GPEDAT; + S3C24X0_REG32 GPEUP; + S3C24X0_REG32 res5; + S3C24X0_REG32 GPFCON; + S3C24X0_REG32 GPFDAT; + S3C24X0_REG32 GPFUP; + S3C24X0_REG32 res6; + S3C24X0_REG32 GPGCON; + S3C24X0_REG32 GPGDAT; + S3C24X0_REG32 GPGUP; + S3C24X0_REG32 res7; + S3C24X0_REG32 GPHCON; + S3C24X0_REG32 GPHDAT; + S3C24X0_REG32 GPHUP; + S3C24X0_REG32 res8; + + S3C24X0_REG32 MISCCR; + S3C24X0_REG32 DCLKCON; + S3C24X0_REG32 EXTINT0; + S3C24X0_REG32 EXTINT1; + S3C24X0_REG32 EXTINT2; + S3C24X0_REG32 EINTFLT0; + S3C24X0_REG32 EINTFLT1; + S3C24X0_REG32 EINTFLT2; + S3C24X0_REG32 EINTFLT3; + S3C24X0_REG32 EINTMASK; + S3C24X0_REG32 EINTPEND; + S3C24X0_REG32 GSTATUS0; + S3C24X0_REG32 GSTATUS1; + S3C24X0_REG32 GSTATUS2; + S3C24X0_REG32 GSTATUS3; + S3C24X0_REG32 GSTATUS4; +#endif +}; + + +/* RTC (see manual chapter 17) */ +struct s3c24x0_rtc { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[67]; + S3C24X0_REG8 RTCCON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 TICNT; + S3C24X0_REG8 res3[11]; + S3C24X0_REG8 RTCALM; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 ALMSEC; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 ALMMIN; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 ALMHOUR; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 ALMDATE; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 ALMMON; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 ALMYEAR; + S3C24X0_REG8 res10[3]; + S3C24X0_REG8 RTCRST; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 BCDSEC; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 BCDMIN; + S3C24X0_REG8 res13[3]; + S3C24X0_REG8 BCDHOUR; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 BCDDATE; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 BCDDAY; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 BCDMON; + S3C24X0_REG8 res17[3]; + S3C24X0_REG8 BCDYEAR; +#else /* little endian */ + S3C24X0_REG8 res0[64]; + S3C24X0_REG8 RTCCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 TICNT; + S3C24X0_REG8 res2[11]; + S3C24X0_REG8 RTCALM; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 ALMSEC; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 ALMMIN; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 ALMHOUR; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 ALMDATE; + S3C24X0_REG8 res7[3]; + S3C24X0_REG8 ALMMON; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 ALMYEAR; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 RTCRST; + S3C24X0_REG8 res10[3]; + S3C24X0_REG8 BCDSEC; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 BCDMIN; + S3C24X0_REG8 res12[3]; + S3C24X0_REG8 BCDHOUR; + S3C24X0_REG8 res13[3]; + S3C24X0_REG8 BCDDATE; + S3C24X0_REG8 res14[3]; + S3C24X0_REG8 BCDDAY; + S3C24X0_REG8 res15[3]; + S3C24X0_REG8 BCDMON; + S3C24X0_REG8 res16[3]; + S3C24X0_REG8 BCDYEAR; + S3C24X0_REG8 res17[3]; +#endif +}; + + +/* ADC (see manual chapter 16) */ +struct s3c2400_adc { + S3C24X0_REG32 ADCCON; + S3C24X0_REG32 ADCDAT; +}; + + +/* ADC (see manual chapter 16) */ +struct s3c2410_adc { + S3C24X0_REG32 ADCCON; + S3C24X0_REG32 ADCTSC; + S3C24X0_REG32 ADCDLY; + S3C24X0_REG32 ADCDAT0; + S3C24X0_REG32 ADCDAT1; +}; + + +/* SPI (see manual chapter 22) */ +struct s3c24x0_spi_channel { + S3C24X0_REG8 SPCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 SPSTA; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 SPPIN; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 SPPRE; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 SPTDAT; + S3C24X0_REG8 res5[3]; + S3C24X0_REG8 SPRDAT; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 res7[16]; +}; + +struct s3c24x0_spi { + struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; +}; + + +/* MMC INTERFACE (see S3C2400 manual chapter 19) */ +struct s3c2400_mmc { +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 MMCON; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 MMCRR; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 MMFCON; + S3C24X0_REG8 res4[3]; + S3C24X0_REG8 MMSTA; + S3C24X0_REG16 res5; + S3C24X0_REG16 MMFSTA; + S3C24X0_REG8 res6[3]; + S3C24X0_REG8 MMPRE; + S3C24X0_REG16 res7; + S3C24X0_REG16 MMLEN; + S3C24X0_REG8 res8[3]; + S3C24X0_REG8 MMCR7; + S3C24X0_REG32 MMRSP[4]; + S3C24X0_REG8 res9[3]; + S3C24X0_REG8 MMCMD0; + S3C24X0_REG32 MMCMD1; + S3C24X0_REG16 res10; + S3C24X0_REG16 MMCR16; + S3C24X0_REG8 res11[3]; + S3C24X0_REG8 MMDAT; +#else + S3C24X0_REG8 MMCON; + S3C24X0_REG8 res1[3]; + S3C24X0_REG8 MMCRR; + S3C24X0_REG8 res2[3]; + S3C24X0_REG8 MMFCON; + S3C24X0_REG8 res3[3]; + S3C24X0_REG8 MMSTA; + S3C24X0_REG8 res4[3]; + S3C24X0_REG16 MMFSTA; + S3C24X0_REG16 res5; + S3C24X0_REG8 MMPRE; + S3C24X0_REG8 res6[3]; + S3C24X0_REG16 MMLEN; + S3C24X0_REG16 res7; + S3C24X0_REG8 MMCR7; + S3C24X0_REG8 res8[3]; + S3C24X0_REG32 MMRSP[4]; + S3C24X0_REG8 MMCMD0; + S3C24X0_REG8 res9[3]; + S3C24X0_REG32 MMCMD1; + S3C24X0_REG16 MMCR16; + S3C24X0_REG16 res10; + S3C24X0_REG8 MMDAT; + S3C24X0_REG8 res11[3]; +#endif +}; + + +/* SD INTERFACE (see S3C2410 manual chapter 19) */ +struct s3c2410_sdi { + S3C24X0_REG32 SDICON; + S3C24X0_REG32 SDIPRE; + S3C24X0_REG32 SDICARG; + S3C24X0_REG32 SDICCON; + S3C24X0_REG32 SDICSTA; + S3C24X0_REG32 SDIRSP0; + S3C24X0_REG32 SDIRSP1; + S3C24X0_REG32 SDIRSP2; + S3C24X0_REG32 SDIRSP3; + S3C24X0_REG32 SDIDTIMER; + S3C24X0_REG32 SDIBSIZE; + S3C24X0_REG32 SDIDCON; + S3C24X0_REG32 SDIDCNT; + S3C24X0_REG32 SDIDSTA; + S3C24X0_REG32 SDIFSTA; +#ifdef __BIG_ENDIAN + S3C24X0_REG8 res[3]; + S3C24X0_REG8 SDIDAT; +#else + S3C24X0_REG8 SDIDAT; + S3C24X0_REG8 res[3]; +#endif + S3C24X0_REG32 SDIIMSK; +}; + +#endif /*__S3C24X0_H__*/ diff --git a/include/s3c2400.h b/include/s3c2400.h deleted file mode 100644 index 062259d10..000000000 --- a/include/s3c2400.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c2400.h - * Version : 31.3.2003 - * - * Based on S3C2400X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2400_H__ -#define __S3C2400_H__ - -#define S3C24X0_UART_CHANNELS 2 -#define S3C24X0_SPI_CHANNELS 1 -#define PALETTE (0x14A00400) /* SJS */ - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, -}; - -/*S3C2400 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x14000000 -#define S3C24X0_USB_HOST_BASE 0x14200000 -#define S3C24X0_INTERRUPT_BASE 0x14400000 -#define S3C24X0_DMA_BASE 0x14600000 -#define S3C24X0_CLOCK_POWER_BASE 0x14800000 -#define S3C24X0_LCD_BASE 0x14A00000 -#define S3C24X0_UART_BASE 0x15000000 -#define S3C24X0_TIMER_BASE 0x15100000 -#define S3C24X0_USB_DEVICE_BASE 0x15200140 -#define S3C24X0_WATCHDOG_BASE 0x15300000 -#define S3C24X0_I2C_BASE 0x15400000 -#define S3C24X0_I2S_BASE 0x15508000 -#define S3C24X0_GPIO_BASE 0x15600000 -#define S3C24X0_RTC_BASE 0x15700000 -#define S3C24X0_ADC_BASE 0x15800000 -#define S3C24X0_SPI_BASE 0x15900000 -#define S3C2400_MMC_BASE 0x15A00000 - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} -static inline struct s3c2400_adc *s3c2400_get_base_adc(void) -{ - return (struct s3c2400_adc *)S3C24X0_ADC_BASE; -} -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} -static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) -{ - return (struct s3c2400_mmc *)S3C2400_MMC_BASE; -} - -#endif /*__S3C2400_H__*/ diff --git a/include/s3c2410.h b/include/s3c2410.h deleted file mode 100644 index 03b33b492..000000000 --- a/include/s3c2410.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c2410.h - * Version : 31.3.2003 - * - * Based on S3C2410X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2410_H__ -#define __S3C2410_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2410 only supports 512 Byte HW ECC */ -#define S3C2410_ECCSIZE 512 -#define S3C2410_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2410 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2410_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2410_SDI_BASE 0x5A000000 - - -/* include common stuff */ -#include - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} -static inline struct s3c2410_nand *s3c2410_get_base_nand(void) -{ - return (struct s3c2410_nand *)S3C2410_NAND_BASE; -} -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} -static inline struct s3c2410_adc *s3c2410_get_base_adc(void) -{ - return (struct s3c2410_adc *)S3C2410_ADC_BASE; -} -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} -static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void) -{ - return (struct s3c2410_sdi *)S3C2410_SDI_BASE; -} - -#endif /*__S3C2410_H__*/ diff --git a/include/s3c24x0.h b/include/s3c24x0.h deleted file mode 100644 index 56a551aeb..000000000 --- a/include/s3c24x0.h +++ /dev/null @@ -1,656 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c24x0.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C24X0 SoC - ************************************************/ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -typedef volatile u8 S3C24X0_REG8; -typedef volatile u16 S3C24X0_REG16; -typedef volatile u32 S3C24X0_REG32; - -/* Memory controller (see manual chapter 5) */ -struct s3c24x0_memctl { - S3C24X0_REG32 BWSCON; - S3C24X0_REG32 BANKCON[8]; - S3C24X0_REG32 REFRESH; - S3C24X0_REG32 BANKSIZE; - S3C24X0_REG32 MRSRB6; - S3C24X0_REG32 MRSRB7; -}; - - -/* USB HOST (see manual chapter 12) */ -struct s3c24x0_usb_host { - S3C24X0_REG32 HcRevision; - S3C24X0_REG32 HcControl; - S3C24X0_REG32 HcCommonStatus; - S3C24X0_REG32 HcInterruptStatus; - S3C24X0_REG32 HcInterruptEnable; - S3C24X0_REG32 HcInterruptDisable; - S3C24X0_REG32 HcHCCA; - S3C24X0_REG32 HcPeriodCuttendED; - S3C24X0_REG32 HcControlHeadED; - S3C24X0_REG32 HcControlCurrentED; - S3C24X0_REG32 HcBulkHeadED; - S3C24X0_REG32 HcBuldCurrentED; - S3C24X0_REG32 HcDoneHead; - S3C24X0_REG32 HcRmInterval; - S3C24X0_REG32 HcFmRemaining; - S3C24X0_REG32 HcFmNumber; - S3C24X0_REG32 HcPeriodicStart; - S3C24X0_REG32 HcLSThreshold; - S3C24X0_REG32 HcRhDescriptorA; - S3C24X0_REG32 HcRhDescriptorB; - S3C24X0_REG32 HcRhStatus; - S3C24X0_REG32 HcRhPortStatus1; - S3C24X0_REG32 HcRhPortStatus2; -}; - - -/* INTERRUPT (see manual chapter 14) */ -struct s3c24x0_interrupt { - S3C24X0_REG32 SRCPND; - S3C24X0_REG32 INTMOD; - S3C24X0_REG32 INTMSK; - S3C24X0_REG32 PRIORITY; - S3C24X0_REG32 INTPND; - S3C24X0_REG32 INTOFFSET; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 SUBSRCPND; - S3C24X0_REG32 INTSUBMSK; -#endif -}; - - -/* DMAS (see manual chapter 8) */ -struct s3c24x0_dma { - S3C24X0_REG32 DISRC; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 DISRCC; -#endif - S3C24X0_REG32 DIDST; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 DIDSTC; -#endif - S3C24X0_REG32 DCON; - S3C24X0_REG32 DSTAT; - S3C24X0_REG32 DCSRC; - S3C24X0_REG32 DCDST; - S3C24X0_REG32 DMASKTRIG; -#ifdef CONFIG_S3C2400 - S3C24X0_REG32 res[1]; -#endif -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 res[7]; -#endif -}; - -struct s3c24x0_dmas { - struct s3c24x0_dma dma[4]; -}; - - -/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ -/* (see S3C2410 manual chapter 7) */ -struct s3c24x0_clock_power { - S3C24X0_REG32 LOCKTIME; - S3C24X0_REG32 MPLLCON; - S3C24X0_REG32 UPLLCON; - S3C24X0_REG32 CLKCON; - S3C24X0_REG32 CLKSLOW; - S3C24X0_REG32 CLKDIVN; -}; - - -/* LCD CONTROLLER (see manual chapter 15) */ -struct s3c24x0_lcd { - S3C24X0_REG32 LCDCON1; - S3C24X0_REG32 LCDCON2; - S3C24X0_REG32 LCDCON3; - S3C24X0_REG32 LCDCON4; - S3C24X0_REG32 LCDCON5; - S3C24X0_REG32 LCDSADDR1; - S3C24X0_REG32 LCDSADDR2; - S3C24X0_REG32 LCDSADDR3; - S3C24X0_REG32 REDLUT; - S3C24X0_REG32 GREENLUT; - S3C24X0_REG32 BLUELUT; - S3C24X0_REG32 res[8]; - S3C24X0_REG32 DITHMODE; - S3C24X0_REG32 TPAL; -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 LCDINTPND; - S3C24X0_REG32 LCDSRCPND; - S3C24X0_REG32 LCDINTMSK; - S3C24X0_REG32 LPCSEL; -#endif -}; - - -/* NAND FLASH (see S3C2410 manual chapter 6) */ -struct s3c2410_nand { - S3C24X0_REG32 NFCONF; - S3C24X0_REG32 NFCMD; - S3C24X0_REG32 NFADDR; - S3C24X0_REG32 NFDATA; - S3C24X0_REG32 NFSTAT; - S3C24X0_REG32 NFECC; -}; - - -/* UART (see manual chapter 11) */ -struct s3c24x0_uart { - S3C24X0_REG32 ULCON; - S3C24X0_REG32 UCON; - S3C24X0_REG32 UFCON; - S3C24X0_REG32 UMCON; - S3C24X0_REG32 UTRSTAT; - S3C24X0_REG32 UERSTAT; - S3C24X0_REG32 UFSTAT; - S3C24X0_REG32 UMSTAT; -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 URXH; -#else /* Little Endian */ - S3C24X0_REG8 UTXH; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 URXH; - S3C24X0_REG8 res2[3]; -#endif - S3C24X0_REG32 UBRDIV; -}; - - -/* PWM TIMER (see manual chapter 10) */ -struct s3c24x0_timer { - S3C24X0_REG32 TCNTB; - S3C24X0_REG32 TCMPB; - S3C24X0_REG32 TCNTO; -}; - -struct s3c24x0_timers { - S3C24X0_REG32 TCFG0; - S3C24X0_REG32 TCFG1; - S3C24X0_REG32 TCON; - struct s3c24x0_timer ch[4]; - S3C24X0_REG32 TCNTB4; - S3C24X0_REG32 TCNTO4; -}; - - -/* USB DEVICE (see manual chapter 13) */ -struct s3c24x0_usb_dev_fifos { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 EP_FIFO_REG; -#else /* little endian */ - S3C24X0_REG8 EP_FIFO_REG; - S3C24X0_REG8 res[3]; -#endif -}; - -struct s3c24x0_usb_dev_dmas { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 EP_DMA_TTC_H; -#else /* little endian */ - S3C24X0_REG8 EP_DMA_CON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 EP_DMA_UNIT; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_DMA_FIFO; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_DMA_TTC_L; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_DMA_TTC_M; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_DMA_TTC_H; - S3C24X0_REG8 res6[3]; -#endif -}; - -struct s3c24x0_usb_device { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res4[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res6[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; -#else /* little endian */ - S3C24X0_REG8 FUNC_ADDR_REG; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 PWR_REG; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 EP_INT_REG; - S3C24X0_REG8 res3[15]; - S3C24X0_REG8 USB_INT_REG; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 EP_INT_EN_REG; - S3C24X0_REG8 res5[15]; - S3C24X0_REG8 USB_INT_EN_REG; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 FRAME_NUM1_REG; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 FRAME_NUM2_REG; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 INDEX_REG; - S3C24X0_REG8 res9[7]; - S3C24X0_REG8 MAXP_REG; - S3C24X0_REG8 res10[7]; - S3C24X0_REG8 EP0_CSR_IN_CSR1_REG; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 IN_CSR2_REG; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 OUT_CSR1_REG; - S3C24X0_REG8 res13[7]; - S3C24X0_REG8 OUT_CSR2_REG; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 OUT_FIFO_CNT1_REG; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 OUT_FIFO_CNT2_REG; - S3C24X0_REG8 res16[3]; -#endif /* __BIG_ENDIAN */ - struct s3c24x0_usb_dev_fifos fifo[5]; - struct s3c24x0_usb_dev_dmas dma[5]; -}; - - -/* WATCH DOG TIMER (see manual chapter 18) */ -struct s3c24x0_watchdog { - S3C24X0_REG32 WTCON; - S3C24X0_REG32 WTDAT; - S3C24X0_REG32 WTCNT; -}; - - -/* IIC (see manual chapter 20) */ -struct s3c24x0_i2c { - S3C24X0_REG32 IICCON; - S3C24X0_REG32 IICSTAT; - S3C24X0_REG32 IICADD; - S3C24X0_REG32 IICDS; -}; - - -/* IIS (see manual chapter 21) */ -struct s3c24x0_i2s { -#ifdef __BIG_ENDIAN - S3C24X0_REG16 res1; - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res5; - S3C24X0_REG16 IISFIFO; -#else /* little endian */ - S3C24X0_REG16 IISCON; - S3C24X0_REG16 res1; - S3C24X0_REG16 IISMOD; - S3C24X0_REG16 res2; - S3C24X0_REG16 IISPSR; - S3C24X0_REG16 res3; - S3C24X0_REG16 IISFCON; - S3C24X0_REG16 res4; - S3C24X0_REG16 IISFIFO; - S3C24X0_REG16 res5; -#endif -}; - - -/* I/O PORT (see manual chapter 9) */ -struct s3c24x0_gpio { -#ifdef CONFIG_S3C2400 - S3C24X0_REG32 PACON; - S3C24X0_REG32 PADAT; - - S3C24X0_REG32 PBCON; - S3C24X0_REG32 PBDAT; - S3C24X0_REG32 PBUP; - - S3C24X0_REG32 PCCON; - S3C24X0_REG32 PCDAT; - S3C24X0_REG32 PCUP; - - S3C24X0_REG32 PDCON; - S3C24X0_REG32 PDDAT; - S3C24X0_REG32 PDUP; - - S3C24X0_REG32 PECON; - S3C24X0_REG32 PEDAT; - S3C24X0_REG32 PEUP; - - S3C24X0_REG32 PFCON; - S3C24X0_REG32 PFDAT; - S3C24X0_REG32 PFUP; - - S3C24X0_REG32 PGCON; - S3C24X0_REG32 PGDAT; - S3C24X0_REG32 PGUP; - - S3C24X0_REG32 OPENCR; - - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 EXTINT; -#endif -#ifdef CONFIG_S3C2410 - S3C24X0_REG32 GPACON; - S3C24X0_REG32 GPADAT; - S3C24X0_REG32 res1[2]; - S3C24X0_REG32 GPBCON; - S3C24X0_REG32 GPBDAT; - S3C24X0_REG32 GPBUP; - S3C24X0_REG32 res2; - S3C24X0_REG32 GPCCON; - S3C24X0_REG32 GPCDAT; - S3C24X0_REG32 GPCUP; - S3C24X0_REG32 res3; - S3C24X0_REG32 GPDCON; - S3C24X0_REG32 GPDDAT; - S3C24X0_REG32 GPDUP; - S3C24X0_REG32 res4; - S3C24X0_REG32 GPECON; - S3C24X0_REG32 GPEDAT; - S3C24X0_REG32 GPEUP; - S3C24X0_REG32 res5; - S3C24X0_REG32 GPFCON; - S3C24X0_REG32 GPFDAT; - S3C24X0_REG32 GPFUP; - S3C24X0_REG32 res6; - S3C24X0_REG32 GPGCON; - S3C24X0_REG32 GPGDAT; - S3C24X0_REG32 GPGUP; - S3C24X0_REG32 res7; - S3C24X0_REG32 GPHCON; - S3C24X0_REG32 GPHDAT; - S3C24X0_REG32 GPHUP; - S3C24X0_REG32 res8; - - S3C24X0_REG32 MISCCR; - S3C24X0_REG32 DCLKCON; - S3C24X0_REG32 EXTINT0; - S3C24X0_REG32 EXTINT1; - S3C24X0_REG32 EXTINT2; - S3C24X0_REG32 EINTFLT0; - S3C24X0_REG32 EINTFLT1; - S3C24X0_REG32 EINTFLT2; - S3C24X0_REG32 EINTFLT3; - S3C24X0_REG32 EINTMASK; - S3C24X0_REG32 EINTPEND; - S3C24X0_REG32 GSTATUS0; - S3C24X0_REG32 GSTATUS1; - S3C24X0_REG32 GSTATUS2; - S3C24X0_REG32 GSTATUS3; - S3C24X0_REG32 GSTATUS4; -#endif -}; - - -/* RTC (see manual chapter 17) */ -struct s3c24x0_rtc { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[67]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res3[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res17[3]; - S3C24X0_REG8 BCDYEAR; -#else /* little endian */ - S3C24X0_REG8 res0[64]; - S3C24X0_REG8 RTCCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 TICNT; - S3C24X0_REG8 res2[11]; - S3C24X0_REG8 RTCALM; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 ALMSEC; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 ALMMIN; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 ALMHOUR; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 ALMDATE; - S3C24X0_REG8 res7[3]; - S3C24X0_REG8 ALMMON; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 ALMYEAR; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 RTCRST; - S3C24X0_REG8 res10[3]; - S3C24X0_REG8 BCDSEC; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 BCDMIN; - S3C24X0_REG8 res12[3]; - S3C24X0_REG8 BCDHOUR; - S3C24X0_REG8 res13[3]; - S3C24X0_REG8 BCDDATE; - S3C24X0_REG8 res14[3]; - S3C24X0_REG8 BCDDAY; - S3C24X0_REG8 res15[3]; - S3C24X0_REG8 BCDMON; - S3C24X0_REG8 res16[3]; - S3C24X0_REG8 BCDYEAR; - S3C24X0_REG8 res17[3]; -#endif -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2400_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCDAT; -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2410_adc { - S3C24X0_REG32 ADCCON; - S3C24X0_REG32 ADCTSC; - S3C24X0_REG32 ADCDLY; - S3C24X0_REG32 ADCDAT0; - S3C24X0_REG32 ADCDAT1; -}; - - -/* SPI (see manual chapter 22) */ -struct s3c24x0_spi_channel { - S3C24X0_REG8 SPCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 SPSTA; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 SPPIN; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 SPPRE; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 SPTDAT; - S3C24X0_REG8 res5[3]; - S3C24X0_REG8 SPRDAT; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 res7[16]; -}; - -struct s3c24x0_spi { - struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; -}; - - -/* MMC INTERFACE (see S3C2400 manual chapter 19) */ -struct s3c2400_mmc { -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res4[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG16 res5; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG8 res6[3]; - S3C24X0_REG8 MMPRE; - S3C24X0_REG16 res7; - S3C24X0_REG16 MMLEN; - S3C24X0_REG8 res8[3]; - S3C24X0_REG8 MMCR7; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 res9[3]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 res10; - S3C24X0_REG16 MMCR16; - S3C24X0_REG8 res11[3]; - S3C24X0_REG8 MMDAT; -#else - S3C24X0_REG8 MMCON; - S3C24X0_REG8 res1[3]; - S3C24X0_REG8 MMCRR; - S3C24X0_REG8 res2[3]; - S3C24X0_REG8 MMFCON; - S3C24X0_REG8 res3[3]; - S3C24X0_REG8 MMSTA; - S3C24X0_REG8 res4[3]; - S3C24X0_REG16 MMFSTA; - S3C24X0_REG16 res5; - S3C24X0_REG8 MMPRE; - S3C24X0_REG8 res6[3]; - S3C24X0_REG16 MMLEN; - S3C24X0_REG16 res7; - S3C24X0_REG8 MMCR7; - S3C24X0_REG8 res8[3]; - S3C24X0_REG32 MMRSP[4]; - S3C24X0_REG8 MMCMD0; - S3C24X0_REG8 res9[3]; - S3C24X0_REG32 MMCMD1; - S3C24X0_REG16 MMCR16; - S3C24X0_REG16 res10; - S3C24X0_REG8 MMDAT; - S3C24X0_REG8 res11[3]; -#endif -}; - - -/* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c2410_sdi { - S3C24X0_REG32 SDICON; - S3C24X0_REG32 SDIPRE; - S3C24X0_REG32 SDICARG; - S3C24X0_REG32 SDICCON; - S3C24X0_REG32 SDICSTA; - S3C24X0_REG32 SDIRSP0; - S3C24X0_REG32 SDIRSP1; - S3C24X0_REG32 SDIRSP2; - S3C24X0_REG32 SDIRSP3; - S3C24X0_REG32 SDIDTIMER; - S3C24X0_REG32 SDIBSIZE; - S3C24X0_REG32 SDIDCON; - S3C24X0_REG32 SDIDCNT; - S3C24X0_REG32 SDIDSTA; - S3C24X0_REG32 SDIFSTA; -#ifdef __BIG_ENDIAN - S3C24X0_REG8 res[3]; - S3C24X0_REG8 SDIDAT; -#else - S3C24X0_REG8 SDIDAT; - S3C24X0_REG8 res[3]; -#endif - S3C24X0_REG32 SDIIMSK; -}; - -#endif /*__S3C24X0_H__*/ -- cgit v1.2.3 From 47e801bec360e69e4b087a141d015b318e1b0212 Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Wed, 4 Nov 2009 16:07:59 +0900 Subject: s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xx This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang --- board/samsung/smdk6400/lowlevel_init.S | 2 +- board/samsung/smdk6400/smdk6400.c | 2 +- cpu/arm1176/cpu.c | 2 +- cpu/arm1176/s3c64xx/cpu_init.S | 2 +- cpu/arm1176/s3c64xx/reset.S | 2 +- cpu/arm1176/s3c64xx/speed.c | 2 +- cpu/arm1176/s3c64xx/timer.c | 2 +- cpu/arm1176/start.S | 2 +- drivers/mtd/nand/s3c64xx.c | 2 +- drivers/serial/s3c64xx.c | 2 +- drivers/usb/host/s3c64xx-hcd.c | 2 +- include/asm-arm/arch-s3c64xx/s3c6400.h | 895 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-s3c64xx/s3c64x0.h | 90 ++++ include/s3c6400.h | 895 --------------------------------- include/s3c64x0.h | 90 ---- 15 files changed, 996 insertions(+), 996 deletions(-) create mode 100644 include/asm-arm/arch-s3c64xx/s3c6400.h create mode 100644 include/asm-arm/arch-s3c64xx/s3c64x0.h delete mode 100644 include/s3c6400.h delete mode 100644 include/s3c64x0.h (limited to 'drivers') diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S index 47f72f613..30d88780d 100644 --- a/board/samsung/smdk6400/lowlevel_init.S +++ b/board/samsung/smdk6400/lowlevel_init.S @@ -34,7 +34,7 @@ #include #include -#include +#include #ifdef CONFIG_SERIAL1 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index 561c0c831..78aaa9e13 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -30,7 +30,7 @@ #include #include -#include +#include /* ------------------------------------------------------------------------- */ #define CS8900_Tacs 0x0 /* 0clk address set-up */ diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c index d1a332748..2c0014f2b 100644 --- a/cpu/arm1176/cpu.c +++ b/cpu/arm1176/cpu.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include static void cache_flush (void); diff --git a/cpu/arm1176/s3c64xx/cpu_init.S b/cpu/arm1176/s3c64xx/cpu_init.S index 32bb467f2..df88cba34 100644 --- a/cpu/arm1176/s3c64xx/cpu_init.S +++ b/cpu/arm1176/s3c64xx/cpu_init.S @@ -24,7 +24,7 @@ */ #include -#include +#include .globl mem_ctrl_asm_init mem_ctrl_asm_init: diff --git a/cpu/arm1176/s3c64xx/reset.S b/cpu/arm1176/s3c64xx/reset.S index 315b13f8d..eae572e4f 100644 --- a/cpu/arm1176/s3c64xx/reset.S +++ b/cpu/arm1176/s3c64xx/reset.S @@ -21,7 +21,7 @@ * MA 02111-1307 USA */ -#include +#include .globl reset_cpu reset_cpu: diff --git a/cpu/arm1176/s3c64xx/speed.c b/cpu/arm1176/s3c64xx/speed.c index 5c335a55a..11962acad 100644 --- a/cpu/arm1176/s3c64xx/speed.c +++ b/cpu/arm1176/s3c64xx/speed.c @@ -31,7 +31,7 @@ */ #include -#include +#include #define APLL 0 #define MPLL 1 diff --git a/cpu/arm1176/s3c64xx/timer.c b/cpu/arm1176/s3c64xx/timer.c index 22a5b7770..85ce9cd99 100644 --- a/cpu/arm1176/s3c64xx/timer.c +++ b/cpu/arm1176/s3c64xx/timer.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include static ulong timer_load_val; diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index cb891df17..2bb9bf208 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -35,7 +35,7 @@ #ifdef CONFIG_ENABLE_MMU #include #endif -#include +#include #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c index edaf55a14..084e47564 100644 --- a/drivers/mtd/nand/s3c64xx.c +++ b/drivers/mtd/nand/s3c64xx.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/serial/s3c64xx.c b/drivers/serial/s3c64xx.c index 1b974e04f..6d22df7cf 100644 --- a/drivers/serial/s3c64xx.c +++ b/drivers/serial/s3c64xx.c @@ -23,7 +23,7 @@ #include -#include +#include #ifdef CONFIG_SERIAL1 #define UART_NR S3C64XX_UART0 diff --git a/drivers/usb/host/s3c64xx-hcd.c b/drivers/usb/host/s3c64xx-hcd.c index 274a4ed30..cd295dabb 100644 --- a/drivers/usb/host/s3c64xx-hcd.c +++ b/drivers/usb/host/s3c64xx-hcd.c @@ -25,7 +25,7 @@ */ #include -#include +#include int usb_cpu_init(void) { diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h new file mode 100644 index 000000000..e527c08b1 --- /dev/null +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h @@ -0,0 +1,895 @@ +/* + * (C) Copyright 2007 + * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. + * - only support for S3C6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c6400.h + * + * Based on S3C6400 User's manual Rev 0.0 + ************************************************/ + +#ifndef __S3C6400_H__ +#define __S3C6400_H__ + +#define S3C64XX_UART_CHANNELS 3 +#define S3C64XX_SPI_CHANNELS 2 + +#include + +#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 + +/* Clock & Power Controller for mDirac3*/ +#define APLL_LOCK_OFFSET 0x00 +#define MPLL_LOCK_OFFSET 0x04 +#define EPLL_LOCK_OFFSET 0x08 +#define APLL_CON_OFFSET 0x0C +#define MPLL_CON_OFFSET 0x10 +#define EPLL_CON0_OFFSET 0x14 +#define EPLL_CON1_OFFSET 0x18 +#define CLK_SRC_OFFSET 0x1C +#define CLK_DIV0_OFFSET 0x20 +#define CLK_DIV1_OFFSET 0x24 +#define CLK_DIV2_OFFSET 0x28 +#define CLK_OUT_OFFSET 0x2C +#define HCLK_GATE_OFFSET 0x30 +#define PCLK_GATE_OFFSET 0x34 +#define SCLK_GATE_OFFSET 0x38 +#define AHB_CON0_OFFSET 0x100 +#define AHB_CON1_OFFSET 0x104 +#define AHB_CON2_OFFSET 0x108 +#define SELECT_DMA_OFFSET 0x110 +#define SW_RST_OFFSET 0x114 +#define SYS_ID_OFFSET 0x118 +#define MEM_SYS_CFG_OFFSET 0x120 +#define QOS_OVERRIDE0_OFFSET 0x124 +#define QOS_OVERRIDE1_OFFSET 0x128 +#define MEM_CFG_STAT_OFFSET 0x12C +#define PWR_CFG_OFFSET 0x804 +#define EINT_MASK_OFFSET 0x808 +#define NOR_CFG_OFFSET 0x810 +#define STOP_CFG_OFFSET 0x814 +#define SLEEP_CFG_OFFSET 0x818 +#define OSC_FREQ_OFFSET 0x820 +#define OSC_STABLE_OFFSET 0x824 +#define PWR_STABLE_OFFSET 0x828 +#define FPC_STABLE_OFFSET 0x82C +#define MTC_STABLE_OFFSET 0x830 +#define OTHERS_OFFSET 0x900 +#define RST_STAT_OFFSET 0x904 +#define WAKEUP_STAT_OFFSET 0x908 +#define BLK_PWR_STAT_OFFSET 0x90C +#define INF_REG0_OFFSET 0xA00 +#define INF_REG1_OFFSET 0xA04 +#define INF_REG2_OFFSET 0xA08 +#define INF_REG3_OFFSET 0xA0C +#define INF_REG4_OFFSET 0xA10 +#define INF_REG5_OFFSET 0xA14 +#define INF_REG6_OFFSET 0xA18 +#define INF_REG7_OFFSET 0xA1C + +#define OSC_CNT_VAL_OFFSET 0x824 +#define PWR_CNT_VAL_OFFSET 0x828 +#define FPC_CNT_VAL_OFFSET 0x82C +#define MTC_CNT_VAL_OFFSET 0x830 + +#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) +#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) +#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) +#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) +#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) +#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) +#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) +#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) +#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) +#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) +#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) +#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) +#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) +#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) +#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) +#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) +#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) +#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) +#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + SELECT_DMA_OFFSET) +#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) +#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) +#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MEM_SYS_CFG_OFFSET) +#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + QOS_OVERRIDE0_OFFSET) +#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + QOS_OVERRIDE1_OFFSET) +#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MEM_CFG_STAT_OFFSET) +#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) +#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) +#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) +#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) +#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) +#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) +#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + OSC_CNT_VAL_OFFSET) +#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + PWR_CNT_VAL_OFFSET) +#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + FPC_CNT_VAL_OFFSET) +#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + MTC_CNT_VAL_OFFSET) +#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) +#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) +#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + WAKEUP_STAT_OFFSET) +#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ + BLK_PWR_STAT_OFFSET) +#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) +#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) +#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) +#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) +#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) +#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) +#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) +#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) + +#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) +#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) +#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) +#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) +#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) +#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) +#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) +#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) +#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) +#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) +#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) +#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) +#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) +#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) +#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) +#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) +#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) +#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) +#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) +#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) +#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) +#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) +#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) +#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) +#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) +#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) +#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) +#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) +#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) +#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) +#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) +#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) +#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) +#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) +#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) +#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) +#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) +#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) +#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) +#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) +#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) +#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) +#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) +#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) +#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) +#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) +#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) + + +/* + * GPIO + */ +#define ELFIN_GPIO_BASE 0x7f008000 + +#define GPACON_OFFSET 0x00 +#define GPADAT_OFFSET 0x04 +#define GPAPUD_OFFSET 0x08 +#define GPACONSLP_OFFSET 0x0C +#define GPAPUDSLP_OFFSET 0x10 +#define GPBCON_OFFSET 0x20 +#define GPBDAT_OFFSET 0x24 +#define GPBPUD_OFFSET 0x28 +#define GPBCONSLP_OFFSET 0x2C +#define GPBPUDSLP_OFFSET 0x30 +#define GPCCON_OFFSET 0x40 +#define GPCDAT_OFFSET 0x44 +#define GPCPUD_OFFSET 0x48 +#define GPCCONSLP_OFFSET 0x4C +#define GPCPUDSLP_OFFSET 0x50 +#define GPDCON_OFFSET 0x60 +#define GPDDAT_OFFSET 0x64 +#define GPDPUD_OFFSET 0x68 +#define GPDCONSLP_OFFSET 0x6C +#define GPDPUDSLP_OFFSET 0x70 +#define GPECON_OFFSET 0x80 +#define GPEDAT_OFFSET 0x84 +#define GPEPUD_OFFSET 0x88 +#define GPECONSLP_OFFSET 0x8C +#define GPEPUDSLP_OFFSET 0x90 +#define GPFCON_OFFSET 0xA0 +#define GPFDAT_OFFSET 0xA4 +#define GPFPUD_OFFSET 0xA8 +#define GPFCONSLP_OFFSET 0xAC +#define GPFPUDSLP_OFFSET 0xB0 +#define GPGCON_OFFSET 0xC0 +#define GPGDAT_OFFSET 0xC4 +#define GPGPUD_OFFSET 0xC8 +#define GPGCONSLP_OFFSET 0xCC +#define GPGPUDSLP_OFFSET 0xD0 +#define GPHCON0_OFFSET 0xE0 +#define GPHCON1_OFFSET 0xE4 +#define GPHDAT_OFFSET 0xE8 +#define GPHPUD_OFFSET 0xEC +#define GPHCONSLP_OFFSET 0xF0 +#define GPHPUDSLP_OFFSET 0xF4 +#define GPICON_OFFSET 0x100 +#define GPIDAT_OFFSET 0x104 +#define GPIPUD_OFFSET 0x108 +#define GPICONSLP_OFFSET 0x10C +#define GPIPUDSLP_OFFSET 0x110 +#define GPJCON_OFFSET 0x120 +#define GPJDAT_OFFSET 0x124 +#define GPJPUD_OFFSET 0x128 +#define GPJCONSLP_OFFSET 0x12C +#define GPJPUDSLP_OFFSET 0x130 +#define MEM0DRVCON_OFFSET 0x1D0 +#define MEM1DRVCON_OFFSET 0x1D4 +#define GPKCON0_OFFSET 0x800 +#define GPKCON1_OFFSET 0x804 +#define GPKDAT_OFFSET 0x808 +#define GPKPUD_OFFSET 0x80C +#define GPLCON0_OFFSET 0x810 +#define GPLCON1_OFFSET 0x814 +#define GPLDAT_OFFSET 0x818 +#define GPLPUD_OFFSET 0x81C +#define GPMCON_OFFSET 0x820 +#define GPMDAT_OFFSET 0x824 +#define GPMPUD_OFFSET 0x828 +#define GPNCON_OFFSET 0x830 +#define GPNDAT_OFFSET 0x834 +#define GPNPUD_OFFSET 0x838 +#define GPOCON_OFFSET 0x140 +#define GPODAT_OFFSET 0x144 +#define GPOPUD_OFFSET 0x148 +#define GPOCONSLP_OFFSET 0x14C +#define GPOPUDSLP_OFFSET 0x150 +#define GPPCON_OFFSET 0x160 +#define GPPDAT_OFFSET 0x164 +#define GPPPUD_OFFSET 0x168 +#define GPPCONSLP_OFFSET 0x16C +#define GPPPUDSLP_OFFSET 0x170 +#define GPQCON_OFFSET 0x180 +#define GPQDAT_OFFSET 0x184 +#define GPQPUD_OFFSET 0x188 +#define GPQCONSLP_OFFSET 0x18C +#define GPQPUDSLP_OFFSET 0x190 + +#define EINTPEND_OFFSET 0x924 + +#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) +#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) +#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) +#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) +#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) +#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) +#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) +#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) +#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) +#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) +#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) +#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) +#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) +#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) +#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) +#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) +#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) +#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) +#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) +#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) +#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) +#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) +#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) +#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) +#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) +#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) +#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) +#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) +#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) +#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) +#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) +#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) +#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) +#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) +#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) +#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) +#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) +#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) +#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) +#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) +#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) +#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) +#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) +#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) +#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) +#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) +#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) +#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) +#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) +#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) +#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) +#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) +#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) +#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) +#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) +#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) +#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) +#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) +#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) +#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) +#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) +#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) +#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) +#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) +#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) +#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) +#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) +#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) +#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) +#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) +#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) +#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) +#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) +#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) +#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) +#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) +#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) +#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) +#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) +#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) + +/* + * Bus Matrix + */ +#define ELFIN_MEM_SYS_CFG 0x7e00f120 + +#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) + +#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 +#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT + +#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) +#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) +#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) +#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) +#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) +#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) +#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) +#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) +#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) +#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) +#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) +#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) +#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) +#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) +#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) +#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) +#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) +#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) +#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) +#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) +#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) +#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) +#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) +#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) +#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) +#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) +#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) +#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) +#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) +#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) +#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) +#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) +#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) +#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) +#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) +#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) +#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) +#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) +#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) +#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) +#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) +#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) +#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) +#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) +#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) +#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) +#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) +#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) +#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) +#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) +#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) +#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) +#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) +#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) +#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) +#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) +#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) +#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) +#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) +#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) +#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) +#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) +#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) +#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) +#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) +#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) +#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) +#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) +#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) +#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) +#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) +#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) +#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) +#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) +#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) +#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) +#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) +#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) +#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) +#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) + +/* + * Memory controller + */ +#define ELFIN_SROM_BASE 0x70000000 + +#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) +#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) +#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) +#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) +#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) +#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) +#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) + +/* + * SDRAM Controller + */ +#define ELFIN_DMC0_BASE 0x7e000000 +#define ELFIN_DMC1_BASE 0x7e001000 + +#define INDEX_DMC_MEMC_STATUS 0x00 +#define INDEX_DMC_MEMC_CMD 0x04 +#define INDEX_DMC_DIRECT_CMD 0x08 +#define INDEX_DMC_MEMORY_CFG 0x0C +#define INDEX_DMC_REFRESH_PRD 0x10 +#define INDEX_DMC_CAS_LATENCY 0x14 +#define INDEX_DMC_T_DQSS 0x18 +#define INDEX_DMC_T_MRD 0x1C +#define INDEX_DMC_T_RAS 0x20 +#define INDEX_DMC_T_RC 0x24 +#define INDEX_DMC_T_RCD 0x28 +#define INDEX_DMC_T_RFC 0x2C +#define INDEX_DMC_T_RP 0x30 +#define INDEX_DMC_T_RRD 0x34 +#define INDEX_DMC_T_WR 0x38 +#define INDEX_DMC_T_WTR 0x3C +#define INDEX_DMC_T_XP 0x40 +#define INDEX_DMC_T_XSR 0x44 +#define INDEX_DMC_T_ESR 0x48 +#define INDEX_DMC_MEMORY_CFG2 0x4C +#define INDEX_DMC_CHIP_0_CFG 0x200 +#define INDEX_DMC_CHIP_1_CFG 0x204 +#define INDEX_DMC_CHIP_2_CFG 0x208 +#define INDEX_DMC_CHIP_3_CFG 0x20C +#define INDEX_DMC_USER_STATUS 0x300 +#define INDEX_DMC_USER_CONFIG 0x304 + +/* + * Memory Chip direct command + */ +#define DMC_NOP0 0x0c0000 +#define DMC_NOP1 0x1c0000 +#define DMC_PA0 0x000000 /* Precharge all */ +#define DMC_PA1 0x100000 +#define DMC_AR0 0x040000 /* Autorefresh */ +#define DMC_AR1 0x140000 +#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ +#define DMC_SDR_MR1 0x180032 +#define DMC_DDR_MR0 0x080162 +#define DMC_DDR_MR1 0x180162 +#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ +#define DMC_mDDR_MR1 0x180032 +#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ +#define DMC_mSDR_EMR1 0x1a0000 +#define DMC_DDR_EMR0 0x090000 +#define DMC_DDR_EMR1 0x190000 +#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ +#define DMC_mDDR_EMR1 0x1a0000 + +/* + * Definitions for memory configuration + * Set memory configuration + * active_chips = 1'b0 (1 chip) + * qos_master_chip = 3'b000(ARID[3:0]) + * memory burst = 3'b010(burst 4) + * stop_mem_clock = 1'b0(disable dynamical stop) + * auto_power_down = 1'b0(disable auto power-down mode) + * power_down_prd = 6'b00_0000(0 cycle for auto power-down) + * ap_bit = 1'b0 (bit position of auto-precharge is 10) + * row_bits = 3'b010(# row address 13) + * column_bits = 3'b010(# column address 10 ) + * + * Set user configuration + * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR + * + * Set chip select for chip [n] + * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff + * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] + */ + +/* + * Nand flash controller + */ +#define ELFIN_NAND_BASE 0x70200000 + +#define NFCONF_OFFSET 0x00 +#define NFCONT_OFFSET 0x04 +#define NFCMMD_OFFSET 0x08 +#define NFADDR_OFFSET 0x0c +#define NFDATA_OFFSET 0x10 +#define NFMECCDATA0_OFFSET 0x14 +#define NFMECCDATA1_OFFSET 0x18 +#define NFSECCDATA0_OFFSET 0x1c +#define NFSBLK_OFFSET 0x20 +#define NFEBLK_OFFSET 0x24 +#define NFSTAT_OFFSET 0x28 +#define NFESTAT0_OFFSET 0x2c +#define NFESTAT1_OFFSET 0x30 +#define NFMECC0_OFFSET 0x34 +#define NFMECC1_OFFSET 0x38 +#define NFSECC_OFFSET 0x3c +#define NFMLCBITPT_OFFSET 0x40 + +#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) +#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) +#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) +#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) +#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) +#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) +#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) +#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) +#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) +#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) +#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) +#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) +#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) +#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) +#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) +#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) + +#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) +#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) +#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) +#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) +#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) +#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) +#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) +#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) +#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) +#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) +#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) +#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) +#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) +#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) +#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) +#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) +#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) + +#define NFCONF_ECC_4BIT (1<<24) + +#define NFCONT_ECC_ENC (1<<18) +#define NFCONT_WP (1<<16) +#define NFCONT_MECCLOCK (1<<7) +#define NFCONT_SECCLOCK (1<<6) +#define NFCONT_INITMECC (1<<5) +#define NFCONT_INITSECC (1<<4) +#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) +#define NFCONT_CS_ALT (1<<2) +#define NFCONT_CS (1<<1) +#define NFCONT_ENABLE (1<<0) + +#define NFSTAT_ECCENCDONE (1<<7) +#define NFSTAT_ECCDECDONE (1<<6) +#define NFSTAT_RnB (1<<0) + +#define NFESTAT0_ECCBUSY (1<<31) + +/* + * Interrupt + */ +#define ELFIN_VIC0_BASE_ADDR 0x71200000 +#define ELFIN_VIC1_BASE_ADDR 0x71300000 +#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ +#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ +#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ +#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ +#define oVECTADDR 0xF00 /* VIC ADDRESS */ + +/* + * Watchdog timer + */ +#define ELFIN_WATCHDOG_BASE 0x7E004000 + +#define WTCON_REG __REG(0x7E004004) +#define WTDAT_REG __REG(0x7E004008) +#define WTCNT_REG __REG(0x7E00400C) + + +/* + * UART + */ +#define ELFIN_UART_BASE 0x7F005000 + +#define ELFIN_UART0_OFFSET 0x0000 +#define ELFIN_UART1_OFFSET 0x0400 +#define ELFIN_UART2_OFFSET 0x0800 + +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 + +#define ULCON0_REG __REG(0x7F005000) +#define UCON0_REG __REG(0x7F005004) +#define UFCON0_REG __REG(0x7F005008) +#define UMCON0_REG __REG(0x7F00500C) +#define UTRSTAT0_REG __REG(0x7F005010) +#define UERSTAT0_REG __REG(0x7F005014) +#define UFSTAT0_REG __REG(0x7F005018) +#define UMSTAT0_REG __REG(0x7F00501c) +#define UTXH0_REG __REG(0x7F005020) +#define URXH0_REG __REG(0x7F005024) +#define UBRDIV0_REG __REG(0x7F005028) +#define UDIVSLOT0_REG __REG(0x7F00502c) +#define UINTP0_REG __REG(0x7F005030) +#define UINTSP0_REG __REG(0x7F005034) +#define UINTM0_REG __REG(0x7F005038) + +#define ULCON1_REG __REG(0x7F005400) +#define UCON1_REG __REG(0x7F005404) +#define UFCON1_REG __REG(0x7F005408) +#define UMCON1_REG __REG(0x7F00540C) +#define UTRSTAT1_REG __REG(0x7F005410) +#define UERSTAT1_REG __REG(0x7F005414) +#define UFSTAT1_REG __REG(0x7F005418) +#define UMSTAT1_REG __REG(0x7F00541c) +#define UTXH1_REG __REG(0x7F005420) +#define URXH1_REG __REG(0x7F005424) +#define UBRDIV1_REG __REG(0x7F005428) +#define UDIVSLOT1_REG __REG(0x7F00542c) +#define UINTP1_REG __REG(0x7F005430) +#define UINTSP1_REG __REG(0x7F005434) +#define UINTM1_REG __REG(0x7F005438) + +#define UTRSTAT_TX_EMPTY (1 << 2) +#define UTRSTAT_RX_READY (1 << 0) +#define UART_ERR_MASK 0xF + +/* + * PWM timer + */ +#define ELFIN_TIMER_BASE 0x7F006000 + +#define TCFG0_REG __REG(0x7F006000) +#define TCFG1_REG __REG(0x7F006004) +#define TCON_REG __REG(0x7F006008) +#define TCNTB0_REG __REG(0x7F00600c) +#define TCMPB0_REG __REG(0x7F006010) +#define TCNTO0_REG __REG(0x7F006014) +#define TCNTB1_REG __REG(0x7F006018) +#define TCMPB1_REG __REG(0x7F00601c) +#define TCNTO1_REG __REG(0x7F006020) +#define TCNTB2_REG __REG(0x7F006024) +#define TCMPB2_REG __REG(0x7F006028) +#define TCNTO2_REG __REG(0x7F00602c) +#define TCNTB3_REG __REG(0x7F006030) +#define TCMPB3_REG __REG(0x7F006034) +#define TCNTO3_REG __REG(0x7F006038) +#define TCNTB4_REG __REG(0x7F00603c) +#define TCNTO4_REG __REG(0x7F006040) + +/* Fields */ +#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ +#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ +#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ +#define fTCFG1_MUX4 Fld(4, 16) +/* bits */ +#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) +#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) +#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) +#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ +#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ +#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ +#define COUNT_4_ON (TCON_4_ONOFF * 1) +#define COUNT_4_OFF (TCON_4_ONOFF * 0) +#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ +#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) +#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) +#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ +#define TIMER3_IVT_ON (TCON_3_INVERT * 1) +#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) +#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ +#define TIMER3_MANUP (TCON_3_MAN*1) +#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) +#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ +#define TIMER3_ON (TCON_3_ONOFF * 1) +#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) + +#if defined(CONFIG_CLK_400_100_50) +#define STARTUP_AMDIV 400 +#define STARTUP_MDIV 400 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_400_133_66) +#define STARTUP_AMDIV 400 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_533_133_66) +#define STARTUP_AMDIV 533 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#elif defined(CONFIG_CLK_667_133_66) +#define STARTUP_AMDIV 667 +#define STARTUP_MDIV 533 +#define STARTUP_PDIV 6 +#define STARTUP_SDIV 1 +#endif + +#define STARTUP_PCLKDIV 3 +#define STARTUP_HCLKX2DIV 1 +#define STARTUP_HCLKDIV 1 +#define STARTUP_MPLLDIV 1 +#define STARTUP_APLLDIV 0 + +#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ + (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) +#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_MDIV) + +#if defined(CONFIG_SYNC_MODE) +#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_MDIV) +#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ + (STARTUP_HCLKDIV + 1)) +#else +#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ + (STARTUP_PDIV << 8) | STARTUP_SDIV) +#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ + STARTUP_PDIV) * STARTUP_AMDIV) +#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ + (STARTUP_HCLKDIV + 1)) +#endif + + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG2 0xB45 +#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ +#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ + +/* Memory Parameters */ +/* DDR Parameters */ +#define DDR_tREFRESH 7800 /* ns */ +#define DDR_tRAS 45 /* ns (min: 45ns)*/ +#define DDR_tRC 68 /* ns (min: 67.5ns)*/ +#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ +#define DDR_tRFC 80 /* ns (min: 80ns)*/ +#define DDR_tRP 23 /* ns (min: 22.5ns)*/ +#define DDR_tRRD 15 /* ns (min: 15ns)*/ +#define DDR_tWR 15 /* ns (min: 15ns)*/ +#define DDR_tXSR 120 /* ns (min: 120ns)*/ +#define DDR_CASL 3 /* CAS Latency 3 */ + +/* + * mDDR memory configuration + */ + +#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) + +#define DMC_DDR_BA_EMRS 2 +#define DMC_DDR_MEM_CASLAT 3 +/* 6 Set Cas Latency to 3 */ +#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) +/* Min 0.75 ~ 1.25 */ +#define DMC_DDR_t_DQSS 1 +/* Min 2 tck */ +#define DMC_DDR_t_MRD 2 +/* 7, Min 45ns */ +#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) +/* 10, Min 67.5ns */ +#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) +/* 4,5(TRM), Min 22.5ns */ +#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) +#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) +/* 11,18(TRM) Min 80ns */ +#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) +#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) +/* 4, 5(TRM) Min 22.5ns */ +#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) +#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) +/* 3, Min 15ns */ +#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) +/* Min 15ns */ +#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) +#define DMC_DDR_t_WTR 2 +/* 1tck + tIS(1.5ns) */ +#define DMC_DDR_t_XP 2 +/* 17, Min 120ns */ +#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) +#define DMC_DDR_t_ESR DMC_DDR_t_XSR +/* TRM 2656 */ +#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) +/* 2b01 : mDDR */ +#define DMC_DDR_USER_CONFIG 1 + +#ifndef __ASSEMBLY__ +enum s3c64xx_uarts_nr { + S3C64XX_UART0, + S3C64XX_UART1, + S3C64XX_UART2, +}; + +#include "s3c64x0.h" + +static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) +{ + return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); +} +#endif + +#endif /*__S3C6400_H__*/ diff --git a/include/asm-arm/arch-s3c64xx/s3c64x0.h b/include/asm-arm/arch-s3c64xx/s3c64x0.h new file mode 100644 index 000000000..0bbf1d0c4 --- /dev/null +++ b/include/asm-arm/arch-s3c64xx/s3c64x0.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2003 + * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : S3C64XX.h + * Version : 31.3.2003 + * + * common stuff for SAMSUNG S3C64XX SoC + ************************************************/ + +#ifndef __S3C64XX_H__ +#define __S3C64XX_H__ + +#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) +#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! +#endif + +#include + +/* UART (see manual chapter 11) */ +typedef struct { + volatile u32 ULCON; + volatile u32 UCON; + volatile u32 UFCON; + volatile u32 UMCON; + volatile u32 UTRSTAT; + volatile u32 UERSTAT; + volatile u32 UFSTAT; + volatile u32 UMSTAT; +#ifdef __BIG_ENDIAN + volatile u8 res1[3]; + volatile u8 UTXH; + volatile u8 res2[3]; + volatile u8 URXH; +#else /* Little Endian */ + volatile u8 UTXH; + volatile u8 res1[3]; + volatile u8 URXH; + volatile u8 res2[3]; +#endif + volatile u32 UBRDIV; +#ifdef __BIG_ENDIAN + volatile u8 res3[2]; + volatile u16 UDIVSLOT; +#else + volatile u16 UDIVSLOT; + volatile u8 res3[2]; +#endif +} s3c64xx_uart; + +/* PWM TIMER (see manual chapter 10) */ +typedef struct { + volatile u32 TCNTB; + volatile u32 TCMPB; + volatile u32 TCNTO; +} s3c64xx_timer; + +typedef struct { + volatile u32 TCFG0; + volatile u32 TCFG1; + volatile u32 TCON; + s3c64xx_timer ch[4]; + volatile u32 TCNTB4; + volatile u32 TCNTO4; +} s3c64xx_timers; + +#endif /*__S3C64XX_H__*/ diff --git a/include/s3c6400.h b/include/s3c6400.h deleted file mode 100644 index e527c08b1..000000000 --- a/include/s3c6400.h +++ /dev/null @@ -1,895 +0,0 @@ -/* - * (C) Copyright 2007 - * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. - * - only support for S3C6400 - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c6400.h - * - * Based on S3C6400 User's manual Rev 0.0 - ************************************************/ - -#ifndef __S3C6400_H__ -#define __S3C6400_H__ - -#define S3C64XX_UART_CHANNELS 3 -#define S3C64XX_SPI_CHANNELS 2 - -#include - -#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* Clock & Power Controller for mDirac3*/ -#define APLL_LOCK_OFFSET 0x00 -#define MPLL_LOCK_OFFSET 0x04 -#define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 -#define EPLL_CON1_OFFSET 0x18 -#define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 -#define CLK_DIV2_OFFSET 0x28 -#define CLK_OUT_OFFSET 0x2C -#define HCLK_GATE_OFFSET 0x30 -#define PCLK_GATE_OFFSET 0x34 -#define SCLK_GATE_OFFSET 0x38 -#define AHB_CON0_OFFSET 0x100 -#define AHB_CON1_OFFSET 0x104 -#define AHB_CON2_OFFSET 0x108 -#define SELECT_DMA_OFFSET 0x110 -#define SW_RST_OFFSET 0x114 -#define SYS_ID_OFFSET 0x118 -#define MEM_SYS_CFG_OFFSET 0x120 -#define QOS_OVERRIDE0_OFFSET 0x124 -#define QOS_OVERRIDE1_OFFSET 0x128 -#define MEM_CFG_STAT_OFFSET 0x12C -#define PWR_CFG_OFFSET 0x804 -#define EINT_MASK_OFFSET 0x808 -#define NOR_CFG_OFFSET 0x810 -#define STOP_CFG_OFFSET 0x814 -#define SLEEP_CFG_OFFSET 0x818 -#define OSC_FREQ_OFFSET 0x820 -#define OSC_STABLE_OFFSET 0x824 -#define PWR_STABLE_OFFSET 0x828 -#define FPC_STABLE_OFFSET 0x82C -#define MTC_STABLE_OFFSET 0x830 -#define OTHERS_OFFSET 0x900 -#define RST_STAT_OFFSET 0x904 -#define WAKEUP_STAT_OFFSET 0x908 -#define BLK_PWR_STAT_OFFSET 0x90C -#define INF_REG0_OFFSET 0xA00 -#define INF_REG1_OFFSET 0xA04 -#define INF_REG2_OFFSET 0xA08 -#define INF_REG3_OFFSET 0xA0C -#define INF_REG4_OFFSET 0xA10 -#define INF_REG5_OFFSET 0xA14 -#define INF_REG6_OFFSET 0xA18 -#define INF_REG7_OFFSET 0xA1C - -#define OSC_CNT_VAL_OFFSET 0x824 -#define PWR_CNT_VAL_OFFSET 0x828 -#define FPC_CNT_VAL_OFFSET 0x82C -#define MTC_CNT_VAL_OFFSET 0x830 - -#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - SELECT_DMA_OFFSET) -#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_CFG_STAT_OFFSET) -#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MTC_CNT_VAL_OFFSET) -#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - BLK_PWR_STAT_OFFSET) -#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - -#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) -#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) -#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) -#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) -#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - - -/* - * GPIO - */ -#define ELFIN_GPIO_BASE 0x7f008000 - -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4 -#define GPFPUD_OFFSET 0xA8 -#define GPFCONSLP_OFFSET 0xAC -#define GPFPUDSLP_OFFSET 0xB0 -#define GPGCON_OFFSET 0xC0 -#define GPGDAT_OFFSET 0xC4 -#define GPGPUD_OFFSET 0xC8 -#define GPGCONSLP_OFFSET 0xCC -#define GPGPUDSLP_OFFSET 0xD0 -#define GPHCON0_OFFSET 0xE0 -#define GPHCON1_OFFSET 0xE4 -#define GPHDAT_OFFSET 0xE8 -#define GPHPUD_OFFSET 0xEC -#define GPHCONSLP_OFFSET 0xF0 -#define GPHPUDSLP_OFFSET 0xF4 -#define GPICON_OFFSET 0x100 -#define GPIDAT_OFFSET 0x104 -#define GPIPUD_OFFSET 0x108 -#define GPICONSLP_OFFSET 0x10C -#define GPIPUDSLP_OFFSET 0x110 -#define GPJCON_OFFSET 0x120 -#define GPJDAT_OFFSET 0x124 -#define GPJPUD_OFFSET 0x128 -#define GPJCONSLP_OFFSET 0x12C -#define GPJPUDSLP_OFFSET 0x130 -#define MEM0DRVCON_OFFSET 0x1D0 -#define MEM1DRVCON_OFFSET 0x1D4 -#define GPKCON0_OFFSET 0x800 -#define GPKCON1_OFFSET 0x804 -#define GPKDAT_OFFSET 0x808 -#define GPKPUD_OFFSET 0x80C -#define GPLCON0_OFFSET 0x810 -#define GPLCON1_OFFSET 0x814 -#define GPLDAT_OFFSET 0x818 -#define GPLPUD_OFFSET 0x81C -#define GPMCON_OFFSET 0x820 -#define GPMDAT_OFFSET 0x824 -#define GPMPUD_OFFSET 0x828 -#define GPNCON_OFFSET 0x830 -#define GPNDAT_OFFSET 0x834 -#define GPNPUD_OFFSET 0x838 -#define GPOCON_OFFSET 0x140 -#define GPODAT_OFFSET 0x144 -#define GPOPUD_OFFSET 0x148 -#define GPOCONSLP_OFFSET 0x14C -#define GPOPUDSLP_OFFSET 0x150 -#define GPPCON_OFFSET 0x160 -#define GPPDAT_OFFSET 0x164 -#define GPPPUD_OFFSET 0x168 -#define GPPCONSLP_OFFSET 0x16C -#define GPPPUDSLP_OFFSET 0x170 -#define GPQCON_OFFSET 0x180 -#define GPQDAT_OFFSET 0x184 -#define GPQPUD_OFFSET 0x188 -#define GPQCONSLP_OFFSET 0x18C -#define GPQPUDSLP_OFFSET 0x190 - -#define EINTPEND_OFFSET 0x924 - -#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Bus Matrix - */ -#define ELFIN_MEM_SYS_CFG 0x7e00f120 - -#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) - -#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 -#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT - -#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Memory controller - */ -#define ELFIN_SROM_BASE 0x70000000 - -#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) -#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) -#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) -#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) -#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) -#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) -#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) - -/* - * SDRAM Controller - */ -#define ELFIN_DMC0_BASE 0x7e000000 -#define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS 0x00 -#define INDEX_DMC_MEMC_CMD 0x04 -#define INDEX_DMC_DIRECT_CMD 0x08 -#define INDEX_DMC_MEMORY_CFG 0x0C -#define INDEX_DMC_REFRESH_PRD 0x10 -#define INDEX_DMC_CAS_LATENCY 0x14 -#define INDEX_DMC_T_DQSS 0x18 -#define INDEX_DMC_T_MRD 0x1C -#define INDEX_DMC_T_RAS 0x20 -#define INDEX_DMC_T_RC 0x24 -#define INDEX_DMC_T_RCD 0x28 -#define INDEX_DMC_T_RFC 0x2C -#define INDEX_DMC_T_RP 0x30 -#define INDEX_DMC_T_RRD 0x34 -#define INDEX_DMC_T_WR 0x38 -#define INDEX_DMC_T_WTR 0x3C -#define INDEX_DMC_T_XP 0x40 -#define INDEX_DMC_T_XSR 0x44 -#define INDEX_DMC_T_ESR 0x48 -#define INDEX_DMC_MEMORY_CFG2 0x4C -#define INDEX_DMC_CHIP_0_CFG 0x200 -#define INDEX_DMC_CHIP_1_CFG 0x204 -#define INDEX_DMC_CHIP_2_CFG 0x208 -#define INDEX_DMC_CHIP_3_CFG 0x20C -#define INDEX_DMC_USER_STATUS 0x300 -#define INDEX_DMC_USER_CONFIG 0x304 - -/* - * Memory Chip direct command - */ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 /* Precharge all */ -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 /* Autorefresh */ -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ -#define DMC_mDDR_EMR1 0x1a0000 - -/* - * Definitions for memory configuration - * Set memory configuration - * active_chips = 1'b0 (1 chip) - * qos_master_chip = 3'b000(ARID[3:0]) - * memory burst = 3'b010(burst 4) - * stop_mem_clock = 1'b0(disable dynamical stop) - * auto_power_down = 1'b0(disable auto power-down mode) - * power_down_prd = 6'b00_0000(0 cycle for auto power-down) - * ap_bit = 1'b0 (bit position of auto-precharge is 10) - * row_bits = 3'b010(# row address 13) - * column_bits = 3'b010(# column address 10 ) - * - * Set user configuration - * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - * - * Set chip select for chip [n] - * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] - */ - -/* - * Nand flash controller - */ -#define ELFIN_NAND_BASE 0x70200000 - -#define NFCONF_OFFSET 0x00 -#define NFCONT_OFFSET 0x04 -#define NFCMMD_OFFSET 0x08 -#define NFADDR_OFFSET 0x0c -#define NFDATA_OFFSET 0x10 -#define NFMECCDATA0_OFFSET 0x14 -#define NFMECCDATA1_OFFSET 0x18 -#define NFSECCDATA0_OFFSET 0x1c -#define NFSBLK_OFFSET 0x20 -#define NFEBLK_OFFSET 0x24 -#define NFSTAT_OFFSET 0x28 -#define NFESTAT0_OFFSET 0x2c -#define NFESTAT1_OFFSET 0x30 -#define NFMECC0_OFFSET 0x34 -#define NFMECC1_OFFSET 0x38 -#define NFSECC_OFFSET 0x3c -#define NFMLCBITPT_OFFSET 0x40 - -#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_ECC_4BIT (1<<24) - -#define NFCONT_ECC_ENC (1<<18) -#define NFCONT_WP (1<<16) -#define NFCONT_MECCLOCK (1<<7) -#define NFCONT_SECCLOCK (1<<6) -#define NFCONT_INITMECC (1<<5) -#define NFCONT_INITSECC (1<<4) -#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) -#define NFCONT_CS_ALT (1<<2) -#define NFCONT_CS (1<<1) -#define NFCONT_ENABLE (1<<0) - -#define NFSTAT_ECCENCDONE (1<<7) -#define NFSTAT_ECCDECDONE (1<<6) -#define NFSTAT_RnB (1<<0) - -#define NFESTAT0_ECCBUSY (1<<31) - -/* - * Interrupt - */ -#define ELFIN_VIC0_BASE_ADDR 0x71200000 -#define ELFIN_VIC1_BASE_ADDR 0x71300000 -#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ -#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ -#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ -#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ -#define oVECTADDR 0xF00 /* VIC ADDRESS */ - -/* - * Watchdog timer - */ -#define ELFIN_WATCHDOG_BASE 0x7E004000 - -#define WTCON_REG __REG(0x7E004004) -#define WTDAT_REG __REG(0x7E004008) -#define WTCNT_REG __REG(0x7E00400C) - - -/* - * UART - */ -#define ELFIN_UART_BASE 0x7F005000 - -#define ELFIN_UART0_OFFSET 0x0000 -#define ELFIN_UART1_OFFSET 0x0400 -#define ELFIN_UART2_OFFSET 0x0800 - -#define ULCON_OFFSET 0x00 -#define UCON_OFFSET 0x04 -#define UFCON_OFFSET 0x08 -#define UMCON_OFFSET 0x0C -#define UTRSTAT_OFFSET 0x10 -#define UERSTAT_OFFSET 0x14 -#define UFSTAT_OFFSET 0x18 -#define UMSTAT_OFFSET 0x1C -#define UTXH_OFFSET 0x20 -#define URXH_OFFSET 0x24 -#define UBRDIV_OFFSET 0x28 -#define UDIVSLOT_OFFSET 0x2C -#define UINTP_OFFSET 0x30 -#define UINTSP_OFFSET 0x34 -#define UINTM_OFFSET 0x38 - -#define ULCON0_REG __REG(0x7F005000) -#define UCON0_REG __REG(0x7F005004) -#define UFCON0_REG __REG(0x7F005008) -#define UMCON0_REG __REG(0x7F00500C) -#define UTRSTAT0_REG __REG(0x7F005010) -#define UERSTAT0_REG __REG(0x7F005014) -#define UFSTAT0_REG __REG(0x7F005018) -#define UMSTAT0_REG __REG(0x7F00501c) -#define UTXH0_REG __REG(0x7F005020) -#define URXH0_REG __REG(0x7F005024) -#define UBRDIV0_REG __REG(0x7F005028) -#define UDIVSLOT0_REG __REG(0x7F00502c) -#define UINTP0_REG __REG(0x7F005030) -#define UINTSP0_REG __REG(0x7F005034) -#define UINTM0_REG __REG(0x7F005038) - -#define ULCON1_REG __REG(0x7F005400) -#define UCON1_REG __REG(0x7F005404) -#define UFCON1_REG __REG(0x7F005408) -#define UMCON1_REG __REG(0x7F00540C) -#define UTRSTAT1_REG __REG(0x7F005410) -#define UERSTAT1_REG __REG(0x7F005414) -#define UFSTAT1_REG __REG(0x7F005418) -#define UMSTAT1_REG __REG(0x7F00541c) -#define UTXH1_REG __REG(0x7F005420) -#define URXH1_REG __REG(0x7F005424) -#define UBRDIV1_REG __REG(0x7F005428) -#define UDIVSLOT1_REG __REG(0x7F00542c) -#define UINTP1_REG __REG(0x7F005430) -#define UINTSP1_REG __REG(0x7F005434) -#define UINTM1_REG __REG(0x7F005438) - -#define UTRSTAT_TX_EMPTY (1 << 2) -#define UTRSTAT_RX_READY (1 << 0) -#define UART_ERR_MASK 0xF - -/* - * PWM timer - */ -#define ELFIN_TIMER_BASE 0x7F006000 - -#define TCFG0_REG __REG(0x7F006000) -#define TCFG1_REG __REG(0x7F006004) -#define TCON_REG __REG(0x7F006008) -#define TCNTB0_REG __REG(0x7F00600c) -#define TCMPB0_REG __REG(0x7F006010) -#define TCNTO0_REG __REG(0x7F006014) -#define TCNTB1_REG __REG(0x7F006018) -#define TCMPB1_REG __REG(0x7F00601c) -#define TCNTO1_REG __REG(0x7F006020) -#define TCNTB2_REG __REG(0x7F006024) -#define TCMPB2_REG __REG(0x7F006028) -#define TCNTO2_REG __REG(0x7F00602c) -#define TCNTB3_REG __REG(0x7F006030) -#define TCMPB3_REG __REG(0x7F006034) -#define TCNTO3_REG __REG(0x7F006038) -#define TCNTB4_REG __REG(0x7F00603c) -#define TCNTO4_REG __REG(0x7F006040) - -/* Fields */ -#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ -#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ -#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ -#define fTCFG1_MUX4 Fld(4, 16) -/* bits */ -#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) -#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) -#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) -#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ -#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ -#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ -#define COUNT_4_ON (TCON_4_ONOFF * 1) -#define COUNT_4_OFF (TCON_4_ONOFF * 0) -#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ -#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) -#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) -#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ -#define TIMER3_IVT_ON (TCON_3_INVERT * 1) -#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) -#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ -#define TIMER3_MANUP (TCON_3_MAN*1) -#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) -#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ -#define TIMER3_ON (TCON_3_ONOFF * 1) -#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) - -#if defined(CONFIG_CLK_400_100_50) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 400 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_400_133_66) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_533_133_66) -#define STARTUP_AMDIV 533 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_667_133_66) -#define STARTUP_AMDIV 667 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#endif - -#define STARTUP_PCLKDIV 3 -#define STARTUP_HCLKX2DIV 1 -#define STARTUP_HCLKDIV 1 -#define STARTUP_MPLLDIV 1 -#define STARTUP_APLLDIV 0 - -#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ - (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) -#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) - -#if defined(CONFIG_SYNC_MODE) -#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#else -#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_AMDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#endif - - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ -#define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ - -/* Memory Parameters */ -/* DDR Parameters */ -#define DDR_tREFRESH 7800 /* ns */ -#define DDR_tRAS 45 /* ns (min: 45ns)*/ -#define DDR_tRC 68 /* ns (min: 67.5ns)*/ -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ -#define DDR_tRFC 80 /* ns (min: 80ns)*/ -#define DDR_tRP 23 /* ns (min: 22.5ns)*/ -#define DDR_tRRD 15 /* ns (min: 15ns)*/ -#define DDR_tWR 15 /* ns (min: 15ns)*/ -#define DDR_tXSR 120 /* ns (min: 120ns)*/ -#define DDR_CASL 3 /* CAS Latency 3 */ - -/* - * mDDR memory configuration - */ - -#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) - -#define DMC_DDR_BA_EMRS 2 -#define DMC_DDR_MEM_CASLAT 3 -/* 6 Set Cas Latency to 3 */ -#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) -/* Min 0.75 ~ 1.25 */ -#define DMC_DDR_t_DQSS 1 -/* Min 2 tck */ -#define DMC_DDR_t_MRD 2 -/* 7, Min 45ns */ -#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) -/* 10, Min 67.5ns */ -#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) -/* 4,5(TRM), Min 22.5ns */ -#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) -#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) -/* 11,18(TRM) Min 80ns */ -#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) -#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) -/* 4, 5(TRM) Min 22.5ns */ -#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) -#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) -/* 3, Min 15ns */ -#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) -/* Min 15ns */ -#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) -#define DMC_DDR_t_WTR 2 -/* 1tck + tIS(1.5ns) */ -#define DMC_DDR_t_XP 2 -/* 17, Min 120ns */ -#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) -#define DMC_DDR_t_ESR DMC_DDR_t_XSR -/* TRM 2656 */ -#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) -/* 2b01 : mDDR */ -#define DMC_DDR_USER_CONFIG 1 - -#ifndef __ASSEMBLY__ -enum s3c64xx_uarts_nr { - S3C64XX_UART0, - S3C64XX_UART1, - S3C64XX_UART2, -}; - -#include "s3c64x0.h" - -static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) -{ - return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); -} -#endif - -#endif /*__S3C6400_H__*/ diff --git a/include/s3c64x0.h b/include/s3c64x0.h deleted file mode 100644 index 0bbf1d0c4..000000000 --- a/include/s3c64x0.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2003 - * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : S3C64XX.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C64XX SoC - ************************************************/ - -#ifndef __S3C64XX_H__ -#define __S3C64XX_H__ - -#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) -#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! -#endif - -#include - -/* UART (see manual chapter 11) */ -typedef struct { - volatile u32 ULCON; - volatile u32 UCON; - volatile u32 UFCON; - volatile u32 UMCON; - volatile u32 UTRSTAT; - volatile u32 UERSTAT; - volatile u32 UFSTAT; - volatile u32 UMSTAT; -#ifdef __BIG_ENDIAN - volatile u8 res1[3]; - volatile u8 UTXH; - volatile u8 res2[3]; - volatile u8 URXH; -#else /* Little Endian */ - volatile u8 UTXH; - volatile u8 res1[3]; - volatile u8 URXH; - volatile u8 res2[3]; -#endif - volatile u32 UBRDIV; -#ifdef __BIG_ENDIAN - volatile u8 res3[2]; - volatile u16 UDIVSLOT; -#else - volatile u16 UDIVSLOT; - volatile u8 res3[2]; -#endif -} s3c64xx_uart; - -/* PWM TIMER (see manual chapter 10) */ -typedef struct { - volatile u32 TCNTB; - volatile u32 TCMPB; - volatile u32 TCNTO; -} s3c64xx_timer; - -typedef struct { - volatile u32 TCFG0; - volatile u32 TCFG1; - volatile u32 TCON; - s3c64xx_timer ch[4]; - volatile u32 TCNTB4; - volatile u32 TCNTO4; -} s3c64xx_timers; - -#endif /*__S3C64XX_H__*/ -- cgit v1.2.3 From 940032260914076b1594906334b2e3f7af6fb7cf Mon Sep 17 00:00:00 2001 From: Minkyu Kang Date: Tue, 10 Nov 2009 20:23:50 +0900 Subject: s5pc1xx: serial: fix the error check logic Because of Frame error, Parity error and Overrun error are occured only receive operation, need to masking when error checking. Signed-off-by: Minkyu Kang --- drivers/serial/serial_s5pc1xx.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_s5pc1xx.c b/drivers/serial/serial_s5pc1xx.c index 68c06a919..73669a9f1 100644 --- a/drivers/serial/serial_s5pc1xx.c +++ b/drivers/serial/serial_s5pc1xx.c @@ -98,14 +98,24 @@ int serial_init_dev(const int dev_index) return 0; } -static int serial_err_check(const int dev_index) +static int serial_err_check(const int dev_index, int op) { struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index); + unsigned int mask; + + /* + * UERSTAT + * Break Detect [3] + * Frame Err [2] : receive operation + * Parity Err [1] : receive operation + * Overrun Err [0] : receive operation + */ + if (op) + mask = 0x8; + else + mask = 0xf; - if (readl(&uart->uerstat) & 0xf) - return 1; - - return 0; + return readl(&uart->uerstat) & mask; } /* @@ -119,7 +129,7 @@ int serial_getc_dev(const int dev_index) /* wait for character to arrive */ while (!(readl(&uart->utrstat) & 0x1)) { - if (serial_err_check(dev_index)) + if (serial_err_check(dev_index, 0)) return 0; } @@ -135,7 +145,7 @@ void serial_putc_dev(const char c, const int dev_index) /* wait for room in the tx FIFO */ while (!(readl(&uart->utrstat) & 0x2)) { - if (serial_err_check(dev_index)) + if (serial_err_check(dev_index, 1)) return; } -- cgit v1.2.3 From ac67804fbb2d82a19170066c02af7053d474ce8d Mon Sep 17 00:00:00 2001 From: "kevin.morfitt@fearnside-systems.co.uk" Date: Tue, 17 Nov 2009 18:30:34 +0900 Subject: Add a unified s3c24x0 header file This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt Signed-off-by: Minkyu Kang --- board/mpl/vcma9/vcma9.c | 2 +- board/mpl/vcma9/vcma9.h | 2 +- board/samsung/smdk2400/smdk2400.c | 2 +- board/samsung/smdk2410/smdk2410.c | 2 +- board/sbc2410x/sbc2410x.c | 2 +- board/trab/cmd_trab.c | 2 +- board/trab/rs485.c | 2 +- board/trab/rs485.h | 2 +- board/trab/trab.c | 2 +- board/trab/trab_fkt.c | 2 +- board/trab/tsc2000.c | 2 +- board/trab/vfd.c | 2 +- cpu/arm920t/s3c24x0/interrupts.c | 6 +----- cpu/arm920t/s3c24x0/speed.c | 13 +++---------- cpu/arm920t/s3c24x0/timer.c | 15 +++------------ cpu/arm920t/s3c24x0/usb.c | 17 +++++++---------- cpu/arm920t/s3c24x0/usb_ohci.c | 11 +++-------- cpu/arm920t/start.S | 4 ++-- drivers/i2c/s3c24x0_i2c.c | 6 +----- drivers/mtd/nand/s3c2410_nand.c | 2 +- drivers/rtc/s3c24x0_rtc.c | 6 +----- drivers/serial/serial_s3c24x0.c | 6 +----- drivers/usb/host/ohci-hcd.c | 3 +-- include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h | 27 +++++++++++++++++++++++++++ include/common.h | 5 +++-- include/configs/VCMA9.h | 7 ++++--- include/configs/sbc2410x.h | 7 ++++--- include/configs/smdk2400.h | 7 ++++--- include/configs/smdk2410.h | 7 ++++--- include/configs/trab.h | 9 +++++---- 30 files changed, 87 insertions(+), 95 deletions(-) create mode 100644 include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h (limited to 'drivers') diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index f3bd28845..1835677a8 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 2c4305c6a..94fd2faf3 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -25,7 +25,7 @@ * Global routines used for VCMA9 *****************************************************************************/ -#include +#include extern int mem_test(unsigned long start, unsigned long ramsize,int mode); diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c index be0c70ad0..1294d3f1b 100644 --- a/board/samsung/smdk2400/smdk2400.c +++ b/board/samsung/smdk2400/smdk2400.c @@ -27,7 +27,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/smdk2410/smdk2410.c b/board/samsung/smdk2410/smdk2410.c index a8cf2874a..5d1a8bb0c 100644 --- a/board/samsung/smdk2410/smdk2410.c +++ b/board/samsung/smdk2410/smdk2410.c @@ -27,7 +27,7 @@ #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c index 6768c028c..3a936778e 100644 --- a/board/sbc2410x/sbc2410x.c +++ b/board/sbc2410x/sbc2410x.c @@ -30,7 +30,7 @@ #include #include -#include +#include #if defined(CONFIG_CMD_NAND) #include diff --git a/board/trab/cmd_trab.c b/board/trab/cmd_trab.c index a01ffcc02..472d7d81e 100644 --- a/board/trab/cmd_trab.c +++ b/board/trab/cmd_trab.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include /* diff --git a/board/trab/rs485.c b/board/trab/rs485.c index f402c5990..ad0c13665 100644 --- a/board/trab/rs485.c +++ b/board/trab/rs485.c @@ -22,7 +22,7 @@ */ #include -#include +#include #include "rs485.h" static void rs485_setbrg (void); diff --git a/board/trab/rs485.h b/board/trab/rs485.h index 4a2d83f0b..16d69bbd5 100644 --- a/board/trab/rs485.h +++ b/board/trab/rs485.h @@ -24,7 +24,7 @@ #ifndef _RS485_H_ #define _RS485_H_ -#include +#include int rs485_init (void); int rs485_getc (void); diff --git a/board/trab/trab.c b/board/trab/trab.c index f8836ff37..71fd22c15 100644 --- a/board/trab/trab.c +++ b/board/trab/trab.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/trab/trab_fkt.c b/board/trab/trab_fkt.c index 940e12f25..2df9a0440 100644 --- a/board/trab/trab_fkt.c +++ b/board/trab/trab_fkt.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include "tsc2000.h" #include "rs485.h" diff --git a/board/trab/tsc2000.c b/board/trab/tsc2000.c index f757202de..5890624f0 100644 --- a/board/trab/tsc2000.c +++ b/board/trab/tsc2000.c @@ -26,7 +26,7 @@ */ #include -#include +#include #include #include #include "tsc2000.h" diff --git a/board/trab/vfd.c b/board/trab/vfd.c index 8d9a05716..b7eb8cce0 100644 --- a/board/trab/vfd.c +++ b/board/trab/vfd.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c index 3e8422e14..879fda66a 100644 --- a/cpu/arm920t/s3c24x0/interrupts.c +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -31,11 +31,7 @@ #include -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #include void do_irq (struct pt_regs *pt_regs) diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c index 85c73a3ee..b13283a79 100644 --- a/cpu/arm920t/s3c24x0/speed.c +++ b/cpu/arm920t/s3c24x0/speed.c @@ -30,15 +30,10 @@ */ #include -#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) +#ifdef CONFIG_S3C24X0 #include - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #define MPLL 0 #define UPLL 1 @@ -100,6 +95,4 @@ ulong get_UCLK(void) return get_PLLCLK(UPLL); } -#endif /* defined(CONFIG_S3C2400) || - defined (CONFIG_S3C2410) || - defined (CONFIG_TRAB) */ +#endif /* CONFIG_S3C24X0 */ diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index 2667da6e8..cd06f6b58 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -30,17 +30,10 @@ */ #include -#if defined(CONFIG_S3C2400) || \ - defined(CONFIG_S3C2410) || \ - defined(CONFIG_TRAB) +#ifdef CONFIG_S3C24X0 #include - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include int timer_load_val = 0; static ulong timer_clk; @@ -225,6 +218,4 @@ void reset_cpu(ulong ignored) /*NOTREACHED*/ } -#endif /* defined(CONFIG_S3C2400) || - defined (CONFIG_S3C2410) || - defined (CONFIG_TRAB) */ +#endif /* CONFIG_S3C24X0 */ diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c index 5e19cda8f..e468ed08f 100644 --- a/cpu/arm920t/s3c24x0/usb.c +++ b/cpu/arm920t/s3c24x0/usb.c @@ -23,15 +23,11 @@ #include -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) - -#if defined(CONFIG_S3C2400) -# include -#elif defined(CONFIG_S3C2410) -# include -#endif +#if defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) +#include #include int usb_cpu_init(void) @@ -70,5 +66,6 @@ int usb_cpu_init_fail(void) return 0; } -# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */ -#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ +#endif /* defined(CONFIG_USB_OHCI_NEW) && \ + defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \ + defined(CONFIG_S3C24X0) */ diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c index 41119922e..5aa8d64a5 100644 --- a/cpu/arm920t/s3c24x0/usb_ohci.c +++ b/cpu/arm920t/s3c24x0/usb_ohci.c @@ -36,14 +36,9 @@ #include /* #include no PCI on the S3C24X0 */ -#ifdef CONFIG_USB_OHCI - -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) +#include #include #include #include @@ -1757,4 +1752,4 @@ int usb_lowlevel_stop(void) return 0; } -#endif /* CONFIG_USB_OHCI */ +#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */ diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 114427a16..779f192e5 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -131,7 +131,7 @@ copyex: bne copyex #endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) +#ifdef CONFIG_S3C24X0 /* turn off the watchdog */ # if defined(CONFIG_S3C2400) @@ -166,7 +166,7 @@ copyex: ldr r0, =CLKDIVN mov r1, #3 str r1, [r0] -#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */ +#endif /* CONFIG_S3C24X0 */ /* * we do sys-critical inits only at reboot, diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 8fecc6e3f..c8371cf73 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -27,11 +27,7 @@ */ #include -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #include #include diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c index 2f89b8c96..a27d47e5f 100644 --- a/drivers/mtd/nand/s3c2410_nand.c +++ b/drivers/mtd/nand/s3c2410_nand.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #define S3C2410_NFCONF_EN (1<<15) diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c index 2d78f93ae..04de5ca54 100644 --- a/drivers/rtc/s3c24x0_rtc.c +++ b/drivers/rtc/s3c24x0_rtc.c @@ -30,11 +30,7 @@ #if (defined(CONFIG_CMD_DATE)) -#if defined(CONFIG_S3C2400) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include #include #include diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c index 914d07cda..5dd4dd816 100644 --- a/drivers/serial/serial_s3c24x0.c +++ b/drivers/serial/serial_s3c24x0.c @@ -19,11 +19,7 @@ */ #include -#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB) -#include -#elif defined(CONFIG_S3C2410) -#include -#endif +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 67d478f87..b03a60044 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -65,8 +65,7 @@ #endif #if defined(CONFIG_ARM920T) || \ - defined(CONFIG_S3C2400) || \ - defined(CONFIG_S3C2410) || \ + defined(CONFIG_S3C24X0) || \ defined(CONFIG_S3C6400) || \ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ diff --git a/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h new file mode 100644 index 000000000..c37d4a108 --- /dev/null +++ b/include/asm-arm/arch-s3c24x0/s3c24x0_cpu.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2009 + * Kevin Morfitt, Fearnside Systems Ltd, + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifdef CONFIG_S3C2400 + #include +#elif defined CONFIG_S3C2410 + #include +#else + #error Please define the s3c24x0 cpu type +#endif diff --git a/include/common.h b/include/common.h index f7c93bf5a..8ee80c139 100644 --- a/include/common.h +++ b/include/common.h @@ -495,8 +495,9 @@ int prt_mpc8220_clks (void); ulong get_OPB_freq (void); ulong get_PCI_freq (void); #endif -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ - defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400) +#if defined(CONFIG_S3C24X0) || \ + defined(CONFIG_LH7A40X) || \ + defined(CONFIG_S3C6400) ulong get_FCLK (void); ulong get_HCLK (void); ulong get_PCLK (void); diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 618b7f0a7..ebc81c400 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,9 +33,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index e6886cf7f..025ad0953 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -43,9 +43,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */ diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index a1beb65d0..fd51219af 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -34,9 +34,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T core */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ +#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index c57751bf9..f9d1e5518 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -33,9 +33,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ -#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ diff --git a/include/configs/trab.h b/include/configs/trab.h index 97f30cea7..9827195e8 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -40,10 +40,11 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ -#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ -#define CONFIG_TRAB 1 /* on a TRAB Board */ -#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ +#define CONFIG_ARM920T 1 /* This is an arm920t CPU */ +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */ +#define CONFIG_TRAB 1 /* on a TRAB Board */ +#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ /* automatic software updates (see board/trab/auto_update.c) */ #define CONFIG_AUTO_UPDATE 1 -- cgit v1.2.3 From 39ba774f9b02c44b8fd4df44afac932800c18662 Mon Sep 17 00:00:00 2001 From: Po-Yu Chuang Date: Wed, 11 Nov 2009 17:26:00 +0800 Subject: arm: A320: driver for FTRTC010 real time clock This patch adds an FTRTC010 driver for Faraday A320 evaluation board. Signed-off-by: Po-Yu Chuang --- drivers/rtc/Makefile | 1 + drivers/rtc/ftrtc010.c | 124 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 drivers/rtc/ftrtc010.c (limited to 'drivers') diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index ea7d899ea..772a49a90 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_RTC_DS1556) += ds1556.o COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o COBJS-$(CONFIG_RTC_DS3231) += ds3231.o +COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-$(CONFIG_RTC_M41T11) += m41t11.o COBJS-$(CONFIG_RTC_M41T60) += m41t60.o diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c new file mode 100644 index 000000000..7738a7aca --- /dev/null +++ b/drivers/rtc/ftrtc010.c @@ -0,0 +1,124 @@ +/* + * Faraday FTRTC010 Real Time Clock + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include + +struct ftrtc010 { + unsigned int sec; /* 0x00 */ + unsigned int min; /* 0x04 */ + unsigned int hour; /* 0x08 */ + unsigned int day; /* 0x0c */ + unsigned int alarm_sec; /* 0x10 */ + unsigned int alarm_min; /* 0x14 */ + unsigned int alarm_hour; /* 0x18 */ + unsigned int record; /* 0x1c */ + unsigned int cr; /* 0x20 */ +}; + +/* + * RTC Control Register + */ +#define FTRTC010_CR_ENABLE (1 << 0) +#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ +#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ +#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ +#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ + +static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; + +static void ftrtc010_enable(void) +{ + writel(FTRTC010_CR_ENABLE, &rtc->cr); +} + +/* + * return current time in seconds + */ +static unsigned long ftrtc010_time(void) +{ + unsigned long day; + unsigned long hour; + unsigned long minute; + unsigned long second; + unsigned long second2; + + do { + second = readl(&rtc->sec); + day = readl(&rtc->day); + hour = readl(&rtc->hour); + minute = readl(&rtc->min); + second2 = readl(&rtc->sec); + } while (second != second2); + + return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; +} + +/* + * Get the current time from the RTC + */ + +int rtc_get(struct rtc_time *tmp) +{ + unsigned long now; + + debug("%s(): record register: %x\n", + __func__, readl(&rtc->record)); + + now = ftrtc010_time() + readl(&rtc->record); + + to_tm(now, tmp); + + return 0; +} + +/* + * Set the RTC + */ +int rtc_set(struct rtc_time *tmp) +{ + unsigned long new; + unsigned long now; + + debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + __func__, + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, + tmp->tm_min, tmp->tm_sec); + + now = ftrtc010_time(); + + debug("%s(): write %lx to record register\n", __func__, new - now); + + writel(new - now, &rtc->record); + + return 0; +} + +void rtc_reset(void) +{ + debug("%s()\n", __func__); + ftrtc010_enable(); +} -- cgit v1.2.3 From 7c15121f4007751af8c45c978c4ad7d6c5ff11f9 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Mon, 23 Nov 2009 16:36:05 +0530 Subject: omap3_mmc: Encapsulate twl4030 under option CONFIG_TWL4030_POWER Fixes the build/compilation error if we try to re-use the omap3_mmc code without TWL4030_POWER. Signed-off-by: Vaibhav Hiremath --- drivers/mmc/omap3_mmc.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 513dd25b0..96c0e653b 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -63,7 +63,9 @@ unsigned char mmc_board_init(void) { t2_t *t2_base = (t2_t *)T2_BASE; +#if defined(CONFIG_TWL4030_POWER) twl4030_power_mmc_init(); +#endif writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, -- cgit v1.2.3 From 4b142febff71eabdb7ddbb125c7b583b24ddc434 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 3 Dec 2009 11:21:21 +0100 Subject: common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher --- README | 9 +-------- common/cmd_fdt.c | 14 ++------------ common/cmd_ide.c | 4 ++-- common/cmd_onenand.c | 4 ---- common/image.c | 4 ---- cpu/mpc85xx/mp.c | 4 ---- disk/part.c | 2 +- drivers/mtd/nand/nand_util.c | 4 ---- fs/ubifs/ubifs.c | 4 ---- include/common.h | 2 -- include/configs/ASH405.h | 2 -- include/configs/CMS700.h | 2 -- include/configs/HH405.h | 2 -- include/configs/HUB405.h | 2 -- include/configs/IDS8247.h | 2 -- include/configs/MPC8313ERDB.h | 1 - include/configs/MPC8315ERDB.h | 1 - include/configs/MPC8360ERDK.h | 1 - include/configs/MPC837XEMDS.h | 3 --- include/configs/MPC837XERDB.h | 3 --- include/configs/MPC8536DS.h | 4 ---- include/configs/MPC8540ADS.h | 3 --- include/configs/MPC8541CDS.h | 3 --- include/configs/MPC8544DS.h | 3 --- include/configs/MPC8548CDS.h | 3 --- include/configs/MPC8555CDS.h | 3 --- include/configs/MPC8560ADS.h | 3 --- include/configs/MPC8568MDS.h | 3 --- include/configs/MPC8569MDS.h | 3 --- include/configs/MPC8572DS.h | 3 --- include/configs/MPC8610HPCD.h | 3 --- include/configs/MPC8641HPCN.h | 4 ---- include/configs/P1_P2_RDB.h | 3 --- include/configs/P2020DS.h | 3 --- include/configs/PLU405.h | 2 -- include/configs/PPChameleonEVB.h | 2 -- include/configs/SIMPC8313.h | 1 - include/configs/TQM8272.h | 2 -- include/configs/TQM85xx.h | 2 -- include/configs/VOH405.h | 2 -- include/configs/WUH405.h | 2 -- include/configs/XPEDITE5170.h | 3 --- include/configs/XPEDITE5200.h | 3 --- include/configs/XPEDITE5370.h | 3 --- include/configs/acadia.h | 2 -- include/configs/afeb9260.h | 1 - include/configs/apollon.h | 2 -- include/configs/aria.h | 2 -- include/configs/at91cap9adk.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9m10g45ek.h | 2 -- include/configs/at91sam9rlek.h | 1 - include/configs/bfin_adi_common.h | 3 --- include/configs/cpu9260.h | 1 - include/configs/davinci_dm355evm.h | 1 - include/configs/davinci_dm355leopard.h | 1 - include/configs/davinci_dm365evm.h | 1 - include/configs/davinci_dm6467evm.h | 1 - include/configs/davinci_dvevm.h | 1 - include/configs/davinci_schmoogie.h | 1 - include/configs/davinci_sffsdr.h | 1 - include/configs/davinci_sonata.h | 1 - include/configs/delta.h | 2 -- include/configs/devkit8000.h | 2 -- include/configs/keymile-common.h | 2 -- include/configs/kilauea.h | 2 -- include/configs/mecp5123.h | 2 -- include/configs/meesc.h | 1 - include/configs/mpc5121ads.h | 2 -- include/configs/netstar.h | 2 -- include/configs/nhk8815.h | 1 - include/configs/omap3_beagle.h | 2 -- include/configs/omap3_evm.h | 2 -- include/configs/omap3_overo.h | 2 -- include/configs/omap3_pandora.h | 3 --- include/configs/omap3_zoom1.h | 3 --- include/configs/omap3_zoom2.h | 2 -- include/configs/openrd_base.h | 1 - include/configs/pdnb3.h | 1 - include/configs/pm9261.h | 3 --- include/configs/pm9263.h | 1 - include/configs/quad100hd.h | 1 - include/configs/rd6281a.h | 1 - include/configs/sbc35_a9g20.h | 1 - include/configs/sbc8641d.h | 3 --- include/configs/sc3.h | 2 -- include/configs/sheevaplug.h | 1 - include/configs/smdk6400.h | 2 -- include/configs/smdkc100.h | 2 -- include/configs/socrates.h | 2 -- include/configs/tny_a9260.h | 1 - include/configs/vct.h | 6 ------ include/configs/zylonite.h | 2 -- include/ppc4xx.h | 6 ------ lib_generic/vsprintf.c | 18 +----------------- 97 files changed, 7 insertions(+), 239 deletions(-) (limited to 'drivers') diff --git a/README b/README index fe6ca98d8..22e35c39b 100644 --- a/README +++ b/README @@ -777,7 +777,7 @@ The following options need to be configured: CONFIG_LBA48 Set this to enable support for disks larger than 137GB - Also look at CONFIG_SYS_64BIT_LBA ,CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL + Also look at CONFIG_SYS_64BIT_LBA. Whithout these , LBA48 support uses 32bit variables and will 'only' support disks up to 2.1TB. @@ -2524,13 +2524,6 @@ use the "saveenv" command to store a valid environment. - CONFIG_SYS_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state. -- CONFIG_SYS_64BIT_VSPRINTF: - Makes vsprintf (and all *printf functions) support printing - of 64bit values by using the L quantifier - -- CONFIG_SYS_64BIT_STRTOUL: - Adds simple_strtoull that returns a 64bit value - - CONFIG_NS16550_MIN_FUNCTIONS: Define this if you desire to only have use of the NS16550_init and NS16550_putc functions for the serial driver located at diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index 919a0bf6e..5df79ae3e 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -364,13 +364,8 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } else if (strncmp(argv[1], "me", 2) == 0) { uint64_t addr, size; int err; -#ifdef CONFIG_SYS_64BIT_STRTOUL - addr = simple_strtoull(argv[2], NULL, 16); - size = simple_strtoull(argv[3], NULL, 16); -#else - addr = simple_strtoul(argv[2], NULL, 16); - size = simple_strtoul(argv[3], NULL, 16); -#endif + addr = simple_strtoull(argv[2], NULL, 16); + size = simple_strtoull(argv[3], NULL, 16); err = fdt_fixup_memory(working_fdt, addr, size); if (err < 0) return err; @@ -402,13 +397,8 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } else if (argv[2][0] == 'a') { uint64_t addr, size; int err; -#ifdef CONFIG_SYS_64BIT_STRTOUL addr = simple_strtoull(argv[3], NULL, 16); size = simple_strtoull(argv[4], NULL, 16); -#else - addr = simple_strtoul(argv[3], NULL, 16); - size = simple_strtoul(argv[4], NULL, 16); -#endif err = fdt_add_mem_rsv(working_fdt, addr, size); if (err < 0) { diff --git a/common/cmd_ide.c b/common/cmd_ide.c index ec9a1df38..093ca9f90 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -1354,7 +1354,7 @@ ulong ide_read (int device, lbaint_t blknr, ulong blkcnt, void *buffer) } if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) { -#if defined(CONFIG_SYS_64BIT_LBA) && defined(CONFIG_SYS_64BIT_VSPRINTF) +#if defined(CONFIG_SYS_64BIT_LBA) printf ("Error (no IRQ) dev %d blk %Ld: status 0x%02x\n", device, blknr, c); #else @@ -1444,7 +1444,7 @@ ulong ide_write (int device, lbaint_t blknr, ulong blkcnt, void *buffer) c = ide_wait (device, IDE_TIME_OUT); /* can't take over 500 ms */ if ((c&(ATA_STAT_DRQ|ATA_STAT_BUSY|ATA_STAT_ERR)) != ATA_STAT_DRQ) { -#if defined(CONFIG_SYS_64BIT_LBA) && defined(CONFIG_SYS_64BIT_VSPRINTF) +#if defined(CONFIG_SYS_64BIT_LBA) printf ("Error (no IRQ) dev %d blk %Ld: status 0x%02x\n", device, blknr, c); #else diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 9090940ae..565257cf4 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -19,10 +19,6 @@ #include -#if !defined(CONFIG_SYS_64BIT_VSPRINTF) -#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! -#endif - static struct mtd_info *mtd; static loff_t next_ofs; diff --git a/common/image.c b/common/image.c index 5cc3ab49d..82e7aa436 100644 --- a/common/image.c +++ b/common/image.c @@ -436,11 +436,7 @@ phys_size_t getenv_bootm_size(void) char *s = getenv ("bootm_size"); if (s) { phys_size_t tmp; -#ifdef CONFIG_SYS_64BIT_STRTOUL tmp = (phys_size_t)simple_strtoull (s, NULL, 16); -#else - tmp = (phys_size_t)simple_strtoul (s, NULL, 16); -#endif return tmp; } diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 00b645069..7626eb8e7 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -90,11 +90,7 @@ int cpu_release(int nr, int argc, char *argv[]) return 1; } -#ifdef CONFIG_SYS_64BIT_STRTOUL boot_addr = simple_strtoull(argv[0], NULL, 16); -#else - boot_addr = simple_strtoul(argv[0], NULL, 16); -#endif /* handle pir, r3, r6 */ for (i = 1; i < 4; i++) { diff --git a/disk/part.c b/disk/part.c index 9ced4527f..b6bae1794 100644 --- a/disk/part.c +++ b/disk/part.c @@ -196,7 +196,7 @@ void dev_print (block_dev_desc_t *dev_desc) if (dev_desc->lba48) printf (" Supports 48-bit addressing\n"); #endif -#if defined(CONFIG_SYS_64BIT_LBA) && defined(CONFIG_SYS_64BIT_VSPRINTF) +#if defined(CONFIG_SYS_64BIT_LBA) printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n", mb_quot, mb_rem, gb_quot, gb_rem, diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 7085d42cc..df7f1400f 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -41,10 +41,6 @@ #include #include -#if !defined(CONFIG_SYS_64BIT_VSPRINTF) -#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! -#endif - typedef struct erase_info erase_info_t; typedef struct mtd_info mtd_info_t; diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 82f1c547d..3fc79909e 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -26,10 +26,6 @@ #include "ubifs.h" #include -#if !defined(CONFIG_SYS_64BIT_VSPRINTF) -#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! -#endif - DECLARE_GLOBAL_DATA_PTR; /* compress.c */ diff --git a/include/common.h b/include/common.h index 749d35cab..00b543408 100644 --- a/include/common.h +++ b/include/common.h @@ -617,9 +617,7 @@ void udelay (unsigned long); /* lib_generic/vsprintf.c */ ulong simple_strtoul(const char *cp,char **endp,unsigned int base); -#ifdef CONFIG_SYS_64BIT_VSPRINTF unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); -#endif long simple_strtol(const char *cp,char **endp,unsigned int base); void panic(const char *fmt, ...) __attribute__ ((format (__printf__, 1, 2))); diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 694a87b97..5cb0f1e28 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -160,8 +160,6 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 2384925a2..ae8494d57 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -165,8 +165,6 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 1a2266ff7..92335239d 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -219,8 +219,6 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 518d94d61..ea502d42c 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -160,8 +160,6 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 147a8b267..71bb7b48c 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -263,8 +263,6 @@ #define CONFIG_SYS_NAND0_BASE 0xE1000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - #endif /* CONFIG_CMD_NAND */ /*----------------------------------------------------------------------- diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 5927e7639..0a4ba2915 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -236,7 +236,6 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 8eaff5d06..79376b3c5 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -228,7 +228,6 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2<= 0xc0000000) #define CONFIG_ENABLE_MMU #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 3632b847f..96410413a 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -188,8 +188,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - /* LIME GDC */ #define CONFIG_SYS_LIME_BASE 0xc8000000 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ diff --git a/include/configs/tny_a9260.h b/include/configs/tny_a9260.h index 5b70a7bec..4ad081b0b 100644 --- a/include/configs/tny_a9260.h +++ b/include/configs/tny_a9260.h @@ -138,7 +138,6 @@ #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #endif #define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" diff --git a/include/configs/vct.h b/include/configs/vct.h index 20bf48148..1b894a60e 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -283,12 +283,6 @@ int vct_gpio_get(int pin); #define CONFIG_BOOTCOMMAND "run test3" #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -/* - * Needed for 64bit printf format - */ -#define CONFIG_SYS_64BIT_VSPRINTF 1 -#define CONFIG_SYS_64BIT_STRTOUL 1 - /* * UBI configuration */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 36c341e7c..d0fc13888 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -205,8 +205,6 @@ #define CONFIG_SYS_NAND_SENDCMD_RETRY 3 #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - /* NAND Timing Parameters (in ns) */ #define NAND_TIMING_tCH 10 #define NAND_TIMING_tCS 0 diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 5024db447..ee30a4ca3 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -100,12 +100,6 @@ #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ #if defined(CONFIG_440) -/* - * Enable long long (%ll ...) printf format on 440 PPC's since most of - * them support 36bit physical addressing - */ -#define CONFIG_SYS_64BIT_VSPRINTF -#define CONFIG_SYS_64BIT_STRTOUL #include #else #include diff --git a/lib_generic/vsprintf.c b/lib_generic/vsprintf.c index 3d95728ef..8c58a9366 100644 --- a/lib_generic/vsprintf.c +++ b/lib_generic/vsprintf.c @@ -21,21 +21,10 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #endif -#ifdef CONFIG_SYS_64BIT_VSPRINTF #include # define NUM_TYPE long long -#else -# define NUM_TYPE long -#define do_div(n, base) ({ \ - unsigned int __res; \ - __res = ((unsigned NUM_TYPE) n) % base; \ - n = ((unsigned NUM_TYPE) n) / base; \ - __res; \ -}) -#endif #define noinline __attribute__((noinline)) - const char hex_asc[] = "0123456789abcdef"; #define hex_asc_lo(x) hex_asc[((x) & 0x0f)] #define hex_asc_hi(x) hex_asc[((x) & 0xf0) >> 4] @@ -104,7 +93,6 @@ int ustrtoul(const char *cp, char **endp, unsigned int base) return result; } -#ifdef CONFIG_SYS_64BIT_STRTOUL unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base) { unsigned long long result = 0, value; @@ -132,7 +120,6 @@ unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int ba *endp = (char *) cp; return result; } -#endif /* CONFIG_SYS_64BIT_STRTOUL */ /* we use this so that we can do without the ctype library */ #define is_digit(c) ((c) >= '0' && (c) <= '9') @@ -631,12 +618,9 @@ int vsprintf(char *buf, const char *fmt, va_list args) --fmt; continue; } -#ifdef CONFIG_SYS_64BIT_VSPRINTF if (qualifier == 'L') /* "quad" for 64 bit variables */ num = va_arg(args, unsigned long long); - else -#endif - if (qualifier == 'l') { + else if (qualifier == 'l') { num = va_arg(args, unsigned long); if (flags & SIGN) num = (signed long) num; -- cgit v1.2.3 From f4cfe42758192d09f8375e384cc000aa70d97029 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Dec 2009 09:01:43 +0100 Subject: nand: Fix access to last block in NAND devices Currently, the last block of NAND devices can't be accessed. This patch fixes this issue by correcting the boundary checking (off-by-one error). Signed-off-by: Stefan Roese Cc: Scott Wood Cc: Wolfgang Denk --- drivers/mtd/nand/nand_util.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 7085d42cc..61bf7e684 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -490,7 +490,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, len_incl_bad = get_len_incl_bad (nand, offset, *length); - if ((offset + len_incl_bad) >= nand->size) { + if ((offset + len_incl_bad) > nand->size) { printf ("Attempt to write outside the flash area\n"); return -EINVAL; } @@ -562,7 +562,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, len_incl_bad = get_len_incl_bad (nand, offset, *length); - if ((offset + len_incl_bad) >= nand->size) { + if ((offset + len_incl_bad) > nand->size) { printf ("Attempt to read outside the flash area\n"); return -EINVAL; } -- cgit v1.2.3 From b7ad4109da342dfc787468fc713d88d0a8b9e67a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 16 Oct 2009 00:06:35 -0500 Subject: NET: LAN91C96 CONFIG_NET_MULTIify Make the lan91c96 driver capable of CONFIG_NET_MULTI to be clean for the new arch, add a a lil detect function Most of the formatting change was done to keep checkpatch silent, but a few functions and #if 0ed code which does not make sense for NET_MULTI have been removed Now, use the lan91c96_initialize() function to init the driver Signed-off-by: Nishanth Menon Signed-off-by: Ben Warren --- drivers/net/Makefile | 2 +- drivers/net/lan91c96.c | 452 ++++++++++++++++++++----------------------------- drivers/net/lan91c96.h | 110 ++++++------ include/netdev.h | 1 + 4 files changed, 236 insertions(+), 329 deletions(-) (limited to 'drivers') diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fc9887b51..904727e1b 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -44,7 +44,7 @@ COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o -COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o +COBJS-$(CONFIG_LAN91C96) += lan91c96.o COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o diff --git a/drivers/net/lan91c96.c b/drivers/net/lan91c96.c index 65565bcb0..90e400249 100644 --- a/drivers/net/lan91c96.c +++ b/drivers/net/lan91c96.c @@ -60,6 +60,7 @@ #include #include +#include #include "lan91c96.h" #include @@ -108,11 +109,7 @@ * *------------------------------------------------------------------------ */ -#define CARDNAME "LAN91C96" - -#define SMC_BASE_ADDRESS CONFIG_LAN91C96_BASE - -#define SMC_DEV_NAME "LAN91C96" +#define DRIVER_NAME "LAN91C96" #define SMC_ALLOC_MAX_TRY 5 #define SMC_TX_TIMEOUT 30 @@ -124,64 +121,12 @@ #undef USE_32_BIT #endif -/*----------------------------------------------------------------- - * - * The driver can be entered at any of the following entry points. - * - *----------------------------------------------------------------- - */ - -extern int eth_init (bd_t * bd); -extern void eth_halt (void); -extern int eth_rx (void); -extern int eth_send (volatile void *packet, int length); -#if 0 -static int smc_hw_init (void); -#endif - -/* - * This is called by register_netdev(). It is responsible for - * checking the portlist for the SMC9000 series chipset. If it finds - * one, then it will initialize the device, find the hardware information, - * and sets up the appropriate device parameters. - * NOTE: Interrupts are *OFF* when this procedure is called. - * - * NB:This shouldn't be static since it is referred to externally. - */ -int smc_init (void); - -/* - * This is called by unregister_netdev(). It is responsible for - * cleaning up before the driver is finally unregistered and discarded. - */ -void smc_destructor (void); - -/* - * The kernel calls this function when someone wants to use the device, - * typically 'ifconfig ethX up'. - */ -static int smc_open (bd_t *bd); - - -/* - * This is called by the kernel in response to 'ifconfig ethX down'. It - * is responsible for cleaning up everything that the open routine - * does, and maybe putting the card into a powerdown state. - */ -static int smc_close (void); - -/* - * This is a separate procedure to handle the receipt of a packet, to - * leave the interrupt code looking slightly cleaner - */ -static int smc_rcv (void); - /* See if a MAC address is defined in the current environment. If so use it. If not . print a warning and set the environment and other globals with the default. . If an EEPROM is present it really should be consulted. */ -int smc_get_ethaddr(bd_t *bd); -int get_rom_mac(unsigned char *v_rom_mac); +static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev); +static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac); /* ------------------------------------------------------------ * Internal routines @@ -195,7 +140,7 @@ static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c }; * the default mac address. */ -void smc_set_mac_addr (const unsigned char *addr) +static void smc_set_mac_addr(const unsigned char *addr) { int i; @@ -204,45 +149,21 @@ void smc_set_mac_addr (const unsigned char *addr) } } -/* - * smc_get_macaddr is no longer used. If you want to override the default - * mac address, call smc_get_mac_addr as a part of the board initialisation. - */ - -#if 0 -void smc_get_macaddr (byte * addr) -{ - /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ - unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); - int i; - - - for (i = 0; i < 6; i++) { - addr[0] = *(dnp1110_mac + 0); - addr[1] = *(dnp1110_mac + 1); - addr[2] = *(dnp1110_mac + 2); - addr[3] = *(dnp1110_mac + 3); - addr[4] = *(dnp1110_mac + 4); - addr[5] = *(dnp1110_mac + 5); - } -} -#endif /* 0 */ - /*********************************************** * Show available memory * ***********************************************/ -void dump_memory_info (void) +void dump_memory_info(struct eth_device *dev) { word mem_info; word old_bank; - old_bank = SMC_inw (LAN91C96_BANK_SELECT) & 0xF; + old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF; - SMC_SELECT_BANK (0); - mem_info = SMC_inw (LAN91C96_MIR); + SMC_SELECT_BANK(dev, 0); + mem_info = SMC_inw(dev, LAN91C96_MIR); PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048); - SMC_SELECT_BANK (old_bank); + SMC_SELECT_BANK(dev, old_bank); } /* @@ -252,28 +173,15 @@ void dump_memory_info (void) static void print_packet (byte *, int); #endif -/* #define tx_done(dev) 1 */ - - -/* this does a soft reset on the device */ -static void smc_reset (void); - -/* Enable Interrupts, Receive, and Transmit */ -static void smc_enable (void); - -/* this puts the device in an inactive state */ -static void smc_shutdown (void); - - -static int poll4int (byte mask, int timeout) +static int poll4int (struct eth_device *dev, byte mask, int timeout) { int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; int is_timeout = 0; - word old_bank = SMC_inw (LAN91C96_BANK_SELECT); + word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT); PRINTK2 ("Polling...\n"); - SMC_SELECT_BANK (2); - while ((SMC_inw (LAN91C96_INT_STATS) & mask) == 0) { + SMC_SELECT_BANK(dev, 2); + while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) { if (get_timer (0) >= tmo) { is_timeout = 1; break; @@ -281,7 +189,7 @@ static int poll4int (byte mask, int timeout) } /* restore old bank selection */ - SMC_SELECT_BANK (old_bank); + SMC_SELECT_BANK(dev, old_bank); if (is_timeout) return 1; @@ -290,7 +198,7 @@ static int poll4int (byte mask, int timeout) } /* - * Function: smc_reset( void ) + * Function: smc_reset * Purpose: * This sets the SMC91111 chip to its normal state, hopefully from whatever * mess that any other DOS driver has put it in. @@ -306,28 +214,28 @@ static int poll4int (byte mask, int timeout) * 5. clear all interrupts * */ -static void smc_reset (void) +static void smc_reset(struct eth_device *dev) { - PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME); + PRINTK2("%s:smc_reset\n", dev->name); /* This resets the registers mostly to defaults, but doesn't affect EEPROM. That seems unnecessary */ - SMC_SELECT_BANK (0); - SMC_outw (LAN91C96_RCR_SOFT_RST, LAN91C96_RCR); + SMC_SELECT_BANK(dev, 0); + SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR); udelay (10); /* Disable transmit and receive functionality */ - SMC_outw (0, LAN91C96_RCR); - SMC_outw (0, LAN91C96_TCR); + SMC_outw(dev, 0, LAN91C96_RCR); + SMC_outw(dev, 0, LAN91C96_TCR); /* set the control register */ - SMC_SELECT_BANK (1); - SMC_outw (SMC_inw (LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8, + SMC_SELECT_BANK(dev, 1); + SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8, LAN91C96_CONTROL); /* Disable all interrupts */ - SMC_outb (0, LAN91C96_INT_MASK); + SMC_outb(dev, 0, LAN91C96_INT_MASK); } /* @@ -338,24 +246,24 @@ static void smc_reset (void) * 2. Enable the transmitter * 3. Enable the receiver */ -static void smc_enable () +static void smc_enable(struct eth_device *dev) { - PRINTK2 ("%s:smc_enable\n", SMC_DEV_NAME); - SMC_SELECT_BANK (0); + PRINTK2("%s:smc_enable\n", dev->name); + SMC_SELECT_BANK(dev, 0); /* Initialize the Memory Configuration Register. See page 49 of the LAN91C96 data sheet for details. */ - SMC_outw (LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR); + SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR); /* Initialize the Transmit Control Register */ - SMC_outw (LAN91C96_TCR_TXENA, LAN91C96_TCR); + SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR); /* Initialize the Receive Control Register * FIXME: * The promiscuous bit set because I could not receive ARP reply * packets from the server when I send a ARP request. It only works * when I set the promiscuous bit */ - SMC_outw (LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR); + SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR); } /* @@ -372,18 +280,18 @@ static void smc_enable () * the manual says that it will wake up in response to any I/O requests * in the register space. Empirical results do not show this working. */ -static void smc_shutdown () +static void smc_shutdown(struct eth_device *dev) { - PRINTK2 (CARDNAME ":smc_shutdown\n"); + PRINTK2("%s:smc_shutdown\n", dev->name); /* no more interrupts for me */ - SMC_SELECT_BANK (2); - SMC_outb (0, LAN91C96_INT_MASK); + SMC_SELECT_BANK(dev, 2); + SMC_outb(dev, 0, LAN91C96_INT_MASK); /* and tell the card to stay away from that nasty outside world */ - SMC_SELECT_BANK (0); - SMC_outb (0, LAN91C96_RCR); - SMC_outb (0, LAN91C96_TCR); + SMC_SELECT_BANK(dev, 0); + SMC_outb(dev, 0, LAN91C96_RCR); + SMC_outb(dev, 0, LAN91C96_TCR); } @@ -405,7 +313,8 @@ static void smc_shutdown () * Enable the transmit interrupt, so I know if it failed * Free the kernel data if I actually sent it. */ -static int smc_send_packet (volatile void *packet, int packet_length) +static int smc_send_packet(struct eth_device *dev, volatile void *packet, + int packet_length) { byte packet_no; unsigned long ioaddr; @@ -417,7 +326,7 @@ static int smc_send_packet (volatile void *packet, int packet_length) byte status; - PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME); + PRINTK3("%s:smc_hardware_send_packet\n", dev->name); length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; @@ -437,30 +346,31 @@ static int smc_send_packet (volatile void *packet, int packet_length) numPages >>= 8; /* Divide by 256 */ if (numPages > 7) { - printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); + printf("%s: Far too big packet error. \n", dev->name); return 0; } /* now, try to allocate the memory */ - SMC_SELECT_BANK (2); - SMC_outw (LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU); + SMC_SELECT_BANK(dev, 2); + SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU); again: try++; time_out = MEMORY_WAIT_TIME; do { - status = SMC_inb (LAN91C96_INT_STATS); + status = SMC_inb(dev, LAN91C96_INT_STATS); if (status & LAN91C96_IST_ALLOC_INT) { - SMC_outb (LAN91C96_IST_ALLOC_INT, LAN91C96_INT_STATS); + SMC_outb(dev, LAN91C96_IST_ALLOC_INT, + LAN91C96_INT_STATS); break; } } while (--time_out); if (!time_out) { PRINTK2 ("%s: memory allocation, try %d failed ...\n", - SMC_DEV_NAME, try); + dev->name, try); if (try < SMC_ALLOC_MAX_TRY) goto again; else @@ -468,30 +378,30 @@ static int smc_send_packet (volatile void *packet, int packet_length) } PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", - SMC_DEV_NAME, try); + dev->name, try); /* I can send the packet now.. */ - ioaddr = SMC_BASE_ADDRESS; + ioaddr = dev->iobase; buf = (byte *) packet; /* If I get here, I _know_ there is a packet slot waiting for me */ - packet_no = SMC_inb (LAN91C96_ARR); + packet_no = SMC_inb(dev, LAN91C96_ARR); if (packet_no & LAN91C96_ARR_FAILED) { /* or isn't there? BAD CHIP! */ - printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); + printf("%s: Memory allocation failed. \n", dev->name); return 0; } /* we have a packet address, so tell the card to use it */ - SMC_outb (packet_no, LAN91C96_PNR); + SMC_outb(dev, packet_no, LAN91C96_PNR); /* point to the beginning of the packet */ - SMC_outw (LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); + SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); - PRINTK3 ("%s: Trying to xmit packet of length %x\n", - SMC_DEV_NAME, length); + PRINTK3("%s: Trying to xmit packet of length %x\n", + dev->name, length); #if SMC_DEBUG > 2 printf ("Transmitting Packet\n"); @@ -501,11 +411,11 @@ static int smc_send_packet (volatile void *packet, int packet_length) /* send the packet length ( +6 for status, length and ctl byte ) and the status word ( set to zeros ) */ #ifdef USE_32_BIT - SMC_outl ((length + 6) << 16, LAN91C96_DATA_HIGH); + SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH); #else - SMC_outw (0, LAN91C96_DATA_HIGH); + SMC_outw(dev, 0, LAN91C96_DATA_HIGH); /* send the packet length ( +6 for status words, length, and ctl */ - SMC_outw ((length + 6), LAN91C96_DATA_HIGH); + SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH); #endif /* USE_32_BIT */ /* send the actual data @@ -516,54 +426,52 @@ static int smc_send_packet (volatile void *packet, int packet_length) * almost as much time as is saved? */ #ifdef USE_32_BIT - SMC_outsl (LAN91C96_DATA_HIGH, buf, length >> 2); + SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2); if (length & 0x2) - SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))), LAN91C96_DATA_HIGH); #else - SMC_outsw (LAN91C96_DATA_HIGH, buf, (length) >> 1); + SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1); #endif /* USE_32_BIT */ /* Send the last byte, if there is one. */ if ((length & 1) == 0) { - SMC_outw (0, LAN91C96_DATA_HIGH); + SMC_outw(dev, 0, LAN91C96_DATA_HIGH); } else { - SMC_outw (buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH); + SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH); } /* and let the chipset deal with it */ - SMC_outw (LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU); /* poll for TX INT */ - if (poll4int (LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) { + if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) { /* sending failed */ - PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); + PRINTK2("%s: TX timeout, sending failed...\n", dev->name); /* release packet */ - SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); /* wait for MMU getting ready (low) */ - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (10); - } - PRINTK2 ("MMU ready\n"); + PRINTK2("MMU ready\n"); return 0; } else { /* ack. int */ - SMC_outw (LAN91C96_IST_TX_INT, LAN91C96_INT_STATS); + SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS); - PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length); + PRINTK2("%s: Sent packet of length %d \n", dev->name, length); /* release packet */ - SMC_outw (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU); /* wait for MMU getting ready (low) */ - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) { + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (10); - } PRINTK2 ("MMU ready\n"); } @@ -571,20 +479,6 @@ static int smc_send_packet (volatile void *packet, int packet_length) return length; } -/*------------------------------------------------------------------------- - * smc_destructor( struct net_device * dev ) - * Input parameters: - * dev, pointer to the device structure - * - * Output: - * None. - *-------------------------------------------------------------------------- - */ -void smc_destructor () -{ - PRINTK2 (CARDNAME ":smc_destructor\n"); -} - /* * Open and Initialize the board @@ -592,20 +486,20 @@ void smc_destructor () * Set up everything, reset the card, etc .. * */ -static int smc_open (bd_t *bd) +static int smc_open(bd_t *bd, struct eth_device *dev) { int i, err; /* used to set hw ethernet address */ - PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME); + PRINTK2("%s:smc_open\n", dev->name); /* reset the hardware */ - smc_reset (); - smc_enable (); - - SMC_SELECT_BANK (1); + smc_reset(dev); + smc_enable(dev); - err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ + SMC_SELECT_BANK(dev, 1); + /* set smc_mac_addr, and sync it with u-boot globals */ + err = smc_get_ethaddr(bd, dev); if (err < 0) return -1; #ifdef USE_32_BIT @@ -614,11 +508,11 @@ static int smc_open (bd_t *bd) address = smc_mac_addr[i + 1] << 8; address |= smc_mac_addr[i]; - SMC_outw (address, LAN91C96_IA0 + i); + SMC_outw(dev, address, LAN91C96_IA0 + i); } #else for (i = 0; i < 6; i++) - SMC_outb (smc_mac_addr[i], LAN91C96_IA0 + i); + SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i); #endif return 0; } @@ -635,7 +529,7 @@ static int smc_open (bd_t *bd) * o otherwise, read in the packet *------------------------------------------------------------- */ -static int smc_rcv () +static int smc_rcv(struct eth_device *dev) { int packet_number; word status; @@ -647,26 +541,26 @@ static int smc_rcv () #endif - SMC_SELECT_BANK (2); - packet_number = SMC_inw (LAN91C96_FIFO); + SMC_SELECT_BANK(dev, 2); + packet_number = SMC_inw(dev, LAN91C96_FIFO); if (packet_number & LAN91C96_FIFO_RXEMPTY) { return 0; } - PRINTK3 ("%s:smc_rcv\n", SMC_DEV_NAME); + PRINTK3("%s:smc_rcv\n", dev->name); /* start reading from the start of the packet */ - SMC_outw (LAN91C96_PTR_READ | LAN91C96_PTR_RCV | + SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV | LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER); /* First two words are status and packet_length */ #ifdef USE_32_BIT - stat_len = SMC_inl (LAN91C96_DATA_HIGH); + stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH); status = stat_len & 0xffff; packet_length = stat_len >> 16; #else - status = SMC_inw (LAN91C96_DATA_HIGH); - packet_length = SMC_inw (LAN91C96_DATA_HIGH); + status = SMC_inw(dev, LAN91C96_DATA_HIGH); + packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH); #endif packet_length &= 0x07ff; /* mask off top bits */ @@ -690,13 +584,14 @@ static int smc_rcv () to send the DWORDs or the bytes first, or some mixture. A mixture might improve already slow PIO performance */ - SMC_insl (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 2); + SMC_insl(dev, LAN91C96_DATA_HIGH, NetRxPackets[0], + packet_length >> 2); /* read the left over bytes */ if (packet_length & 3) { int i; byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3)); - dword leftover = SMC_inl (LAN91C96_DATA_HIGH); + dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH); for (i = 0; i < (packet_length & 3); i++) *tail++ = (byte) (leftover >> (8 * i)) & 0xff; @@ -704,13 +599,14 @@ static int smc_rcv () #else PRINTK3 (" Reading %d words and %d byte(s) \n", (packet_length >> 1), packet_length & 1); - SMC_insw (LAN91C96_DATA_HIGH, NetRxPackets[0], packet_length >> 1); + SMC_insw(dev, LAN91C96_DATA_HIGH, NetRxPackets[0], + packet_length >> 1); #endif /* USE_32_BIT */ #if SMC_DEBUG > 2 printf ("Receiving Packet\n"); - print_packet (NetRxPackets[0], packet_length); + print_packet((byte *)NetRxPackets[0], packet_length); #endif } else { /* error ... */ @@ -718,13 +614,13 @@ static int smc_rcv () is_error = 1; } - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (1); /* Wait until not busy */ /* error or good, tell the card to get rid of this packet */ - SMC_outw (LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU); + SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU); - while (SMC_inw (LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) + while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY) udelay (1); /* Wait until not busy */ if (!is_error) { @@ -745,18 +641,18 @@ static int smc_rcv () * an 'ifconfig ethX down' * -----------------------------------------------------*/ -static int smc_close () +static int smc_close(struct eth_device *dev) { - PRINTK2 ("%s:smc_close\n", SMC_DEV_NAME); + PRINTK2("%s:smc_close\n", dev->name); /* clear everything */ - smc_shutdown (); + smc_shutdown(dev); return 0; } #if SMC_DEBUG > 2 -static void print_packet (byte * buf, int length) +static void print_packet(byte *buf, int length) { #if 0 int i; @@ -792,86 +688,40 @@ static void print_packet (byte * buf, int length) } #endif /* SMC_DEBUG > 2 */ -int eth_init (bd_t * bd) -{ - return (smc_open(bd)); -} - -void eth_halt () +static int lan91c96_init(struct eth_device *dev, bd_t *bd) { - smc_close (); + return smc_open(bd, dev); } -int eth_rx () +static void lan91c96_halt(struct eth_device *dev) { - return smc_rcv (); + smc_close(dev); } -int eth_send (volatile void *packet, int length) +static int lan91c96_recv(struct eth_device *dev) { - return smc_send_packet (packet, length); + return smc_rcv(dev); } - -#if 0 -/*------------------------------------------------------------------------- - * smc_hw_init() - * - * Function: - * Reset and enable the device, check if the I/O space location - * is correct - * - * Input parameters: - * None - * - * Output: - * 0 --> success - * 1 --> error - *-------------------------------------------------------------------------- - */ -static int smc_hw_init () +static int lan91c96_send(struct eth_device *dev, volatile void *packet, + int length) { - unsigned short status_test; - - /* The attribute register of the LAN91C96 is located at address - 0x0e000000 on the lubbock platform */ - volatile unsigned *attaddr = (unsigned *) (0x0e000000); - - /* first reset, then enable the device. Sequence is critical */ - attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_SRESET; - udelay (100); - attaddr[LAN91C96_ECOR] &= ~LAN91C96_ECOR_SRESET; - attaddr[LAN91C96_ECOR] |= LAN91C96_ECOR_ENABLE; - - /* force 16-bit mode */ - attaddr[LAN91C96_ECSR] &= ~LAN91C96_ECSR_IOIS8; - udelay (100); - - /* check if the I/O address is correct, the upper byte of the - bank select register should read 0x33 */ - - status_test = SMC_inw (LAN91C96_BANK_SELECT); - if ((status_test & 0xFF00) != 0x3300) { - printf ("Failed to initialize ethernetchip\n"); - return 1; - } - return 0; + return smc_send_packet(dev, packet, length); } -#endif /* 0 */ -/* smc_get_ethaddr (bd_t * bd) +/* smc_get_ethaddr * * This checks both the environment and the ROM for an ethernet address. If * found, the environment takes precedence. */ -int smc_get_ethaddr (bd_t * bd) +static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev) { uchar v_mac[6]; if (!eth_getenv_enetaddr("ethaddr", v_mac)) { /* get ROM mac value if any */ - if (!get_rom_mac(v_mac)) { + if (!get_rom_mac(dev, v_mac)) { printf("\n*** ERROR: ethaddr is NOT set !!\n"); return -1; } @@ -888,7 +738,7 @@ int smc_get_ethaddr (bd_t * bd) * Note, this has omly been tested for the OMAP730 P2. */ -int get_rom_mac (unsigned char *v_rom_mac) +static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac) { #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; @@ -897,11 +747,75 @@ int get_rom_mac (unsigned char *v_rom_mac) return (1); #else int i; - SMC_SELECT_BANK (1); + SMC_SELECT_BANK(dev, 1); for (i=0; i<6; i++) { - v_rom_mac[i] = SMC_inb (LAN91C96_IA0 + i); + v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i); } return (1); #endif } + +/* Structure to detect the device IDs */ +struct id_type { + u8 id; + char *name; +}; +static struct id_type supported_chips[] = { + {0, ""}, /* Dummy entry to prevent id check failure */ + {9, "LAN91C110"}, + {8, "LAN91C100FD"}, + {7, "LAN91C100"}, + {5, "LAN91C95"}, + {4, "LAN91C94/LAN91C96"}, + {3, "LAN91C90/LAN91C92"}, +}; +/* lan91c96_detect_chip + * See: + * http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf + * page 71 - that is the closest we get to detect this device + */ +static int lan91c96_detect_chip(struct eth_device *dev) +{ + u8 chip_id; + int r; + SMC_SELECT_BANK(dev, 3); + chip_id = SMC_inw(dev, 0xA) & LAN91C96_REV_REVID; + SMC_SELECT_BANK(dev, 0); + for (r = 0; r < sizeof(supported_chips) / sizeof(struct id_type); r++) + if (chip_id == supported_chips[r].id) + return r; + return 0; +} + +int lan91c96_initialize(u8 dev_num, int base_addr) +{ + struct eth_device *dev; + int r = 0; + + dev = malloc(sizeof(*dev)); + if (!dev) { + free(dev); + return 0; + } + memset(dev, 0, sizeof(*dev)); + + dev->iobase = base_addr; + + /* Try to detect chip. Will fail if not present. */ + r = lan91c96_detect_chip(dev); + if (!r) { + free(dev); + return 0; + } + get_rom_mac(dev, dev->enetaddr); + + dev->init = lan91c96_init; + dev->halt = lan91c96_halt; + dev->send = lan91c96_send; + dev->recv = lan91c96_recv; + sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num); + + eth_register(dev); + return 0; +} diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h index 5beddda04..6fbb0e3cb 100644 --- a/drivers/net/lan91c96.h +++ b/drivers/net/lan91c96.h @@ -46,14 +46,6 @@ #include #include -/* - * This function may be called by the board specific initialisation code - * in order to override the default mac address. - */ - -void smc_set_mac_addr(const unsigned char *addr); - - /* I want some simple types */ typedef unsigned char byte; @@ -86,66 +78,71 @@ typedef unsigned long int dword; #define SMC_IO_SHIFT 0 #endif -#define SMCREG(r) (SMC_BASE_ADDRESS+((r)<iobase+((r)<>= 8; \ else __v &= 0xff; \ __v; }) -#define SMC_outl(d,r) (*((volatile dword *)SMCREG(r)) = d) -#define SMC_outw(d,r) (*((volatile word *)SMCREG(r)) = d) -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d) +#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d) +#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw(edev, (r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw(edev, __w, (r)&~1); \ }) -#define SMC_outsl(r,b,l) ({ int __i; \ +#define SMC_outsl(edev, r, b, l) ({ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl( *(__b2 + __i), r ); \ + SMC_outl(edev, *(__b2 + __i),\ + r); \ } \ }) -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(edev, r, b, l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r ); \ + SMC_outw(edev, *(__b2 + __i),\ + r); \ } \ }) -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(edev, r, b, l) ({ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl(r); \ - SMC_inl(0); \ + *(__b2 + __i) = SMC_inl(edev,\ + r); \ + SMC_inl(edev, 0); \ }; \ }) -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(edev, r, b, l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw(edev,\ + r); \ + SMC_inw(edev, 0); \ }; \ }) -#define SMC_insb(r,b,l) ({ int __i ; \ +#define SMC_insb(edev, r, b, l) ({ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb(r); \ - SMC_inb(0); \ + *(__b2 + __i) = SMC_inb(edev,\ + r); \ + SMC_inb(edev, 0); \ }; \ }) @@ -155,40 +152,35 @@ typedef unsigned long int dword; * We have only 16 Bit PCMCIA access on Socket 0 */ -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) +#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r)))) +#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\ + SMC_inw(edev, r)&0xFF) -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d) +#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \ + word __w = SMC_inw(edev, (r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw(edev, __w, (r)&~1); \ }) -#if 0 -#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) -#else -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(edev, r, b, l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r); \ + SMC_outw(edev, *(__b2 + __i),\ + r); \ } \ }) -#endif -#if 0 -#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) -#else -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(edev, r, b, l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw(edev,\ + r); \ + SMC_inw(edev, 0); \ }; \ }) -#endif #endif @@ -608,25 +600,25 @@ typedef unsigned long int dword; /* select a register bank, 0 to 3 */ -#define SMC_SELECT_BANK(x) { SMC_outw( x, LAN91C96_BANK_SELECT ); } +#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); } /* this enables an interrupt in the interrupt mask register */ -#define SMC_ENABLE_INT(x) {\ +#define SMC_ENABLE_INT(edev, x) {\ unsigned char mask;\ - SMC_SELECT_BANK(2);\ - mask = SMC_inb( LAN91C96_INT_MASK );\ + SMC_SELECT_BANK(edev, 2);\ + mask = SMC_inb(edev, LAN91C96_INT_MASK);\ mask |= (x);\ - SMC_outb( mask, LAN91C96_INT_MASK ); \ + SMC_outb(edev, mask, LAN91C96_INT_MASK); \ } /* this disables an interrupt from the interrupt mask register */ -#define SMC_DISABLE_INT(x) {\ +#define SMC_DISABLE_INT(edev, x) {\ unsigned char mask;\ - SMC_SELECT_BANK(2);\ - mask = SMC_inb( LAN91C96_INT_MASK );\ + SMC_SELECT_BANK(edev, 2);\ + mask = SMC_inb(edev, LAN91C96_INT_MASK);\ mask &= ~(x);\ - SMC_outb( mask, LAN91C96_INT_MASK ); \ + SMC_outb(edev, mask, LAN91C96_INT_MASK); \ } /*---------------------------------------------------------------------- diff --git a/include/netdev.h b/include/netdev.h index a91368e66..a9d5ec983 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -57,6 +57,7 @@ int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); int inca_switch_initialize(bd_t *bis); int kirkwood_egiga_initialize(bd_t *bis); +int lan91c96_initialize(u8 dev_num, int base_addr); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); int mcdmafec_initialize(bd_t *bis); int mcffec_initialize(bd_t *bis); -- cgit v1.2.3 From 2ab4a4d0952b754b1c74f4d2b12b83d600d449c8 Mon Sep 17 00:00:00 2001 From: Reinhard Arlt Date: Fri, 4 Dec 2009 09:52:17 +0100 Subject: net: e1000: Add support for the Intel 82546GB controller This chip is equipped for example on the esd PMC-ETH2-GB board. So let's add it to the list of supported chips to the e1000 driver. Signed-off-by: Reinhard Arlt Signed-off-by: Stefan Roese Signed-off-by: Ben Warren --- drivers/net/e1000.c | 1 + include/pci_ids.h | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 7f9f783c4..2825342ff 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -79,6 +79,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, diff --git a/include/pci_ids.h b/include/pci_ids.h index d783c5b1a..edfdc1e0a 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1828,6 +1828,7 @@ #define PCI_DEVICE_ID_INTEL_82546EB_COPPER 0x1010 #define PCI_DEVICE_ID_INTEL_82545EM_FIBER 0x1011 #define PCI_DEVICE_ID_INTEL_82546EB_FIBER 0x1012 +#define PCI_DEVICE_ID_INTEL_82546GB_COPPER 0x1079 #define PCI_DEVICE_ID_INTEL_82540EM_LOM 0x1015 #define PCI_DEVICE_ID_INTEL_82545GM_COPPER 0x1026 #define PCI_DEVICE_ID_INTEL_82559 0x1030 -- cgit v1.2.3 From c179a2896e6a5138e30786f1d7961d880dbd6d31 Mon Sep 17 00:00:00 2001 From: John Ogness Date: Fri, 11 Dec 2009 09:47:28 +0100 Subject: fec_mxc: incomplete error handling fec_init() will only allocate fec->base_ptr if it is non-NULL. But the cleanup routine on error will free the pointer without setting it to NULL. This means that a later call to fec_init() would result in using an invalid pointer. Signed-off-by: John Ogness Signed-off-by: Ben Warren --- drivers/net/fec_mxc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ad073077c..19116f253 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -450,6 +450,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) */ if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { free(fec->base_ptr); + fec->base_ptr = NULL; return -ENOMEM; } fec_tbd_init(fec); -- cgit v1.2.3 From 076cd24cb4278c125c8f36df386852dc0fcfefae Mon Sep 17 00:00:00 2001 From: Thomas Weber Date: Wed, 9 Dec 2009 09:38:04 +0100 Subject: net: dm9000x: fix debug output commit 60f61e6d7655400bb785a2ef637581679941f6d1 breaks compile with gcc by introducing __func__ instead of constant string "func" in the macro call but missed to change the macro. Signed-off-by: Thomas Weber Signed-off-by: Ben Warren --- drivers/net/dm9000x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index 73dd33572..a7fef5603 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -75,7 +75,7 @@ TODO: external MII is not functional, only internal at the moment. #define DM9000_DMP_PACKET(func,packet,length) \ do { \ int i; \ - printf(func ": length: %d\n", length); \ + printf("%s: length: %d\n", func, length); \ for (i = 0; i < length; i++) { \ if (i % 8 == 0) \ printf("\n%s: %02x: ", func, i); \ -- cgit v1.2.3 From d02ffbf8d72085035f746c63c2609daf20a84765 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Dec 2009 14:12:11 -0600 Subject: drivers/bios_emulator: Fix compile error in .depend not being generated make -C drivers/bios_emulator/ make[2]: Entering directory `drivers/bios_emulator' In file included from atibios.c:49: biosemui.h:47:21: error: biosemu.h: No such file or directory ... x86emu/decode.c:40:28: error: x86emu/x86emui.h: No such file or directory ... Due to lack of proper CPPFLAGS being passed to .depend generation rule Signed-off-by: Kumar Gala --- drivers/bios_emulator/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index dd9c102ba..feba4da75 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -23,6 +23,7 @@ EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ CFLAGS += $(EXTRA_CFLAGS) HOSTCFLAGS += $(EXTRA_CFLAGS) +CPPFLAGS += $(EXTRA_CFLAGS) all: $(LIB) -- cgit v1.2.3 From 8f8bd565f35ff8a068727bfcf8975c50df082043 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sat, 31 Oct 2009 12:37:38 -0500 Subject: USB Consolidate descriptor definitions The header files usb.h and usbdescriptors.h have the same nameed structure definitions for usb_config_descriptor usb_interface_descriptor usb_endpoint_descriptor usb_device_descriptor usb_string_descriptor These are out right duplicates in usb.h usb_device_descriptor usb_string_descriptor This one has extra unused elements usb_endpoint_descriptor unsigned char bRefresh unsigned char bSynchAddress; These in usb.h have extra elements at the end of the usb 2.0 specified descriptor and are used. usb_config_descriptor usb_interface_descriptor The change is to consolidate the definition of the descriptors to usbdescriptors.h. The dublicates in usb.h are removed. The extra element structure will have their name shorted by removing the '_descriptor' suffix. So usb_config_descriptor -> usb_config usb_interface_descriptor -> usb_interface For these, the common descriptor elements are accessed now by an element 'desc'. As an example - if (iface->bInterfaceClass != USB_CLASS_HUB) + if (iface->desc.bInterfaceClass != USB_CLASS_HUB) This has been compile tested on MAKEALL arm, ppc and mips. Signed-off-by: Tom Rix --- common/cmd_usb.c | 20 ++++++------- common/usb.c | 35 +++++++++++------------ common/usb_kbd.c | 22 ++++++++------ common/usb_storage.c | 16 +++++------ cpu/ppc4xx/usbdev.c | 4 +-- drivers/usb/host/ehci-hcd.c | 2 +- drivers/usb/musb/musb_hcd.c | 2 +- include/usb.h | 70 ++++++--------------------------------------- 8 files changed, 61 insertions(+), 110 deletions(-) (limited to 'drivers') diff --git a/common/cmd_usb.c b/common/cmd_usb.c index 7b8ee6b48..1e297d53d 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -157,7 +157,7 @@ void usb_display_desc(struct usb_device *dev) { if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) { printf("%d: %s, USB Revision %x.%x\n", dev->devnum, - usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass), + usb_get_class_desc(dev->config.if_desc[0].desc.bInterfaceClass), (dev->descriptor.bcdUSB>>8) & 0xff, dev->descriptor.bcdUSB & 0xff); @@ -174,7 +174,7 @@ void usb_display_desc(struct usb_device *dev) } else { printf(" - Class: (from Interface) %s\n", usb_get_class_desc( - dev->config.if_desc[0].bInterfaceClass)); + dev->config.if_desc[0].desc.bInterfaceClass)); } printf(" - PacketSize: %d Configurations: %d\n", dev->descriptor.bMaxPacketSize0, @@ -187,14 +187,14 @@ void usb_display_desc(struct usb_device *dev) } -void usb_display_conf_desc(struct usb_config_descriptor *config, +void usb_display_conf_desc(struct usb_configuration_descriptor *config, struct usb_device *dev) { printf(" Configuration: %d\n", config->bConfigurationValue); printf(" - Interfaces: %d %s%s%dmA\n", config->bNumInterfaces, (config->bmAttributes & 0x40) ? "Self Powered " : "Bus Powered ", (config->bmAttributes & 0x20) ? "Remote Wakeup " : "", - config->MaxPower*2); + config->bMaxPower*2); if (config->iConfiguration) { printf(" - "); usb_display_string(dev, config->iConfiguration); @@ -246,16 +246,16 @@ void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc) /* main routine to diasplay the configs, interfaces and endpoints */ void usb_display_config(struct usb_device *dev) { - struct usb_config_descriptor *config; - struct usb_interface_descriptor *ifdesc; + struct usb_config *config; + struct usb_interface *ifdesc; struct usb_endpoint_descriptor *epdesc; int i, ii; config = &dev->config; - usb_display_conf_desc(config, dev); + usb_display_conf_desc(&config->desc, dev); for (i = 0; i < config->no_of_if; i++) { ifdesc = &config->if_desc[i]; - usb_display_if_desc(ifdesc, dev); + usb_display_if_desc(&ifdesc->desc, dev); for (ii = 0; ii < ifdesc->no_of_ep; ii++) { epdesc = &ifdesc->ep_desc[ii]; usb_display_ep_desc(epdesc); @@ -319,9 +319,9 @@ void usb_show_tree_graph(struct usb_device *dev, char *pre) pre[index++] = has_child ? '|' : ' '; pre[index] = 0; printf(" %s (%s, %dmA)\n", usb_get_class_desc( - dev->config.if_desc[0].bInterfaceClass), + dev->config.if_desc[0].desc.bInterfaceClass), portspeed(dev->speed), - dev->config.MaxPower * 2); + dev->config.desc.bMaxPower * 2); if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial)) printf(" %s %s %s %s\n", pre, dev->mf, dev->prod, dev->serial); printf(" %s\n", pre); diff --git a/common/usb.c b/common/usb.c index 87fca7070..eef4b34a7 100644 --- a/common/usb.c +++ b/common/usb.c @@ -299,8 +299,8 @@ int usb_set_maxpacket(struct usb_device *dev) { int i, ii; - for (i = 0; i < dev->config.bNumInterfaces; i++) - for (ii = 0; ii < dev->config.if_desc[i].bNumEndpoints; ii++) + for (i = 0; i < dev->config.desc.bNumInterfaces; i++) + for (ii = 0; ii < dev->config.if_desc[i].desc.bNumEndpoints; ii++) usb_set_maxpacket_ep(dev, &dev->config.if_desc[i].ep_desc[ii]); @@ -330,14 +330,14 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) return -1; } memcpy(&dev->config, buffer, buffer[0]); - le16_to_cpus(&(dev->config.wTotalLength)); + le16_to_cpus(&(dev->config.desc.wTotalLength)); dev->config.no_of_if = 0; - index = dev->config.bLength; + index = dev->config.desc.bLength; /* Ok the first entry must be a configuration entry, * now process the others */ head = (struct usb_descriptor_header *) &buffer[index]; - while (index + 1 < dev->config.wTotalLength) { + while (index + 1 < dev->config.desc.wTotalLength) { switch (head->bDescriptorType) { case USB_DT_INTERFACE: if (((struct usb_interface_descriptor *) \ @@ -350,7 +350,7 @@ int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno) dev->config.if_desc[ifno].no_of_ep = 0; dev->config.if_desc[ifno].num_altsetting = 1; curr_if_num = - dev->config.if_desc[ifno].bInterfaceNumber; + dev->config.if_desc[ifno].desc.bInterfaceNumber; } else { /* found alternate setting for the interface */ dev->config.if_desc[ifno].num_altsetting++; @@ -440,10 +440,9 @@ int usb_get_configuration_no(struct usb_device *dev, { int result; unsigned int tmp; - struct usb_config_descriptor *config; + struct usb_configuration_descriptor *config; - - config = (struct usb_config_descriptor *)&buffer[0]; + config = (struct usb_configuration_descriptor *)&buffer[0]; result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 9); if (result < 9) { if (result < 0) @@ -489,11 +488,11 @@ int usb_set_address(struct usb_device *dev) */ int usb_set_interface(struct usb_device *dev, int interface, int alternate) { - struct usb_interface_descriptor *if_face = NULL; + struct usb_interface *if_face = NULL; int ret, i; - for (i = 0; i < dev->config.bNumInterfaces; i++) { - if (dev->config.if_desc[i].bInterfaceNumber == interface) { + for (i = 0; i < dev->config.desc.bNumInterfaces; i++) { + if (dev->config.if_desc[i].desc.bInterfaceNumber == interface) { if_face = &dev->config.if_desc[i]; break; } @@ -897,7 +896,7 @@ int usb_new_device(struct usb_device *dev) usb_parse_config(dev, &tmpbuf[0], 0); usb_set_maxpacket(dev); /* we set the default configuration here */ - if (usb_set_configuration(dev, dev->config.bConfigurationValue)) { + if (usb_set_configuration(dev, dev->config.desc.bConfigurationValue)) { printf("failed to set default configuration " \ "len %d, status %lX\n", dev->act_len, dev->status); return -1; @@ -1347,21 +1346,21 @@ int usb_hub_configure(struct usb_device *dev) int usb_hub_probe(struct usb_device *dev, int ifnum) { - struct usb_interface_descriptor *iface; + struct usb_interface *iface; struct usb_endpoint_descriptor *ep; int ret; iface = &dev->config.if_desc[ifnum]; /* Is it a hub? */ - if (iface->bInterfaceClass != USB_CLASS_HUB) + if (iface->desc.bInterfaceClass != USB_CLASS_HUB) return 0; /* Some hubs have a subclass of 1, which AFAICT according to the */ /* specs is not defined, but it works */ - if ((iface->bInterfaceSubClass != 0) && - (iface->bInterfaceSubClass != 1)) + if ((iface->desc.bInterfaceSubClass != 0) && + (iface->desc.bInterfaceSubClass != 1)) return 0; /* Multiple endpoints? What kind of mutant ninja-hub is this? */ - if (iface->bNumEndpoints != 1) + if (iface->desc.bNumEndpoints != 1) return 0; ep = &iface->ep_desc[0]; /* Output endpoint? Curiousier and curiousier.. */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c index b458d7728..9957dcc32 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -229,7 +229,7 @@ int usb_kbd_deregister(void) static void usb_kbd_setled(struct usb_device *dev) { - struct usb_interface_descriptor *iface; + struct usb_interface *iface; iface = &dev->config.if_desc[0]; leds=0; if(scroll_lock!=0) @@ -242,7 +242,7 @@ static void usb_kbd_setled(struct usb_device *dev) leds|=1; usb_control_msg(dev, usb_sndctrlpipe(dev, 0), USB_REQ_SET_REPORT, USB_TYPE_CLASS | USB_RECIP_INTERFACE, - 0x200, iface->bInterfaceNumber,(void *)&leds, 1, 0); + 0x200, iface->desc.bInterfaceNumber, (void *)&leds, 1, 0); } @@ -348,17 +348,21 @@ static int usb_kbd_irq(struct usb_device *dev) /* probes the USB device dev for keyboard type */ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) { - struct usb_interface_descriptor *iface; + struct usb_interface *iface; struct usb_endpoint_descriptor *ep; int pipe,maxp; if (dev->descriptor.bNumConfigurations != 1) return 0; iface = &dev->config.if_desc[ifnum]; - if (iface->bInterfaceClass != 3) return 0; - if (iface->bInterfaceSubClass != 1) return 0; - if (iface->bInterfaceProtocol != 1) return 0; - if (iface->bNumEndpoints != 1) return 0; + if (iface->desc.bInterfaceClass != 3) + return 0; + if (iface->desc.bInterfaceSubClass != 1) + return 0; + if (iface->desc.bInterfaceProtocol != 1) + return 0; + if (iface->desc.bNumEndpoints != 1) + return 0; ep = &iface->ep_desc[0]; @@ -367,9 +371,9 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) USB_KBD_PRINTF("USB KBD found set protocol...\n"); /* ok, we found a USB Keyboard, install it */ /* usb_kbd_get_hid_desc(dev); */ - usb_set_protocol(dev, iface->bInterfaceNumber, 0); + usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0); USB_KBD_PRINTF("USB KBD found set idle...\n"); - usb_set_idle(dev, iface->bInterfaceNumber, REPEAT_RATE, 0); + usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0); memset(&new[0], 0, 8); memset(&old[0], 0, 8); repeat_delay=0; diff --git a/common/usb_storage.c b/common/usb_storage.c index 19613f28c..391948b18 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1070,7 +1070,7 @@ retry_it: int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss) { - struct usb_interface_descriptor *iface; + struct usb_interface *iface; int i; unsigned int flags = 0; @@ -1094,9 +1094,9 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, #endif if (dev->descriptor.bDeviceClass != 0 || - iface->bInterfaceClass != USB_CLASS_MASS_STORAGE || - iface->bInterfaceSubClass < US_SC_MIN || - iface->bInterfaceSubClass > US_SC_MAX) { + iface->desc.bInterfaceClass != USB_CLASS_MASS_STORAGE || + iface->desc.bInterfaceSubClass < US_SC_MIN || + iface->desc.bInterfaceSubClass > US_SC_MAX) { /* if it's not a mass storage, we go no further */ return 0; } @@ -1119,8 +1119,8 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, ss->subclass = subclass; ss->protocol = protocol; } else { - ss->subclass = iface->bInterfaceSubClass; - ss->protocol = iface->bInterfaceProtocol; + ss->subclass = iface->desc.bInterfaceSubClass; + ss->protocol = iface->desc.bInterfaceProtocol; } /* set the handler pointers based on the protocol */ @@ -1153,7 +1153,7 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, * An optional interrupt is OK (necessary for CBI protocol). * We will ignore any others. */ - for (i = 0; i < iface->bNumEndpoints; i++) { + for (i = 0; i < iface->desc.bNumEndpoints; i++) { /* is it an BULK endpoint? */ if ((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) { @@ -1178,7 +1178,7 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, ss->ep_in, ss->ep_out, ss->ep_int); /* Do some basic sanity checks, and bail if we find a problem */ - if (usb_set_interface(dev, iface->bInterfaceNumber, 0) || + if (usb_set_interface(dev, iface->desc.bInterfaceNumber, 0) || !ss->ep_in || !ss->ep_out || (ss->protocol == US_PR_CBI && ss->ep_int == 0)) { USB_STOR_PRINTF("Problems with device\n"); diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index 5bb4f3ce6..fe398afc0 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -21,7 +21,7 @@ void process_endpoints(unsigned short usb2d0_intrin) { /*will hold the packet received */ struct usb_device_descriptor usb_device_packet; - struct usb_config_descriptor usb_config_packet; + struct usb_configuration_descriptor usb_config_packet; struct usb_string_descriptor usb_string_packet; struct devrequest setup_packet; unsigned int *setup_packet_pt; @@ -99,7 +99,7 @@ void process_endpoints(unsigned short usb2d0_intrin) usb_config_packet.bConfigurationValue = 1; usb_config_packet.iConfiguration = 0; usb_config_packet.bmAttributes = 0x40; - usb_config_packet.MaxPower = 0; + usb_config_packet.bMaxPower = 0; /*put packet in fifo */ packet_pt = (unsigned char *)&usb_config_packet; diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 324c308f4..ba85991e8 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -96,7 +96,7 @@ static struct descriptor { * UE_DIR_IN | EHCI_INTR_ENDPT */ 3, /* bmAttributes: UE_INTERRUPT */ - 8, 0, /* wMaxPacketSize */ + 8, /* wMaxPacketSize */ 255 /* bInterval */ }, }; diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 4ca94cb31..555d2dc1b 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -803,7 +803,7 @@ void usb_event_poll() { struct stdio_dev *dev; struct usb_device *usb_kbd_dev; - struct usb_interface_descriptor *iface; + struct usb_interface *iface; struct usb_endpoint_descriptor *ep; int pipe; int maxp; diff --git a/include/usb.h b/include/usb.h index 7c47098d8..4148d67e1 100644 --- a/include/usb.h +++ b/include/usb.h @@ -27,6 +27,7 @@ #define _USB_H_ #include +#include /* Everything is aribtrary */ #define USB_ALTSETTINGALLOC 4 @@ -41,13 +42,6 @@ #define USB_CNTL_TIMEOUT 100 /* 100ms timeout */ -/* String descriptor */ -struct usb_string_descriptor { - unsigned char bLength; - unsigned char bDescriptorType; - unsigned short wData[1]; -} __attribute__ ((packed)); - /* device request (setup) */ struct devrequest { unsigned char requesttype; @@ -63,47 +57,9 @@ struct usb_descriptor_header { unsigned char bDescriptorType; } __attribute__ ((packed)); -/* Device descriptor */ -struct usb_device_descriptor { - unsigned char bLength; - unsigned char bDescriptorType; - unsigned short bcdUSB; - unsigned char bDeviceClass; - unsigned char bDeviceSubClass; - unsigned char bDeviceProtocol; - unsigned char bMaxPacketSize0; - unsigned short idVendor; - unsigned short idProduct; - unsigned short bcdDevice; - unsigned char iManufacturer; - unsigned char iProduct; - unsigned char iSerialNumber; - unsigned char bNumConfigurations; -} __attribute__ ((packed)); - -/* Endpoint descriptor */ -struct usb_endpoint_descriptor { - unsigned char bLength; - unsigned char bDescriptorType; - unsigned char bEndpointAddress; - unsigned char bmAttributes; - unsigned short wMaxPacketSize; - unsigned char bInterval; - unsigned char bRefresh; - unsigned char bSynchAddress; -} __attribute__ ((packed)) __attribute__ ((aligned(2))); - -/* Interface descriptor */ -struct usb_interface_descriptor { - unsigned char bLength; - unsigned char bDescriptorType; - unsigned char bInterfaceNumber; - unsigned char bAlternateSetting; - unsigned char bNumEndpoints; - unsigned char bInterfaceClass; - unsigned char bInterfaceSubClass; - unsigned char bInterfaceProtocol; - unsigned char iInterface; +/* Interface */ +struct usb_interface { + struct usb_interface_descriptor desc; unsigned char no_of_ep; unsigned char num_altsetting; @@ -112,20 +68,12 @@ struct usb_interface_descriptor { struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS]; } __attribute__ ((packed)); - -/* Configuration descriptor information.. */ -struct usb_config_descriptor { - unsigned char bLength; - unsigned char bDescriptorType; - unsigned short wTotalLength; - unsigned char bNumInterfaces; - unsigned char bConfigurationValue; - unsigned char iConfiguration; - unsigned char bmAttributes; - unsigned char MaxPower; +/* Configuration information.. */ +struct usb_config { + struct usb_configuration_descriptor desc; unsigned char no_of_if; /* number of interfaces */ - struct usb_interface_descriptor if_desc[USB_MAXINTERFACES]; + struct usb_interface if_desc[USB_MAXINTERFACES]; } __attribute__ ((packed)); enum { @@ -156,7 +104,7 @@ struct usb_device { int configno; /* selected config number */ struct usb_device_descriptor descriptor; /* Device Descriptor */ - struct usb_config_descriptor config; /* config descriptor */ + struct usb_config config; /* config descriptor */ int have_langid; /* whether string_langid is valid yet */ int string_langid; /* language ID for strings */ -- cgit v1.2.3 From bffbb2a86d2a3aa28bd8f9869aa553082fb5af5f Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sat, 31 Oct 2009 12:37:40 -0500 Subject: TWL4030 Add usb PHY support The twl4030 provides a PHY device for connecting a link device, like musb, to physical connection. This change adds the twl4030 usb registers and functions for initializing the PHY as required by omap3. Signed-off-by: Tom Rix --- Makefile | 1 + drivers/usb/phy/Makefile | 44 +++++++++++ drivers/usb/phy/twl4030.c | 189 ++++++++++++++++++++++++++++++++++++++++++++++ include/twl4030.h | 143 +++++++++++++++++++++++++++++++---- 4 files changed, 362 insertions(+), 15 deletions(-) create mode 100644 drivers/usb/phy/Makefile create mode 100644 drivers/usb/phy/twl4030.c (limited to 'drivers') diff --git a/Makefile b/Makefile index 536ccb3e3..b3ab8b3c1 100644 --- a/Makefile +++ b/Makefile @@ -243,6 +243,7 @@ LIBS += drivers/twserial/libtws.a LIBS += drivers/usb/gadget/libusb_gadget.a LIBS += drivers/usb/host/libusb_host.a LIBS += drivers/usb/musb/libusb_musb.a +LIBS += drivers/usb/phy/libusb_phy.a LIBS += drivers/video/libvideo.a LIBS += drivers/watchdog/libwatchdog.a LIBS += common/libcommon.a diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile new file mode 100644 index 000000000..200b907d9 --- /dev/null +++ b/drivers/usb/phy/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (c) 2009 Wind River Systems, Inc. +# Tom Rix +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libusb_phy.a + +COBJS-$(CONFIG_TWL4030_USB) += twl4030.o +COBJS-y := twl4030.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/usb/phy/twl4030.c b/drivers/usb/phy/twl4030.c new file mode 100644 index 000000000..54d2e615c --- /dev/null +++ b/drivers/usb/phy/twl4030.c @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This is file is based on + * repository git.gitorious.org/u-boot-omap3/mainline.git, + * branch omap3-dev-usb, file drivers/usb/gadget/twl4030_usb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------ + * + * * (C) Copyright 2009 Atin Malaviya (atin.malaviya@gmail.com) + * + * Based on: twl4030_usb.c in linux 2.6 (drivers/i2c/chips/twl4030_usb.c) + * Copyright (C) 2004-2007 Texas Instruments + * Copyright (C) 2008 Nokia Corporation + * Contact: Felipe Balbi + * + * Author: Atin Malaviya (atin.malaviya@gmail.com) + * + * ------------------------------------------------------------------------ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Defines for bits in registers */ +#define OPMODE_MASK (3 << 3) +#define XCVRSELECT_MASK (3 << 0) +#define CARKITMODE (1 << 2) +#define OTG_ENAB (1 << 5) +#define PHYPWD (1 << 0) +#define CLOCKGATING_EN (1 << 2) +#define CLK32K_EN (1 << 1) +#define REQ_PHY_DPLL_CLK (1 << 0) +#define PHY_DPLL_CLK (1 << 0) + +static int twl4030_usb_write(u8 address, u8 data) +{ + int ret; + + ret = twl4030_i2c_write_u8(TWL4030_CHIP_USB, data, address); + if (ret != 0) + printf("TWL4030:USB:Write[0x%x] Error %d\n", address, ret); + + return ret; +} + +static int twl4030_usb_read(u8 address) +{ + u8 data; + int ret; + + ret = twl4030_i2c_read_u8(TWL4030_CHIP_USB, &data, address); + if (ret == 0) + ret = data; + else + printf("TWL4030:USB:Read[0x%x] Error %d\n", address, ret); + + return ret; +} + +static void twl4030_usb_ldo_init(void) +{ + /* Enable writing to power configuration registers */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0xC0, + TWL4030_PM_MASTER_PROTECT_KEY); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x0C, + TWL4030_PM_MASTER_PROTECT_KEY); + + /* put VUSB3V1 LDO in active state */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB_DEDICATED2); + + /* input to VUSB3V1 LDO is from VBAT, not VBUS */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x14, + TWL4030_PM_RECEIVER_VUSB_DEDICATED1); + + /* turn on 3.1V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, + TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB3V1_TYPE); + + /* turn on 1.5V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, + TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB1V5_TYPE); + + /* turn on 1.8V regulator */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x20, + TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, 0x00, + TWL4030_PM_RECEIVER_VUSB1V8_TYPE); + + /* disable access to power configuration registers */ + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, 0x00, + TWL4030_PM_MASTER_PROTECT_KEY); +} + +static void twl4030_phy_power(void) +{ + u8 pwr, clk; + + /* Power the PHY */ + pwr = twl4030_usb_read(TWL4030_USB_PHY_PWR_CTRL); + pwr &= ~PHYPWD; + twl4030_usb_write(TWL4030_USB_PHY_PWR_CTRL, pwr); + /* Enable clocks */ + clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); + clk |= CLOCKGATING_EN | CLK32K_EN; + twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); +} + +/* + * Initiaze the ULPI interface + * ULPI : Universal Transceiver Macrocell Low Pin Interface + * An interface between the USB link controller like musb and the + * the PHY or transceiver that drives the actual bus. + */ +int twl4030_usb_ulpi_init(void) +{ + long timeout = 1000 * 1000; /* 1 sec */; + u8 clk, sts, pwr; + + /* twl4030 ldo init */ + twl4030_usb_ldo_init(); + + /* Enable the twl4030 phy */ + twl4030_phy_power(); + + /* Enable DPLL to access PHY registers over I2C */ + clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); + clk |= REQ_PHY_DPLL_CLK; + twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); + + /* Check if the PHY DPLL is locked */ + sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); + while (!(sts & PHY_DPLL_CLK) && 0 < timeout) { + udelay(10); + sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); + timeout -= 10; + } + + /* Final check */ + sts = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL_STS); + if (!(sts & PHY_DPLL_CLK)) { + printf("Error:TWL4030:USB Timeout setting PHY DPLL clock\n"); + return -1; + } + + /* + * There are two circuit blocks attached to the PHY, + * Carkit and USB OTG. Disable Carkit and enable USB OTG + */ + twl4030_usb_write(TWL4030_USB_IFC_CTRL_CLR, CARKITMODE); + pwr = twl4030_usb_read(TWL4030_USB_POWER_CTRL); + pwr |= OTG_ENAB; + twl4030_usb_write(TWL4030_USB_POWER_CTRL_SET, pwr); + + /* Clear the opmode bits to ensure normal encode */ + twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, OPMODE_MASK); + + /* Clear the xcvrselect bits to enable the high speed transeiver */ + twl4030_usb_write(TWL4030_USB_FUNC_CTRL_CLR, XCVRSELECT_MASK); + + /* Let ULPI control the DPLL clock */ + clk = twl4030_usb_read(TWL4030_USB_PHY_CLK_CTRL); + clk &= ~REQ_PHY_DPLL_CLK; + twl4030_usb_write(TWL4030_USB_PHY_CLK_CTRL, clk); + + return 0; +} diff --git a/include/twl4030.h b/include/twl4030.h index f260ecb8b..feaec47b3 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -342,21 +342,129 @@ #define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0) /* USB */ -#define TWL4030_USB_FUNC_CTRL (0x04) -#define TWL4030_USB_OPMODE_MASK (3 << 3) -#define TWL4030_USB_XCVRSELECT_MASK (3 << 0) -#define TWL4030_USB_IFC_CTRL (0x07) -#define TWL4030_USB_CARKITMODE (1 << 2) -#define TWL4030_USB_POWER_CTRL (0xAC) -#define TWL4030_USB_OTG_ENAB (1 << 5) -#define TWL4030_USB_PHY_PWR_CTRL (0xFD) -#define TWL4030_USB_PHYPWD (1 << 0) -#define TWL4030_USB_PHY_CLK_CTRL (0xFE) -#define TWL4030_USB_CLOCKGATING_EN (1 << 2) -#define TWL4030_USB_CLK32K_EN (1 << 1) -#define TWL4030_USB_REQ_PHY_DPLL_CLK (1 << 0) -#define TWL4030_USB_PHY_CLK_CTRL_STS (0xFF) -#define TWL4030_USB_PHY_DPLL_CLK (1 << 0) +#define TWL4030_USB_VENDOR_ID_LO 0x00 +#define TWL4030_USB_VENDOR_ID_HI 0x01 +#define TWL4030_USB_PRODUCT_ID_LO 0x02 +#define TWL4030_USB_PRODUCT_ID_HI 0x03 +#define TWL4030_USB_FUNC_CTRL 0x04 +#define TWL4030_USB_FUNC_CTRL_SET 0x05 +#define TWL4030_USB_FUNC_CTRL_CLR 0x06 +#define TWL4030_USB_IFC_CTRL 0x07 +#define TWL4030_USB_IFC_CTRL_SET 0x08 +#define TWL4030_USB_IFC_CTRL_CLR 0x09 +#define TWL4030_USB_OTG_CTRL 0x0A +#define TWL4030_USB_OTG_CTRL_SET 0x0B +#define TWL4030_USB_OTG_CTRL_CLR 0x0C +#define TWL4030_USB_USB_INT_EN_RISE 0x0D +#define TWL4030_USB_USB_INT_EN_RISE_SET 0x0E +#define TWL4030_USB_USB_INT_EN_RISE_CLR 0x0F +#define TWL4030_USB_USB_INT_EN_FALL 0x10 +#define TWL4030_USB_USB_INT_EN_FALL_SET 0x11 +#define TWL4030_USB_USB_INT_EN_FALL_CLR 0x12 +#define TWL4030_USB_USB_INT_STS 0x13 +#define TWL4030_USB_USB_INT_LATCH 0x14 +#define TWL4030_USB_DEBUG 0x15 +#define TWL4030_USB_SCRATCH_REG 0x16 +#define TWL4030_USB_SCRATCH_REG_SET 0x17 +#define TWL4030_USB_SCRATCH_REG_CLR 0x18 +#define TWL4030_USB_CARKIT_CTRL 0x19 +#define TWL4030_USB_CARKIT_CTRL_SET 0x1A +#define TWL4030_USB_CARKIT_CTRL_CLR 0x1B +#define TWL4030_USB_CARKIT_INT_DELAY 0x1C +#define TWL4030_USB_CARKIT_INT_EN 0x1D +#define TWL4030_USB_CARKIT_INT_EN_SET 0x1E +#define TWL4030_USB_CARKIT_INT_EN_CLR 0x1F +#define TWL4030_USB_CARKIT_INT_STS 0x20 +#define TWL4030_USB_CARKIT_INT_LATCH 0x21 +#define TWL4030_USB_CARKIT_PLS_CTRL 0x22 +#define TWL4030_USB_CARKIT_PLS_CTRL_SET 0x23 +#define TWL4030_USB_CARKIT_PLS_CTRL_CLR 0x24 +#define TWL4030_USB_TRANS_POS_WIDTH 0x25 +#define TWL4030_USB_TRANS_NEG_WIDTH 0x26 +#define TWL4030_USB_RCV_PLTY_RECOVERY 0x27 +#define TWL4030_USB_MCPC_CTRL 0x30 +#define TWL4030_USB_MCPC_CTRL_SET 0x31 +#define TWL4030_USB_MCPC_CTRL_CLR 0x32 +#define TWL4030_USB_MCPC_IO_CTRL 0x33 +#define TWL4030_USB_MCPC_IO_CTRL_SET 0x34 +#define TWL4030_USB_MCPC_IO_CTRL_CLR 0x35 +#define TWL4030_USB_MCPC_CTRL2 0x36 +#define TWL4030_USB_MCPC_CTRL2_SET 0x37 +#define TWL4030_USB_MCPC_CTRL2_CLR 0x38 +#define TWL4030_USB_OTHER_FUNC_CTRL 0x80 +#define TWL4030_USB_OTHER_FUNC_CTRL_SET 0x81 +#define TWL4030_USB_OTHER_FUNC_CTRL_CLR 0x82 +#define TWL4030_USB_OTHER_IFC_CTRL 0x83 +#define TWL4030_USB_OTHER_IFC_CTRL_SET 0x84 +#define TWL4030_USB_OTHER_IFC_CTRL_CLR 0x85 +#define TWL4030_USB_OTHER_INT_EN_RISE_SET 0x87 +#define TWL4030_USB_OTHER_INT_EN_RISE_CLR 0x88 +#define TWL4030_USB_OTHER_INT_EN_FALL 0x89 +#define TWL4030_USB_OTHER_INT_EN_FALL_SET 0x8A +#define TWL4030_USB_OTHER_INT_EN_FALL_CLR 0x8B +#define TWL4030_USB_OTHER_INT_STS 0x8C +#define TWL4030_USB_OTHER_INT_LATCH 0x8D +#define TWL4030_USB_ID_STATUS 0x96 +#define TWL4030_USB_CARKIT_SM_1_INT_EN 0x97 +#define TWL4030_USB_CARKIT_SM_1_INT_EN_SET 0x98 +#define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR 0x99 +#define TWL4030_USB_CARKIT_SM_1_INT_STS 0x9A +#define TWL4030_USB_CARKIT_SM_1_INT_LATCH 0x9B +#define TWL4030_USB_CARKIT_SM_2_INT_EN 0x9C +#define TWL4030_USB_CARKIT_SM_2_INT_EN_SET 0x9D +#define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR 0x9E +#define TWL4030_USB_CARKIT_SM_2_INT_STS 0x9F +#define TWL4030_USB_CARKIT_SM_2_INT_LATCH 0xA0 +#define TWL4030_USB_CARKIT_SM_CTRL 0xA1 +#define TWL4030_USB_CARKIT_SM_CTRL_SET 0xA2 +#define TWL4030_USB_CARKIT_SM_CTRL_CLR 0xA3 +#define TWL4030_USB_CARKIT_SM_CMD 0xA4 +#define TWL4030_USB_CARKIT_SM_CMD_SET 0xA5 +#define TWL4030_USB_CARKIT_SM_CMD_CLR 0xA6 +#define TWL4030_USB_CARKIT_SM_CMD_STS 0xA7 +#define TWL4030_USB_CARKIT_SM_STATUS 0xA8 +#define TWL4030_USB_CARKIT_SM_ERR_STATUS 0xAA +#define TWL4030_USB_CARKIT_SM_CTRL_STATE 0xAB +#define TWL4030_USB_POWER_CTRL 0xAC +#define TWL4030_USB_POWER_CTRL_SET 0xAD +#define TWL4030_USB_POWER_CTRL_CLR 0xAE +#define TWL4030_USB_OTHER_IFC_CTRL2 0xAF +#define TWL4030_USB_OTHER_IFC_CTRL2_SET 0xB0 +#define TWL4030_USB_OTHER_IFC_CTRL2_CLR 0xB1 +#define TWL4030_USB_REG_CTRL_EN 0xB2 +#define TWL4030_USB_REG_CTRL_EN_SET 0xB3 +#define TWL4030_USB_REG_CTRL_EN_CLR 0xB4 +#define TWL4030_USB_REG_CTRL_ERROR 0xB5 +#define TWL4030_USB_OTHER_FUNC_CTRL2 0xB8 +#define TWL4030_USB_OTHER_FUNC_CTRL2_SET 0xB9 +#define TWL4030_USB_OTHER_FUNC_CTRL2_CLR 0xBA +#define TWL4030_USB_CARKIT_ANA_CTRL 0xBB +#define TWL4030_USB_CARKIT_ANA_CTRL_SET 0xBC +#define TWL4030_USB_CARKIT_ANA_CTRL_CLR 0xBD +#define TWL4030_USB_VBUS_DEBOUNCE 0xC0 +#define TWL4030_USB_ID_DEBOUNCE 0xC1 +#define TWL4030_USB_TPH_DP_CON_MIN 0xC2 +#define TWL4030_USB_TPH_DP_CON_MAX 0xC3 +#define TWL4030_USB_TCR_DP_CON_MIN 0xC4 +#define TWL4030_USB_TCR_DP_CON_MAX 0xC5 +#define TWL4030_USB_TPH_DP_PD_SHORT 0xC6 +#define TWL4030_USB_TPH_CMD_DLY 0xC7 +#define TWL4030_USB_TPH_DET_RST 0xC8 +#define TWL4030_USB_TPH_AUD_BIAS 0xC9 +#define TWL4030_USB_TCR_UART_DET_MIN 0xCA +#define TWL4030_USB_TCR_UART_DET_MAX 0xCB +#define TWL4030_USB_TPH_ID_INT_PW 0xCD +#define TWL4030_USB_TACC_ID_INT_WAIT 0xCE +#define TWL4030_USB_TACC_ID_INT_PW 0xCF +#define TWL4030_USB_TPH_CMD_WAIT 0xD0 +#define TWL4030_USB_TPH_ACK_WAIT 0xD1 +#define TWL4030_USB_TPH_DP_DISC_DET 0xD2 +#define TWL4030_USB_VBAT_TIMER 0xD3 +#define TWL4030_USB_CARKIT_4W_DEBUG 0xE0 +#define TWL4030_USB_CARKIT_5W_DEBUG 0xE1 +#define TWL4030_USB_PHY_PWR_CTRL 0xFD +#define TWL4030_USB_PHY_CLK_CTRL 0xFE +#define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF /* * Convience functions to read and write from TWL4030 @@ -398,4 +506,9 @@ void twl4030_power_mmc_init(void); */ void twl4030_led_init(void); +/* + * USB + */ +int twl4030_usb_ulpi_init(void); + #endif /* TWL4030_H */ -- cgit v1.2.3 From f298e4b6dd56df3e35a13a6ddd572ca3baf06ad2 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sat, 31 Oct 2009 12:37:41 -0500 Subject: OMAP3 Add usb device support This change adds the usb device support for musb. Omap3 platform support added at the same level as davinci. The interface for usbtty to use the musb device support was added. Verified on omap3 beagle, zoom1 and zoom2. Signed-off-by: Tom Rix --- drivers/serial/usbtty.h | 2 + drivers/usb/musb/Makefile | 2 + drivers/usb/musb/musb_core.c | 8 +- drivers/usb/musb/musb_core.h | 40 ++ drivers/usb/musb/musb_debug.h | 205 +++++++++ drivers/usb/musb/musb_udc.c | 963 ++++++++++++++++++++++++++++++++++++++++++ drivers/usb/musb/omap3.c | 129 ++++++ drivers/usb/musb/omap3.h | 48 +++ include/usb.h | 3 +- include/usb/musb_udc.h | 54 +++ 10 files changed, 1451 insertions(+), 3 deletions(-) create mode 100644 drivers/usb/musb/musb_debug.h create mode 100644 drivers/usb/musb/musb_udc.c create mode 100644 drivers/usb/musb/omap3.c create mode 100644 drivers/usb/musb/omap3.h create mode 100644 include/usb/musb_udc.h (limited to 'drivers') diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index f746d6317..6b6c4a162 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -29,6 +29,8 @@ #include #elif defined(CONFIG_OMAP1510) #include +#elif defined(CONFIG_MUSB_UDC) +#include #elif defined(CONFIG_PXA27X) #include #endif diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile index 09e0a5f32..f2ccd9fe0 100644 --- a/drivers/usb/musb/Makefile +++ b/drivers/usb/musb/Makefile @@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_musb.a COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o +COBJS-$(CONFIG_MUSB_UDC) += musb_udc.o musb_core.o COBJS-$(CONFIG_USB_DAVINCI) += davinci.o +COBJS-$(CONFIG_USB_OMAP3) += omap3.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c index ec57fc811..22f3dba0c 100644 --- a/drivers/usb/musb/musb_core.c +++ b/drivers/usb/musb/musb_core.c @@ -32,7 +32,9 @@ struct musb_regs *musbr; */ void musb_start(void) { +#if defined(CONFIG_MUSB_HCD) u8 devctl; +#endif /* disable all interrupts */ writew(0, &musbr->intrtxe); @@ -74,9 +76,10 @@ void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) /* Configure fifo size and fifo base address */ writeb(idx, &musbr->txfifosz); writew(fifoaddr >> 3, &musbr->txfifoadd); + + csr = readw(&musbr->txcsr); #if defined(CONFIG_MUSB_HCD) /* clear the data toggle bit */ - csr = readw(&musbr->txcsr); writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); #endif /* Flush fifo if required */ @@ -87,9 +90,10 @@ void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) /* Configure fifo size and fifo base address */ writeb(idx, &musbr->rxfifosz); writew(fifoaddr >> 3, &musbr->rxfifoadd); + + csr = readw(&musbr->rxcsr); #if defined(CONFIG_MUSB_HCD) /* clear the data toggle bit */ - csr = readw(&musbr->rxcsr); writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); #endif /* Flush fifo if required */ diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index f9da3f0b2..15c7f49a3 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -40,6 +40,36 @@ #define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ +/* EP0 */ +struct musb_ep0_regs { + u16 reserved4; + u16 csr0; + u16 reserved5; + u16 reserved6; + u16 count0; + u8 host_type0; + u8 host_naklimit0; + u8 reserved7; + u8 reserved8; + u8 reserved9; + u8 configdata; +}; + +/* EP 1-15 */ +struct musb_epN_regs { + u16 txmaxp; + u16 txcsr; + u16 rxmaxp; + u16 rxcsr; + u16 rxcount; + u8 txtype; + u8 txinterval; + u8 rxtype; + u8 rxinterval; + u8 reserved0; + u8 fifosize; +}; + /* Mentor USB core register overlay structure */ struct musb_regs { /* common registers */ @@ -97,6 +127,16 @@ struct musb_regs { u8 rxhubaddr; u8 rxhubport; } tar[16]; + /* + * end point registers + * ep0 elements are valid when array index is 0 + * otherwise epN is valid + */ + union musb_ep_regs { + struct musb_ep0_regs ep0; + struct musb_epN_regs epN; + } ep[16]; + } __attribute__((aligned(32))); /* diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h new file mode 100644 index 000000000..62380ffc6 --- /dev/null +++ b/drivers/usb/musb/musb_debug.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Define MUSB_DEBUG before including this file to get debug macros */ +#ifdef MUSB_DEBUG + +#define MUSB_FLAGS_PRINT(v, x, y) \ + if (((v) & MUSB_##x##_##y)) \ + serial_printf("\t\t"#y"\n") + +static inline void musb_print_pwr(u8 b) +{ + serial_printf("\tpower 0x%2.2x\n", b); + MUSB_FLAGS_PRINT(b, POWER, ISOUPDATE); + MUSB_FLAGS_PRINT(b, POWER, SOFTCONN); + MUSB_FLAGS_PRINT(b, POWER, HSENAB); + MUSB_FLAGS_PRINT(b, POWER, HSMODE); + MUSB_FLAGS_PRINT(b, POWER, RESET); + MUSB_FLAGS_PRINT(b, POWER, RESUME); + MUSB_FLAGS_PRINT(b, POWER, SUSPENDM); + MUSB_FLAGS_PRINT(b, POWER, ENSUSPEND); +} + +static inline void musb_print_csr0(u16 w) +{ + serial_printf("\tcsr0 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, CSR0, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, CSR0_P, SVDSETUPEND); + MUSB_FLAGS_PRINT(w, CSR0_P, SVDRXPKTRDY); + MUSB_FLAGS_PRINT(w, CSR0_P, SENDSTALL); + MUSB_FLAGS_PRINT(w, CSR0_P, SETUPEND); + MUSB_FLAGS_PRINT(w, CSR0_P, DATAEND); + MUSB_FLAGS_PRINT(w, CSR0_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, CSR0, TXPKTRDY); + MUSB_FLAGS_PRINT(w, CSR0, RXPKTRDY); +} + +static inline void musb_print_intrusb(u8 b) +{ + serial_printf("\tintrusb 0x%2.2x\n", b); + MUSB_FLAGS_PRINT(b, INTR, VBUSERROR); + MUSB_FLAGS_PRINT(b, INTR, SESSREQ); + MUSB_FLAGS_PRINT(b, INTR, DISCONNECT); + MUSB_FLAGS_PRINT(b, INTR, CONNECT); + MUSB_FLAGS_PRINT(b, INTR, SOF); + MUSB_FLAGS_PRINT(b, INTR, RESUME); + MUSB_FLAGS_PRINT(b, INTR, SUSPEND); + + if (b & MUSB_INTR_BABBLE) + serial_printf("\t\tMUSB_INTR_RESET or MUSB_INTR_BABBLE\n"); + +} + +static inline void musb_print_intrtx(u16 w) +{ + serial_printf("\tintrtx 0x%4.4x\n", w); +} + +static inline void musb_print_intrrx(u16 w) +{ + serial_printf("\tintrx 0x%4.4x\n", w); +} + +static inline void musb_print_devctl(u8 b) +{ + serial_printf("\tdevctl 0x%2.2x\n", b); + if (b & MUSB_DEVCTL_BDEVICE) + serial_printf("\t\tB device\n"); + else + serial_printf("\t\tA device\n"); + if (b & MUSB_DEVCTL_FSDEV) + serial_printf("\t\tFast Device -(host mode)\n"); + if (b & MUSB_DEVCTL_LSDEV) + serial_printf("\t\tSlow Device -(host mode)\n"); + if (b & MUSB_DEVCTL_HM) + serial_printf("\t\tHost mode\n"); + else + serial_printf("\t\tPeripherial mode\n"); + if (b & MUSB_DEVCTL_HR) + serial_printf("\t\tHost request started(B device)\n"); + else + serial_printf("\t\tHost request finished(B device)\n"); + if (b & MUSB_DEVCTL_BDEVICE) { + if (b & MUSB_DEVCTL_SESSION) + serial_printf("\t\tStart of session(B device)\n"); + else + serial_printf("\t\tEnd of session(B device)\n"); + } else { + if (b & MUSB_DEVCTL_SESSION) + serial_printf("\t\tStart of session(A device)\n"); + else + serial_printf("\t\tEnd of session(A device)\n"); + } +} + +static inline void musb_print_config(u8 b) +{ + serial_printf("\tconfig 0x%2.2x\n", b); + if (b & MUSB_CONFIGDATA_MPRXE) + serial_printf("\t\tAuto combine rx bulk packets\n"); + if (b & MUSB_CONFIGDATA_MPTXE) + serial_printf("\t\tAuto split tx bulk packets\n"); + if (b & MUSB_CONFIGDATA_BIGENDIAN) + serial_printf("\t\tBig Endian ordering\n"); + else + serial_printf("\t\tLittle Endian ordering\n"); + if (b & MUSB_CONFIGDATA_HBRXE) + serial_printf("\t\tHigh speed rx iso endpoint\n"); + if (b & MUSB_CONFIGDATA_HBTXE) + serial_printf("\t\tHigh speed tx iso endpoint\n"); + if (b & MUSB_CONFIGDATA_DYNFIFO) + serial_printf("\t\tDynamic fifo sizing\n"); + if (b & MUSB_CONFIGDATA_SOFTCONE) + serial_printf("\t\tSoft Connect\n"); + if (b & MUSB_CONFIGDATA_UTMIDW) + serial_printf("\t\t16 bit data width\n"); + else + serial_printf("\t\t8 bit data width\n"); +} + +static inline void musb_print_rxmaxp(u16 w) +{ + serial_printf("\trxmaxp 0x%4.4x\n", w); +} + +static inline void musb_print_rxcsr(u16 w) +{ + serial_printf("\trxcsr 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, RXCSR, AUTOCLEAR); + MUSB_FLAGS_PRINT(w, RXCSR, DMAENAB); + MUSB_FLAGS_PRINT(w, RXCSR, DISNYET); + MUSB_FLAGS_PRINT(w, RXCSR, PID_ERR); + MUSB_FLAGS_PRINT(w, RXCSR, DMAMODE); + MUSB_FLAGS_PRINT(w, RXCSR, CLRDATATOG); + MUSB_FLAGS_PRINT(w, RXCSR, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, RXCSR, DATAERROR); + MUSB_FLAGS_PRINT(w, RXCSR, FIFOFULL); + MUSB_FLAGS_PRINT(w, RXCSR, RXPKTRDY); + MUSB_FLAGS_PRINT(w, RXCSR_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, RXCSR_P, SENDSTALL); + MUSB_FLAGS_PRINT(w, RXCSR_P, OVERRUN); + + if (w & MUSB_RXCSR_P_ISO) + serial_printf("\t\tiso mode\n"); + else + serial_printf("\t\tbulk mode\n"); + +} + +static inline void musb_print_txmaxp(u16 w) +{ + serial_printf("\ttxmaxp 0x%4.4x\n", w); +} + +static inline void musb_print_txcsr(u16 w) +{ + serial_printf("\ttxcsr 0x%4.4x\n", w); + MUSB_FLAGS_PRINT(w, TXCSR, TXPKTRDY); + MUSB_FLAGS_PRINT(w, TXCSR, FIFONOTEMPTY); + MUSB_FLAGS_PRINT(w, TXCSR, FLUSHFIFO); + MUSB_FLAGS_PRINT(w, TXCSR, CLRDATATOG); + MUSB_FLAGS_PRINT(w, TXCSR_P, UNDERRUN); + MUSB_FLAGS_PRINT(w, TXCSR_P, SENTSTALL); + MUSB_FLAGS_PRINT(w, TXCSR_P, SENDSTALL); + + if (w & MUSB_TXCSR_MODE) + serial_printf("\t\tTX mode\n"); + else + serial_printf("\t\tRX mode\n"); +} + +#else + +/* stubs */ + +#define musb_print_pwr(b) +#define musb_print_csr0(w) +#define musb_print_intrusb(b) +#define musb_print_intrtx(w) +#define musb_print_intrrx(w) +#define musb_print_devctl(b) +#define musb_print_config(b) +#define musb_print_rxmaxp(w) +#define musb_print_rxcsr(w) +#define musb_print_txmaxp(w) +#define musb_print_txcsr(w) + +#endif /* MUSB_DEBUG */ diff --git a/drivers/usb/musb/musb_udc.c b/drivers/usb/musb/musb_udc.c new file mode 100644 index 000000000..fc43cf4f0 --- /dev/null +++ b/drivers/usb/musb/musb_udc.c @@ -0,0 +1,963 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This file is a rewrite of the usb device part of + * repository git.omapzoom.org/repo/u-boot.git, branch master, + * file cpu/omap3/fastboot.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------- + * + * (C) Copyright 2008 - 2009 + * Windriver, + * Tom Rix + * + * ------------------------------------------------------------------------- + * + * The details of connecting the device to the uboot usb device subsystem + * came from the old omap3 repository www.sakoman.net/u-boot-omap3.git, + * branch omap3-dev-usb, file drivers/usb/usbdcore_musb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------- + * + * (C) Copyright 2008 Texas Instruments Incorporated. + * + * Based on + * u-boot OMAP1510 USB drivers (drivers/usbdcore_omap1510.c) + * twl4030 init based on linux (drivers/i2c/chips/twl4030_usb.c) + * + * Author: Diego Dompe (diego.dompe@ridgerun.com) + * Atin Malaviya (atin.malaviya@gmail.com) + * + * ------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include "../gadget/ep0.h" +#include "musb_core.h" +#if defined(CONFIG_USB_OMAP3) +#include "omap3.h" +#elif defined(CONFIG_USB_DAVINCI) +#include "davinci.h" +#endif + +/* Define MUSB_DEBUG for debugging */ +/* #define MUSB_DEBUG */ +#include "musb_debug.h" + +#define MAX_ENDPOINT 15 + +#define GET_ENDPOINT(dev,ep) \ +(((struct usb_device_instance *)(dev))->bus->endpoint_array + ep) + +#define SET_EP0_STATE(s) \ +do { \ + if ((0 <= (s)) && (SET_ADDRESS >= (s))) { \ + if ((s) != ep0_state) { \ + if ((debug_setup) && (debug_level > 1)) \ + serial_printf("INFO : Changing state " \ + "from %s to %s in %s at " \ + "line %d\n", \ + ep0_state_strings[ep0_state],\ + ep0_state_strings[s], \ + __PRETTY_FUNCTION__, \ + __LINE__); \ + ep0_state = s; \ + } \ + } else { \ + if (debug_level > 0) \ + serial_printf("Error at %s %d with setting " \ + "state %d is invalid\n", \ + __PRETTY_FUNCTION__, __LINE__, s); \ + } \ +} while (0) + +/* static implies these initialized to 0 or NULL */ +static int debug_setup; +static int debug_level; +static struct musb_epinfo epinfo[MAX_ENDPOINT * 2]; +static enum ep0_state_enum { + IDLE = 0, + TX, + RX, + SET_ADDRESS +} ep0_state = IDLE; +static char *ep0_state_strings[4] = { + "IDLE", + "TX", + "RX", + "SET_ADDRESS", +}; + +static struct urb *ep0_urb; +struct usb_endpoint_instance *ep0_endpoint; +static struct usb_device_instance *udc_device; +static int enabled; + +#ifdef MUSB_DEBUG +static void musb_db_regs(void) +{ + u8 b; + u16 w; + + b = readb(&musbr->faddr); + serial_printf("\tfaddr 0x%2.2x\n", b); + + b = readb(&musbr->power); + musb_print_pwr(b); + + w = readw(&musbr->ep[0].ep0.csr0); + musb_print_csr0(w); + + b = readb(&musbr->devctl); + musb_print_devctl(b); + + b = readb(&musbr->ep[0].ep0.configdata); + musb_print_config(b); + + w = readw(&musbr->frame); + serial_printf("\tframe 0x%4.4x\n", w); + + b = readb(&musbr->index); + serial_printf("\tindex 0x%2.2x\n", b); + + w = readw(&musbr->ep[1].epN.rxmaxp); + musb_print_rxmaxp(w); + + w = readw(&musbr->ep[1].epN.rxcsr); + musb_print_rxcsr(w); + + w = readw(&musbr->ep[1].epN.txmaxp); + musb_print_txmaxp(w); + + w = readw(&musbr->ep[1].epN.txcsr); + musb_print_txcsr(w); +} +#else +#define musb_db_regs() +#endif /* DEBUG_MUSB */ + +static void musb_peri_softconnect(void) +{ + u8 power, devctl; + u8 intrusb; + u16 intrrx, intrtx; + + /* Power off MUSB */ + power = readb(&musbr->power); + power &= ~MUSB_POWER_SOFTCONN; + writeb(power, &musbr->power); + + /* Read intr to clear */ + intrusb = readb(&musbr->intrusb); + intrrx = readw(&musbr->intrrx); + intrtx = readw(&musbr->intrtx); + + udelay(1000 * 1000); /* 1 sec */ + + /* Power on MUSB */ + power = readb(&musbr->power); + power |= MUSB_POWER_SOFTCONN; + /* + * The usb device interface is usb 1.1 + * Disable 2.0 high speed by clearring the hsenable bit. + */ + power &= ~MUSB_POWER_HSENAB; + writeb(power, &musbr->power); + + /* Check if device is in b-peripheral mode */ + devctl = readb(&musbr->devctl); + if (!(devctl & MUSB_DEVCTL_BDEVICE) || + (devctl & MUSB_DEVCTL_HM)) { + serial_printf("ERROR : Unsupport USB mode\n"); + serial_printf("Check that mini-B USB cable is attached " + "to the device\n"); + } + + if (debug_setup && (debug_level > 1)) + musb_db_regs(); +} + +static void musb_peri_reset(void) +{ + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s reset\n", __PRETTY_FUNCTION__); + + if (ep0_endpoint) + ep0_endpoint->endpoint_address = 0xff; + + /* Sync sw and hw addresses */ + writeb(udc_device->address, &musbr->faddr); + + SET_EP0_STATE(IDLE); +} + +static void musb_peri_resume(void) +{ + /* noop */ +} + +static void musb_peri_ep0_stall(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_SENDSTALL; + writew(csr0, &musbr->ep[0].ep0.csr0); + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s stall\n", __PRETTY_FUNCTION__); +} + +static void musb_peri_ep0_ack_req(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_SVDRXPKTRDY; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_ep0_tx_ready(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_TXPKTRDY; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_ep0_tx_ready_and_last(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_P_DATAEND); + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_peri_ep0_last(void) +{ + u16 csr0; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + csr0 |= MUSB_CSR0_P_DATAEND; + writew(csr0, &musbr->ep[0].ep0.csr0); +} + +static void musb_peri_ep0_set_address(void) +{ + u8 faddr; + writeb(udc_device->address, &musbr->faddr); + + /* Verify */ + faddr = readb(&musbr->faddr); + if (udc_device->address == faddr) { + SET_EP0_STATE(IDLE); + usbd_device_event_irq(udc_device, DEVICE_ADDRESS_ASSIGNED, 0); + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s Address set to %d\n", + __PRETTY_FUNCTION__, udc_device->address); + } else { + if (debug_level > 0) + serial_printf("ERROR : %s Address missmatch " + "sw %d vs hw %d\n", + __PRETTY_FUNCTION__, + udc_device->address, faddr); + } +} + +static void musb_peri_rx_ack(unsigned int ep) +{ + u16 peri_rxcsr; + + peri_rxcsr = readw(&musbr->ep[ep].epN.rxcsr); + peri_rxcsr &= ~MUSB_RXCSR_RXPKTRDY; + writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr); +} + +static void musb_peri_tx_ready(unsigned int ep) +{ + u16 peri_txcsr; + + peri_txcsr = readw(&musbr->ep[ep].epN.txcsr); + peri_txcsr |= MUSB_TXCSR_TXPKTRDY; + writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); +} + +static void musb_peri_ep0_zero_data_request(int err) +{ + musb_peri_ep0_ack_req(); + + if (err) { + musb_peri_ep0_stall(); + SET_EP0_STATE(IDLE); + } else { + + musb_peri_ep0_last(); + + /* USBD state */ + switch (ep0_urb->device_request.bRequest) { + case USB_REQ_SET_ADDRESS: + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s received set " + "address\n", __PRETTY_FUNCTION__); + break; + + case USB_REQ_SET_CONFIGURATION: + if ((debug_setup) && (debug_level > 1)) + serial_printf("INFO : %s Configured\n", + __PRETTY_FUNCTION__); + usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0); + break; + } + + /* EP0 state */ + if (USB_REQ_SET_ADDRESS == ep0_urb->device_request.bRequest) { + SET_EP0_STATE(SET_ADDRESS); + } else { + SET_EP0_STATE(IDLE); + } + } +} + +static void musb_peri_ep0_rx_data_request(void) +{ + /* + * This is the completion of the data OUT / RX + * + * Host is sending data to ep0 that is not + * part of setup. This comes from the cdc_recv_setup + * op that is device specific. + * + */ + musb_peri_ep0_ack_req(); + + ep0_endpoint->rcv_urb = ep0_urb; + ep0_urb->actual_length = 0; + SET_EP0_STATE(RX); +} + +static void musb_peri_ep0_tx_data_request(int err) +{ + if (err) { + musb_peri_ep0_stall(); + SET_EP0_STATE(IDLE); + } else { + musb_peri_ep0_ack_req(); + + ep0_endpoint->tx_urb = ep0_urb; + ep0_endpoint->sent = 0; + SET_EP0_STATE(TX); + } +} + +static void musb_peri_ep0_idle(void) +{ + u16 count0; + int err; + u16 csr0; + + /* + * Verify addresses + * A lot of confusion can be caused if the address + * in software, udc layer, does not agree with the + * hardware. Since the setting of the hardware address + * must be set after the set address request, the + * usb state machine is out of sync for a few frame. + * It is a good idea to run this check when changes + * are made to the state machine. + */ + if ((debug_level > 0) && + (ep0_state != SET_ADDRESS)) { + u8 faddr; + + faddr = readb(&musbr->faddr); + if (udc_device->address != faddr) { + serial_printf("ERROR : %s addresses do not" + "match sw %d vs hw %d\n", + __PRETTY_FUNCTION__, + udc_device->address, faddr); + udelay(1000 * 1000); + hang(); + } + } + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + if (!(MUSB_CSR0_RXPKTRDY & csr0)) + goto end; + + count0 = readw(&musbr->ep[0].ep0.count0); + if (count0 == 0) + goto end; + + if (count0 != 8) { + if ((debug_setup) && (debug_level > 1)) + serial_printf("WARN : %s SETUP incorrect size %d\n", + __PRETTY_FUNCTION__, count0); + musb_peri_ep0_stall(); + goto end; + } + + read_fifo(0, count0, &ep0_urb->device_request); + + if (debug_level > 2) + print_usb_device_request(&ep0_urb->device_request); + + if (ep0_urb->device_request.wLength == 0) { + err = ep0_recv_setup(ep0_urb); + + /* Zero data request */ + musb_peri_ep0_zero_data_request(err); + } else { + /* Is data coming or going ? */ + u8 reqType = ep0_urb->device_request.bmRequestType; + + if (USB_REQ_DEVICE2HOST == (reqType & USB_REQ_DIRECTION_MASK)) { + err = ep0_recv_setup(ep0_urb); + /* Device to host */ + musb_peri_ep0_tx_data_request(err); + } else { + /* + * Host to device + * + * The RX routine will call ep0_recv_setup + * when the data packet has arrived. + */ + musb_peri_ep0_rx_data_request(); + } + } + +end: + return; +} + +static void musb_peri_ep0_rx(void) +{ + /* + * This is the completion of the data OUT / RX + * + * Host is sending data to ep0 that is not + * part of setup. This comes from the cdc_recv_setup + * op that is device specific. + * + * Pass the data back to driver ep0_recv_setup which + * should give the cdc_recv_setup the chance to handle + * the rx + */ + u16 csr0; + u16 count0; + + if (debug_level > 3) { + if (0 != ep0_urb->actual_length) { + serial_printf("%s finished ? %d of %d\n", + __PRETTY_FUNCTION__, + ep0_urb->actual_length, + ep0_urb->device_request.wLength); + } + } + + if (ep0_urb->device_request.wLength == ep0_urb->actual_length) { + musb_peri_ep0_last(); + SET_EP0_STATE(IDLE); + ep0_recv_setup(ep0_urb); + return; + } + + csr0 = readw(&musbr->ep[0].ep0.csr0); + if (!(MUSB_CSR0_RXPKTRDY & csr0)) + return; + + count0 = readw(&musbr->ep[0].ep0.count0); + + if (count0) { + struct usb_endpoint_instance *endpoint; + u32 length; + u8 *data; + + endpoint = ep0_endpoint; + if (endpoint && endpoint->rcv_urb) { + struct urb *urb = endpoint->rcv_urb; + unsigned int remaining_space = urb->buffer_length - + urb->actual_length; + + if (remaining_space) { + int urb_bad = 0; /* urb is good */ + + if (count0 > remaining_space) + length = remaining_space; + else + length = count0; + + data = (u8 *) urb->buffer_data; + data += urb->actual_length; + + /* The common musb fifo reader */ + read_fifo(0, length, data); + + musb_peri_ep0_ack_req(); + + /* + * urb's actual_length is updated in + * usbd_rcv_complete + */ + usbd_rcv_complete(endpoint, length, urb_bad); + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s no space in " + "rcv buffer\n", + __PRETTY_FUNCTION__); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s problem with " + "endpoint\n", + __PRETTY_FUNCTION__); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s with nothing to do\n", + __PRETTY_FUNCTION__); + } +} + +static void musb_peri_ep0_tx(void) +{ + u16 csr0; + int transfer_size = 0; + unsigned int p, pm; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + /* Check for pending tx */ + if (csr0 & MUSB_CSR0_TXPKTRDY) + goto end; + + /* Check if this is the last packet sent */ + if (ep0_endpoint->sent >= ep0_urb->actual_length) { + SET_EP0_STATE(IDLE); + goto end; + } + + transfer_size = ep0_urb->actual_length - ep0_endpoint->sent; + /* Is the transfer size negative ? */ + if (transfer_size <= 0) { + if (debug_level > 0) + serial_printf("ERROR : %s problem with the" + " transfer size %d\n", + __PRETTY_FUNCTION__, + transfer_size); + SET_EP0_STATE(IDLE); + goto end; + } + + /* Truncate large transfers to the fifo size */ + if (transfer_size > ep0_endpoint->tx_packetSize) + transfer_size = ep0_endpoint->tx_packetSize; + + write_fifo(0, transfer_size, &ep0_urb->buffer[ep0_endpoint->sent]); + ep0_endpoint->sent += transfer_size; + + /* Done or more to send ? */ + if (ep0_endpoint->sent >= ep0_urb->actual_length) + musb_ep0_tx_ready_and_last(); + else + musb_ep0_tx_ready(); + + /* Wait a bit */ + pm = 10; + for (p = 0; p < pm; p++) { + csr0 = readw(&musbr->ep[0].ep0.csr0); + if (!(csr0 & MUSB_CSR0_TXPKTRDY)) + break; + + /* Double the delay. */ + udelay(1 << pm); + } + + if ((ep0_endpoint->sent >= ep0_urb->actual_length) && (p < pm)) + SET_EP0_STATE(IDLE); + +end: + return; +} + +static void musb_peri_ep0(void) +{ + u16 csr0; + + if (SET_ADDRESS == ep0_state) + return; + + csr0 = readw(&musbr->ep[0].ep0.csr0); + + /* Error conditions */ + if (MUSB_CSR0_P_SENTSTALL & csr0) { + csr0 &= ~MUSB_CSR0_P_SENTSTALL; + writew(csr0, &musbr->ep[0].ep0.csr0); + SET_EP0_STATE(IDLE); + } + if (MUSB_CSR0_P_SETUPEND & csr0) { + csr0 |= MUSB_CSR0_P_SVDSETUPEND; + writew(csr0, &musbr->ep[0].ep0.csr0); + SET_EP0_STATE(IDLE); + if ((debug_setup) && (debug_level > 1)) + serial_printf("WARN: %s SETUPEND\n", + __PRETTY_FUNCTION__); + } + + /* Normal states */ + if (IDLE == ep0_state) + musb_peri_ep0_idle(); + + if (TX == ep0_state) + musb_peri_ep0_tx(); + + if (RX == ep0_state) + musb_peri_ep0_rx(); +} + +static void musb_peri_rx_ep(unsigned int ep) +{ + u16 peri_rxcount = readw(&musbr->ep[ep].epN.rxcount); + + if (peri_rxcount) { + struct usb_endpoint_instance *endpoint; + u32 length; + u8 *data; + + endpoint = GET_ENDPOINT(udc_device, ep); + if (endpoint && endpoint->rcv_urb) { + struct urb *urb = endpoint->rcv_urb; + unsigned int remaining_space = urb->buffer_length - + urb->actual_length; + + if (remaining_space) { + int urb_bad = 0; /* urb is good */ + + if (peri_rxcount > remaining_space) + length = remaining_space; + else + length = peri_rxcount; + + data = (u8 *) urb->buffer_data; + data += urb->actual_length; + + /* The common musb fifo reader */ + read_fifo(ep, length, data); + + musb_peri_rx_ack(ep); + + /* + * urb's actual_length is updated in + * usbd_rcv_complete + */ + usbd_rcv_complete(endpoint, length, urb_bad); + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d no space " + "in rcv buffer\n", + __PRETTY_FUNCTION__, ep); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d problem with " + "endpoint\n", + __PRETTY_FUNCTION__, ep); + } + + } else { + if (debug_level > 0) + serial_printf("ERROR : %s %d with nothing to do\n", + __PRETTY_FUNCTION__, ep); + } +} + +static void musb_peri_rx(u16 intr) +{ + unsigned int ep; + + /* Check for EP0 */ + if (0x01 & intr) + musb_peri_ep0(); + + for (ep = 1; ep < 16; ep++) { + if ((1 << ep) & intr) + musb_peri_rx_ep(ep); + } +} + +static void musb_peri_tx(u16 intr) +{ + /* Check for EP0 */ + if (0x01 & intr) + musb_peri_ep0_tx(); + + /* + * Use this in the future when handling epN tx + * + * u8 ep; + * + * for (ep = 1; ep < 16; ep++) { + * if ((1 << ep) & intr) { + * / * handle tx for this endpoint * / + * } + * } + */ +} + +void udc_irq(void) +{ + /* This is a high freq called function */ + if (enabled) { + u8 intrusb; + + intrusb = readb(&musbr->intrusb); + + /* + * See drivers/usb/gadget/mpc8xx_udc.c for + * state diagram going from detached through + * configuration. + */ + if (MUSB_INTR_RESUME & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_ACTIVITY, 0); + musb_peri_resume(); + } + + musb_peri_ep0(); + + if (MUSB_INTR_RESET & intrusb) { + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + musb_peri_reset(); + } + + if (MUSB_INTR_DISCONNECT & intrusb) { + /* cable unplugged from hub/host */ + usbd_device_event_irq(udc_device, DEVICE_RESET, 0); + musb_peri_reset(); + usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0); + } + + if (MUSB_INTR_SOF & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_ACTIVITY, 0); + musb_peri_resume(); + } + + if (MUSB_INTR_SUSPEND & intrusb) { + usbd_device_event_irq(udc_device, + DEVICE_BUS_INACTIVE, 0); + } + + if (ep0_state != SET_ADDRESS) { + u16 intrrx, intrtx; + + intrrx = readw(&musbr->intrrx); + intrtx = readw(&musbr->intrtx); + + if (intrrx) + musb_peri_rx(intrrx); + + if (intrtx) + musb_peri_tx(intrtx); + } else { + if (MUSB_INTR_SOF & intrusb) { + u8 faddr; + faddr = readb(&musbr->faddr); + /* + * Setting of the address can fail. + * Normally it succeeds the second time. + */ + if (udc_device->address != faddr) + musb_peri_ep0_set_address(); + } + } + } +} + +void udc_set_nak(int ep_num) +{ + /* noop */ +} + +void udc_unset_nak(int ep_num) +{ + /* noop */ +} + +int udc_endpoint_write(struct usb_endpoint_instance *endpoint) +{ + int ret = 0; + + /* Transmit only if the hardware is available */ + if (endpoint->tx_urb && endpoint->state == 0) { + unsigned int ep = endpoint->endpoint_address & + USB_ENDPOINT_NUMBER_MASK; + + u16 peri_txcsr = readw(&musbr->ep[ep].epN.txcsr); + + /* Error conditions */ + if (peri_txcsr & MUSB_TXCSR_P_UNDERRUN) { + peri_txcsr &= ~MUSB_TXCSR_P_UNDERRUN; + writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); + } + + if (debug_level > 1) + musb_print_txcsr(peri_txcsr); + + /* Check if a packet is waiting to be sent */ + if (!(peri_txcsr & MUSB_TXCSR_TXPKTRDY)) { + u32 length; + u8 *data; + struct urb *urb = endpoint->tx_urb; + unsigned int remaining_packet = urb->actual_length - + endpoint->sent; + + if (endpoint->tx_packetSize < remaining_packet) + length = endpoint->tx_packetSize; + else + length = remaining_packet; + + data = (u8 *) urb->buffer; + data += endpoint->sent; + + /* common musb fifo function */ + write_fifo(ep, length, data); + + musb_peri_tx_ready(ep); + + endpoint->last = length; + /* usbd_tx_complete will take care of updating 'sent' */ + usbd_tx_complete(endpoint); + } + } else { + if (debug_level > 0) + serial_printf("ERROR : %s Problem with urb %p " + "or ep state %d\n", + __PRETTY_FUNCTION__, + endpoint->tx_urb, endpoint->state); + } + + return ret; +} + +void udc_setup_ep(struct usb_device_instance *device, unsigned int id, + struct usb_endpoint_instance *endpoint) +{ + if (0 == id) { + /* EP0 */ + ep0_endpoint = endpoint; + ep0_endpoint->endpoint_address = 0xff; + ep0_urb = usbd_alloc_urb(device, endpoint); + } else if (MAX_ENDPOINT >= id) { + int ep_addr; + + /* Check the direction */ + ep_addr = endpoint->endpoint_address; + if (USB_DIR_IN == (ep_addr & USB_ENDPOINT_DIR_MASK)) { + /* IN */ + epinfo[(id * 2) + 1].epsize = endpoint->tx_packetSize; + } else { + /* OUT */ + epinfo[id * 2].epsize = endpoint->rcv_packetSize; + } + + musb_configure_ep(&epinfo[0], + sizeof(epinfo) / sizeof(struct musb_epinfo)); + } else { + if (debug_level > 0) + serial_printf("ERROR : %s endpoint request %d " + "exceeds maximum %d\n", + __PRETTY_FUNCTION__, id, MAX_ENDPOINT); + } +} + +void udc_connect(void) +{ + /* noop */ +} + +void udc_disconnect(void) +{ + /* noop */ +} + +void udc_enable(struct usb_device_instance *device) +{ + /* Save the device structure pointer */ + udc_device = device; + + enabled = 1; +} + +void udc_disable(void) +{ + enabled = 0; +} + +void udc_startup_events(struct usb_device_instance *device) +{ + /* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */ + usbd_device_event_irq(device, DEVICE_INIT, 0); + + /* + * The DEVICE_CREATE event puts the USB device in the state + * STATE_ATTACHED. + */ + usbd_device_event_irq(device, DEVICE_CREATE, 0); + + /* Resets the address to 0 */ + usbd_device_event_irq(device, DEVICE_RESET, 0); + + udc_enable(device); +} + +int udc_init(void) +{ + int ret; + int ep_loop; + + ret = musb_platform_init(); + if (ret < 0) + goto end; + + /* Configure all the endpoint FIFO's and start usb controller */ + musbr = musb_cfg.regs; + + /* Initialize the endpoints */ + for (ep_loop = 0; ep_loop < MAX_ENDPOINT * 2; ep_loop++) { + epinfo[ep_loop].epnum = (ep_loop / 2) + 1; + epinfo[ep_loop].epdir = ep_loop % 2; /* OUT, IN */ + epinfo[ep_loop].epsize = 0; + } + + musb_peri_softconnect(); + + ret = 0; +end: + + return ret; +} diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c new file mode 100644 index 000000000..3e502e7d8 --- /dev/null +++ b/drivers/usb/musb/omap3.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This is file is based on + * repository git.gitorious.org/u-boot-omap3/mainline.git, + * branch omap3-dev-usb, file drivers/usb/host/omap3530_usb.c + * + * This is the unique part of its copyright : + * + * ------------------------------------------------------------------------ + * + * Copyright (c) 2009 Texas Instruments + * + * ------------------------------------------------------------------------ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "omap3.h" + +static int platform_needs_initialization = 1; + +struct musb_config musb_cfg = { + (struct musb_regs *)MENTOR_USB0_BASE, + OMAP3_USB_TIMEOUT, + 0 +}; + +/* + * OMAP3 USB OTG registers. + */ +struct omap3_otg_regs { + u32 revision; + u32 sysconfig; + u32 sysstatus; + u32 interfsel; + u32 simenable; + u32 forcestdby; +}; + +static struct omap3_otg_regs *otg; + +#define OMAP3_OTG_SYSCONFIG_SMART_STANDBY_MODE 0x2000 +#define OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE 0x1000 +#define OMAP3_OTG_SYSCONFIG_SMART_IDLE_MODE 0x0010 +#define OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE 0x0008 +#define OMAP3_OTG_SYSCONFIG_ENABLEWAKEUP 0x0004 +#define OMAP3_OTG_SYSCONFIG_SOFTRESET 0x0002 +#define OMAP3_OTG_SYSCONFIG_AUTOIDLE 0x0001 + +#define OMAP3_OTG_SYSSTATUS_RESETDONE 0x0001 + +#define OMAP3_OTG_INTERFSEL_OMAP 0x0001 + +#define OMAP3_OTG_FORCESTDBY_STANDBY 0x0001 + + +#ifdef DEBUG_MUSB_OMAP3 +static void musb_db_otg_regs(void) +{ + u32 l; + l = readl(&otg->revision); + serial_printf("OTG_REVISION 0x%x\n", l); + l = readl(&otg->sysconfig); + serial_printf("OTG_SYSCONFIG 0x%x\n", l); + l = readl(&otg->sysstatus); + serial_printf("OTG_SYSSTATUS 0x%x\n", l); + l = readl(&otg->interfsel); + serial_printf("OTG_INTERFSEL 0x%x\n", l); + l = readl(&otg->forcestdby); + serial_printf("OTG_FORCESTDBY 0x%x\n", l); +} +#endif + +int musb_platform_init(void) +{ + int ret = -1; + + if (platform_needs_initialization) { + u32 stdby; + + if (twl4030_usb_ulpi_init()) { + serial_printf("ERROR: %s Could not initialize PHY\n", + __PRETTY_FUNCTION__); + goto end; + } + + otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE; + + /* Set OTG to always be on */ + writel(OMAP3_OTG_SYSCONFIG_NO_STANDBY_MODE | + OMAP3_OTG_SYSCONFIG_NO_IDLE_MODE, &otg->sysconfig); + + /* Set the interface */ + writel(OMAP3_OTG_INTERFSEL_OMAP, &otg->interfsel); + + /* Clear force standby */ + stdby = readl(&otg->forcestdby); + stdby &= ~OMAP3_OTG_FORCESTDBY_STANDBY; + writel(stdby, &otg->forcestdby); + + platform_needs_initialization = 0; + } + + ret = platform_needs_initialization; +end: + return ret; + +} + +void musb_platform_deinit(void) +{ + /* noop */ +} diff --git a/drivers/usb/musb/omap3.h b/drivers/usb/musb/omap3.h new file mode 100644 index 000000000..20fc9d294 --- /dev/null +++ b/drivers/usb/musb/omap3.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This file is based on the file drivers/usb/musb/davinci.h + * + * This is the unique part of its copyright: + * + * -------------------------------------------------------------------- + * + * Copyright (c) 2008 Texas Instruments + * Author: Thomas Abraham t-abraham@ti.com, Texas Instruments + * + * -------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUSB_OMAP3_H_ +#define _MUSB_OMAP3_H_ + +#include "musb_core.h" + +/* Base address of MUSB registers */ +#define MENTOR_USB0_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) + +/* Base address of OTG registers */ +#define OMAP3_OTG_BASE (MENTOR_USB0_BASE + 0x400) + +/* Timeout for USB module */ +#define OMAP3_USB_TIMEOUT 0x3FFFFFF + +int musb_platform_init(void); + +#endif /* _MUSB_OMAP3_H */ + diff --git a/include/usb.h b/include/usb.h index 4148d67e1..1cc3e4229 100644 --- a/include/usb.h +++ b/include/usb.h @@ -131,7 +131,8 @@ struct usb_device { #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ - defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) + defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \ + defined(CONFIG_USB_OMAP3) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); diff --git a/include/usb/musb_udc.h b/include/usb/musb_udc.h new file mode 100644 index 000000000..ef37dbbcc --- /dev/null +++ b/include/usb/musb_udc.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __MUSB_UDC_H__ +#define __MUSB_UDC_H__ + +#include + +/* UDC level routines */ +void udc_irq(void); +void udc_set_nak(int ep_num); +void udc_unset_nak(int ep_num); +int udc_endpoint_write(struct usb_endpoint_instance *endpoint); +void udc_setup_ep(struct usb_device_instance *device, unsigned int id, + struct usb_endpoint_instance *endpoint); +void udc_connect(void); +void udc_disconnect(void); +void udc_enable(struct usb_device_instance *device); +void udc_disable(void); +void udc_startup_events(struct usb_device_instance *device); +int udc_init(void); + +/* usbtty */ +#ifdef CONFIG_USB_TTY + +#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */ +#define UDC_INT_ENDPOINT 1 +#define UDC_INT_PACKET_SIZE 64 +#define UDC_OUT_ENDPOINT 2 +#define UDC_OUT_PACKET_SIZE 64 +#define UDC_IN_ENDPOINT 3 +#define UDC_IN_PACKET_SIZE 64 +#define UDC_BULK_PACKET_SIZE 64 + +#endif /* CONFIG_USB_TTY */ + +#endif /* __MUSB_UDC_H__ */ + -- cgit v1.2.3 From ae4caf2fb53cc7be5d59a649b8aee86d542cbb6f Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sat, 31 Oct 2009 12:37:46 -0500 Subject: OMAP3 USB Initialize twl4030 only if required OMAP3EVM uses ISP1504 phy and so twl4030 related init is not required. Submitted-by: Ajay Kumar Gupta Signed-off-by: Tom Rix --- drivers/usb/musb/omap3.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/musb/omap3.c b/drivers/usb/musb/omap3.c index 3e502e7d8..ea98c3cac 100644 --- a/drivers/usb/musb/omap3.c +++ b/drivers/usb/musb/omap3.c @@ -94,12 +94,17 @@ int musb_platform_init(void) if (platform_needs_initialization) { u32 stdby; + /* + * OMAP3EVM uses ISP1504 phy and so + * twl4030 related init is not required. + */ +#ifdef CONFIG_TWL4030_USB if (twl4030_usb_ulpi_init()) { serial_printf("ERROR: %s Could not initialize PHY\n", __PRETTY_FUNCTION__); goto end; } - +#endif otg = (struct omap3_otg_regs *)OMAP3_OTG_BASE; /* Set OTG to always be on */ -- cgit v1.2.3 From 87d93a1ba2ae23550e1370adb7a3b00af0831165 Mon Sep 17 00:00:00 2001 From: Wolfgang Wegner Date: Wed, 9 Dec 2009 15:16:47 +0100 Subject: move prototypes for gunzip() and zunzip() to common.h Prototype for gunzip/zunzip was only in lib_generic/gunzip.c and thus repeated in every file using it. This patch moves the prototypes to common.h and removes all prototypes distributed anywhere else. Signed-off-by: Wolfgang Wegner --- board/bf527-ezkit/video.c | 2 -- board/bf533-stamp/video.c | 2 -- board/bf548-ezkit/video.c | 2 -- board/cm-bf548/video.c | 2 -- board/dave/PPChameleonEVB/PPChameleonEVB.c | 3 --- board/esd/apc405/apc405.c | 3 --- board/esd/ash405/ash405.c | 4 ---- board/esd/cpci405/cpci405.c | 1 - board/esd/hh405/hh405.c | 4 ---- board/esd/pci405/pci405.c | 1 - board/esd/plu405/plu405.c | 3 --- board/esd/tasreg/tasreg.c | 1 - board/esd/voh405/voh405.c | 4 ---- board/esd/wuh405/wuh405.c | 4 ---- board/mpl/common/common_util.c | 1 - board/prodrive/pdnb3/pdnb3.c | 1 - common/cmd_bmp.c | 2 -- common/cmd_bootm.c | 1 - common/cmd_license.c | 1 - common/cmd_mem.c | 2 -- drivers/video/cfb_console.c | 2 -- fs/ubifs/ubifs.h | 3 --- include/common.h | 5 +++++ lib_generic/gunzip.c | 3 --- 24 files changed, 5 insertions(+), 52 deletions(-) (limited to 'drivers') diff --git a/board/bf527-ezkit/video.c b/board/bf527-ezkit/video.c index 0b6b7b2e7..57652be29 100644 --- a/board/bf527-ezkit/video.c +++ b/board/bf527-ezkit/video.c @@ -16,8 +16,6 @@ #include #include -int gunzip(void *, int, unsigned char *, unsigned long *); - #define DMA_SIZE16 2 #include diff --git a/board/bf533-stamp/video.c b/board/bf533-stamp/video.c index 28ffa618f..939bd35a0 100644 --- a/board/bf533-stamp/video.c +++ b/board/bf533-stamp/video.c @@ -20,8 +20,6 @@ #include #include -int gunzip(void *, int, unsigned char *, unsigned long *); - #define DMA_SIZE16 2 #include diff --git a/board/bf548-ezkit/video.c b/board/bf548-ezkit/video.c index f4f1becae..10b08e2bf 100644 --- a/board/bf548-ezkit/video.c +++ b/board/bf548-ezkit/video.c @@ -16,8 +16,6 @@ #include #include -int gunzip(void *, int, unsigned char *, unsigned long *); - #define DMA_SIZE16 2 #include diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index 078734269..4097f09e1 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -16,8 +16,6 @@ #include #include -int gunzip(void *, int, unsigned char *, unsigned long *); - #ifdef CONFIG_VIDEO #define DMA_SIZE16 2 diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index 06de6e0b1..6bc70ef9a 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; /* ------------------------------------------------------------------------- */ -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - int board_early_init_f (void) { out32(GPIO0_OR, CONFIG_SYS_NAND0_CE); /* set initial outputs */ diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 409a0540b..72c0907e0 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -54,9 +54,6 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - #ifdef CONFIG_LCD_USED /* logo bitmap data - gzip compressed and generated by bin2c */ unsigned char logo_bmp[] = diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 5f0e67cbb..061595931 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -48,10 +48,6 @@ const unsigned char fpgadata[] = #include "../common/fpga.c" -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - int board_early_init_f (void) { /* diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index c29c876d6..24db8830c 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -89,7 +89,6 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); /* Prototypes */ int cpci405_version(void); -int gunzip(void *, int, unsigned char *, unsigned long *); void lxt971_no_sleep(void); int board_early_init_f(void) diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 132531b39..4251d51b2 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -251,10 +251,6 @@ const unsigned char fpgadata[] = #include "../common/fpga.c" -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - /* logo bitmap data - gzip compressed and generated by bin2c */ unsigned char logo_bmp_320[] = { diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 34a163240..536485727 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -34,7 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; /* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); unsigned long fpga_done_state(void); unsigned long fpga_init_state(void); diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index fcffdf67c..e385a78a2 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -46,9 +46,6 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - int board_early_init_f(void) { /* diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c index 18444427f..bd9fb2fc2 100644 --- a/board/esd/tasreg/tasreg.c +++ b/board/esd/tasreg/tasreg.c @@ -29,7 +29,6 @@ /* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len); int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 3f81665eb..a5600de6f 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -48,10 +48,6 @@ const unsigned char fpgadata[] = #include "../common/fpga.c" -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - /* logo bitmap data - gzip compressed and generated by bin2c */ unsigned char logo_bmp_320[] = { diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index f2591d57f..01966eec2 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -46,10 +46,6 @@ const unsigned char fpgadata[] = #include "../common/fpga.c" -/* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); - - int board_early_init_f (void) { /* diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 61af4aea1..32bf24493 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -48,7 +48,6 @@ DECLARE_GLOBAL_DATA_PTR; #define FIRM_START 0xFFF00000 #endif -extern int gunzip(void *, int, uchar *, unsigned long *); extern int mem_test(ulong start, ulong ramsize, int quiet); #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c index c323456d6..69f8f9bbc 100644 --- a/board/prodrive/pdnb3/pdnb3.c +++ b/board/prodrive/pdnb3/pdnb3.c @@ -29,7 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; /* Prototypes */ -int gunzip(void *, int, unsigned char *, unsigned long *); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* predefine these here for FPGA programming (before including fpga.c) */ diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index faa10a414..74ab24ca9 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -35,8 +35,6 @@ static int bmp_info (ulong addr); static int bmp_display (ulong addr, int x, int y); -int gunzip(void *, int, unsigned char *, unsigned long *); - /* * Allocate and decompress a BMP image using gunzip(). * diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index efd6aec0c..94ddac37c 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -63,7 +63,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern int gunzip (void *dst, int dstlen, unsigned char *src, unsigned long *lenp); #ifndef CONFIG_SYS_BOOTM_LEN #define CONFIG_SYS_BOOTM_LEN 0x800000 /* use 8MByte as default max gunzip size */ #endif diff --git a/common/cmd_license.c b/common/cmd_license.c index c6f272ad3..85a4871de 100644 --- a/common/cmd_license.c +++ b/common/cmd_license.c @@ -29,7 +29,6 @@ #include #include #include -int gunzip(void *, int, unsigned char *, unsigned long *); int do_license(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { diff --git a/common/cmd_mem.c b/common/cmd_mem.c index a34b342f0..183933076 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -1225,8 +1225,6 @@ int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif #ifdef CONFIG_CMD_UNZIP -int gunzip (void *, int, unsigned char *, unsigned long *); - int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { unsigned long src, dst; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 16d6689f2..c07a26e3c 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -403,8 +403,6 @@ static const int video_font_draw_table32[16][4] = { { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } }; -int gunzip(void *, int, unsigned char *, unsigned long *); - /******************************************************************************/ static void video_drawchars (int xx, int yy, unsigned char *s, int count) diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 06772af36..0af471afb 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -2140,7 +2140,4 @@ int ubifs_decompress(const void *buf, int len, void *out, int *out_len, /* todo: Move these to a common U-Boot header */ int lzo1x_decompress_safe(const unsigned char *in, size_t in_len, unsigned char *out, size_t *out_len); - -int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, - int stoponerr, int offset); #endif /* !__UBIFS_H__ */ diff --git a/include/common.h b/include/common.h index 00b543408..07897f682 100644 --- a/include/common.h +++ b/include/common.h @@ -612,6 +612,11 @@ ulong usec2ticks (unsigned long usec); ulong ticks2usec (unsigned long ticks); int init_timebase (void); +/* lib_generic/gunzip.c */ +int gunzip(void *, int, unsigned char *, unsigned long *); +int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, + int stoponerr, int offset); + /* lib_generic/time.c */ void udelay (unsigned long); diff --git a/lib_generic/gunzip.c b/lib_generic/gunzip.c index d59a4482b..d2b7ad477 100644 --- a/lib_generic/gunzip.c +++ b/lib_generic/gunzip.c @@ -36,11 +36,8 @@ #define RESERVED 0xe0 #define DEFLATED 8 -int gunzip(void *, int, unsigned char *, unsigned long *); void *zalloc(void *, unsigned, unsigned); void zfree(void *, void *, unsigned); -int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp, - int stoponerr, int offset); void *zalloc(void *x, unsigned items, unsigned size) { -- cgit v1.2.3