From 30563a04bff73fd4fbd840b846f4b6459759a839 Mon Sep 17 00:00:00 2001
From: Nishanth Menon <nm@ti.com>
Date: Sat, 7 Nov 2009 10:51:24 -0500
Subject: OMAP3:SDRC: introduce DDR types

Micron DDR timings based on:
http://www.sakoman.net/cgi-bin/gitweb.cgi?p=x-load-omap3.git;a=blob;f=include/asm/arch-omap3/mem.h;h=e6fbfe3947f5d0d85fea776e30821d4017316d86;hb=HEAD

Introduce Micron DDR timings and provide
CONFIG_OMAP3_INFINEON_DDR and CONFIG_OMAP3_MICRON_DDR config
options to allow for platform files to setup their timings as
per the type of DDR selected

Reported-by: Steve Sakoman in http://www.nabble.com/forum/Permalink.jtp?root=25779518&post=25959734&page=y

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 include/asm-arm/arch-omap3/mem.h | 91 +++++++++++++++++++++++++++++++---------
 1 file changed, 72 insertions(+), 19 deletions(-)

(limited to 'include/asm-arm')

diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 5496a618c..9439758e4 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -68,25 +68,78 @@ enum {
  *	TCKE = 2
  *	XSR = 120/6 = 20
  */
-#define TDAL_165	6
-#define TDPL_165	3
-#define TRRD_165	2
-#define TRCD_165	3
-#define TRP_165		3
-#define TRAS_165	7
-#define TRC_165		10
-#define TRFC_165	21
-#define V_ACTIMA_165	((TRFC_165 << 27) | (TRC_165 << 22) | \
-			(TRAS_165 << 18) | (TRP_165 << 15) |  \
-			(TRCD_165 << 12) | (TRRD_165 << 9) |  \
-			(TDPL_165 << 6) | (TDAL_165))
-
-#define TWTR_165	1
-#define TCKE_165	1
-#define TXP_165		5
-#define XSR_165		23
-#define V_ACTIMB_165	(((TCKE_165 << 12) | (XSR_165 << 0)) |	\
-			(TXP_165 << 8) | (TWTR_165 << 16))
+#define INFINEON_TDAL_165	6
+#define INFINEON_TDPL_165	3
+#define INFINEON_TRRD_165	2
+#define INFINEON_TRCD_165	3
+#define INFINEON_TRP_165	3
+#define INFINEON_TRAS_165	7
+#define INFINEON_TRC_165	10
+#define INFINEON_TRFC_165	12
+#define INFINEON_V_ACTIMA_165	((INFINEON_TRFC_165 << 27) |		\
+		(INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) |	\
+		(INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) |	\
+		(INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) |	\
+		(INFINEON_TDAL_165))
+
+#define INFINEON_TWTR_165	1
+#define INFINEON_TCKE_165	2
+#define INFINEON_TXP_165	2
+#define INFINEON_XSR_165	20
+#define INFINEON_V_ACTIMB_165	((INFINEON_TCKE_165 << 12) |		\
+		(INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) |	\
+		(INFINEON_TWTR_165 << 16))
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
+ * ACTIMA
+ *	TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
+ *	TDPL (Twr)	= 15/6	= 2.5 -> 3
+ *	TRRD		= 12/6	= 2
+ *	TRCD		= 18/6	= 3
+ *	TRP		= 18/6	= 3
+ *	TRAS		= 42/6	= 7
+ *	TRC		= 60/6	= 10
+ *	TRFC		= 125/6	= 21
+ * ACTIMB
+ *	TWTR		= 1
+ *	TCKE		= 1
+ *	TXSR		= 138/6	= 23
+ *	TXP		= 25/6	= 4.1 ~5
+ */
+#define MICRON_TDAL_165		6
+#define MICRON_TDPL_165		3
+#define MICRON_TRRD_165		2
+#define MICRON_TRCD_165		3
+#define MICRON_TRP_165		3
+#define MICRON_TRAS_165		7
+#define MICRON_TRC_165		10
+#define MICRON_TRFC_165		21
+#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) |			\
+		(MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) |	\
+		(MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) |	\
+		(MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) |	\
+		(MICRON_TDAL_165))
+
+#define MICRON_TWTR_165		1
+#define MICRON_TCKE_165		1
+#define MICRON_XSR_165		23
+#define MICRON_TXP_165		5
+#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) |			\
+		(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) |	\
+		(MICRON_TWTR_165 << 16))
+
+#ifdef CONFIG_OMAP3_INFINEON_DDR
+#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
+#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
+#endif
+#ifdef CONFIG_OMAP3_MICRON_DDR
+#define V_ACTIMA_165 MICRON_V_ACTIMA_165
+#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#endif
+
+#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
+#error "Please choose the right DDR type in config header"
+#endif
 
 /*
  * GPMC settings -
-- 
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