From 4c24e8288c601cb773ab02528b48a8577970e867 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sat, 30 Aug 2008 17:28:36 +0200 Subject: avr32: data_bits should reflect the actual number of data bits Make the data_bits enum in struct sdram_config reflect the actual number of data bits on the bus, i.e. 16 or 32. Having 0 mean 16 bits and 1 mean 32 bits is just too confusing. Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/sdram.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-avr32') diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h index 7bdefc1fd..762acfa07 100644 --- a/include/asm-avr32/sdram.h +++ b/include/asm-avr32/sdram.h @@ -25,8 +25,8 @@ struct sdram_config { /* Number of data bits. */ enum { - SDRAM_DATA_16BIT, - SDRAM_DATA_32BIT, + SDRAM_DATA_16BIT = 16, + SDRAM_DATA_32BIT = 32, } data_bits; /* Number of address bits */ -- cgit v1.2.3 From ab0df36fc7db9dda0b786b909f653e279dfeb9cf Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Fri, 29 Aug 2008 21:09:49 +0200 Subject: avr32: refactor the portmux/gpio code - Separate the portmux configuration functionality from the GPIO pin control API. - Separate the controller-specific code from the chip-specific code. - Allow "ganged" port configuration (multiple pins at once). - Add more flexibility to the "canned" peripheral select functions: - Allow using more than 23 address bits, more chip selects, as well as NAND- and CF-specific pins. - Make the MACB SPEED pin optional, and choose between MII/RMII using a parameter instead of an #ifdef. - Make it possible to use other MMC slots than slot 0, and support different MMC/SDCard data bus widths. - Use more reasonable pull-up defaults; floating pins may consume a lot of power. - Get rid of some custom portmux code from the mimc200 board code. The old gpio/portmux API couldn't really handle its requirements, but the new one can. - Add documentation. The end result is slightly smaller code for all boards. Which isn't really the point, but at least it isn't any larger. This has been verified on ATSTK1002 and ATNGW100. I'd appreciate if the board maintainers could help me test this on their boards. In particular, the mimc200 port has lost a lot of code, so I'm hoping Mark can help me out. Signed-off-by: Haavard Skinnemoen Cc: Hans-Christian Egtvedt Cc: Mark Jackson Cc: Alex Raimondi Cc: Julien May Changes since v1: * Enable pullup on NWAIT * Add missing include to portmux-pio.h * Rename CONFIG_PIO2 -> CONFIG_PORTMUX_PIO to match docs --- board/atmel/atngw100/atngw100.c | 15 +- board/atmel/atstk1000/atstk1000.c | 12 +- board/earthlcd/favr-32-ezkit/favr-32-ezkit.c | 10 +- board/mimc/mimc200/mimc200.c | 88 +++--------- board/miromico/hammerhead/hammerhead.c | 12 +- cpu/at32ap/Makefile | 2 +- cpu/at32ap/at32ap700x/Makefile | 2 +- cpu/at32ap/at32ap700x/gpio.c | 199 ------------------------- cpu/at32ap/at32ap700x/portmux.c | 204 ++++++++++++++++++++++++++ cpu/at32ap/pio.c | 116 --------------- cpu/at32ap/portmux-pio.c | 92 ++++++++++++ doc/README.AVR32-port-muxing | 208 +++++++++++++++++++++++++++ include/asm-avr32/arch-at32ap700x/gpio.h | 184 ++---------------------- include/asm-avr32/arch-at32ap700x/portmux.h | 89 ++++++++++++ include/asm-avr32/arch-common/portmux-pio.h | 138 ++++++++++++++++++ include/configs/atngw100.h | 2 +- include/configs/atstk1002.h | 2 +- include/configs/atstk1003.h | 2 +- include/configs/atstk1004.h | 2 +- include/configs/atstk1006.h | 2 +- include/configs/favr-32-ezkit.h | 2 +- include/configs/hammerhead.h | 2 +- include/configs/mimc200.h | 2 +- 23 files changed, 795 insertions(+), 592 deletions(-) delete mode 100644 cpu/at32ap/at32ap700x/gpio.c create mode 100644 cpu/at32ap/at32ap700x/portmux.c delete mode 100644 cpu/at32ap/pio.c create mode 100644 cpu/at32ap/portmux-pio.c create mode 100644 doc/README.AVR32-port-muxing create mode 100644 include/asm-avr32/arch-at32ap700x/portmux.h create mode 100644 include/asm-avr32/arch-common/portmux-pio.h (limited to 'include/asm-avr32') diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index 7f3e48541..03544aa21 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,18 +51,18 @@ int board_early_init_f(void) /* Enable SDRAM in the EBI mux */ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - gpio_enable_ebi(); - gpio_enable_usart1(); + portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) - gpio_enable_macb0(); - gpio_enable_macb1(); + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); + portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); #endif #if defined(CONFIG_MMC) - gpio_enable_mmci(); + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); #endif #if defined(CONFIG_ATMEL_SPI) - gpio_enable_spi0(1 << 0); + portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW); #endif return 0; @@ -108,7 +109,7 @@ int board_eth_init(bd_t *bi) #ifdef CONFIG_ATMEL_SPI #include -#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA3 +#define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 915b1c353..cc400a92f 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -24,8 +24,8 @@ #include #include #include -#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -77,14 +77,14 @@ int board_early_init_f(void) /* Enable SDRAM in the EBI mux */ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - gpio_enable_ebi(); - gpio_enable_usart1(); + portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) - gpio_enable_macb0(); - gpio_enable_macb1(); + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); + portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); #endif #if defined(CONFIG_MMC) - gpio_enable_mmci(); + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); #endif return 0; diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c index da69e754f..b2ddd089d 100644 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -22,8 +22,8 @@ #include #include #include -#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -49,13 +49,13 @@ int board_early_init_f(void) /* Enable SDRAM in the EBI mux */ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - gpio_enable_ebi(); - gpio_enable_usart3(); + portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart3(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) - gpio_enable_macb0(); + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); #endif #if defined(CONFIG_MMC) - gpio_enable_mmci(); + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); #endif return 0; diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 4ece11ac8..4da467860 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #define SM_PM_GCCTRL 0x0060 @@ -53,98 +54,51 @@ int board_early_init_f(void) /* Enable SDRAM in the EBI mux */ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - gpio_enable_ebi(); - gpio_enable_usart1(); - - /* enable higher address lines for larger flash devices */ - gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */ - gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */ - gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */ - - /* enable data flash chip select */ - gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */ + /* Enable 26 address bits and NCS2 */ + portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); /* de-assert "force sys reset" pin */ - gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */ - gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT); + portmux_select_gpio(PORTMUX_PORT_D, 1 << 15, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); /* init custom i/o */ /* cpu type inputs */ - gpio_select_pio(GPIO_PIN_PE19, 0); - gpio_select_pio(GPIO_PIN_PE20, 0); - gpio_select_pio(GPIO_PIN_PE23, 0); + portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23), + PORTMUX_DIR_INPUT); /* main board type inputs */ - gpio_select_pio(GPIO_PIN_PB19, 0); - gpio_select_pio(GPIO_PIN_PB29, 0); + portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29), + PORTMUX_DIR_INPUT); /* DEBUG input (use weak pullup) */ - gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP); + portmux_select_gpio(PORTMUX_PORT_E, 1 << 21, + PORTMUX_DIR_INPUT | PORTMUX_PULL_UP); /* are we suppressing the console ? */ - if (gpio_get_value(GPIO_PIN_PE21) == 1) + if (gpio_get_value(GPIO_PIN_PE(21)) == 1) gd->flags |= GD_FLG_SILENT; /* reset phys */ - gpio_select_pio(GPIO_PIN_PE24, 0); - gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */ - gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT); + portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT); + portmux_select_gpio(PORTMUX_PORT_C, 1 << 18, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); /* GCLK0 - 10MHz clock */ writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL); - gpio_select_periph_A(GPIO_PIN_PA30, 0); + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, PORTMUX_FUNC_A, 0); udelay(5000); /* release phys reset */ - gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */ + gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */ #if defined(CONFIG_MACB) /* init macb0 pins */ - gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ - gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ - gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ - gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ - gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ - gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ - gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ - gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ - gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ - gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ - gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ - gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ - gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ - gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ - gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ - gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ - gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ -#endif - - /* init macb1 pins */ - gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ - gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ - gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ - gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ - gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ - gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ - gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ - gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ - gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ - gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ - gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ - gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ - gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ - gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ - gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ - gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ - gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ -#endif + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); + portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); #endif #if defined(CONFIG_MMC) - gpio_enable_mmci(); + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); #endif return 0; diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index 738ece2fe..3d6cf9b28 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -29,9 +29,9 @@ #include #include #include -#include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -65,14 +65,14 @@ int board_early_init_f(void) /* Enable SDRAM in the EBI mux */ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); - gpio_enable_ebi(); - gpio_enable_usart1(); + portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) - gpio_enable_macb0(); + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); #endif #if defined(CONFIG_MMC) - gpio_enable_mmci(); + portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW); #endif return 0; } @@ -107,7 +107,7 @@ void gclk_init(void) /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ /* Select GCLK3 peripheral function */ - gpio_select_periph_A(GPIO_PIN_PB29, 0); + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, PORTMUX_FUNC_A, 0); /* Enable GCLK3 with no input divider, from OSC0 (crystal) */ sm_writel(PM_GCCTRL(3), SM_BIT(CEN)); diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index 33dc42768..100cf3e74 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -34,7 +34,7 @@ COBJS-y += hsdramc.o COBJS-y += exception.o COBJS-y += cache.o COBJS-y += interrupts.o -COBJS-y += pio.o +COBJS-$(CONFIG_PORTMUX_PIO) += portmux-pio.o SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile index 740423563..46e6ef661 100644 --- a/cpu/at32ap/at32ap700x/Makefile +++ b/cpu/at32ap/at32ap700x/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(SOC).a -COBJS := gpio.o clk.o +COBJS := portmux.o clk.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c deleted file mode 100644 index 56ba2f90c..000000000 --- a/cpu/at32ap/at32ap700x/gpio.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#include - -#include -#include -#include - -/* - * Lots of small functions here. We depend on --gc-sections getting - * rid of the ones we don't need. - */ -void gpio_enable_ebi(void) -{ -#ifdef CFG_HSDRAMC -#ifndef CFG_SDRAM_16BIT - gpio_select_periph_A(GPIO_PIN_PE0, 0); - gpio_select_periph_A(GPIO_PIN_PE1, 0); - gpio_select_periph_A(GPIO_PIN_PE2, 0); - gpio_select_periph_A(GPIO_PIN_PE3, 0); - gpio_select_periph_A(GPIO_PIN_PE4, 0); - gpio_select_periph_A(GPIO_PIN_PE5, 0); - gpio_select_periph_A(GPIO_PIN_PE6, 0); - gpio_select_periph_A(GPIO_PIN_PE7, 0); - gpio_select_periph_A(GPIO_PIN_PE8, 0); - gpio_select_periph_A(GPIO_PIN_PE9, 0); - gpio_select_periph_A(GPIO_PIN_PE10, 0); - gpio_select_periph_A(GPIO_PIN_PE11, 0); - gpio_select_periph_A(GPIO_PIN_PE12, 0); - gpio_select_periph_A(GPIO_PIN_PE13, 0); - gpio_select_periph_A(GPIO_PIN_PE14, 0); - gpio_select_periph_A(GPIO_PIN_PE15, 0); -#endif - gpio_select_periph_A(GPIO_PIN_PE26, 0); -#endif -} - -#ifdef AT32AP700x_CHIP_HAS_USART -void gpio_enable_usart0(void) -{ - gpio_select_periph_B(GPIO_PIN_PA8, 0); - gpio_select_periph_B(GPIO_PIN_PA9, 0); -} - -void gpio_enable_usart1(void) -{ - gpio_select_periph_A(GPIO_PIN_PA17, 0); - gpio_select_periph_A(GPIO_PIN_PA18, 0); -} - -void gpio_enable_usart2(void) -{ - gpio_select_periph_B(GPIO_PIN_PB26, 0); - gpio_select_periph_B(GPIO_PIN_PB27, 0); -} - -void gpio_enable_usart3(void) -{ - gpio_select_periph_B(GPIO_PIN_PB17, 0); - gpio_select_periph_B(GPIO_PIN_PB18, 0); -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_MACB -void gpio_enable_macb0(void) -{ - gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ - gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ - gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ - gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ - gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ - gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ - gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ - gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ - gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ - gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ - gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ - gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ - gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ - gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ - gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ - gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ - gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ - gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */ -#endif -} - -void gpio_enable_macb1(void) -{ - gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ - gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ - gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ - gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ - gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ - gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ - gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ - gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ - gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ - gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ -#if !defined(CONFIG_RMII) - gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ - gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ - gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ - gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ - gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ - gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ - gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ - gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ - gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */ -#endif -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_MMCI -void gpio_enable_mmci(void) -{ - gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */ - gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */ - gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */ - gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */ - gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */ - gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */ -} -#endif - -#ifdef AT32AP700x_CHIP_HAS_SPI -void gpio_enable_spi0(unsigned long cs_mask) -{ - gpio_select_periph_A(GPIO_PIN_PA0, 0); /* MISO */ - gpio_select_periph_A(GPIO_PIN_PA1, 0); /* MOSI */ - gpio_select_periph_A(GPIO_PIN_PA2, 0); /* SCK */ - - /* Set up NPCSx as GPIO outputs, initially high */ - if (cs_mask & (1 << 0)) { - gpio_set_value(GPIO_PIN_PA3, 1); - gpio_select_pio(GPIO_PIN_PA3, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 1)) { - gpio_set_value(GPIO_PIN_PA4, 1); - gpio_select_pio(GPIO_PIN_PA4, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 2)) { - gpio_set_value(GPIO_PIN_PA5, 1); - gpio_select_pio(GPIO_PIN_PA5, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 3)) { - gpio_set_value(GPIO_PIN_PA20, 1); - gpio_select_pio(GPIO_PIN_PA20, GPIOF_OUTPUT); - } -} - -void gpio_enable_spi1(unsigned long cs_mask) -{ - gpio_select_periph_B(GPIO_PIN_PA0, 0); /* MISO */ - gpio_select_periph_B(GPIO_PIN_PB1, 0); /* MOSI */ - gpio_select_periph_B(GPIO_PIN_PB5, 0); /* SCK */ - - /* Set up NPCSx as GPIO outputs, initially high */ - if (cs_mask & (1 << 0)) { - gpio_set_value(GPIO_PIN_PB2, 1); - gpio_select_pio(GPIO_PIN_PB2, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 1)) { - gpio_set_value(GPIO_PIN_PB3, 1); - gpio_select_pio(GPIO_PIN_PB3, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 2)) { - gpio_set_value(GPIO_PIN_PB4, 1); - gpio_select_pio(GPIO_PIN_PB4, GPIOF_OUTPUT); - } - if (cs_mask & (1 << 3)) { - gpio_set_value(GPIO_PIN_PA27, 1); - gpio_select_pio(GPIO_PIN_PA27, GPIOF_OUTPUT); - } -} -#endif diff --git a/cpu/at32ap/at32ap700x/portmux.c b/cpu/at32ap/at32ap700x/portmux.c new file mode 100644 index 000000000..2a3b004b0 --- /dev/null +++ b/cpu/at32ap/at32ap700x/portmux.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include + +#include +#include +#include + +/* + * Lots of small functions here. We depend on --gc-sections getting + * rid of the ones we don't need. + */ +void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, + unsigned long flags, unsigned long drive_strength) +{ + unsigned long porte_mask = 0; + + if (bus_width > 16) + portmux_select_peripheral(PORTMUX_PORT_E, 0xffff, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); + if (addr_width > 23) + porte_mask |= (((1 << (addr_width - 23)) - 1) & 7) << 16; + if (flags & PORTMUX_EBI_CS(2)) + porte_mask |= 1 << 25; + if (flags & PORTMUX_EBI_CS(4)) + porte_mask |= 1 << 21; + if (flags & PORTMUX_EBI_CS(5)) + porte_mask |= 1 << 22; + if (flags & (PORTMUX_EBI_CF(0) | PORTMUX_EBI_CF(1))) + porte_mask |= (1 << 19) | (1 << 20) | (1 << 23); + + portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, + PORTMUX_FUNC_A, 0); + + if (flags & PORTMUX_EBI_NWAIT) + portmux_select_peripheral(PORTMUX_PORT_E, 1 << 24, + PORTMUX_FUNC_A, PORTMUX_PULL_UP); +} + +#ifdef AT32AP700x_CHIP_HAS_MACB +void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength) +{ + unsigned long portc_mask; + + portc_mask = (1 << 3) /* TXD0 */ + | (1 << 4) /* TXD1 */ + | (1 << 7) /* TXEN */ + | (1 << 8) /* TXCK */ + | (1 << 9) /* RXD0 */ + | (1 << 10) /* RXD1 */ + | (1 << 13) /* RXER */ + | (1 << 15) /* RXDV */ + | (1 << 16) /* MDC */ + | (1 << 17); /* MDIO */ + + if (flags & PORTMUX_MACB_MII) + portc_mask |= (1 << 0) /* COL */ + | (1 << 1) /* CRS */ + | (1 << 2) /* TXER */ + | (1 << 5) /* TXD2 */ + | (1 << 6) /* TXD3 */ + | (1 << 11) /* RXD2 */ + | (1 << 12) /* RXD3 */ + | (1 << 14); /* RXCK */ + + if (flags & PORTMUX_MACB_SPEED) + portc_mask |= (1 << 18);/* SPD */ + + /* REVISIT: Some pins are probably pure outputs */ + portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); +} + +void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength) +{ + unsigned long portc_mask = 0; + unsigned long portd_mask; + + portd_mask = (1 << 13) /* TXD0 */ + | (1 << 14) /* TXD1 */ + | (1 << 11) /* TXEN */ + | (1 << 12) /* TXCK */ + | (1 << 10) /* RXD0 */ + | (1 << 6) /* RXD1 */ + | (1 << 5) /* RXER */ + | (1 << 4) /* RXDV */ + | (1 << 3) /* MDC */ + | (1 << 2); /* MDIO */ + + if (flags & PORTMUX_MACB_MII) + portc_mask = (1 << 19) /* COL */ + | (1 << 23) /* CRS */ + | (1 << 26) /* TXER */ + | (1 << 27) /* TXD2 */ + | (1 << 28) /* TXD3 */ + | (1 << 29) /* RXD2 */ + | (1 << 30) /* RXD3 */ + | (1 << 24); /* RXCK */ + + if (flags & PORTMUX_MACB_SPEED) + portd_mask |= (1 << 15);/* SPD */ + + /* REVISIT: Some pins are probably pure outputs */ + portmux_select_peripheral(PORTMUX_PORT_D, portc_mask, + PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); + portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, + PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); +} +#endif + +#ifdef AT32AP700x_CHIP_HAS_MMCI +void portmux_enable_mmci(unsigned int slot, unsigned long flags, + unsigned long drive_strength) +{ + unsigned long mask; + unsigned long portmux_flags = PORTMUX_PULL_UP; + + /* First, the common CLK signal. It doesn't need a pull-up */ + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 10, + PORTMUX_FUNC_A, 0); + + if (flags & PORTMUX_MMCI_EXT_PULLUP) + portmux_flags = 0; + + /* Then, the per-slot signals */ + switch (slot) { + case 0: + mask = (1 << 11) | (1 << 12); /* CMD and DATA0 */ + if (flags & PORTMUX_MMCI_4BIT) + /* DATA1..DATA3 */ + mask |= (1 << 13) | (1 << 14) | (1 << 15); + portmux_select_peripheral(PORTMUX_PORT_A, mask, + PORTMUX_FUNC_A, portmux_flags); + break; + case 1: + mask = (1 << 6) | (1 << 7); /* CMD and DATA0 */ + if (flags & PORTMUX_MMCI_4BIT) + /* DATA1..DATA3 */ + mask |= (1 << 8) | (1 << 9) | (1 << 10); + portmux_select_peripheral(PORTMUX_PORT_B, mask, + PORTMUX_FUNC_B, portmux_flags); + break; + } +} +#endif + +#ifdef AT32AP700x_CHIP_HAS_SPI +void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength) +{ + unsigned long pin_mask; + + /* MOSI and SCK */ + portmux_select_peripheral(PORTMUX_PORT_A, (1 << 1) | (1 << 2), + PORTMUX_FUNC_A, 0); + /* MISO may float */ + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 0, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); + + /* Set up NPCSx as GPIO outputs, initially high */ + pin_mask = (cs_mask & 7) << 3; + if (cs_mask & (1 << 3)) + pin_mask |= 1 << 20; + + portmux_select_gpio(PORTMUX_PORT_A, pin_mask, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); +} + +void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength) +{ + /* MOSI and SCK */ + portmux_select_peripheral(PORTMUX_PORT_B, (1 << 1) | (1 << 5), + PORTMUX_FUNC_B, 0); + /* MISO may float */ + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 0, + PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); + + /* Set up NPCSx as GPIO outputs, initially high */ + portmux_select_gpio(PORTMUX_PORT_B, (cs_mask & 7) << 2, + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); + portmux_select_gpio(PORTMUX_PORT_A, (cs_mask & 8) << (27 - 3), + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); +} +#endif diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c deleted file mode 100644 index f64004b65..000000000 --- a/cpu/at32ap/pio.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#include - -#include -#include -#include - -#include "pio2.h" - -void gpio_select_periph_A(unsigned int pin, int use_pullup) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - pio2_writel(base, ASR, mask); - pio2_writel(base, PDR, mask); - if (use_pullup) - pio2_writel(base, PUER, mask); - else - pio2_writel(base, PUDR, mask); -} - -void gpio_select_periph_B(unsigned int pin, int use_pullup) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - pio2_writel(base, BSR, mask); - pio2_writel(base, PDR, mask); - if (use_pullup) - pio2_writel(base, PUER, mask); - else - pio2_writel(base, PUDR, mask); -} - -void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - if (gpiof_flags & GPIOF_OUTPUT) { - if (gpiof_flags & GPIOF_MULTIDRV) - pio2_writel(base, MDER, mask); - else - pio2_writel(base, MDDR, mask); - pio2_writel(base, PUDR, mask); - pio2_writel(base, OER, mask); - } else { - if (gpiof_flags & GPIOF_PULLUP) - pio2_writel(base, PUER, mask); - else - pio2_writel(base, PUDR, mask); - if (gpiof_flags & GPIOF_DEGLITCH) - pio2_writel(base, IFER, mask); - else - pio2_writel(base, IFDR, mask); - pio2_writel(base, ODR, mask); - } - - pio2_writel(base, PER, mask); -} - -void gpio_set_value(unsigned int pin, int value) -{ - void *base = gpio_pin_to_addr(pin); - uint32_t mask = 1 << (pin & 0x1f); - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - if (value) - pio2_writel(base, SODR, mask); - else - pio2_writel(base, CODR, mask); -} - -int gpio_get_value(unsigned int pin) -{ - void *base = gpio_pin_to_addr(pin); - int value; - - if (!base) - panic("Invalid GPIO pin %u\n", pin); - - value = pio2_readl(base, PDSR); - return (value >> (pin & 0x1f)) & 1; -} diff --git a/cpu/at32ap/portmux-pio.c b/cpu/at32ap/portmux-pio.c new file mode 100644 index 000000000..a29f94e3b --- /dev/null +++ b/cpu/at32ap/portmux-pio.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include + +void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags) +{ + if (flags & PORTMUX_PULL_UP) + pio_writel(port, PUER, pin_mask); + else + pio_writel(port, PUDR, pin_mask); + + switch (func) { + case PORTMUX_FUNC_A: + pio_writel(port, ASR, pin_mask); + break; + case PORTMUX_FUNC_B: + pio_writel(port, BSR, pin_mask); + break; + } + + pio_writel(port, PDR, pin_mask); +} + +void portmux_select_gpio(void *port, unsigned long pin_mask, + unsigned long flags) +{ + if (flags & PORTMUX_PULL_UP) + pio_writel(port, PUER, pin_mask); + else + pio_writel(port, PUDR, pin_mask); + + if (flags & PORTMUX_OPEN_DRAIN) + pio_writel(port, MDER, pin_mask); + else + pio_writel(port, MDDR, pin_mask); + + if (flags & PORTMUX_DIR_OUTPUT) { + if (flags & PORTMUX_INIT_HIGH) + pio_writel(port, SODR, pin_mask); + else + pio_writel(port, CODR, pin_mask); + pio_writel(port, OER, pin_mask); + } else { + pio_writel(port, ODR, pin_mask); + } + + pio_writel(port, PER, pin_mask); +} + +void pio_set_output_value(unsigned int pin, int value) +{ + void *port = pio_pin_to_port(pin); + + if (!port) + panic("Invalid GPIO pin %u\n", pin); + + __pio_set_output_value(port, pin & 0x1f, value); +} + +int pio_get_input_value(unsigned int pin) +{ + void *port = pio_pin_to_port(pin); + + if (!port) + panic("Invalid GPIO pin %u\n", pin); + + return __pio_get_input_value(port, pin & 0x1f); +} diff --git a/doc/README.AVR32-port-muxing b/doc/README.AVR32-port-muxing new file mode 100644 index 000000000..b53799d33 --- /dev/null +++ b/doc/README.AVR32-port-muxing @@ -0,0 +1,208 @@ +AVR32 Port multiplexer configuration +==================================== + +On AVR32 chips, most external I/O pins are routed through a port +multiplexer. There are currently two kinds of port multiplexer +hardware around with different register interfaces: + + * PIO (AT32AP700x; this is also used on ARM AT91 chips) + * GPIO (all other AVR32 chips) + +The "PIO" variant supports multiplexing up to two peripherals per pin +in addition to GPIO (software control). Each pin has configurable +pull-up, glitch filter, interrupt and multi-drive capabilities. + +The "GPIO" variant supports multiplexing up to four peripherals per +pin in addition to GPIO. Each pin has configurable +pull-up/pull-down/buskeeper, glitch filter, interrupt, open-drain and +schmitt-trigger capabilities, as well as configurable drive strength +and slew rate control. + +Both controllers are configured using the same API, but the functions +may accept different values for some parameters depending on the +actual portmux implementation, and some parameters may be ignored by +one of the implementation (e.g. the "PIO" implementation will ignore +the drive strength flags since the hardware doesn't support +configurable drive strength.) + +Selecting the portmux implementation +------------------------------------ +Since u-boot is lacking a Kconfig-style configuration engine, the +portmux implementation must be selected manually by defining one of +the following symbols: + + CONFIG_PORTMUX_PIO + CONFIG_PORTMUX_GPIO + +depending on which implementation the chip in question uses. + +Identifying pins +---------------- +The portmux configuration functions described below identify the pins +to act on based on two parameters: A "port" (i.e. a block of pins +that somehow belong together) and a pin mask. Both are defined in an +implementation-specific manner. + +The available ports are defined on the form + + #define PORTMUX_PORT_A (something) + +where "A" matches the identifier given in the chip's data sheet, and +"something" is whatever the portmux implementation needs to identify +the port (usually a memory address). + +The pin mask is a bitmask where each '1' bit indicates a pin to apply +the current operation to. The width of the bitmask may vary from port +to port, but it is never wider than 32 bits (which is the width of +'unsigned long' on avr32). + +Selecting functions +------------------- +Each pin can either be assigned to one of a predefined set of on-chip +peripherals, or it can be set up to be controlled by software. For the +former case, the portmux implementation defines an enum containing all +the possible peripheral functions that can be selected. For example, +the PIO implementation, which allows multiplexing two peripherals per +pin, defines it like this: + + enum portmux_function { + PORTMUX_FUNC_A, + PORTMUX_FUNC_B, + }; + +To configure a set of pins to be connected to a given peripheral +function, the following function is used. + + void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags); + +To configure a set of pins to be controlled by software (GPIO), the +following function is used. In this case, no "function" argument is +required since "GPIO" is a function in its own right. + + void portmux_select_gpio(void *port, unsigned int pin_mask, + unsigned long flags); + +Both of these functions take a "flags" parameter which may be used to +alter the default configuration of the pin. This is a bitmask of +various flags defined in an implementation-specific way, but the names +of the flags are the same on all implementations. + + PORTMUX_DIR_OUTPUT + PORTMUX_DIR_INPUT + +These mutually-exlusive flags configure the initial direction of the +pins. PORTMUX_DIR_OUTPUT means that the pins are driven by the CPU, +while PORTMUX_DIR_INPUT means that the pins are tristated by the CPU. +These flags are ignored by portmux_select_peripheral(). + + PORTMUX_INIT_HIGH + PORTMUX_INIT_LOW + +These mutually-exclusive flags configure the initial state of the +pins: High (Vdd) or low (Vss). They are only effective when +portmux_select_gpio() is called with the PORTMUX_DIR_OUTPUT flag set. + + PORTMUX_PULL_UP + PORTMUX_PULL_DOWN + PORTMUX_BUSKEEPER + +These mutually-exclusive flags are used to enable any on-chip CMOS +resistors connected to the pins. PORTMUX_PULL_UP causes the pins to be +pulled up to Vdd, PORTMUX_PULL_DOWN causes the pins to be pulled down +to Vss, and PORTMUX_BUSKEEPER will keep the pins in whatever state +they were left in by whatever was driving them last. If none of the +flags are specified, the pins are left floating if no one are driving +them; this is only recommended for always-output pins (e.g. extern +address and control lines driven by the CPU.) + +Note that the "PIO" implementation will silently ignore the +PORTMUX_PULL_DOWN flag and interpret PORTMUX_BUSKEEPER as +PORTMUX_PULL_UP. + + PORTMUX_DRIVE_MIN + PORTMUX_DRIVE_LOW + PORTMUX_DRIVE_HIGH + PORTMUX_DRIVE_MAX + +These mutually-exlusive flags determine the drive strength of the +pins. PORTMUX_DRIVE_MIN will give low power-consumption, but may cause +corruption of high-speed signals. PORTMUX_DRIVE_MAX will give high +power-consumption, but may be necessary on pins toggling at very high +speeds. PORTMUX_DRIVE_LOW and PORTMUX_DRIVE_HIGH specify something in +between the other two. + +Note that setting the drive strength too high may cause excessive +overshoot and EMI problems, which may in turn cause signal corruption. +Also note that the "PIO" implementation will silently ignore these +flags. + + PORTMUX_OPEN_DRAIN + +This flag will configure the pins as "open drain", i.e. setting the +pin state to 0 will drive it low, while setting it to 1 will leave it +floating (or, in most cases, let it be pulled high by an internal or +external pull-up resistor.) In the data sheet for chips using the +"PIO" variant, this mode is called "multi-driver". + +Enabling specific peripherals +----------------------------- +In addition to the above functions, each chip provides a set of +functions for setting up the port multiplexer to use a given +peripheral. The following are some of the functions available. + +All the functions below take a "drive_strength" parameter, which must +be one of the PORTMUX_DRIVE_x flags specified above. Any other +portmux flags will be silently filtered out. + +To set up the External Bus Interface (EBI), call + + void portmux_enable_ebi(unsigned int bus_width, + unsigned long flags, unsigned long drive_strength) + +where "bus_width" must be either 16 or 32. "flags" can be any +combination of the following flags. + + PORTMUX_EBI_CS(x) /* Enable chip select x */ + PORTMUX_EBI_NAND /* Enable NAND flash interface */ + PORTMUX_EBI_CF(x) /* Enable CompactFlash interface x */ + PORTMUX_EBI_NWAIT /* Enable NWAIT signal */ + +To set up a USART, call + + void portmux_enable_usartX(unsigned long drive_strength); + +where X is replaced by the USART instance to be configured. + +To set up an ethernet MAC: + + void portmux_enable_macbX(unsigned long flags, + unsigned long drive_strength); + +where X is replaced by the MACB instance to be configured. "flags" can +be any combination of the following flags. + + PORTMUX_MACB_RMII /* Just set up the RMII interface */ + PORTMUX_MACB_MII /* Set up full MII interface */ + PORTMUX_MACB_SPEED /* Enable the SPEED pin */ + +To set up the MMC controller: + + void portmux_enable_mmci(unsigned long slot, unsigned long flags + unsigned long drive_strength); + +where "slot" identifies which of the alternative SD card slots to +enable. "flags" can be any combination of the following flags: + + PORTMUX_MMCI_4BIT /* Enable 4-bit SD card interface */ + PORTMUX_MMCI_8BIT /* Enable 8-bit MMC+ interface */ + PORTMUX_MMCI_EXT_PULLUP /* Board has external pull-ups */ + +To set up a SPI controller: + + void portmux_enable_spiX(unsigned long cs_mask, + unsigned long drive_strength); + +where X is replaced by the SPI instance to be configured. "cs_mask" is +a 4-bit bitmask specifying which of the four standard chip select +lines to set up as GPIOs. diff --git a/include/asm-avr32/arch-at32ap700x/gpio.h b/include/asm-avr32/arch-at32ap700x/gpio.h index 8c922c7c6..303e35313 100644 --- a/include/asm-avr32/arch-at32ap700x/gpio.h +++ b/include/asm-avr32/arch-at32ap700x/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Atmel Corporation + * Copyright (C) 2006, 2008 Atmel Corporation * * See file CREDITS for list of people who contributed to this * project. @@ -31,161 +31,17 @@ * Pin numbers identifying specific GPIO pins on the chip. */ #define GPIO_PIOA_BASE (0) -#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0) -#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1) -#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2) -#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3) -#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4) -#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5) -#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6) -#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7) -#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8) -#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9) -#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10) -#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11) -#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12) -#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13) -#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14) -#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15) -#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16) -#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17) -#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18) -#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19) -#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20) -#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21) -#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22) -#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23) -#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24) -#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25) -#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26) -#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27) -#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28) -#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29) -#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30) -#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31) - #define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32) -#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0) -#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1) -#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2) -#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3) -#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4) -#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5) -#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6) -#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7) -#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8) -#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9) -#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10) -#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11) -#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12) -#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13) -#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14) -#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15) -#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16) -#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17) -#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18) -#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19) -#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20) -#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21) -#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22) -#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23) -#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24) -#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25) -#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26) -#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27) -#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28) -#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29) -#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30) - #define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32) -#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0) -#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1) -#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2) -#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3) -#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4) -#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5) -#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6) -#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7) -#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8) -#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9) -#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10) -#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11) -#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12) -#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13) -#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14) -#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15) -#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16) -#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17) -#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18) -#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19) -#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20) -#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21) -#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22) -#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23) -#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24) -#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25) -#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26) -#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27) -#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28) -#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29) -#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30) -#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31) - #define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32) -#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0) -#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1) -#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2) -#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3) -#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4) -#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5) -#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6) -#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7) -#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8) -#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9) -#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10) -#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11) -#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12) -#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13) -#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14) -#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15) -#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16) -#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17) - #define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32) -#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0) -#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1) -#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2) -#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3) -#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4) -#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5) -#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6) -#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7) -#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8) -#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9) -#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10) -#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11) -#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12) -#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13) -#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14) -#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15) -#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16) -#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17) -#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18) -#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19) -#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20) -#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21) -#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22) -#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23) -#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24) -#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25) -#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26) +#define GPIO_PIN_PA(x) (GPIO_PIOA_BASE + (x)) +#define GPIO_PIN_PB(x) (GPIO_PIOB_BASE + (x)) +#define GPIO_PIN_PC(x) (GPIO_PIOC_BASE + (x)) +#define GPIO_PIN_PD(x) (GPIO_PIOD_BASE + (x)) +#define GPIO_PIN_PE(x) (GPIO_PIOE_BASE + (x)) -#define GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */ -#define GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */ -#define GPIOF_DEGLITCH 0x00000004 /* (IN) Filter glitches */ -#define GPIOF_MULTIDRV 0x00000008 /* Enable multidriver option */ - -static inline void *gpio_pin_to_addr(unsigned int pin) +static inline void *pio_pin_to_port(unsigned int pin) { switch (pin >> 5) { case 0: @@ -203,30 +59,6 @@ static inline void *gpio_pin_to_addr(unsigned int pin) } } -void gpio_select_periph_A(unsigned int pin, int use_pullup); -void gpio_select_periph_B(unsigned int pin, int use_pullup); -void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags); -void gpio_set_value(unsigned int pin, int value); -int gpio_get_value(unsigned int pin); - -void gpio_enable_ebi(void); - -#ifdef AT32AP700x_CHIP_HAS_USART -void gpio_enable_usart0(void); -void gpio_enable_usart1(void); -void gpio_enable_usart2(void); -void gpio_enable_usart3(void); -#endif -#ifdef AT32AP700x_CHIP_HAS_MACB -void gpio_enable_macb0(void); -void gpio_enable_macb1(void); -#endif -#ifdef AT32AP700x_CHIP_HAS_MMCI -void gpio_enable_mmci(void); -#endif -#ifdef AT32AP700x_CHIP_HAS_SPI -void gpio_enable_spi0(unsigned long cs_mask); -void gpio_enable_spi1(unsigned long cs_mask); -#endif +#include #endif /* __ASM_AVR32_ARCH_GPIO_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/include/asm-avr32/arch-at32ap700x/portmux.h new file mode 100644 index 000000000..96fe70d4b --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/portmux.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_PORTMUX_H__ +#define __ASM_AVR32_ARCH_PORTMUX_H__ + +#include + +#define PORTMUX_PORT_A ((void *)PIOA_BASE) +#define PORTMUX_PORT_B ((void *)PIOB_BASE) +#define PORTMUX_PORT_C ((void *)PIOC_BASE) +#define PORTMUX_PORT_D ((void *)PIOD_BASE) +#define PORTMUX_PORT_E ((void *)PIOE_BASE) + +void portmux_enable_ebi(unsigned int bus_width, unsigned int addr_width, + unsigned long flags, unsigned long drive_strength); + +#define PORTMUX_EBI_CS(x) (1 << (x)) +#define PORTMUX_EBI_NAND (1 << 6) +#define PORTMUX_EBI_CF(x) (1 << ((x) + 7)) +#define PORTMUX_EBI_NWAIT (1 << 9) + +#ifdef AT32AP700x_CHIP_HAS_USART +static inline void portmux_enable_usart0(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_A, (1 << 8) | (1 << 9), + PORTMUX_FUNC_B, 0); +} + +static inline void portmux_enable_usart1(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_A, (1 << 17) | (1 << 18), + PORTMUX_FUNC_A, 0); +} + +static inline void portmux_enable_usart2(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_B, (1 << 26) | (1 << 27), + PORTMUX_FUNC_B, 0); +} + +static inline void portmux_enable_usart3(unsigned long drive_strength) +{ + portmux_select_peripheral(PORTMUX_PORT_B, (1 << 17) | (1 << 18), + PORTMUX_FUNC_B, 0); +} +#endif +#ifdef AT32AP700x_CHIP_HAS_MACB +void portmux_enable_macb0(unsigned long flags, unsigned long drive_strength); +void portmux_enable_macb1(unsigned long flags, unsigned long drive_strength); + +#define PORTMUX_MACB_RMII (0) +#define PORTMUX_MACB_MII (1 << 0) +#define PORTMUX_MACB_SPEED (1 << 1) + +#endif +#ifdef AT32AP700x_CHIP_HAS_MMCI +void portmux_enable_mmci(unsigned int slot, unsigned long flags, + unsigned long drive_strength); + +#define PORTMUX_MMCI_4BIT (1 << 0) +#define PORTMUX_MMCI_8BIT (PORTMUX_MMCI_4BIT | (1 << 1)) +#define PORTMUX_MMCI_EXT_PULLUP (1 << 2) + +#endif +#ifdef AT32AP700x_CHIP_HAS_SPI +void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength); +void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength); +#endif + +#endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */ diff --git a/include/asm-avr32/arch-common/portmux-pio.h b/include/asm-avr32/arch-common/portmux-pio.h new file mode 100644 index 000000000..1abe5be25 --- /dev/null +++ b/include/asm-avr32/arch-common/portmux-pio.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2006, 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __AVR32_PORTMUX_PIO_H__ +#define __AVR32_PORTMUX_PIO_H__ + +#include + +/* PIO register offsets */ +#define PIO_PER 0x0000 +#define PIO_PDR 0x0004 +#define PIO_PSR 0x0008 +#define PIO_OER 0x0010 +#define PIO_ODR 0x0014 +#define PIO_OSR 0x0018 +#define PIO_IFER 0x0020 +#define PIO_IFDR 0x0024 +#define PIO_ISFR 0x0028 +#define PIO_SODR 0x0030 +#define PIO_CODR 0x0034 +#define PIO_ODSR 0x0038 +#define PIO_PDSR 0x003c +#define PIO_IER 0x0040 +#define PIO_IDR 0x0044 +#define PIO_IMR 0x0048 +#define PIO_ISR 0x004c +#define PIO_MDER 0x0050 +#define PIO_MDDR 0x0054 +#define PIO_MDSR 0x0058 +#define PIO_PUDR 0x0060 +#define PIO_PUER 0x0064 +#define PIO_PUSR 0x0068 +#define PIO_ASR 0x0070 +#define PIO_BSR 0x0074 +#define PIO_ABSR 0x0078 +#define PIO_OWER 0x00a0 +#define PIO_OWDR 0x00a4 +#define PIO_OWSR 0x00a8 + +/* Hardware register access */ +#define pio_readl(base, reg) \ + __raw_readl((void *)base + PIO_##reg) +#define pio_writel(base, reg, value) \ + __raw_writel((value), (void *)base + PIO_##reg) + +/* Portmux API starts here. See doc/README.AVR32-port-muxing */ + +enum portmux_function { + PORTMUX_FUNC_A, + PORTMUX_FUNC_B, +}; + +/* Pull-down, buskeeper and drive strength are not supported */ +#define PORTMUX_DIR_INPUT (0 << 0) +#define PORTMUX_DIR_OUTPUT (1 << 0) +#define PORTMUX_INIT_LOW (0 << 1) +#define PORTMUX_INIT_HIGH (1 << 1) +#define PORTMUX_PULL_UP (1 << 2) +#define PORTMUX_PULL_DOWN (0) +#define PORTMUX_BUSKEEPER PORTMUX_PULL_UP +#define PORTMUX_DRIVE_MIN (0) +#define PORTMUX_DRIVE_LOW (0) +#define PORTMUX_DRIVE_HIGH (0) +#define PORTMUX_DRIVE_MAX (0) +#define PORTMUX_OPEN_DRAIN (1 << 3) + +void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags); +void portmux_select_gpio(void *port, unsigned long pin_mask, + unsigned long flags); + +/* Internal helper functions */ + +static inline void __pio_set_output_value(void *port, unsigned int pin, + int value) +{ + /* + * value will usually be constant, but it's pretty cheap + * either way. + */ + if (value) + pio_writel(port, SODR, 1 << pin); + else + pio_writel(port, CODR, 1 << pin); +} + +static inline int __pio_get_input_value(void *port, unsigned int pin) +{ + return (pio_readl(port, PDSR) >> pin) & 1; +} + +void pio_set_output_value(unsigned int pin, int value); +int pio_get_input_value(unsigned int pin); + +/* GPIO API starts here */ + +/* + * GCC doesn't realize that the constant case is extremely trivial, + * so we need to help it make the right decision by using + * always_inline. + */ +__attribute__((always_inline)) +static inline void gpio_set_value(unsigned int pin, int value) +{ + if (__builtin_constant_p(pin)) + __pio_set_output_value(pio_pin_to_port(pin), pin & 0x1f, value); + else + pio_set_output_value(pin, value); +} + +__attribute__((always_inline)) +static inline int gpio_get_value(unsigned int pin) +{ + if (__builtin_constant_p(pin)) + return __pio_get_input_value(pio_pin_to_port(pin), pin & 0x1f); + else + return pio_get_input_value(pin); +} + +#endif /* __AVR32_PORTMUX_PIO_H__ */ diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 6d8c1b22a..323b096ab 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -124,7 +124,7 @@ #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 3a7d27354..85cedb2fb 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -149,7 +149,7 @@ #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h index 55ea7f290..9aa0692c0 100644 --- a/include/configs/atstk1003.h +++ b/include/configs/atstk1003.h @@ -133,7 +133,7 @@ #undef CONFIG_CMD_XIMG #define CONFIG_ATMEL_USART 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 #define CONFIG_ATMEL_MCI 1 diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h index 369c61964..d8ce339c2 100644 --- a/include/configs/atstk1004.h +++ b/include/configs/atstk1004.h @@ -133,7 +133,7 @@ #undef CONFIG_CMD_XIMG #define CONFIG_ATMEL_USART 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 #define CONFIG_ATMEL_MCI 1 diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index 902f822e4..d4b2f12aa 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -149,7 +149,7 @@ #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index a27c02ad2..3c9420cf9 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -146,7 +146,7 @@ #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index c44d62eb0..fca411186 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -117,7 +117,7 @@ #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 57f64ba40..0506b93c7 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -121,7 +121,7 @@ #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 -#define CONFIG_PIO2 1 +#define CONFIG_PORTMUX_PIO 1 #define CFG_NR_PIOS 5 #define CFG_HSDRAMC 1 #define CONFIG_MMC 1 -- cgit v1.2.3 From 98090cd75cdb40b2ab94c806c338540a5716748b Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 31 Aug 2008 18:05:32 +0200 Subject: avr32: Add gclk helper functions Add two helper functions for configuring and enabling generic clocks: - gclk_enable_output: Enables output on a GCLKx pin - gclk_set_rate: Configures a gclk to run at a specific rate This should eliminate any reason to go mucking about with PM registers from board code. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/at32ap700x/clk.c | 25 +++++++++ include/asm-avr32/arch-at32ap700x/clk.h | 99 ++++++++++++++++++++++++++++++++- 2 files changed, 122 insertions(+), 2 deletions(-) (limited to 'include/asm-avr32') diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c index b3aa03495..a6a6c885e 100644 --- a/cpu/at32ap/at32ap700x/clk.c +++ b/cpu/at32ap/at32ap700x/clk.c @@ -25,6 +25,7 @@ #include #include +#include #include "sm.h" @@ -66,3 +67,27 @@ void clk_init(void) sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); #endif } + +unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, + unsigned long rate, unsigned long parent_rate) +{ + unsigned long divider; + + if (rate == 0 || parent_rate == 0) { + sm_writel(PM_GCCTRL(id), 0); + return 0; + } + + divider = (parent_rate + rate / 2) / rate; + if (divider <= 1) { + sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN)); + rate = parent_rate; + } else { + divider = min(255, divider / 2 - 1); + sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN) + | SM_BF(DIV, divider)); + rate = parent_rate / (2 * (divider + 1)); + } + + return rate; +} diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index e9a4fe4d6..b2710a4ba 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -23,11 +23,13 @@ #define __ASM_AVR32_ARCH_CLK_H__ #include +#include #ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#define PLL0_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#define MAIN_CLK_RATE PLL0_RATE #else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#define MAIN_CLK_RATE (CFG_OSC0_HZ) #endif static inline unsigned long get_cpu_clk_rate(void) @@ -87,4 +89,97 @@ extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) +/* Generic clock control */ +enum gclk_parent { + GCLK_PARENT_OSC0 = 0, + GCLK_PARENT_OSC1 = 1, + GCLK_PARENT_PLL0 = 2, + GCLK_PARENT_PLL1 = 3, +}; + +/* Some generic clocks have specific roles */ +#define GCLK_DAC_SAMPLE_CLK 6 +#define GCLK_LCDC_PIXCLK 7 + +extern unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent, + unsigned long rate, unsigned long parent_rate); + +/** + * gclk_set_rate - configure and enable a generic clock + * @id: Which GCLK[id] to enable + * @parent: Parent clock feeding the GCLK + * @rate: Target rate of the GCLK in Hz + * + * Returns the actual GCLK rate in Hz, after rounding to the nearest + * supported rate. + * + * All three parameters are usually constant, hence the inline. + */ +static inline unsigned long gclk_set_rate(unsigned int id, + enum gclk_parent parent, unsigned long rate) +{ + unsigned long parent_rate; + + if (id > 7) + return 0; + + switch (parent) { + case GCLK_PARENT_OSC0: + parent_rate = CFG_OSC0_HZ; + break; +#ifdef CFG_OSC1_HZ + case GCLK_PARENT_OSC1: + parent_rate = CFG_OSC1_HZ; + break; +#endif +#ifdef PLL0_RATE + case GCLK_PARENT_PLL0: + parent_rate = PLL0_RATE; + break; +#endif +#ifdef PLL1_RATE + case GCLK_PARENT_PLL1: + parent_rate = PLL1_RATE; + break; +#endif + default: + parent_rate = 0; + break; + } + + return __gclk_set_rate(id, parent, rate, parent_rate); +} + +/** + * gclk_enable_output - enable output on a GCLK pin + * @id: Which GCLK[id] pin to enable + * @drive_strength: Drive strength of external GCLK pin, if applicable + */ +static inline void gclk_enable_output(unsigned int id, + unsigned long drive_strength) +{ + switch (id) { + case 0: + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 30, + PORTMUX_FUNC_A, drive_strength); + break; + case 1: + portmux_select_peripheral(PORTMUX_PORT_A, 1 << 31, + PORTMUX_FUNC_A, drive_strength); + break; + case 2: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 19, + PORTMUX_FUNC_A, drive_strength); + break; + case 3: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 29, + PORTMUX_FUNC_A, drive_strength); + break; + case 4: + portmux_select_peripheral(PORTMUX_PORT_B, 1 << 30, + PORTMUX_FUNC_A, drive_strength); + break; + } +} + #endif /* __ASM_AVR32_ARCH_CLK_H__ */ -- cgit v1.2.3 From 36d375faf5cff98e8dca32aabbbb1ec6036437dd Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 31 Aug 2008 18:24:24 +0200 Subject: avr32: Use board_postclk_init instead of gclk_init Replace the avr32-specific gclk_init() board hook with the standard board_postclk_init() hook which is supposed to run at the same point during initialization. Provide a dummy weak alias for boards not implementing this hook. The cost of this is: - 2 bytes for the dummy function (retal 0) - 2 bytes for each unnecessary function call (short rcall) which is a pretty small price to pay for avoiding lots of #ifdef clutter. In this particular case, all boards probably end up slightly smaller because we avoid the conditional checking if the gclk_init symbol is NULL. Signed-off-by: Haavard Skinnemoen --- board/miromico/hammerhead/hammerhead.c | 3 ++- cpu/at32ap/cpu.c | 3 --- include/asm-avr32/arch-at32ap700x/clk.h | 1 - lib_avr32/board.c | 8 ++++++++ 4 files changed, 10 insertions(+), 5 deletions(-) (limited to 'include/asm-avr32') diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index bf432cba8..867052789 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -100,9 +100,10 @@ void board_init_info(void) gd->bd->bi_phy_id[0] = 0x01; } -void gclk_init(void) +int board_postclk_init(void) { /* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */ gclk_enable_output(3, PORTMUX_DRIVE_LOW); gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000); + return 0; } diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c index 1a1370289..0ba836180 100644 --- a/cpu/at32ap/cpu.c +++ b/cpu/at32ap/cpu.c @@ -65,9 +65,6 @@ int cpu_init(void) sysreg_write(EVBA, (unsigned long)&_evba); asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET)); - if(gclk_init) - gclk_init(); - return 0; } diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index b2710a4ba..21545a3c1 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -84,7 +84,6 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id) #endif extern void clk_init(void); -extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ #define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) diff --git a/lib_avr32/board.c b/lib_avr32/board.c index d6423d4f3..19d76d2ca 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -47,6 +47,13 @@ static unsigned long mem_malloc_start = 0; static unsigned long mem_malloc_end = 0; static unsigned long mem_malloc_brk = 0; +/* Weak aliases for optional board functions */ +static int __do_nothing(void) +{ + return 0; +} +int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); + /* The malloc area is right below the monitor image in RAM */ static void mem_malloc_init(void) { @@ -187,6 +194,7 @@ void board_init_f(ulong board_type) /* Perform initialization sequence */ board_early_init_f(); cpu_init(); + board_postclk_init(); env_init(); init_baudrate(); serial_init(); -- cgit v1.2.3 From 25e6854d42c11046a468576179b5494f850311b2 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Sun, 31 Aug 2008 18:46:35 +0200 Subject: avr32: use board_early_init_r instead of board_init_info Replace the avr32-specific board_init_info hook by the standard board_early_init_r hook and make it optional. board_early_init_r() runs somewhat earlier than board_init_info used to do, but this isn't a problem for any of the in-tree boards. Signed-off-by: Haavard Skinnemoen --- board/atmel/atngw100/atngw100.c | 3 ++- board/atmel/atstk1000/atstk1000.c | 3 ++- board/earthlcd/favr-32-ezkit/favr-32-ezkit.c | 3 ++- board/mimc/mimc200/mimc200.c | 3 ++- board/miromico/hammerhead/hammerhead.c | 3 ++- include/asm-avr32/initcalls.h | 1 - lib_avr32/board.c | 4 +++- 7 files changed, 13 insertions(+), 7 deletions(-) (limited to 'include/asm-avr32') diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index 03544aa21..480d5255f 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -88,10 +88,11 @@ phys_size_t initdram(int board_type) return actual_size; } -void board_init_info(void) +int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; gd->bd->bi_phy_id[1] = 0x03; + return 0; } extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index cc400a92f..7be39931e 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -110,10 +110,11 @@ phys_size_t initdram(int board_type) return actual_size; } -void board_init_info(void) +int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x10; gd->bd->bi_phy_id[1] = 0x11; + return 0; } extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c index b2ddd089d..d53ca4c13 100644 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -81,9 +81,10 @@ phys_size_t initdram(int board_type) return actual_size; } -void board_init_info(void) +int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; + return 0; } #if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET) diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 4da467860..c30bcb6d3 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -124,10 +124,11 @@ phys_size_t initdram(int board_type) return actual_size; } -void board_init_info(void) +int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; gd->bd->bi_phy_id[1] = 0x03; + return 0; } /* SPI chip select control */ diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index 867052789..7fd078125 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -95,9 +95,10 @@ phys_size_t initdram(int board_type) return actual_size; } -void board_init_info(void) +int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; + return 0; } int board_postclk_init(void) diff --git a/include/asm-avr32/initcalls.h b/include/asm-avr32/initcalls.h index 583e5dc10..57a278b6a 100644 --- a/include/asm-avr32/initcalls.h +++ b/include/asm-avr32/initcalls.h @@ -26,6 +26,5 @@ extern int cpu_init(void); extern int timer_init(void); -extern void board_init_info(void); #endif /* __ASM_AVR32_INITCALLS_H__ */ diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 19d76d2ca..4ed6c9663 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -53,6 +53,7 @@ static int __do_nothing(void) return 0; } int board_postclk_init(void) __attribute__((weak, alias("__do_nothing"))); +int board_early_init_r(void) __attribute__((weak, alias("__do_nothing"))); /* The malloc area is right below the monitor image in RAM */ static void mem_malloc_init(void) @@ -282,6 +283,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) gd->flags |= GD_FLG_RELOC; gd->reloc_off = dest_addr - CFG_MONITOR_BASE; + board_early_init_r(); + monitor_flash_len = _edata - _text; /* @@ -318,7 +321,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) mem_malloc_init(); malloc_bin_reloc(); dma_alloc_init(); - board_init_info(); enable_interrupts(); -- cgit v1.2.3 From baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 Mon Sep 17 00:00:00 2001 From: Haavard Skinnemoen Date: Mon, 1 Sep 2008 14:00:07 +0200 Subject: avr32: Add support for "GPIO" port mux The "GPIO" port mux is used on AVR32 UC3 parts as well as AT32AP7200 and all later AVR32 chips. This patch adds a driver for it, implementing the same API as the existing portmux-pio driver but with more functionality. Signed-off-by: Haavard Skinnemoen --- cpu/at32ap/Makefile | 1 + cpu/at32ap/portmux-gpio.c | 107 +++++++++++++++ include/asm-avr32/arch-common/portmux-gpio.h | 193 +++++++++++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 cpu/at32ap/portmux-gpio.c create mode 100644 include/asm-avr32/arch-common/portmux-gpio.h (limited to 'include/asm-avr32') diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index 100cf3e74..e08f27383 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -35,6 +35,7 @@ COBJS-y += exception.o COBJS-y += cache.o COBJS-y += interrupts.o COBJS-$(CONFIG_PORTMUX_PIO) += portmux-pio.o +COBJS-$(CONFIG_PORTMUX_GPIO) += portmux-gpio.o SRCS := $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/at32ap/portmux-gpio.c b/cpu/at32ap/portmux-gpio.c new file mode 100644 index 000000000..9acd040d1 --- /dev/null +++ b/cpu/at32ap/portmux-gpio.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include + +#include +#include +#include + +void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags) +{ + /* Both pull-up and pull-down set means buskeeper */ + if (flags & PORTMUX_PULL_DOWN) + gpio_writel(port, PDERS, pin_mask); + else + gpio_writel(port, PDERC, pin_mask); + if (flags & PORTMUX_PULL_UP) + gpio_writel(port, PUERS, pin_mask); + else + gpio_writel(port, PUERC, pin_mask); + + /* Select drive strength */ + if (flags & PORTMUX_DRIVE_LOW) + gpio_writel(port, ODCR0S, pin_mask); + else + gpio_writel(port, ODCR0C, pin_mask); + if (flags & PORTMUX_DRIVE_HIGH) + gpio_writel(port, ODCR1S, pin_mask); + else + gpio_writel(port, ODCR1C, pin_mask); + + /* Select function */ + if (func & PORTMUX_FUNC_B) + gpio_writel(port, PMR0S, pin_mask); + else + gpio_writel(port, PMR0C, pin_mask); + if (func & PORTMUX_FUNC_C) + gpio_writel(port, PMR1S, pin_mask); + else + gpio_writel(port, PMR1C, pin_mask); + + /* Disable GPIO (i.e. enable peripheral) */ + gpio_writel(port, GPERC, pin_mask); +} + +void portmux_select_gpio(void *port, unsigned long pin_mask, + unsigned long flags) +{ + /* Both pull-up and pull-down set means buskeeper */ + if (flags & PORTMUX_PULL_DOWN) + gpio_writel(port, PDERS, pin_mask); + else + gpio_writel(port, PDERC, pin_mask); + if (flags & PORTMUX_PULL_UP) + gpio_writel(port, PUERS, pin_mask); + else + gpio_writel(port, PUERC, pin_mask); + + /* Enable open-drain mode if requested */ + if (flags & PORTMUX_OPEN_DRAIN) + gpio_writel(port, ODMERS, pin_mask); + else + gpio_writel(port, ODMERC, pin_mask); + + /* Select drive strength */ + if (flags & PORTMUX_DRIVE_LOW) + gpio_writel(port, ODCR0S, pin_mask); + else + gpio_writel(port, ODCR0C, pin_mask); + if (flags & PORTMUX_DRIVE_HIGH) + gpio_writel(port, ODCR1S, pin_mask); + else + gpio_writel(port, ODCR1C, pin_mask); + + /* Select direction and initial pin state */ + if (flags & PORTMUX_DIR_OUTPUT) { + if (flags & PORTMUX_INIT_HIGH) + gpio_writel(port, OVRS, pin_mask); + else + gpio_writel(port, OVRC, pin_mask); + gpio_writel(port, ODERS, pin_mask); + } else { + gpio_writel(port, ODERC, pin_mask); + } + + /* Enable GPIO */ + gpio_writel(port, GPERS, pin_mask); +} diff --git a/include/asm-avr32/arch-common/portmux-gpio.h b/include/asm-avr32/arch-common/portmux-gpio.h new file mode 100644 index 000000000..24943ecdb --- /dev/null +++ b/include/asm-avr32/arch-common/portmux-gpio.h @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2008 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __AVR32_PORTMUX_GPIO_H__ +#define __AVR32_PORTMUX_GPIO_H__ + +#include + +/* Register offsets */ +struct gpio_regs { + u32 GPER; + u32 GPERS; + u32 GPERC; + u32 GPERT; + u32 PMR0; + u32 PMR0S; + u32 PMR0C; + u32 PMR0T; + u32 PMR1; + u32 PMR1S; + u32 PMR1C; + u32 PMR1T; + u32 __reserved0[4]; + u32 ODER; + u32 ODERS; + u32 ODERC; + u32 ODERT; + u32 OVR; + u32 OVRS; + u32 OVRC; + u32 OVRT; + u32 PVR; + u32 __reserved_PVRS; + u32 __reserved_PVRC; + u32 __reserved_PVRT; + u32 PUER; + u32 PUERS; + u32 PUERC; + u32 PUERT; + u32 PDER; + u32 PDERS; + u32 PDERC; + u32 PDERT; + u32 IER; + u32 IERS; + u32 IERC; + u32 IERT; + u32 IMR0; + u32 IMR0S; + u32 IMR0C; + u32 IMR0T; + u32 IMR1; + u32 IMR1S; + u32 IMR1C; + u32 IMR1T; + u32 GFER; + u32 GFERS; + u32 GFERC; + u32 GFERT; + u32 IFR; + u32 __reserved_IFRS; + u32 IFRC; + u32 __reserved_IFRT; + u32 ODMER; + u32 ODMERS; + u32 ODMERC; + u32 ODMERT; + u32 __reserved1[4]; + u32 ODCR0; + u32 ODCR0S; + u32 ODCR0C; + u32 ODCR0T; + u32 ODCR1; + u32 ODCR1S; + u32 ODCR1C; + u32 ODCR1T; + u32 __reserved2[4]; + u32 OSRR0; + u32 OSRR0S; + u32 OSRR0C; + u32 OSRR0T; + u32 __reserved3[8]; + u32 STER; + u32 STERS; + u32 STERC; + u32 STERT; + u32 __reserved4[35]; + u32 VERSION; +}; + +/* Register access macros */ +#define gpio_readl(port, reg) \ + __raw_readl(&((struct gpio_regs *)port)->reg) +#define gpio_writel(gpio, reg, value) \ + __raw_writel(value, &((struct gpio_regs *)port)->reg) + +/* Portmux API starts here. See doc/README.AVR32-port-muxing */ + +enum portmux_function { + PORTMUX_FUNC_A, + PORTMUX_FUNC_B, + PORTMUX_FUNC_C, + PORTMUX_FUNC_D, +}; + +#define PORTMUX_DIR_INPUT (0 << 0) +#define PORTMUX_DIR_OUTPUT (1 << 0) +#define PORTMUX_INIT_LOW (0 << 1) +#define PORTMUX_INIT_HIGH (1 << 1) +#define PORTMUX_PULL_UP (1 << 2) +#define PORTMUX_PULL_DOWN (2 << 2) +#define PORTMUX_BUSKEEPER (3 << 2) +#define PORTMUX_DRIVE_MIN (0 << 4) +#define PORTMUX_DRIVE_LOW (1 << 4) +#define PORTMUX_DRIVE_HIGH (2 << 4) +#define PORTMUX_DRIVE_MAX (3 << 4) +#define PORTMUX_OPEN_DRAIN (1 << 6) + +void portmux_select_peripheral(void *port, unsigned long pin_mask, + enum portmux_function func, unsigned long flags); +void portmux_select_gpio(void *port, unsigned long pin_mask, + unsigned long flags); + +/* Internal helper functions */ + +static inline void *gpio_pin_to_port(unsigned int pin) +{ + return (void *)GPIO_BASE + (pin >> 5) * 0x200; +} + +static inline void __gpio_set_output_value(void *port, unsigned int pin, + int value) +{ + if (value) + gpio_writel(port, OVRS, 1 << pin); + else + gpio_writel(port, OVRC, 1 << pin); +} + +static inline int __gpio_get_input_value(void *port, unsigned int pin) +{ + return (gpio_readl(port, PVR) >> pin) & 1; +} + +void gpio_set_output_value(unsigned int pin, int value); +int gpio_get_input_value(unsigned int pin); + +/* GPIO API starts here */ + +/* + * GCC doesn't realize that the constant case is extremely trivial, + * so we need to help it make the right decision by using + * always_inline. + */ +__attribute__((always_inline)) +static inline void gpio_set_value(unsigned int pin, int value) +{ + if (__builtin_constant_p(pin)) + __gpio_set_output_value(gpio_pin_to_port(pin), + pin & 0x1f, value); + else + gpio_set_output_value(pin, value); +} + +__attribute__((always_inline)) +static inline int gpio_get_value(unsigned int pin) +{ + if (__builtin_constant_p(pin)) + return __gpio_get_input_value(gpio_pin_to_port(pin), + pin & 0x1f); + else + return gpio_get_input_value(pin); +} + +#endif /* __AVR32_PORTMUX_GPIO_H__ */ -- cgit v1.2.3 From d8f2aa3298610b44127dbc4796d8038aa5847e0b Mon Sep 17 00:00:00 2001 From: Olav Morken Date: Fri, 23 Jan 2009 12:56:27 +0100 Subject: AVR32: Make cacheflush cpu-dependent The AT32UC3A series of processors doesn't contain any cache, and issuing cache control instructions on those will cause an exception. This commit makes cacheflush.h arch-dependent in preparation for the AT32UC3A-support. Signed-off-by: Gunnar Rangoy Signed-off-by: Paul Driveklepp Signed-off-by: Olav Morken Signed-off-by: Haavard Skinnemoen --- board/atmel/atstk1000/flash.c | 2 +- board/earthlcd/favr-32-ezkit/flash.c | 2 +- cpu/at32ap/cache.c | 2 +- include/asm-avr32/dma-mapping.h | 2 +- lib_avr32/board.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include/asm-avr32') diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c index 4d380f3fa..0ba06ddc5 100644 --- a/board/atmel/atstk1000/flash.c +++ b/board/atmel/atstk1000/flash.c @@ -22,7 +22,7 @@ #include #ifdef CONFIG_ATSTK1000_EXT_FLASH -#include +#include #include #include diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c index 5f73ff04d..0a2614667 100644 --- a/board/earthlcd/favr-32-ezkit/flash.c +++ b/board/earthlcd/favr-32-ezkit/flash.c @@ -20,7 +20,7 @@ #include #ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH -#include +#include #include #include diff --git a/cpu/at32ap/cache.c b/cpu/at32ap/cache.c index 16a0565df..28b945669 100644 --- a/cpu/at32ap/cache.c +++ b/cpu/at32ap/cache.c @@ -22,7 +22,7 @@ #include -#include +#include void dcache_clean_range(volatile void *start, size_t size) { diff --git a/include/asm-avr32/dma-mapping.h b/include/asm-avr32/dma-mapping.h index 3b46fa3e6..0be7804da 100644 --- a/include/asm-avr32/dma-mapping.h +++ b/include/asm-avr32/dma-mapping.h @@ -23,7 +23,7 @@ #define __ASM_AVR32_DMA_MAPPING_H #include -#include +#include enum dma_data_direction { DMA_BIDIRECTIONAL = 0, diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 959375a48..57115df09 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -86,7 +86,7 @@ void *sbrk(ptrdiff_t increment) } #ifdef CONFIG_SYS_DMA_ALLOC_LEN -#include +#include #include static unsigned long dma_alloc_start; -- cgit v1.2.3 From a38de083d2979db3680f0d0978c509a172c8fa00 Mon Sep 17 00:00:00 2001 From: Olav Morken Date: Fri, 23 Jan 2009 12:56:28 +0100 Subject: AVR32: Move addrspace.h to arch-directory, and move some functions from io.h to addrspace.h The AVR32A architecture (which AT32UC3A-series is based on) has a different memory layout than the AVR32B-architecture. This patch moves addrspace.h to an arch-dependent directory in preparation for AT32UC3A-support. It also moves some address-space manipulation functions from io.h to addrspace.h. Signed-off-by: Gunnar Rangoy Signed-off-by: Paul Driveklepp Signed-off-by: Olav Morken Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/addrspace.h | 46 --------------- include/asm-avr32/arch-at32ap700x/addrspace.h | 84 +++++++++++++++++++++++++++ include/asm-avr32/io.h | 39 +------------ lib_avr32/bootm.c | 2 +- 4 files changed, 87 insertions(+), 84 deletions(-) delete mode 100644 include/asm-avr32/addrspace.h create mode 100644 include/asm-avr32/arch-at32ap700x/addrspace.h (limited to 'include/asm-avr32') diff --git a/include/asm-avr32/addrspace.h b/include/asm-avr32/addrspace.h deleted file mode 100644 index b2ba1ee2f..000000000 --- a/include/asm-avr32/addrspace.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (C) 2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_ADDRSPACE_H -#define __ASM_AVR32_ADDRSPACE_H - -/* Memory segments when segmentation is enabled */ -#define P0SEG 0x00000000 -#define P1SEG 0x80000000 -#define P2SEG 0xa0000000 -#define P3SEG 0xc0000000 -#define P4SEG 0xe0000000 - -/* Returns the privileged segment base of a given address */ -#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) - -/* Returns the physical address of a PnSEG (n=1,2) address */ -#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) - -/* - * Map an address to a certain privileged segment - */ -#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) -#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) -#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) -#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) - -#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/include/asm-avr32/arch-at32ap700x/addrspace.h b/include/asm-avr32/arch-at32ap700x/addrspace.h new file mode 100644 index 000000000..409eee353 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/addrspace.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ADDRSPACE_H +#define __ASM_AVR32_ADDRSPACE_H + +#include + +/* Memory segments when segmentation is enabled */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + +/* virt_to_phys will only work when address is in P1 or P2 */ +static inline unsigned long virt_to_phys(volatile void *address) +{ + return PHYSADDR(address); +} + +static inline void * phys_to_virt(unsigned long address) +{ + return (void *)P1SEGADDR(address); +} + +#define cached(addr) ((void *)P1SEGADDR(addr)) +#define uncached(addr) ((void *)P2SEGADDR(addr)) + +/* + * Given a physical address and a length, return a virtual address + * that can be used to access the memory range with the caching + * properties specified by "flags". + * + * This implementation works for memory below 512MiB (flash, etc.) as + * well as above 3.5GiB (internal peripherals.) + */ +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (1 << 7) +#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) +#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + if (flags == MAP_WRBACK) + return (void *)P1SEGADDR(paddr); + else + return (void *)P2SEGADDR(paddr); +} + +#endif /* __ASM_AVR32_ADDRSPACE_H */ diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index 50967ac7e..1cb17ead3 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -73,21 +73,8 @@ extern void __readwrite_bug(const char *fn); #define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) #define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) -#include - -/* virt_to_phys will only work when address is in P1 or P2 */ -static inline phys_addr_t virt_to_phys(volatile void *address) -{ - return PHYSADDR(address); -} - -static inline void *phys_to_virt(phys_addr_t address) -{ - return (void *)P1SEGADDR(address); -} - -#define cached(addr) ((void *)P1SEGADDR(addr)) -#define uncached(addr) ((void *)P2SEGADDR(addr)) +#include +/* Provides virt_to_phys, phys_to_virt, cached, uncached, map_physmem */ #endif /* __KERNEL__ */ @@ -95,28 +82,6 @@ static inline void sync(void) { } -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - * - * This implementation works for memory below 512MiB (flash, etc.) as - * well as above 3.5GiB (internal peripherals.) - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (1 << 7) -#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) -#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0)) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - if (flags == MAP_WRBACK) - return (void *)P1SEGADDR(paddr); - else - return (void *)P2SEGADDR(paddr); -} - /* * Take down a mapping set up by map_physmem(). */ diff --git a/lib_avr32/bootm.c b/lib_avr32/bootm.c index 03ab8d1fa..0ca4718c8 100644 --- a/lib_avr32/bootm.c +++ b/lib_avr32/bootm.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.2.3 From f5f652fa91aa69db8117d211af1b4fe09f2edd3b Mon Sep 17 00:00:00 2001 From: Gunnar Rangoy Date: Fri, 23 Jan 2009 12:56:29 +0100 Subject: AVR32: Make GPIO implmentation cpu dependent There are some differences in the implementation of GPIO in the at32uc chip compared to the ap700x series. Signed-off-by: Gunnar Rangoy Signed-off-by: Paul Driveklepp Signed-off-by: Olav Morken Signed-off-by: Haavard Skinnemoen --- include/asm-avr32/arch-at32ap700x/gpio-impl.h | 86 +++++++++++++++++++++++++++ include/asm-avr32/arch-common/portmux-gpio.h | 83 +------------------------- 2 files changed, 88 insertions(+), 81 deletions(-) create mode 100644 include/asm-avr32/arch-at32ap700x/gpio-impl.h (limited to 'include/asm-avr32') diff --git a/include/asm-avr32/arch-at32ap700x/gpio-impl.h b/include/asm-avr32/arch-at32ap700x/gpio-impl.h new file mode 100644 index 000000000..8801bd006 --- /dev/null +++ b/include/asm-avr32/arch-at32ap700x/gpio-impl.h @@ -0,0 +1,86 @@ +#ifndef __ASM_AVR32_ARCH_GPIO_IMPL_H__ +#define __ASM_AVR32_ARCH_GPIO_IMPL_H__ + +/* Register offsets */ +struct gpio_regs { + u32 GPER; + u32 GPERS; + u32 GPERC; + u32 GPERT; + u32 PMR0; + u32 PMR0S; + u32 PMR0C; + u32 PMR0T; + u32 PMR1; + u32 PMR1S; + u32 PMR1C; + u32 PMR1T; + u32 __reserved0[4]; + u32 ODER; + u32 ODERS; + u32 ODERC; + u32 ODERT; + u32 OVR; + u32 OVRS; + u32 OVRC; + u32 OVRT; + u32 PVR; + u32 __reserved_PVRS; + u32 __reserved_PVRC; + u32 __reserved_PVRT; + u32 PUER; + u32 PUERS; + u32 PUERC; + u32 PUERT; + u32 PDER; + u32 PDERS; + u32 PDERC; + u32 PDERT; + u32 IER; + u32 IERS; + u32 IERC; + u32 IERT; + u32 IMR0; + u32 IMR0S; + u32 IMR0C; + u32 IMR0T; + u32 IMR1; + u32 IMR1S; + u32 IMR1C; + u32 IMR1T; + u32 GFER; + u32 GFERS; + u32 GFERC; + u32 GFERT; + u32 IFR; + u32 __reserved_IFRS; + u32 IFRC; + u32 __reserved_IFRT; + u32 ODMER; + u32 ODMERS; + u32 ODMERC; + u32 ODMERT; + u32 __reserved1[4]; + u32 ODCR0; + u32 ODCR0S; + u32 ODCR0C; + u32 ODCR0T; + u32 ODCR1; + u32 ODCR1S; + u32 ODCR1C; + u32 ODCR1T; + u32 __reserved2[4]; + u32 OSRR0; + u32 OSRR0S; + u32 OSRR0C; + u32 OSRR0T; + u32 __reserved3[8]; + u32 STER; + u32 STERS; + u32 STERC; + u32 STERT; + u32 __reserved4[35]; + u32 VERSION; +}; + +#endif /* __ASM_AVR32_ARCH_GPIO_IMPL_H__ */ diff --git a/include/asm-avr32/arch-common/portmux-gpio.h b/include/asm-avr32/arch-common/portmux-gpio.h index 24943ecdb..1306cbe5d 100644 --- a/include/asm-avr32/arch-common/portmux-gpio.h +++ b/include/asm-avr32/arch-common/portmux-gpio.h @@ -24,87 +24,8 @@ #include -/* Register offsets */ -struct gpio_regs { - u32 GPER; - u32 GPERS; - u32 GPERC; - u32 GPERT; - u32 PMR0; - u32 PMR0S; - u32 PMR0C; - u32 PMR0T; - u32 PMR1; - u32 PMR1S; - u32 PMR1C; - u32 PMR1T; - u32 __reserved0[4]; - u32 ODER; - u32 ODERS; - u32 ODERC; - u32 ODERT; - u32 OVR; - u32 OVRS; - u32 OVRC; - u32 OVRT; - u32 PVR; - u32 __reserved_PVRS; - u32 __reserved_PVRC; - u32 __reserved_PVRT; - u32 PUER; - u32 PUERS; - u32 PUERC; - u32 PUERT; - u32 PDER; - u32 PDERS; - u32 PDERC; - u32 PDERT; - u32 IER; - u32 IERS; - u32 IERC; - u32 IERT; - u32 IMR0; - u32 IMR0S; - u32 IMR0C; - u32 IMR0T; - u32 IMR1; - u32 IMR1S; - u32 IMR1C; - u32 IMR1T; - u32 GFER; - u32 GFERS; - u32 GFERC; - u32 GFERT; - u32 IFR; - u32 __reserved_IFRS; - u32 IFRC; - u32 __reserved_IFRT; - u32 ODMER; - u32 ODMERS; - u32 ODMERC; - u32 ODMERT; - u32 __reserved1[4]; - u32 ODCR0; - u32 ODCR0S; - u32 ODCR0C; - u32 ODCR0T; - u32 ODCR1; - u32 ODCR1S; - u32 ODCR1C; - u32 ODCR1T; - u32 __reserved2[4]; - u32 OSRR0; - u32 OSRR0S; - u32 OSRR0C; - u32 OSRR0T; - u32 __reserved3[8]; - u32 STER; - u32 STERS; - u32 STERC; - u32 STERT; - u32 __reserved4[35]; - u32 VERSION; -}; +/* Register layout for this specific device */ +#include /* Register access macros */ #define gpio_readl(port, reg) \ -- cgit v1.2.3