From 621e579b812dd1a2e6777f7cbf6e55e736505823 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 6 Oct 2008 03:44:33 -0400 Subject: Blackfin: fix SWRST register definition The SWRST register is a 16bit, not 32bit, register. Signed-off-by: Mike Frysinger --- include/asm-blackfin/mach-bf561/BF561_cdef.h | 12 ++++++------ include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include/asm-blackfin') diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h index 23e64ca62..d8883f317 100644 --- a/include/asm-blackfin/mach-bf561/BF561_cdef.h +++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h @@ -241,9 +241,9 @@ #define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) #define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) #define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) -#define pSICA_SWRST ((uint32_t volatile *)SICA_SWRST) -#define bfin_read_SICA_SWRST() bfin_read32(SICA_SWRST) -#define bfin_write_SICA_SWRST(val) bfin_write32(SICA_SWRST, val) +#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST) +#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST) +#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val) #define pSICA_SYSCR ((uint32_t volatile *)SICA_SYSCR) #define bfin_read_SICA_SYSCR() bfin_read32(SICA_SYSCR) #define bfin_write_SICA_SYSCR(val) bfin_write32(SICA_SYSCR, val) @@ -292,9 +292,9 @@ #define pSICA_IAR7 ((uint32_t volatile *)SICA_IAR7) #define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7) #define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val) -#define pSICB_SWRST ((uint32_t volatile *)SICB_SWRST) -#define bfin_read_SICB_SWRST() bfin_read32(SICB_SWRST) -#define bfin_write_SICB_SWRST(val) bfin_write32(SICB_SWRST, val) +#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST) +#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST) +#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val) #define pSICB_SYSCR ((uint32_t volatile *)SICB_SYSCR) #define bfin_read_SICB_SYSCR() bfin_read32(SICB_SYSCR) #define bfin_write_SICB_SYSCR(val) bfin_write32(SICB_SYSCR, val) diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h index 297e2629b..4c439e528 100644 --- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h +++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h @@ -897,9 +897,9 @@ #define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */ #define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) #define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val) -#define pSWRST ((uint32_t volatile *)SWRST) /* Software Reset Register (16-bit) */ -#define bfin_read_SWRST() bfin_read32(SWRST) -#define bfin_write_SWRST(val) bfin_write32(SWRST, val) +#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */ +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) #define pSYSCR ((uint32_t volatile *)SYSCR) /* System Configuration register */ #define bfin_read_SYSCR() bfin_read32(SYSCR) #define bfin_write_SYSCR(val) bfin_write32(SYSCR, val) -- cgit v1.2.3