From 66ca92a5ba882807ba8ed8f772c0fc22b25976cc Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Tue, 28 Sep 2004 17:59:53 +0000
Subject: * Patch by Yuli Barcohen, 13 Jul 2004:   Allow clock setting on
 MPC866/MPC885 series chips according to   environment variable `cpuclk'

* Patch by Yuli Barcohen, 20 Apr 2004:
  Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
---
 include/configs/Adder.h | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

(limited to 'include/configs/Adder.h')

diff --git a/include/configs/Adder.h b/include/configs/Adder.h
index 13e6c35cf..f8075466c 100644
--- a/include/configs/Adder.h
+++ b/include/configs/Adder.h
@@ -41,7 +41,14 @@
 #define FEC_ENET
 #endif /* CONFIG_FEC_ENET */
 
-#define CONFIG_8xx_OSCLK	10000000	/* 10 MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+#define CFG_8xx_CPUCLK_MIN		40000000
+#ifdef CONFIG_MPC852T
+#define CFG_8xx_CPUCLK_MAX		50000000
+#else
+#define CFG_8xx_CPUCLK_MAX		120000000
+#endif /* CONFIG_MPC852T */
 
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL  \
 				| CFG_CMD_DHCP   \
@@ -89,6 +96,15 @@
 
 #define CFG_MAMR		0x00802114
 
+/*
+ * 2048	SDRAM rows
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CFG_PTA_PER_CLK		((2048 * 64 * 1000) / (4 * 64))
+
 #define CFG_MEMTEST_START	0x00100000	/* memtest works on		*/
 #define CFG_MEMTEST_END		0x00700000	/* 1 ... 7 MB in SDRAM		*/
 
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