From 0c1c117cf18ffa3fdc0342dfc47c6003fc5fc5a0 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Wed, 30 Mar 2005 23:28:18 +0000
Subject: * Patch by Scott McNutt, 21 Oct 2004:   Add support for Nios-II EPCS
 Controller core.

* Patch by Scott McNutt, 20 Oct 2004:
  Nios-II cleanups:
  - Add sysid command (Nios-II only).
  - Locate default exception trampoline at proper offset.
  - Implement I/O routines (readb, writeb, etc)
  - Implement do_bootm_linux
---
 include/configs/PK1C20.h | 43 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 42 insertions(+), 1 deletion(-)

(limited to 'include/configs/PK1C20.h')

diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index 865c69b5b..91e95186a 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -52,7 +52,7 @@
 #define CFG_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
 #define CFG_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
 #define CFG_SRAM_BASE		0x00800000	/* SRAM base addr	*/
-#define CFG_SRAM_SIZE		0x00200000	/* 2 MByte		*/
+#define CFG_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
 
 /*------------------------------------------------------------------------
  * MEMORY ORGANIZATION
@@ -106,6 +106,14 @@
 
 #define CFG_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
 
+/*------------------------------------------------------------------------
+ * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
+ * epcs device access is enabled. The base address is the epcs
+ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
+ * The register base is currently at offset 0x400 from the memory base.
+ *----------------------------------------------------------------------*/
+#define CFG_NIOS_EPCSBASE	0x00900400	/* EPCS register base	*/
+
 /*------------------------------------------------------------------------
  * DEBUG
  *----------------------------------------------------------------------*/
@@ -172,6 +180,36 @@
 				 CFG_CMD_SAVES	)
 #include <cmd_confdefs.h>
 
+/*------------------------------------------------------------------------
+ * COMPACT FLASH
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_IDE)
+#define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
+#define CFG_IDE_MAXBUS		1		/* 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
+
+#define CFG_ATA_BASE_ADDR	0x00900800	/* ATA base addr	*/
+#define CFG_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
+#define CFG_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
+#define CFG_ATA_REG_OFFSET	0x0040		/* Register offset	*/
+#define CFG_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
+#define CFG_ATA_STRIDE          4		/* Width betwix addrs	*/
+#define CONFIG_DOS_PARTITION
+
+/* Board-specific cf regs */
+#define CFG_CF_PRESENT		0x00900880	/* CF Present PIO base	*/
+#define CFG_CF_POWER		0x00900890	/* CF Power FET PIO base*/
+#define CFG_CF_ATASEL		0x009008a0	/* CF ATASEL PIO base	*/
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
+
+/*------------------------------------------------------------------------
+ * JFFS2
+ *----------------------------------------------------------------------*/
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+#define CFG_JFFS_CUSTOM_PART			/* board defined part	*/
+#endif
+
 /*------------------------------------------------------------------------
  * MISC
  *----------------------------------------------------------------------*/
@@ -185,4 +223,7 @@
 #define CFG_MEMTEST_START	CFG_SDRAM_BASE	/* Start addr for test	*/
 #define CFG_MEMTEST_END		CFG_INIT_SP - 0x00020000
 
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2	"> "
+
 #endif	/* __CONFIG_H */
-- 
cgit v1.2.3