From efa329cb892c8b9a5e453638b3ca57c94b71e9a2 Mon Sep 17 00:00:00 2001
From: wdenk <wdenk>
Date: Tue, 23 Mar 2004 20:18:25 +0000
Subject: * Add start-up delay to make sure power has stabilized before  
 attempting to switch on USB on SX1 board.

* Patch by Josef Wagner, 18 Mar 2004:
  - Add support for MicroSys XM250 board (PXA255)
  - Add support for MicroSys PM828 board (MPC8280)
  - Add support for 32 MB Flash on PM825/826
  - new SDRAM refresh rate for PM825/PM826
  - added support for MicroSys PM520 (MPC5200)
  - replaced Query by Identify command in CPU86/flash.c
    to support 28F160F3B

* Fix wrap around problem with udelay() on ARM920T

* Add support for Macronix flash on TRAB board
---
 include/configs/PM826.h | 28 +++++++++++++++++++---------
 1 file changed, 19 insertions(+), 9 deletions(-)

(limited to 'include/configs/PM826.h')

diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index dc70515d9..942678f69 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -220,15 +220,18 @@
 /*-----------------------------------------------------------------------
  * Flash and Boot ROM mapping
  */
-
+#ifdef CONFIG_FLASH_32MB
+#define	CFG_FLASH0_BASE		0x40000000
+#define	CFG_FLASH0_SIZE		0x02000000
+#else
+#define	CFG_FLASH0_BASE		0xFF000000
+#define	CFG_FLASH0_SIZE		0x00800000
+#endif
 #define	CFG_BOOTROM_BASE	0xFF800000
 #define	CFG_BOOTROM_SIZE	0x00080000
-#define	CFG_FLASH0_BASE		0xFF000000
-#define	CFG_FLASH0_SIZE		0x02000000
 #define CFG_DOC_BASE		0xFF800000
 #define CFG_DOC_SIZE		0x00100000
 
-
 /* Flash bank size (for preliminary settings)
  */
 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
@@ -237,8 +240,11 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#ifdef CONFIG_FLASH_32MB
+#define CFG_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+#else
 #define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */
-
+#endif
 #define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
 
@@ -426,7 +432,6 @@
  * ---- ---     ------- ------  ------
  *  0   60x     GPCM    64 bit  FLASH
  *  1   60x     SDRAM   64 bit  SDRAM
- *  2   Local   SDRAM   32 bit  SDRAM
  *
  */
 
@@ -440,7 +445,12 @@
  */
 #define CFG_MIN_AM_MASK	0xC0000000
 
-#define CFG_MPTPR       0x1F00
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.73 uS (64 MHz Bus Clock)
+ */
+#define CFG_MPTPR       0x2000
+#define CFG_PSRT        0x0E
 
 #define CFG_MRS_OFFS	0x00000000
 
@@ -512,7 +522,7 @@
 
 /* Bank 2 - SDRAM
  */
-#define CFG_PSRT        0x0F
+
 #ifndef CFG_RAMBOOT
 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 			 BRx_PS_64                      |\
-- 
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