From 2853d29b5232e6cee5f8dd21f769d93dd34ffdcf Mon Sep 17 00:00:00 2001
From: stroese <stroese>
Date: Fri, 12 Sep 2003 08:53:54 +0000
Subject: Update configuration.

---
 include/configs/PMC405.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'include/configs/PMC405.h')

diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 54b53bc71..35d49fcec 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -63,6 +63,7 @@
 #define	CONFIG_PHY_ADDR		0	/* PHY address			*/
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_BSP	| \
 				CFG_CMD_PCI	| \
 				CFG_CMD_IRQ	| \
 				CFG_CMD_ELF	| \
@@ -254,6 +255,19 @@
 #define CFG_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CFG_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CFG_FPGA_XC95XL         1           /* using Xilinx XC95XL CPLD      */
+#define CFG_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for CPLD    */
+
+/* FPGA program pin configuration */
+#define CFG_FPGA_PRG            0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CFG_FPGA_CLK            0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CFG_FPGA_DATA           0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT           0x00010000  /* unused (ppc input)            */
+#define CFG_FPGA_DONE           0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-- 
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