From 3c9b1ee17e19bd6d80344678d41a85e52b0be713 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 5 Jun 2009 14:11:33 -0500 Subject: mpc83xx: don't set SICRH_TSOBI1 to RMII/RTBI operation In GMII mode (which operates at 3.3V) both SICRH TSEC1/2 output buffer impedance bits should be clear, i.e., SICRH[TSIOB1] = 0 and SICRH[TSIOB2] = 0. SICRH[TSIOB1] was erroneously being set high. U-Boot always operated this PHY interface in GMII mode. It is assumed this was missed in the clean up by the original board porters, and copied along to the TQM and sbc boards. Signed-off-by: Kim Phillips Acked-by: Ira Snyder Reviewed-by: David Hawkins Tested-by: Paul Gortmaker CC: Dave Liu --- include/configs/sbc8349.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/configs/sbc8349.h') diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index d0338f168..edd928d81 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -519,7 +519,7 @@ #endif /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 -- cgit v1.2.3