From 81b73dec16fd1227369a191e725e10044a9d56b8 Mon Sep 17 00:00:00 2001 From: Gary Jennejohn Date: Fri, 31 Aug 2007 15:21:46 +0200 Subject: ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese . o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese . o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn Signed-off-by: Stefan Roese --- include/configs/sequoia.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/configs/sequoia.h') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 824a81240..c2e138621 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -400,7 +400,8 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ -- cgit v1.2.3