From 5a5958b7de70ae99f0e7cbd5c97ec1346e051587 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 15 Oct 2007 11:29:33 +0200 Subject: ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese --- include/configs/yosemite.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/configs/yosemite.h') diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 6a5b7f1ea..35bce4af9 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -359,6 +359,8 @@ #define CFG_EBC_PB2AP 0x04814500 #define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) +#define CFG_BCSR5_PCI66EN 0x80 + /*----------------------------------------------------------------------- * Cache Configuration */ -- cgit v1.2.3