From 555da61702771fe0f76f3de23b4e7590f3704161 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Tue, 18 Sep 2007 12:36:58 +0800 Subject: mpc83xx: Add the support of MPC8315E SoC The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu --- include/mpc83xx.h | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 87 insertions(+), 6 deletions(-) (limited to 'include/mpc83xx.h') diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 4c230943c..dba1aea4f 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -102,6 +102,10 @@ #define SPR_8313_REV10 0x80B10010 #define SPR_8311E_REV10 0x80B20010 #define SPR_8311_REV10 0x80B30010 +#define SPR_8315E_REV10 0x80B40010 +#define SPR_8315_REV10 0x80B50010 +#define SPR_8314E_REV10 0x80B60010 +#define SPR_8314_REV10 0x80B70010 #define SPR_8379E_REV10 0x80C20010 #define SPR_8379_REV10 0x80C30010 @@ -220,8 +224,8 @@ #define SICRL_URT_CTPR 0x06000000 #define SICRL_IRQ_CTPR 0x00C00000 -#elif defined(CONFIG_MPC831X) -/* SICRL bits - MPC831x specific */ +#elif defined(CONFIG_MPC8313) +/* SICRL bits - MPC8313 specific */ #define SICRL_LBC 0x30000000 #define SICRL_UART 0x0C000000 #define SICRL_SPI_A 0x03000000 @@ -232,7 +236,7 @@ #define SICRL_ETSEC1_A 0x0000000C #define SICRL_ETSEC2_A 0x00000003 -/* SICRH bits - MPC831x specific */ +/* SICRH bits - MPC8313 specific */ #define SICRH_INTR_A 0x02000000 #define SICRH_INTR_B 0x00C00000 #define SICRH_IIC 0x00300000 @@ -249,6 +253,41 @@ #define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI2 0x00000001 +#elif defined(CONFIG_MPC8315) +/* SICRL bits - MPC8315 specific */ +#define SICRL_DMA_CH0 0xc0000000 +#define SICRL_DMA_SPI 0x30000000 +#define SICRL_UART 0x0c000000 +#define SICRL_IRQ4 0x02000000 +#define SICRL_IRQ5 0x01800000 +#define SICRL_IRQ6_7 0x00400000 +#define SICRL_IIC1 0x00300000 +#define SICRL_TDM 0x000c0000 +#define SICRL_TDM_SHARED 0x00030000 +#define SICRL_PCI_A 0x0000c000 +#define SICRL_ELBC_A 0x00003000 +#define SICRL_ETSEC1_A 0x000000c0 +#define SICRL_ETSEC1_B 0x00000030 +#define SICRL_ETSEC1_C 0x0000000c +#define SICRL_TSEXPOBI 0x00000001 + +/* SICRH bits - MPC8315 specific */ +#define SICRH_GPIO_0 0xc0000000 +#define SICRH_GPIO_1 0x30000000 +#define SICRH_GPIO_2 0x0c000000 +#define SICRH_GPIO_3 0x03000000 +#define SICRH_GPIO_4 0x00c00000 +#define SICRH_GPIO_5 0x00300000 +#define SICRH_GPIO_6 0x000c0000 +#define SICRH_GPIO_7 0x00030000 +#define SICRH_GPIO_8 0x0000c000 +#define SICRH_GPIO_9 0x00003000 +#define SICRH_GPIO_10 0x00000c00 +#define SICRH_GPIO_11 0x00000300 +#define SICRH_ETSEC2_A 0x000000c0 +#define SICRH_TSOBI1 0x00000002 +#define SICRH_TSOBI2 0x00000001 + #elif defined(CONFIG_MPC837X) /* SICRL bits - MPC837x specific */ #define SICRL_USB_A 0xC0000000 @@ -447,7 +486,7 @@ #define HRCWL_CE_TO_PLL_1X30 0x0000001E #define HRCWL_CE_TO_PLL_1X31 0x0000001F -#elif defined(CONFIG_MPC837X) +#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315) #define HRCWL_SVCOD 0x30000000 #define HRCWL_SVCOD_SHIFT 28 #define HRCWL_SVCOD_DIV_4 0x00000000 @@ -556,7 +595,7 @@ /* RSR - Reset Status Register */ -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) #define RSR_RSTSRC 0xF0000000 /* Reset source */ #define RSR_RSTSRC_SHIFT 28 #else @@ -677,7 +716,7 @@ #define SCCR_USBCM_2 0x00A00000 #define SCCR_USBCM_3 0x00F00000 -#elif defined(CONFIG_MPC831X) +#elif defined(CONFIG_MPC8313) /* TSEC1 bits are for TSEC2 as well */ #define SCCR_TSEC1CM 0xc0000000 #define SCCR_TSEC1CM_SHIFT 30 @@ -697,6 +736,48 @@ #define SCCR_USBDRCM_2 0x00200000 #define SCCR_USBDRCM_3 0x00300000 +#elif defined(CONFIG_MPC8315) +/* SCCR bits - MPC8315 specific */ +#define SCCR_TSEC1CM 0xc0000000 +#define SCCR_TSEC1CM_SHIFT 30 +#define SCCR_TSEC1CM_0 0x00000000 +#define SCCR_TSEC1CM_1 0x40000000 +#define SCCR_TSEC1CM_2 0x80000000 +#define SCCR_TSEC1CM_3 0xC0000000 + +#define SCCR_TSEC2CM 0x30000000 +#define SCCR_TSEC2CM_SHIFT 28 +#define SCCR_TSEC2CM_0 0x00000000 +#define SCCR_TSEC2CM_1 0x10000000 +#define SCCR_TSEC2CM_2 0x20000000 +#define SCCR_TSEC2CM_3 0x30000000 + +#define SCCR_USBDRCM 0x00300000 +#define SCCR_USBDRCM_SHIFT 20 +#define SCCR_USBDRCM_0 0x00000000 +#define SCCR_USBDRCM_1 0x00100000 +#define SCCR_USBDRCM_2 0x00200000 +#define SCCR_USBDRCM_3 0x00300000 + +#define SCCR_PCIEXP1CM 0x00080000 +#define SCCR_PCIEXP2CM 0x00040000 + +#define SCCR_SATA1CM 0x0000c000 +#define SCCR_SATA1CM_SHIFT 14 +#define SCCR_SATACM 0x0000f000 +#define SCCR_SATACM_SHIFT 8 +#define SCCR_SATACM_0 0x00000000 +#define SCCR_SATACM_1 0x00005000 +#define SCCR_SATACM_2 0x0000a000 +#define SCCR_SATACM_3 0x0000f000 + +#define SCCR_TDMCM 0x000000c0 +#define SCCR_TDMCM_SHIFT 6 +#define SCCR_TDMCM_0 0x00000000 +#define SCCR_TDMCM_1 0x00000040 +#define SCCR_TDMCM_2 0x00000080 +#define SCCR_TDMCM_3 0x000000c0 + #elif defined(CONFIG_MPC837X) /* SCCR bits - MPC837x specific */ #define SCCR_TSEC1CM 0xc0000000 -- cgit v1.2.3